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TMS320DM6467 Digital Media System-on-Chip
Digital Media System-on-Chip (DMSoC)
High-Performance Digital Media 594-MHz C64x+Clock Rate 297-MHz ARM926EJ-SClock Rate Eight 32-Bit C64x+ Instructions/Cycle 4752 C64x+ MIPS Fully Software-Compatible With C64x ARM9Advanced Very-Long-Instruction-Word (VLIW) TMS320C64x+DSP Core Eight Highly Independent Functional Units ALUs (32-/40-Bit), Each Supports Single 32-Bit, Dual 16-Bit, Quad 8-Bit Arithmetic Clock Cycle Multipliers Support Four 16-Bit Multiplies (32-Bit Results) Clock Cycle Eight 8-Bit Multiplies (16-Bit Results) Clock Cycle Load-Store Architecture With Non-Aligned Support 32-Bit General-Purpose Registers Instruction Packing Reduces Code Size Instructions Conditional Additional C64x+Enhancements Protected Mode Operation Exceptions Support Error Detection Program Redirection Hardware Support Modulo Loop Operation C64x+ Instruction Features Byte-Addressable (8-/16-/32-/64-Bit Data) 8-Bit Overflow Protection Bit-Field Extract, Set, Clear Normalization, Saturation, Bit-Counting Compact 16-Bit Instructions Additional Instructions Support Complex Multiplies C64x+ L1/L2 Memory Architecture 32K-Byte Program RAM/Cache (Direct Mapped) 32K-Byte Data RAM/Cache (2-Way Set-Associative) 128K-Byte Unified Mapped RAM/Cache (Flexible RAM/Cache Allocation) ARM926EJ-S Core Support 32-Bit 16-Bit (Thumb® Mode) Instruction Sets Instruction Extensions Single Cycle ARM® Jazelle® Technology EmbeddedICE-RTLogic Real-Time Debug ARM9 Memory Architecture 16K-Byte Instruction Cache 8K-Byte Data Cache 32K-Byte 8K-Byte Embedded Trace Buffer(ETB11TM) With Memory ARM9 Debug Endianness: Little Endian Dual Programmable High-Definition Video Image Co-Processor (HDVICP) Engines Supports Range Encode, Decode, Transcode Operations H.264, MPEG2, VC1, MPEG4 SP/ASP Video Port Interface (VPIF) 8-Bit (BT.656), Single 16-Bit (BT.1120), Single (8-/10-/12-Bit) Video Capture Channels 8-Bit (BT.656) Single 16-Bit (BT.1120) Video Display Channels Video Data Conversion Engine (VDCE) Horizontal Vertical Downscaling Chroma Conversion (4:2:24:2:0) Transport Stream Interface (TSIF) Modules (One Parallel/Serial Serial Only) TSIF MPEG Transport Stream Simultaneous Synchronous Asynchronous Input/Output Streams Absolute Time Stamp Detection Filter With Filter Tables Corresponding Clock Reference Generator (CRGEN) Modules System Time-Clock Recovery
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PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 2007-2008, Texas Instruments Incorporated
TMS320DM6467 Digital Media System-on-Chip
SPRS403A DECEMBER 2007 REVISED 2008 www.ti.com
External Memory Interfaces (EMIFs) 32-Bit DDR2 SDRAM Memory Controller With 256M-Byte Address Space (1.8-V I/O) Asynchronous16-Bit Wide EMIF (EMIFA) With 128M-Byte Address Reach Flash Memory Interfaces (8-/16-Bit-Wide Data) NAND (8-/16-Bit-Wide Data) Enhanced Direct-Memory-Access (EDMA) Controller Independent Channels) Programmable Default Burst Size 10/100/1000 Mb/s Ethernet (EMAC) IEEE 802.3 Compliant (3.3-V Only) Supports GMII Media Independent Interfaces Management Data (MDIO) Module Port With Integrated High-/Full-Speed Client High-/Full-/Low-Speed Host (Mini-Host, Supporting External Device) 32-Bit, 33-MHz, Peripheral Component Interconnect (PCI) Master/Slave Interface Conforms Specification 64-Bit General-Purpose Timers (Each Configurable 32-Bit Timers) 64-Bit Watch Timer Three Configurable UART/IrDA/CIR Modules (One With Modem Control Signals) Supports 1.8432 Mbps UART (0.576 MBAUD) With Programmable Data Encoding
Serial Peripheral Interface (SPI) With Chip-Selects Master/Slave Inter-Integrated Circuit (I2C BusTM) Multichannel Audio Serial Ports (McASPs) Four Serializer Transmit/Receive Port Single Transmit Port S/PDIF 32-Bit Host Port Interface (HPI) VLYNQInterface (FPGA Interface) Pulse Width Modulator (PWM) Outputs ATA/ATAPI (ATA/ATAPI-6 Specification) General-Purpose (GPIO) Pins (Multiplexed With Other Device Functions) On-Chip Bootloader (RBL) Individual Power-Saving Modes ARM/DSP Flexible Clock Generators IEEE-1149.1 (JTAG) BoundaryScan-Compatible 529-Pin Pb-Free Package (ZUT Suffix), 0.8-mm Ball Pitch 0.09-µm/7-Level Metal Process (CMOS) 3.3-V 1.8-V I/O, 1.2-V Internal Applications: Video Digital Media Networked Media Encode/Decode Video Imaging Video Infrastructure Video Conferencing
Digital Media System-on-Chip (DMSoC)
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TMS320DM6467 Digital Media System-on-Chip
Description
TMS320DM6467 (also referenced DM6467) leverages TI's DaVincitechnology meet networked media encode decode application processing needs next-generation embedded devices. DM6467 enables OEMs ODMs quickly bring market devices featuring robust operating systems support, rich user interfaces, high processing performance, long battery life through maximum flexibility fully integrated mixed processor solution. dual-core architecture DM6467 provides benefits both Reduced Instruction Computer (RISC) technologies, incorporating high-performance TMS320C64x+ core ARM926EJ-S core. ARM926EJ-S 32-bit RISC processor core that performs 32-bit 16-bit instructions processes 32-bit, 16-bit, 8-bit data. core uses pipelining that parts processor memory system operate continuously. core incorporates: coprocessor (CP15) protection module Data program Memory Management Units (MMUs) with table look-aside buffers. Separate 16K-byte instruction 8K-byte data caches. Both four-way associative with virtual index virtual (VIVT). TMS320C64x+DSPs highest-performance fixed-point generation TMS320C6000DSP platform. based enhanced version second-generation high-performance, advanced very-long-instruction-word (VLIW) architecture developed Texas Instruments (TI), making these cores excellent choice digital media applications. C64x code-compatible member C6000DSP platform. TMS320C64x+ enhancement C64x+ with added functionality expanded instruction set. reference C64x C64x also applies, unless otherwise noted, C64x+ C64x+ CPU, respectively. With performance 4752 million instructions second (MIPS) clock rate MHz, C64x+ core offers solutions high-performance programming challenges. core possesses operational flexibility high-speed controllers numerical capability array processors. C64x+ core processor general-purpose registers 32-bit word length eight highly independent functional units-two multipliers 32-bit result arithmetic logic units (ALUs). eight functional units include instructions accelerate performance video imaging applications. core produce four 16-bit multiply-accumulates (MACs) cycle total 2376 million MACs second (MMACS), eight 8-bit MACs cycle total 4752 MMACS. more details C64x+ DSP, TMS320C64x/C64x+ Instruction Reference Guide (literature number SPRU732). DM6467 also application-specific hardware logic, on-chip memory, additional on-chip peripherals similar other C6000 platform devices. DM6467 core uses two-level cache-based architecture. Level program cache (L1P) 256K-bit direct mapped cache Level data cache (L1D) 640K-bit 2-way set-associative cache. Level memory/cache (L2) consists 512K-bit memory space that shared between program data space. memory configured mapped memory, cache, combinations two. peripheral includes: configurable video port; 10/100/1000 Mb/s Ethernet (EMAC) with Management Data Input/Output (MDIO) module; 4-bit transfer/4-bit receive VLYNQ interface; inter-integrated circuit (I2C) interface; multichannel audio serial port (McASP0) with serializers; secondary multichannel audio serial port (McASP1) with single transmit serializer; 64-bit general-purpose timers each configurable independent 32-bit timers; 64-bit watchdog timer; configurable 32-bit host port interface (HPI); 33-pins general-purpose input/output (GPIO) with
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Digital Media System-on-Chip (DMSoC)
TMS320DM6467 Digital Media System-on-Chip
SPRS403A DECEMBER 2007 REVISED 2008 www.ti.com
programmable interrupt/event generation modes, multiplexed with other peripherals; UART/IrDA/CIR interfaces with modem interface signals UART0; pulse width modulator (PWM) peripherals; ATA/ATAPI-6 interface; 33-MHz peripheral component interface (PCI); external memory interfaces: asynchronous external memory interface (EMIFA) slower memories/peripherals, higher speed synchronous memory interface DDR2. Ethernet Media Access Controller (EMAC) provides efficient interface between DM6467 network. DM6467 EMAC support both 10Base-T 100Base-TX, Mbits/second (Mbps) Mbps either half- full-duplex mode; 1000Base-TX Gbps) full-duplex mode with hardware flow control quality service (QOS) support. Management Data Input/Output (MDIO) module continuously polls MDIO addresses order enumerate devices system. Once candidate been selected ARM, MDIO module transparently monitors link state reading status register. Link change events stored MDIO module optionally interrupt ARM, allowing poll link status device without continuously performing costly MDIO accesses. PCI, HPI, I2C, SPI, USB2.0, VLYNQ ports allow DM6467 easily control peripheral devices and/or communicate with host processors. DM6467 also includes High-Definition Video/Imaging Co-processor (HDVICP) Video Data Conversion Engine (VDCE) offload many video imaging processing tasks from core, making more MIPS available common video imaging algorithms. more information HDVICP enhanced codecs, such H.264 MPEG4, please contact your nearest sales representative. rich peripheral provides ability control external peripheral devices communicate with external processors. details each peripherals, related sections later this document associated peripheral reference guides. DM6467 complete development tools both DSP. These include compilers, assembly optimizer simplify programming scheduling, Windowsdebugger interface visibility into source code execution.
Digital Media System-on-Chip (DMSoC)
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TMS320DM6467 Digital Media System-on-Chip
Functional Block Diagram
Figure shows functional block diagram device.
JTAG Interface System Control Input Clock(s) PLLs/Clock Generator Power/Sleep Controller Multiplexing Subsystem ARM926EJ-S I-Cache D-Cache Subsystem C64x+ Data High Definition Video-Imaging Coprocessor (HDVICP0) High Definition Video-Imaging Coprocessor (HDVICP1)
Switched Central Resource (SCR)
Peripherals
Serial Interfaces System
EDMA
McASP
UART
GeneralPurpose Timer
Watchdog Timer
CRGEN
VDCE Connectivity Program/Data Storage
TSIF
Video Port
MHz)
VLYNQ
EMAC With MDIO
DDR2 Ctlr (16b/32b)
Async EMIF/ NAND/ SmartMedia
Figure 1-1. TMS320DM6467 Functional Block Diagram
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Digital Media System-on-Chip (DMSoC)
TMS320DM6467 Digital Media System-on-Chip
SPRS403A DECEMBER 2007 REVISED 2008 www.ti.com
Contents
Digital Media System-on-Chip (DMSoC)
Features Description Functional Block Diagram 6.10 6.11 6.12 6.13 6.14 6.15 6.16 6.17 6.18 6.19 6.20 6.21 6.22 6.23 6.24 6.25 6.26 6.27 6.28 Recommended Clock Control Signal Transition Behavior. Power Supplies External Clock Input From DEV_MXI/DEV_CLKIN AUX_MXI/AUX_CLKIN Pins Clock PLLs Enhanced Direct Memory Access (EDMA3) Controller Reset Interrupts External Memory Interface (EMIF) Video Port Interface (VPIF) Transport Stream Interface (TSIF) Clock Recovery Generator (CRGEN) Video Data Conversion Engine (VDCE)
Revision History Device Overview
Device Compatibility. Subsystem Subsystem Memory Summary Assignments Terminal Functions Device Support Documentation Support Device Configurations. System Module Registers Power Considerations Clock Considerations Boot Sequence Configurations Reset Configurations After Reset Multiplexed Configurations. Debugging Considerations System Interconnect System Interconnect Block Diagram Device Operating Conditions.
Device Characteristics Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted) Recommended Operating Conditions Electrical Characteristics Over Recommended Ranges Supply Voltage Operating Temperature (Unless Otherwise Noted)
Peripheral Component Interconnect (PCI) Ethernet (EMAC) Management Data Input/Output (MDIO) Host-Port Interface (HPI) Peripheral Controller VLYNQ Multichannel Audio Serial Port (McASP0/1) Peripherals Serial Peripheral Interface (SPI) Universal Asynchronouse Receiver/Transmitter (UART) Inter-Integrated Circuit (I2C) Pulse Width Modulator (PWM). Timers General-Purpose Input/Output (GPIO). IEEE 1149.1 JTAG
Mechanical Packaging Orderable Information
Thermal Data ZUT. 7.1.1 Packaging Information.
Peripheral Information Electrical Specifications
Parameter Information
Contents
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TMS320DM6467 Digital Media System-on-Chip
Revision History
NOTE: Page numbers previous revisions differ from page numbers current version.
This data manual revision history highlights technical changes made SPRS403 device-specific data manual make SPRS403A revision. Scope: Applicable updates DM646x DMSoC device family, specifically relating TMS320DM6467 device which production data (PD) stage development have been incorporated. EMAC Boot supported this device EM_A[23] function supported this device; PCI_PAR active-high signal
Global Updated/changed applicable device-specific information support device production data (PD) stage development. Updated/changed TBDs where possible. Deleted EM_A[23] function; supported this device; RSV. Section 1.3, Functional Block Diagram: Updated/changed Figure 1-1, TMS320DM6467 Functional Block Diagram Table 2-1, Characteristics DM6467 Processor: Added VDCE, CRGEN, rows Updated/changed Power Sleep Controller (PSC) description Updated/changed address value from "TBD" "0x1000" Updated/changed C64x+ Megamodule Revision address value from "TBD" "0x0000" Table 2-3, Memory Summary: Updated/changed 0x0081 0000 thru 0x0081 7FFF address range from "TBD MPPA Disable" "Hole (MPPA Disable)" Updated/changed 0x1181 0000 thru 0x1181 7FFF address range from "TBD MPPA Disable" "Hole (MPPA Disable)" Added associated footnote Figure 2-6, [Section Updated/changed signal name from "TCLK" "TCK" Table 2-5, BOOT Terminal Functions: Updated/changed "EMAC Boot" "Reserved"; supported this device Table 2-9, Asynchronous External Memory Interface (EMIFA) Terminal Functions, EMIFA Functional Pin: ASYNC: Deleted overbar; PCI_PAR active-high signal Table 2-15, Terminal Functions: Updated/changed USB_R1 signal description Section System Module Registers Section Power Considerations Table 3-1, System Module Register Memory Map: Added cross reference EDMATCCFG Register described paragraph: Updated/changed reference from "TMS320DM646x DMSoC Subsystem Reference Guide (literature number SPRUEP8)" "TMS320DM646x DMSoC Subsystem Reference Guide (literature number SPRUEP9)" Updated/changed section reference "For list multiplexed pins paragraph Section 3.3.2, Clock Control: Added paragraph Table 3-10, BOOTCFG Register Descriptions: Updated/changed "EMAC Boot" "Reserved"; supported this device Table 3-13, Default Functions Affected Device Boot Configuration Pins: Updated/changed "Software modify PINMUX0 footnote
Section Functional Block Diagram Section Device Characteristics
Section Memory Summary
Section 2.6.1 (Bottom View) Section Terminal Functions
Section Clock Considerations Section 3.4.2.3 BOOTCFG Register Section 3.5.1 Device Peripheral Configurations Device Reset Section 3.5.3 Enable (PCIEN) Submit Documentation Feedback
Deleted "These values cannot sentence form "The PCIEN setting captured paragraph
Revision History
TMS320DM6467 Digital Media System-on-Chip
SPRS403A DECEMBER 2007 REVISED 2008 www.ti.com
Section 3.6.2 Peripheral Selection After Device Reset
Section 3.6.2.1, HPICTL Register: Updated/changed "The control register lead-in paragraph Updated/changed Figure 3-14, HPICTL Register [0x01C4 0030]; Bits17:16 Updated/changed Table 3-18, HPICTL Register Descriptions; Bits17:16 Section 3.7.1, Muxing Selection Reset: Updated/changed "The configuration pins CS2BW paragraph Section 3.7.2, Muxing Selection After Reset: Updated/changed "The PINMUX0 PINMUX1 registers paragraph Section 3.7.2.1, PINMUX0 Register Description: Updated/changed combination PINMUX fields sentence Section 3.7.2.2, PINMUX1 Register Description: Updated/changed combination PINMUX fields sentence
Section Multiplexed Configurations
Section 3.7.3 Multiplexing Details Section System Interconnect (NEW) Section Device Operating Conditions
Updated/changed paragraphs this section Deleted Multiplexed DM6467 (was Section 3.7.3.1) Deleted "Device Initialization Sequence After Reset" (was Section 3.8) Added Section System Interconnect (new)
Section 5.1, Absolute Maximum Ratings Over Operating Case Temperature Range (Unless Otherwise Noted): Added "Electrostatic Discharge (ESD) Performance" absolute maximum values Section 5.2, Recommended Operating Conditions: Added separate "High-level input voltage, JTAG [TCK]" parameter Section 5.3, Electrical Characteristics Over Recommended Ranges Supply Voltage Operating Temperature (Unless Otherwise Noted): Updated/changed value Input current (PCI-capable pin) [DC], DVDD33 with opposing internal pullup resistor from "190" "250" Updated/changed value Input current (PCI-capable pin) [DC], DVDD33 with opposing internal pulldown resistor from "-190" "-250" Added "(PCI function only)" TEST CONDITIONS IOH, High-level output current [DC] PCI-capable pins Added "(PCI function only)" TEST CONDITIONS IOL, Low-level output current [DC] PCI-capable pins Updated/Changed value ICDD, Core (CVDD, DEV_CVDD, AUX_CVDD) supply current from "TBD" "1318.58" Updated/Changed value IDDD, 3.3V (DVDD33, USB_VDDA3P3) supply current from "TBD" "25.32" Updated/Changed value IDDD, 1.8V (DVDDR2, PLL1VPRW18, PLL2VPRW18, DEV_DVDD18, AUX_DVDD18, USB_VDD1P8) supply current from "TBD" "255.15" Added "ARM Clock MHz, Clock MHz" ICDD, IDDD(3.3V I/O), IDDD(1.8V I/O) TEST CONDITIONS
Section Power Supplies
Section 6.3, Power Supplies: Updated/changed Power Management Products Suggested Devices link "www.ti.com/processorpower" Section 6.3.1, Power-Supply Sequencing: Updated/changed Power Management Products Suggested Devices link "www.ti.com/processorpower" Updated/changed bullets under "Here summary power sequencing requirements:" paragraph [reversed power sequencing order]
Section RESET Section 6.7.9 Reset Electrical Data/Timing Section 6.11 Transport Stream Interface (TSIF) Revision History
Section 6.7.2, Warm Reset (RESET Pin): Deleted last paragraph this subsection "After boot sequence, follow Section 6.7.9, Reset Electrical Data/Timing: Updated/changed Figure 6-19, Power-Up Timing Updated/changed Figure 6-20, Warm Reset (RESET) Timing Updated/changed "Stream input/outpu (I/O) speed rate bullet
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Section 6.11.4 Transport Stream Interface (TSIF) Electrical Data/Timing
Table 6-40, Timing Requirements TSIF Input: Updated/changed value both SERIAL INPUT PARALLEL INPUT parameter tt(TSCLKIN), Transition time, TSx_CLKIN from "TBD" Added associated footnote Table 6-41, Switching Characteristics Over Recommended Operating Conditions TSIF Output: Updated/changed value both SERIAL OUTPUT PARALLEL OUTPUT parameter tt(TSCLKO), Transition time, TSx_CLKO from "TBD" Added associated footnote Updated/changed values both SERIAL OUTPUT PARALLEL OUTPUT parameter td(TSCLKOV-TSDATAO), Delay time, TSx_CLKO edge TSx_CTL/TSx_DATA output valid from "TBD" "1", "16.5", "1", "16.5" respectively
Section 6.17.4 Electrical Data/Timing Section 6.15.3 EMAC Peripheral Register Description(s) Section 6.18.3 USB2.0 Peripheral Register Description(s)
Table 6-72, Timing Requirements Host-Port Interface Cycles: Updated/changed value parameter th(HSTBH-HDV), Hold time, host data valid after HSTROBE high from "0.15" Table 6-56, Ethernet (EMAC): Updated/changed REGISTER NAME 0x01C8 01D0, MACSRCADDRLO from (Lower 32-bits)" (Lower 16-bits)" [Cleared Documentation Feedback Issue] Table 6-75, USB2.0 Reigsters: Added Core Registers header Deleted 0x01C6 441F second address FIFOSIZE Updated/changed registers Control Status Register Endpoint regions Table 6-76, Switching Characteristics Over Recommended Operating Conditions USB2.0: Updated/changed Parameter USB_R1 "UNIT" value from Added Figure 6-55, Reference Resistor Routing (new) Table 6-87, Switching Characteristics Over Recommended Operating Conditions Transmit Data VLYNQ Module: Updated/changed value parameter td(VCLKH-TXDI), Delay time, VLYNQ_CLOCK high VLYNQ_TXD[3:0] invalid from "2.25" "2.21" Updated/changed value parameter td(VCLKH-TXDV), Delay time, VLYNQ_CLOCK high VLYNQ_TXD[3:0] valid from "7.14" Table 6-89, Data Flop Hold/Setup Timing Constraints: Updated/changed HOLD values except Data Flop
Section 6.18.4 USB2.0 Electrical Data/Timing Section 6.20.3 VLYNQ Electrical Data/Timing
Section 6.22.3 Table 6-106, Additional Output Switching Characteristics 5-Pin Option Master Mode: Electrical Data/Timing Moved Parameters td(CSL-ENA) td(CLK-ENA) Table 6-107, Additional Input Timing Requirements 5-Pin Option Master Mode (new)
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Revision History
TMS320DM6467 Digital Media System-on-Chip
SPRS403A DECEMBER 2007 REVISED 2008 www.ti.com
Device Overview
Device Characteristics
Table provides overview TMS320DM6467 SoC. table shows significant features device, including capacity on-chip RAM, peripherals, internal peripheral frequency relative C64x+ DSP, package type with count. Table 2-1. Characteristics DM6467 Processor
HARDWARE FEATURES DDR2 Memory Controller Asynchronous EMIF (EMIFA) EDMA Timers DM6467 DDR2 (16/32-bit width) Asynchronous (8/16-bit width) RAM, Flash (NOR, NAND) independent channels QDMA channels 64-Bit General Purpose (each configurable separate 32-bit timers) 64-Bit Watchdog (with SIR, MIR, support RTS/CTS flow control) (UART0 Supports Modem Interface) (supports slave devices) (Master/Slave) (one transmit/receive with serializers, transmit only with serializer S/PDIF output) (with MII/GMII Interface) pins outputs (ATA/ATAPI-6) (32-bit, MHz) (16-/32-bit multiplexed address/data) [horizontal vertical downscaling, chroma conversion (4:2:24:2:0)] (peripheral/module clock gating) 8-bit BT.656 capture channels 16-bit capture channel 8-/10-/12-bit video capture channel 8-bit BT.656 display channels 16-bit display channel MPEG transport stream interface Transport Stream Interface (TSIF) with 8-bit parallel serial input output with serial-only input output Each with corresponding clock recovery generator (CRGEN) external VCXO control. High- Full-Speed Device High-, Full-, Low-Speed Host
UART Multichannel Audio Serial Port (McASP) 10/100/1000 Ethernet with Management Data Input/Output (MDIO) Peripherals peripherals pins available same time (for more detail, Device Configurations section). VLYNQ General-Purpose Input/Output Port (GPIO) VDCE Clock Recovery Generator (CRGEN) Power Sleep Controller (PSC)
Configurable Video Port Interface (VPIF)
Device Overview
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TMS320DM6467 Digital Media System-on-Chip
Table 2-1. Characteristics DM6467 Processor (continued)
HARDWARE FEATURES Size (Bytes) DM6467 248KB RAM, 32KB Program (L1P)/Cache 32KB) 32KB Data (L1D)/Cache 32KB) 128KB Unified Mapped RAM/Cache (L2) Organization 16KB I-cache D-cache 32KB 0x1000 0x0000 Section 6.28.1, JTAG (JTAGID) Register Description(s) DM6467 DM6467 ARM926 1.68 ARM926 3.37 (-594) (Bypass), (-594) (Bypass), (-594) 529-Pin (ZUT) 0.09
On-Chip Memory
C64x+ Megamodule Revision JTAG BSDL_ID Frequency Cycle Time Voltage
Control Status Register (CSR.[31:16]) Revision Register (MM_REVID[15:0]) (address location: 0x0181 2000) JTAGID Register (address location: 0x01C4 0028) Core DEV_CLKIN frequency multiplier (27-MHz reference) AUX_CLKIN frequency multiplier (24/48-MHz reference) Product Preview (PP), Advance Information (AI), Production Data (PD)
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Package Process Technology Product Status
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
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Device Overview
TMS320DM6467 Digital Media System-on-Chip
SPRS403A DECEMBER 2007 REVISED 2008 www.ti.com
Device Compatibility
ARM926EJ-S RISC compatible with other ARM9 CPUs from Holdings plc. C64x+ core code-compatible with C6000DSP platform supports features C64x family.
Subsystem
Subsystem designed give ARM926EJ-S (ARM9) master control device. general, responsible configuration control device; including Subsystem, VPSS Subsystem, majority peripherals external memories. Subsystem includes following features: ARM926EJ-S RISC processor ARMv5TEJ (32/16-bit) instruction Little endian operation Co-Processor (CP15) 16KB Instruction cache Data cache Write Buffer 32KB Internal Tightly-Coupled Memory (TCM) (32-bit wide access) Internal (ARM bootloader non-EMIFA boot options) Embedded Trace Module Embedded Trace Buffer (ETM/ETB) Interrupt Controller Controller Power Sleep Controller (PSC) System Module
2.3.1
ARM926EJ-S RISC
Subsystem integrates ARM926EJ-S processor. ARM926EJ-S processor member ARM9 family general-purpose microprocessors. This processor targeted multi-tasking applications where full memory management, high performance, size, power important. ARM926EJ-S processor supports 32-bit THUMB instruction sets, enabling user trade between high performance high code density. Specifically, ARM926EJ-S processor supports ARMv5TEJ instruction set, which includes features efficient execution Java byte codes, providing Java performance similar Just Time (JIT) Java interpreter, without associated code overhead. ARM926EJ-S processor supports debug architecture includes logic assist both hardware software debug. ARM926EJ-S processor Harvard architecture provides complete high performance subsystem, including: ARM926EJ integer core CP15 system control coprocessor Memory Management Unit (MMU) Separate instruction data Caches Write buffer Separate instruction data Tightly-Coupled Memories (TCMs) [internal RAM] interfaces Separate instruction data interfaces Embedded Trace Module Embedded Trace Buffer (ETM/ETB)
Device Overview
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more complete details ARM9, refer ARM926EJ-S Technical Reference Manual, available http://www.arm.com
2.3.2
CP15
ARM926EJ-S system control coprocessor (CP15) used configure control instruction data caches, Tightly-Coupled Memories (TCMs), Memory Management Unit (MMU), other subsystem functions. CP15 registers programmed using instructions, when privileged mode such supervisor system mode.
2.3.3
ARM926EJ-S provides virtual memory features required operating systems such Linux®, Windows® Ultron®, ThreadX®, etc. single level page tables stored main memory used control address translation, permission checks memory region attributes both data instruction accesses. uses single unified Translation Lookaside Buffer (TLB) cache information held page tables. features are: Standard architecture mapping sizes, domains access protection scheme. Mapping sizes are: (sections) 64KB (large pages) (small pages) (tiny pages) Access permissions large pages small pages specified separately each quarter page (subpage permissions) Hardware page table walks Invalidate entire TLB, using CP15 register Invalidate entry, selected MVA, using CP15 register Lockdown entries, using CP15 register
2.3.4
Caches Write Buffer
size Instruction Cache 16KB, Data cache 8KB. Additionally, Caches have following features: Virtual index, virtual tag, addressed using Modified Virtual Address (MVA) Four-way associative, with cache line length eight words line (32-bytes line) with dirty bits Dcache Dcache supports write-through write-back copy back) cache operation, selected memory region using bits translation tables. Critical-word first cache refilling Cache lockdown registers enable control over which cache ways used allocation line fill, providing mechanism both lockdown, controlling cache corruption Dcache stores Physical Address TAG) corresponding each Dcache entry during cache line write-backs, addition Virtual Address stored RAM. This means that involved Dcache write-back operations, removing possibility misses related write-back address. Cache maintenance operations provide efficient invalidation entire Dcache Icache, regions Dcache Icache, regions virtual memory. write buffer used writes noncachable bufferable region, write-through region write misses write-back region. separate buffer incorporated Dcache holding write-back cache line evictions cleaning dirty cache lines. main write buffer 16-word data buffer four-address buffer. Dcache write-back eight data word entries single address entry.
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Device Overview
TMS320DM6467 Digital Media System-on-Chip
SPRS403A DECEMBER 2007 REVISED 2008 www.ti.com
2.3.5
Tightly Coupled Memory (TCM)
internal provided storing real-time performance-critical code/data Interrupt Vector table. internal enables non-EMIFA boot options, such NAND UART. memories interfaced ARM926EJ-S tightly coupled memory interface that provides separate instruction data connections. Since does allow instructions D-TCM data I-TCM bus, arbiter included that both data instructions stored internal RAM/ROM. arbiter also allows accesses RAM/ROM from extra-ARM sources (e.g., EDMA other masters). ARM926EJ-S built-in support direct accesses internal memory from non-ARM master. Because time-critical nature link internal memory, accesses from non-ARM devices treated transfers. Instruction Data accesses differentiated accessing different memory regions, with instruction region from 0x0000 through 0x7FFF data from 0x10000 through 0x17FFF. instruction region 0x0000 data region 0x8000 same physical 32-KB RAM. Placing instruction region 0x0000 necessary allow Interrupt Vector table placed 0x0000, required architecture. internal 32-KB split into physical banks 16KB each, which allows simultaneous instruction data accesses accomplished code data separate banks.
2.3.6
Advanced High-Performance (AHB)
Subsystem uses port ARM926EJ-S connect Config external memories. Arbiters employed arbitrate access separate D-AHB I-AHB Config external memories bus.
2.3.7
Embedded Trace Macrocell (ETM) Embedded Trace Buffer (ETB)
support real-time trace, ARM926EJ-S processor provides interface enable connection Embedded Trace Macrocell (ETM). ARM926ES-J Subsystem DM6467 also includes Embedded Trace Buffer (ETB). Econsists parts: Trace Port provides real-time trace capability ARM9. Triggering facilities provide trigger resources, which include address data comparators, counter, sequencers. DM6467 trace port pinned instead only connected Embedded Trace Buffer. buffer memory. enabled debug tools required read/interpret captured trace data.
2.3.8
Memory Mapping
memory shown Section 2.5, Memory Summary this document. access memories shown following sections.
2.3.8.1 Internal Memories access following internal memories: 32KB Internal interface, logically separated into 16KB pages allow simultaneous access given cycle there separate accesses code (I-TCM bus) data (D-TCM) different memory regions. Internal 2.3.8.2 External Memories access following external memories: DDR2 Synchronous DRAM Asynchronous EMIF Flash NAND Flash
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2.3.8.3 Memories access following memories: 2.3.8.4 ARM-DSP Integration DM6467 integration features follows: visibility from ARM's memory map, Section 2.5, Memory Summary, details Boot Modes Device Configurations section, Section 3.4.1, Boot, details control boot reset Device Configurations section, Section 3.4.2.4, Boot, details control isolation powerdown powerup Section Device Configurations, details Interrupts Section 6.8.1, Interrupts, Section 6.8.2, Interrupts, details
2.3.9
Peripherals
ARM9 access peripherals DM6467 device.
2.3.10 Controller (PLLC)
Subsystem includes Controller. Controller contains registers configuring DM6467's internal PLLs (PLL1 PLL2). Controller provides following configuration control: Bypass Mode multiplier parameters divider parameters power down Oscillator power down PLLs briefly described this document Clocking section. more detailed information PLLs Controller register descriptions, TMS320DM646x DMSoC Subsystem Reference Guide (literature number SPRUEP8).
2.3.11 Power Sleep Controller (PSC)
Subsystem includes Power Sleep Controller (PSC). Through register settings accessible ARM9, provides levels power savings: peripheral/module clock gating power domain shut-off. Brief details given Section 6.3, Power Supplies. more detailed information complete register descriptions PSC, TMS320DM646x DMSoC Subsystem Reference Guide (literature number SPRUEP8).
2.3.12 Interrupt Controller (AINTC)
Interrupt Controller (AINTC) accepts device interrupts maps them either ARM's (interrupt request) (fast interrupt request). Interrupt Controller briefly described this document Interrupts section. detailed information Interrupt Controller, TMS320DM646x DMSoC Subsystem Reference Guide (literature number SPRUEP8).
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2.3.13 System Module
Subsystem includes System module. System module consists registers configuring controlling variety system functions. details register descriptions System module, Section Device Configurations TMS320DM646x DMSoC Subsystem Reference Guide (literature number SPRUEP8).
2.3.14 Power Management
DM6467 several means managing power consumption. There extensive clock gating, which reduces power used global device clocks individual peripheral clocks. Clock management utilized reduce clock frequencies order reduce switching power. more details power management techniques, Section Device Configurations, Section Peripheral Electrical Specifications, TMS320DM646x DMSoC Subsystem Reference Guide (literature number SPRUEP8). DM6467 gives programmer full flexibility previously mentioned capabilities customize optimal power management strategy. Several typical power management scenarios described following sections.
Subsystem
Subsystem includes following features: C64x+ 32KB Program (L1P)/Cache 32KB) 32KB Data (L1D)/Cache 32KB) 128KB Unified Mapped RAM/Cache (L2) Little endian
2.4.1
C64x+ Description
C64x+ Central Processing Unit (CPU) consists eight functional units, register files, data paths shown Figure 2-1. general-purpose register files each contain 32-bit registers total registers. general-purpose registers used data data address pointers. data types supported include packed 8-bit data, packed 16-bit data, 32-bit data, 40-bit data, 64-bit data. Values larger than bits, such 40-bit-long 64-bit-long values stored register pairs, with LSBs data placed even register remaining MSBs next upper register (which always odd-numbered register). eight functional units (.M1, .L1, .D1, .S1, .M2, .L2, .D2, .S2) each capable executing instruction every clock cycle. functional units perform multiply operations. units perform general arithmetic, logical, branch functions. units primarily load data from memory register file store results from register file into memory. C64x+ extends performance C64x core through enhancements features. Each C64x+ unit perform following each clock cycle: multiply, multiply, multiplies, multiplies, multiplies with add/subtract capabilities, four multiplies, four multiplies with operations, four multiplies with add/subtract capabilities (including complex multiply). There also support Galois field multiplication 8-bit 32-bit data. Many communications algorithms such FFTs modems require complex multiplication. complex multiply (CMPY) instruction takes 16-bit inputs produces 32-bit real 32-bit imaginary output. There also complex multiplies with rounding capability that produces 32-bit packed output that contain 16-bit real 16-bit imaginary values. multiply instructions provide extended precision necessary audio other high-precision algorithms variety signed unsigned 32-bit data types.
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(Arithmetic Logic Unit) incorporates ability parallel add/subtract operations pair common inputs. Versions this instruction exist work 32-bit data pairs 16-bit data performing dual 16-bit subtracts parallel. There also saturated forms these instructions. C64x+ core enhances unit several ways. C64x core, dual 16-bit MIN2 MAX2 comparisons were only available units. C64x+ core they also available unit which increases performance algorithms that searching sorting. Finally, increase data packing unpacking throughput, unit allows sustained high performance quad 8-bit/16-bit dual 16-bit instructions. Unpack instructions prepare 8-bit data parallel 16-bit operations. Pack instructions return parallel results output precision including saturation support. Other features include: SPLOOP small instruction buffer that aids creation software pipelining loops where multiple iterations loop executed parallel. SPLOOP buffer reduces code size associated with software pipelining. Furthermore, loops SPLOOP buffer fully interruptible. Compact Instructions native instruction size C6000 devices bits. Many common instructions such MPY, AND, ADD, expressed bits C64x+ compiler restrict code certain registers register file. This compression performed code generation tools. Instruction Enhancement noted above, there instructions such 32-bit multiplications, complex multiplications, packing, sorting, manipulation, 32-bit Galois field multiplication. Exceptions Handling Intended programmer isolating bugs. C64x+ able detect respond exceptions, both from internally detected sources (such illegal op-codes) from system events (such watchdog time expiration). Privilege Defines user supervisor modes operation, allowing operating system give basic level protection sensitive resources. Local memory divided into multiple pages, each with read, write, execute permissions. Time-Stamp Counter Primarily targeted Real-Time Operating System (RTOS) robustness, free-running time-stamp counter implemented which sensitive system stalls. more details C64x+ enhancements over C64x architecture, following documents: TMS320C64x/C64x+ Instruction Reference Guide (literature number SPRU732) TMS320C64x Technical Overview (literature number SPRU395)
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src1
src2
even ST1b ST1a
long
long even src1 src2
Data path
dst2 dst1 src1 src2
LD1b LD1a
src1 src2
src2
src1
LD2a LD2b
src2 src1 dst2 dst1
src2 src1
Data path
even long ST2a ST2b
long even src2
src1
unit, dst2 MSB. unit, dst1 LSB. C64x unit, src2 bits; C64x+ unit, src2 bits. units, connects register files even connects even register files.
Figure 2-1. TMS320C64x+CPU (DSP Core) Data Paths
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Even register file (A0, A4.A30)
register file (A1, A5.A31)
register file (B1, B5.B31) Even register file (B0, B4.B30)
Control Register
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2.4.2
Memory Mapping
memory shown Section 2.5, Memory Summary. Configuration control registers DDR2, EMIFA, Internal supported ARM. access memories shown following sections.
2.4.2.1 Internal Memories access 32KB Internal D-TCM interface (i.e., data only). 2.4.2.2 External Memories access following External memories: DDR2 Synchronous DRAM Asynchronous EMIF Flash 2.4.2.3 Internal Memories access following memories: 2.4.2.4 C64x+ C64x+ core uses two-level cache-based architecture. Level Program memory/cache (L1P) consists memory space that configured mapped memory direct mapped cache. Level Data memory/cache (L1D) consists that configured mapped memory 2-way associated cache. Level memory/cache (L2) consists memory space that shared between program data space. memory configured mapped memory, cache, combination both. Table shows memory C64x+ cache registers device. Table 2-2. C64x+ Cache Registers
ADDRESS RANGE 0x0184 0000 0x0184 0020 0x0184 0024 0x0184 0040 0x0184 0044 0x0184 0048 0x0184 0FFC 0x0184 1000 0x0184 1004 0x0184 1FFC 0x0184 2000 0x0184 2004 0x0184 2008 0x0184 200C 0x0184 2010 0x0184 3FFF 0x0184 4000 0x0184 4004 0x0184 4010 0x0184 4014 0x0184 4018 0x0184 401C REGISTER ACRONYM L2CFG L1PCFG L1PCC L1DCFG L1DCC EDMAWEIGHT L2ALLOC0 L2ALLOC1 L2ALLOC2 L2ALLOC3 L2WBAR L2WWC L2WIBAR L2WIWC L2IBAR L2IWC DESCRIPTION Cache configuration register Size Cache configuration register Freeze Mode Cache configuration register Size Cache configuration register Freeze Mode Cache configuration register Reserved EDMA access control register Reserved allocation register allocation register allocation register allocation register Reserved writeback base address register writeback word count register writeback invalidate base address register writeback invalidate word count register invalidate base address register invalidate word count register
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Table 2-2. C64x+ Cache Registers (continued)
ADDRESS RANGE 0x0184 4020 0x0184 4024 0x0184 4030 0x0184 4034 0x0184 4038 0x0184 4040 0x0184 4044 0x0184 4048 0x0184 404C 0x0184 4050 0x0184 4FFF 0x0184 5000 0x0184 5004 0x0184 5008 0x0184 500C 0x0184 5027 0x0184 5028 0x0184 502C 0x0184 5039 0x0184 5040 0x0184 5044 0x0184 5048 0x0184 8000 0x0184 803C 0x0184 8040 0x0184 8044 0x0184 80FC 0x0184 8100 0x0184 8104 0x0184 8108 0x0184 8124 0x0184 8128 0x0184 812C 0x0184 8130 0x0184 813C 0x0184 8140 0x0184 81FC 0x0184 8200 0x0184 82FC 0x0184 8300 0x0184 83FC REGISTER ACRONYM L1PIBAR L1PIWC L1DWIBAR L1DWIWC L1DWBAR L1DWWC L1DIBAR L1DIWC L2WB L2WBINV L2INV L1PINV L1DWB L1DWBINV L1DINV MAR0 MAR15 MAR16 MAR17 MAR63 MAR64 MAR65 MAR66 MAR73 MAR74 MAR75 MAR76 MAR79 MAR80 MAR127 MAR128 MAR191 MAR192 MAR255 DESCRIPTION invalidate base address register invalidate word count register writeback invalidate base address register writeback invalidate word count register Reserved Block Writeback Block Writeback invalidate base address register invalidate word count register Reserved writeback register writeback invalidate register Global Invalidate without writeback Reserved Global Invalidate Reserved Global Writeback Global Writeback with Invalidate Global Invalidate without writeback Reserved (corresponds byte address 0x0000 0000 0x0FFF FFFF) Memory Attribute Registers (corresponds byte address 0x1000 0000 0x10FF FFFF) Reserved (corresponds byte address 0x1100 0000 0x3FFF FFFF) Reserved (corresponds byte address 0x4000 0000 0x40FF FFFF) Reserved (corresponds byte address 0x4100 0000 0x41FF FFFF) Memory Attribute Registers EMIFA (corresponds byte address 0x4200 0000 0x49FF FFFF) Reserved (corresponds byte address 0x4A00 0000 0x4BFF FFFF) Memory Attribute Registers VLYNQ (corresponds byte address 0x4C00 0000 0x4FFF FFFF) Reserved (corresponds byte address 0x5000 0000 0x7FFF FFFF) Memory Attribute Registers DDR2 (corresponds byte address 0x8000 0000 0xBFFF FFFF) Reserved (corresponds byte address 0xC000 0000 0xFFFF FFFF)
2.4.3
Peripherals
access/controllability following peripherals: HDVICP0/1 EDMA McASP0/1 Timers (Timer0 Timer1) that each configured 64-bit 32-bit timers
2.4.4
Interrupt Controller
Interrupt Controller accepts device interrupts appropriately maps them DSP's available interrupts. Interrupt Controller briefly described this document Interrupts section. more detailed Interrupt Controller, TMS320C64x+ Megamodule Reference Guide (literature number SPRU871).
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Memory Summary
Table shows memory address ranges device. Table depicts expanded Configuration Space (0x0180 0000 through 0x0FFF FFFF). device multiple on-chip memories associated with processors various subsystems. help simplify software development unified memory used where possible maintain consistent view device resources across masters.
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Table 2-3. Memory Summary
MASTER PERIPHERAL ACCESSIBILITY START ADDRESS 0x0000 0000 0x0000 4000 0x0000 8000 0x0001 0000 0x0001 4000 0x0001 8000 0x0002 0000 0x0010 0000 0x0040 0000 0x0050 0000 0x0060 0000 0x0070 0000 0x0080 0000 0x0081 0000 0x0081 8000 0x0083 8000 0x0090 0000 0x0093 0000 0x00A0 0000 0x00E0 0000 0x00E0 8000 0x00F0 0000 0x00F0 8000 0x0180 0000 0x01BC 0000 0x01BC 1000 0x01BC 1800 0x01BC 1900 0x01BC 1C00 0x01C0 0000 0x1000 0000 0x1001 0000 0x1001 4000 0x1001 8000 0x1002 0000 0x1100 0000 0x1140 0000 0x1150 0000 0x1160 0000 0x1170 0000 0x1180 0000 0x1181 0000 0x1181 8000 0x1183 8000 0x1190 0000 0x11E0 0000 0x11E0 8000 ADDRESS 0x0000 3FFF 0x0000 7FFF 0x0000 FFFF 0x0001 3FFF 0x0001 7FFF 0x0001 FFFF 0x000F FFFF 0x003F FFFF 0x004F FFFF 0x005F FFFF 0x006F FFFF 0x007F FFFF 0x0080 FFFF 0x0081 7FFF 0x0083 7FFF 0x008F FFFF 0x0092 FFFF 0x009F FFFF 0x00DF FFFF 0x00E0 7FFF 0x00EF FFFF 0x00F0 7FFF 0x017F FFFF 0x01BB FFFF 0x01BC 0FFF 0x01BC 17FF 0x01BC 18FF 0x01BC 1BFF 0x01BF FFFF 0x0FFF FFFF 0x1000 FFFF 0x1001 3FFF 0x1001 7FFF 0x1001 FFFF 0x10FF FFFF 0x113F FFFF 0x114F FFFF 0x115F FFFF 0x116F FFFF 0x117F FFFF 0x1180 FFFF 0x1181 7FFF 0x1183 7FFF 0x118F FFFF 0x11DF FFFF 0x11E0 7FFF 0x11EF FFFF SIZE (Bytes) 896K 128K 800K 192K 832K Reserved 992K 9184K 3840K 249K 228M 16256K 128K 800K 992K RAM/Cache Reserved RAM/Cache Reserved RAM/Cache Reserved Reserved RAM/Cache Reserved Hole (MPPA Disable) Reserved RAM/Cache Reserved RAM/Cache Reserved Reserved Reserved Reserved RAM0 (Data) RAM1 (Data) (Data) Peripherals Peripherals Peripherals Reserved RAM0 (Data) RAM1 (Data) (Data) Memory Registers Space IceCrusher Reserved RAM/Cache Reserved RAM/Cache Reserved Reserved Reserved Hole (MPPA Disable) Reserved RAM/Cache Reserved Reserved RAM0 (Instruction) RAM1 (Instruction) (Instruction) RAM0 (Data) RAM1 (Data) (Data) Reserved Reserved C64x+ EDMA/ PERIPHERAL Video TSIF VDCE EMAC Port (0/1) VLYNQ
These peripherals have their engine master port interface DMSoC system EDMA data transfers. symbol indicates that peripheral valid connection through device switch fabric memory region identified EDMA access column. MPPA should used disable hole. more information MPPA, TMS320C64x+ Megamodule Reference Guide (SPRU871). HPI's, PCI's, VLYNQ's access configuration peripherals limited, Table 2-4, Configuration Memory Summary details. Device Overview Submit Documentation Feedback
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Table 2-3. Memory Summary (continued)
MASTER PERIPHERAL ACCESSIBILITY START ADDRESS 0x11F0 0000 0x11F0 8000 0x1200 0000 0x2000 0000 0x2000 8000 0x2001 0000 0x2001 8000 0x2010 0000 0x3000 0000 0x4000 0000 0x4040 0000 0x4044 0000 0x4048 0000 0x404C 0000 0x4050 0000 0x4060 0000 0x4064 0000 0x4068 0000 0x406C 0000 0x4070 0000 0x4200 0000 0x4400 0000 0x4600 0000 0x4800 0000 0x4A00 0000 0x4C00 0000 0x5000 0000 0x8000 0000 0x9000 0000 0xA000 0000 0xC000 0000 ADDRESS 0x11F0 7FFF 0x11FF FFFF 0x1FFF FFFF 0x2000 7FFF 0x2000 FFFF 0x2001 7FFF 0x200F FFFF 0x2FFF FFFF 0x3FFF FFFF 0x403F FFFF 0x4043 FFFF 0x4047 FFFF 0x404B FFFF 0x404F FFFF 0x405F FFFF 0x4063 FFFF 0x4067 FFFF 0x406B FFFF 0x406F FFFF 0x41FF FFFF 0x43FF FFFF 0x45FF FFFF 0x47FF FFFF 0x49FF FFFF 0x4BFF FFFF 0x4FFF FFFF 0x7FFF FFFF 0x8FFF FFFF 0x9FFF FFFF 0xBFFF FFFF 0xFFFF FFFF SIZE (Bytes) 992K 224M 928K 255M 256M 256K 256K 256K 256K 256K 256K 256K 256K 768M 256M 256M 512M EMIFA Data (CS2) EMIFA Data (CS3)
RAM/Cache Reserved
C64x+ RAM/Cache Reserved
EDMA/ PERIPHERAL RAM/Cache Reserved
Video TSIF VDCE EMAC Port (0/1)
VLYNQ
DDR2 Control Registers EMIFA Control Registers VLYNQ Control Registers Reserved
DDR2 Control Registers EMIFA Registers VLYNQ Registers Reserved
DDR2 Control Registers EMIFA Registers VLYNQ Registers Reserved
Data Reserved
Data Reserved
Data Reserved
Reserved
Reserved
Reserved
EMIFA Data (CS2) EMIFA Data (CS3)
EMIFA Data (CS2) EMIFA Data (CS3) EMIFA Data (CS4) EMIFA Data (CS5) Reserved
EMIFA Data (CS4) EMIFA Data (CS5) Reserved
EMIFA Data (CS4) EMIFA Data (CS5) Reserved
VLYNQ (Remote Data) VLYNQ (Remote Data) VLYNQ (Remote Data) Reserved DDR2 Memory Controller Reserved Reserved Reserved Reserved DDR2 Memory Controller Reserved Reserved Reserved Reserved DDR2 Memory Controller Reserved Reserved Reserved
EMIFA functionally supported DM6467, therefore, pinned out.
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Table 2-4. Configuration Memory Summary
START ADDRESS 0x0180 0000 0x0181 0000 0x0181 1000 0x0181 2000 0x0182 0000 0x0183 0000 0x0184 0000 0x0185 0000 0x01BC 0000 0x01BC 0100 0x01BC 0200 0x01BC 1000 0x01BC 1800 0x01BC 1900 0x01C0 0000 0x01C1 0000 0x01C1 0400 0x01C1 0800 0x01C1 0C00 0x01C1 1000 0x01C1 2000 0x01C1 2400 0x01C1 2800 0x01C1 3000 0x01C1 3400 0x01C1 3800 0x01C1 A000 0x01C1 A800 0x01C2 0000 0x01C2 0400 0x01C2 0800 0x01C2 0C00 0x01C2 1000 0x01C2 1400 0x01C2 1800 0x01C2 1C00 0x01C2 2000 0x01C2 2400 0x01C2 2800 0x01C2 6000 0x01C2 6400 0x01C2 6800 0x01C4 0000 0x01C4 0800 0x01C4 0C00 0x01C4 1000 0x01C4 2000 0x01C4 8000 0x01C4 8400 ADDRESS 0x0180 FFFF 0x0181 0FFF 0x0181 1FFF 0x0181 2FFF 0x0182 FFFF 0x0183 FFFF 0x0184 FFFF 0x01BB FFFF 0x01BC 00FF 0x01BC 01FF 0x01BC 0FFF 0x01BC 17FF 0x01BC 18FF 0x01BF FFFF 0x01C0 FFFF 0x01C1 03FF 0x01C1 07FF 0x01C1 0BFF 0x01C1 0FFF 0x01C1 1FFF 0x01C1 23FF 0x01C1 27FF 0x01C1 2FFF 0x01C1 33FF 0x01C1 37FF 0x01C1 9FFF 0x01C1 A7FF 0x01C1 FFFF 0x01C2 03FF 0x01C2 07FF 0x01C2 0BFF 0x01C2 0FFF 0x01C2 13FF 0x01C2 17FF 0x01C2 1BFF 0x01C2 1FFF 0x01C2 23FF 0x01C2 27FF 0x01C2 5FFF 0x01C2 63FF 0x01C2 67FF 0x01C3 FFFF 0x01C4 07FF 0x01C4 0BFF 0x01C4 0FFF 0x01C4 1FFF 0x01C4 7FFF 0x01C4 83FF 0x01C6 3FFF SIZE (Bytes) 3520K 3.5K 255744 102K 111K Registers Crusher Reserved EDMA EDMA EDMA EDMA EDMA Reserved Video Port Reserved VDCE TSIF0 TSIF1 Reserved Control Registers Reserved UART0 UART1 UART2 Reserved Timer0 Timer1 Timer2 (Watchdog) PWM0 PWM1 Reserved CRGEN0 CRGEN1 Reserved System Module Controller Controller Power Sleep Controller Reserved Interrupt Controller Reserved Reserved System Module Controller Controller Power Sleep Controller Reserved Reserved Reserved Reserved Timer0 Timer1 Timer2 (Watchdog) Reserved Reserved Reserved Reserved EDMA EDMA EDMA EDMA EDMA Reserved Memory Reserved Reserved ARM/EDMA C64x+ C64x+ Interrupt Controller C64x+ Powerdown Controller C64x+ Security C64x+ Revision C64x+ Reserved C64x+ Memory System Reserved MASTER PERIPHERAL ACCESSIBILITY VLYNQ
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Table 2-4. Configuration Memory Summary (continued)
START ADDRESS 0x01C6 4000 0x01C6 6000 0x01C6 6800 0x01C6 7000 0x01C6 7800 0x01C6 8000 0x01C8 0000 0x01C8 1000 0x01C8 2000 0x01C8 4000 0x01C8 4800 0x01D0 1000 0x01D0 1400 0x01D0 1800 0x01D0 1C00 0x01D0 2000 0x01E0 0000 0x0200 0000 0x0220 0000 0x0240 0000 ADDRESS 0x01C6 5FFF 0x01C6 67FF 0x01C6 6FFF 0x01C6 77FF 0x01C6 7FFF 0x01C7 FFFF 0x01C8 0FFF 0x01C8 1FFF 0x01C8 3FFF 0x01C8 47FF 0x01D0 0FFF 0x01D0 13FF 0x01D0 17FF 0x01D0 1BFF 0x01D0 1FFF 0x01DF FFFF 0x01FF FFFF 0x021F FFFF 0x023F FFFF 0x0FFF FFFF SIZE (Bytes) 498K 1016K 220M ARM/EDMA USB2.0 Registers GPIO Reserved EMAC Control Registers EMAC Control Module Registers EMAC Control Module MDIO Control Registers Reserved McASP0 Registers McASP0 Data Port McASP1 Registers McASP1 Data Port Reserved Reserved Reserved Reserved Reserved Reserved McASP0 Registers McASP0 Data Port McASP1 Registers McASP1 Data Port Reserved Reserved Reserved Reserved Reserved Reserved Reserved C64x+ MASTER PERIPHERAL ACCESSIBILITY VLYNQ
Assignments
Extensive multiplexing used accommodate largest number peripheral functions smallest possible package. multiplexing controlled using combination hardware configuration device reset software programmable register settings. more information muxing, Section 3.7, Multiplexed Configurations, this document.
2.6.1
(Bottom View)
Figure through Figure show bottom view package assignments quadrants
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GP[4]/ STC_CLKIN
VP_DOUT1/ BTMODE1
VP_DOUT6/ DSPBOOT
VP_DOUT5/ PCIEN
VP_DOUT14/ TS1_PSTIN
VP_DOUT9/ TS1_ENAO
AHCLKR0
GP[3]/ AUDIO_CLK0
TOUT1U
VP_DOUT0/ BTMODE0
VP_DOUT3/ BTMODE3
VP_DOUT7
VP_DOUT15/ TS1_DIN
ACLKX0
ACLKR0
AMUTEIN0
GP[2]/ AUDIO_CLK1
TOUT1L
TINP0U
VP_DOUT4/ CS2BW
VP_DOUT12/ TS1_WAITO
AHCLKX0
AMUTE0
AFSR0
AFSX0
TOUT2
TINP1L
TINP0L
VP_DOUT2/ BTMODE2
ACLKX1
AHCLKX1
AXR0[3]
AXR0[2]
GP[0]
RESET
TOUT0U
TOUT0L
SPI_CLK
AXR1[0]
AXR0[0]
AXR0[1]
GP[1]
DVDD33
DVDD33
VLYNQ_ CLOCK
VLYNQ_ SCRUN
SPI_CS1
DVDD33
CVDD
VLYNQ_TXD1
VLYNQ_TXD2
VLYNQ_TXD3
SPI_CS0
SPI_EN
DVDD33
CVDD
MTCLK
VLYNQ_RXD2
VLYNQ_RXD3
VLYNQ_TXD0
SPI_SOMI
DVDD33
CVDD
MTXD7
GMTCLK
VLYNQ_RXD1
VLYNQ_RXD0
SPI_SIMO
CVDD
CVDD
MTXD3
MTXD4
MTXD5
MTXD6
Figure 2-2. [Section
Device Overview
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VP_CLKIN3/ TS1_CLKO
VP_CLKO3/ TS0_CLKO
TS1_CLKIN
UCTS0/ USD0
VP_CLKIN0
VP_DIN4/ TS0_DOUT4/ TS1_WAITO VP_DIN5/ TS0_DOUT5/ TS1_EN_WAITO
VP_DIN0/ TS0_DOUT0
VP_DIN8/ TS0_DIN0
VP_DOUT8/ TS1_WAITIN
VP_DOUT11/ TS1_DOUT
UDSR0/ TS0_PSTO/ GP[37]
URXD0/ TS1_DIN
VP_DIN1/ TS0_DOUT1
VP_DIN9/ TS0_DIN1
VP_CLKO2
VP_DOUT10/ TS1_PSTO
UDCD0/ TS0_WAITIN/ GP[38]
DVDD33
URTS0/ UIRTX0/ TS1_EN_WAITO
VP_DIN6/ TS0_DOUT6/ TS1_PSTIN
VP_DIN2/ TS0_DOUT2
VP_DIN10/ TS0_DIN2
VP_DOUT13/ TS1_EN_WAITO
VP_CLKIN2
URIN0/ GP[8]/ TS1_WAITIN
UDTR0/ TS0_ENAO/ GP[36]
UTXD0/ URCTX0/ TS1_PSTIN
VP_DIN7/ TS0_DOUT7/ TS1_DIN
VP_DIN3/ TS0_DOUT3
VP_DIN11/ TS0_DIN3
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
Figure 2-3. [Section
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VP_DIN15_ VP_VSYNC/ TS0_DIN7 URTS2/ UIRTX2/ TS0_PSTIN/ GP[41] URXD2/ CRG1_VCXI/ GP[39]/ CRG0_VCXI UCTS2/USD2/ CRG0_VCXI/ GP[42]/ TS1_PSTO
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VP_DIN12/ TS0_DIN4
TS0_CLKIN
VP_DIN13_ FIELD/ TS0_DIN5
VP_CLKIN1
UTXD1/ URCTX1/ TS0_DOUT7/ GP[24] UTXD2/URCTX2/ CRG1_PO/ GP[40]/ CRG0_PO
DDR_D[23]
VP_DIN14_ VP_HSYNC/ TS0_DIN6
URTS1/ UIRTX1/ TS0_WAITO/ GP[25] URXD1/ TS0_DIN7/ GP[23]
DVDDR2
DDR_D[28]
DDR_D[21]
DDR_D[20]
UCTS1/USD1/ TS0_EN_WAITO/ GP[26]
DDR_D[31]
DDR_D[29]
DDR_D[22]
DDR_DQM[2]
PWM0/ CRG0_PO/ TS1_ENAO
PWM1/ TS1_DOUT
DDR_D[30]
DVDDR2
DDR_DQS[2]
DVDD33
DDR_DQM[3]
DDR_DQS[3]
DDR_DQS[2]
DDR_D[19]
DVDDR2
DDR_DQS[3]
DDR_D[27]
DDR_D[16]
DDR_D[18]
DVDDR2
DVDDR2
DDR_D[24]
DDR_D[26]
DDR_D[17]
DDR_A[10]
DVDDR2
DVDDR2
DDR_DQGATE2
DDR_D[25]
DDR_DQGATE3
DDR_A[3]
DDR_A[1]
DDR_BA[2]
DDR_A[12]
DVDDR2
DDR_VREF
DDR_BA[0]
DDR_A[7]
DDR_A[5]
DDR_A[9]
DDR_A[14]
Figure 2-4. [Section
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TMS320DM6467 Digital Media System-on-Chip
MTXD1
DVDD33
MTXD2
MTXD0
MTXEN
MCRS
MCOL
MRCLK
MRXD7
MRXD6
MRXD5
DVDD33
DVDD33
CVDD
MRXD4
MRXD3
MRXD2
MRXDV
DVDD33
CVDD
CVDD
RFTCLK
MRXD1
MRXER
MDIO
DVDD33
CVDD
CVDD
MDCLK
MRXD0
PCI_AD0/ HD0/ EM_D0
PCI_AD2/ HD2/ EM_D2 PCI_CBE0/ ATA_CS0/ GP[33]/ EM_A[18] PCI_AD13/ HD13/ EM_D13
PCI_AD4/ HD4/ EM_D4
DVDD33
CVDD
PCI_AD1/ HD1/ EM_D1
PCI_AD3/ HD3/ EM_D3
PCI_AD6/ HD6/ EM_D6
PCI_AD9/ HD9/ EM_D9
DVDD33
PCI_AD5/ HD5/ EM_D5
PCI_AD7/ HD7/ EM_D7
PCI_AD11/ HD11/ EM_D11
PCI_AD15/ HD15/ EM_D15
PCI_TRDY/ HHWIL/ EM_A[16]/(ALE)
PCI_AD18/ DD2/ HD18/ EM_A[2] PCI_AD20/ DD4/ HD20/ EM_A[4] PCI_AD22/ DD6/ HD22/ EM_A[6]
PCI_IDSEL/ HDDIR/ EM_R/W PCI_AD24/ DD8/ HD24/ EM_A[8] PCI_AD26/ DD10/ HD26/ EM_A[10] PCI_AD29/ DD13/ HD29/ EM_A[13] PCI_AD31/ DD15/ HD31/ EM_A[15]
PCI_AD8/ HD8/ EM_D8
PCI_AD10/ HD10/ EM_D10 PCI_CBE1/ ATA_CS1/ GP[32]/ EM_A[19] PCI_SERR/ HDS1/ EM_OE
PCI_AD12/ HD12/ EM_D12
PCI_PAR/ HAS/ EM_DQM0
PCI_STOP/ HCNTL0/ EM_WE PCI_AD21/ DD5/ HD21/ EM_A[5] PCI_AD23/ DD7/ HD23/ EM_A[7] PCI_CBE3/ HR/W/ EM_CS3
PCI_FRAME/ HINT/ EM_BA[0] PCI_AD16/ DD0/ HD16/ EM_A[0] PCI_AD25/ DD9/ HD25/ EM_A[9] PCI_AD27/ DD11/ HD27/ EM_A[11]
PCI_AD14/ HD14/ EM_D14
PCI_PERR/ HCS/ EM_DQM1
PCI_CBE2/ HDS2/ EM_CS2 PCI_AD17/ DD1/ HD17/ EM_A[1] PCI_AD19/ DD3/ HD19/ EM_A[3]
PCI_DEVSEL/ HCNTL1/ EM_BA[1]
DVDD33
RSV1
RSV2
PCI_IRDY/ HRDY/ EM_A[17]/(CLE)
Figure 2-5. [Section
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TMS320DM6467 Digital Media System-on-Chip
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CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
CVDD
RSV7
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DVDD33
DA0/ GP[17]/ EM_A[20] PCI_AD28/ DD12/ HD28/ EM_A[12] PCI_AD30/ DD14/ HD30/ EM_A[14] PCI_REQ/ DMARQ/ GP[11]/ EM_CS5 DA1/ GP[16]/ EM_A[21]
DIOR/ GP[19]/ EM_WAIT5/ (RDY/BSY5) PCI_GNT/ DMACK/ GP[12]/ EM_CS4 PCI_RST/ DA2/ GP[13]/ EM_A[22] INTRQ/ GP[18]/
GP[6]
TRST
DEV_DVSS
DEV_CVDD
AUX_CVDD
IORDY/ GP[21]/ EM_WAIT3/ (RDY/BSY3) PCI_INTA/ EM_WAIT2/ (RDY0/BSY2)
RSV5
DEV_DVDD18
AUX_DVDD18
RTCK
CLKOUT0
PLL1VSS
DEV_VSS
AUX_DVSS
GP[5]
EMU1
PLL1VDD18
DEV_MXI/ DEV_CLKIN
PLL2VDD18
PCI_CLK/ GP[10]
DIOW/ GP[20]/ EM_WAIT4/ (RDY/BSY4)
GP[7]
EMU0
DEV_MXO
PLL2VSS
Figure 2-6. [Section
Device Overview
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TMS320DM6467 Digital Media System-on-Chip
DDR_ZN
DDR_CKE
DDR_BA[1]
DDR_A[6]
DDR_CLK
DDR_ZP
DDR_WE
DDR_CAS
DDR_A[2]
DDR_CLK
DVDDR2
DDR_RAS
DDR_ODT0
DVDDR2
DDR_A[11]
DVDDR2
DDR_DQGATE0
DDR_CS
DDR_DQGATE1
DDR_A[4]
DDR_A[8]
DVDDR2
DDR_D[7]
DDR_A[13]
DDR_D[15]
DDR_A[0]
DVDDR2
DVDDR2
DDR_D[4]
DDR_D[6]
DDR_D[13]
DDR_D[14]
RSV6
USB_VDDA3P3
DDR_DQM[0]
DDR_D[5]
DDR_DQM[1]
DDR_D[12]
USB_ VDDA1P2LDO
USB_VDD1P8
DDR_DQS[0]
DVDDR2
DDR_D[11]
USB_R1
DDR_D[1]
DDR_DQS[0]
DDR_DQS[1]
DDR_DQS[1]
AUX_VSS
USB_VSSREF
DDR_D[2]
DDR_D[0]
DDR_D[10]
DDR_D[8]
AUX_MXI/ AUX_CLKIN
USB_ DRVVBUS/ GP[22]
DVDDR2
DDR_D[3]
DDR_D[9]
AUX_MXO
USB_DP
USB_DN
RSV3
RSV4
Figure 2-7. [Section
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TMS320DM6467 Digital Media System-on-Chip
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Terminal Functions
terminal functions tables (Table through Table 2-32) identify external signal names, associated (ball) numbers along with mechanical package designator, type, whether internal pullup pulldown resistors, functional description. more detailed information device configuration, peripheral selection, multiplexed/shared pin, Device Configurations section this data manual.
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Table 2-5. BOOT Terminal Functions
SIGNAL NAME TYPE OTHER BOOT Boot Mode configuration bits. These pins multiplexed between boot mode Video Port Interface (VPIF). reset, boot mode inputs BTMODE[3:0] sampled determine boot configuration. below boot modes these inputs. more details types boot modes, Section 3.4.1, Boot Modes. After reset, these pins Video port data outputs through (VP_DOUT[3:0]). BTMODE[3:0] 0000 0001 VP_DOUT0/ BTMODE0 I/O/Z DVDD33 0010 Reserved Boot (16-Bit width) PCIEN Boot without auto-initialization PCIEN Boot (32-Bit width) PCIEN Boot with auto-initialization PCIEN EMIFA Direct Boot (ROM/NOR) (PCIEN [error PCIEN defaults UART0] Reserved Boot NAND Flash Boot (PCIEN [error PCIEN UART0 Boot Reserved VLYNQ Boot Reserved Reserved Boot Reserved Boot Mode Emulation Boot (PCIEN DESCRIPTION
0011 0100 VP_DOUT1/ BTMODE1 I/O/Z DVDD33 0101 0110 0111 1000 VP_DOUT2/ BTMODE2 I/O/Z DVDD33 1001 1010 1011 1100 1101 VP_DOUT3/ BTMODE3 I/O/Z DVDD33 1110 1111
DEVICE CONTROL EMIFA space data width. This multiplexed between EMIFA control VPIF. reset, input state sampled EMIFA data width (boot) chip select region. 8-bit-wide EMIFA data bus, CS2BW 16-bit-wide EMIFA data bus, CS2BW After reset, this video port data output (VP_DOUT4). Enable. This multiplexed between Control VPIF. reset, input state sampled enable/disable interface multiplexing. Note: When boot mode used, proper device operation reset PCIEN must "0". function disabled; EMIFA function enabled function enabled After reset, this video port data output (VP_DOUT5).DSP boot source bit. This multiplexed between boot VPIF. reset, input state sampled boot source DSPBOOT. VP_DOUT6/ DSPBOOT I/O/Z DVDD33 booted when DSPBOOT boots from EMIFA when DSPBOOT (and boot mode selected). After reset, this video port data output (VP_DOUT6). VP_DOUT7 I/O/Z DVDD33 reset, proper device operation, this must pulled down external resistor. After reset, this video port data output (VP_DOUT7).
VP_DOUT4/ CS2BW
I/O/Z
DVDD33
VP_DOUT5/ PCIEN
I/O/Z
DVDD33
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.8.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal Device Overview
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Table 2-6. Oscillator/PLL Terminal Functions
SIGNAL NAME DEV_MXI/ DEV_CLKIN DEV_MXO DEV_DVDD18 DEV_DVSS DEV_CVDD DEV_VSS TYPE OTHER OSCILLATOR, DEV_DVDD18 DEV_DVDD18
DESCRIPTION
Crystal input DEV_MXI oscillator (system oscillator, typically MHz). internal oscillator bypassed, this 1.8-V external oscillator clock input. Crystal output oscillator. internal oscillator bypassed, DEV_MXO should left Connect. 1.8-V power supply oscillator. internal oscillator bypassed, DEV_DVDD18 should still connected 1.8-V power supply. ground oscillator. internal oscillator bypassed, DEV_DVSS should connected ground VSS. 1.2-V power supply oscillator. internal oscillator bypassed, DEV_CVDD should connected 1.2-V power supply (CVDD). Ground oscillator. Connect crystal load capacitors. connect board ground (VSS). internal oscillator bypassed, DEV_VSS should still connected ground VSS. Crystal input Auxiliary (AUX) oscillator (24/48 USB, UART2/1/0 McASP1/0). internal oscillator bypassed, this 1.8-V external oscillator clock input. When peripheral used, AUX_MXI should left Connect. Crystal output oscillator. internal oscillator bypassed, AUX_MXO should left Connect. When peripheral used, AUX_MXO should left Connect. 1.8-V power supply oscillator. internal oscillator bypassed, AUX_DVDD18 should still connected 1.8-V power supply. When peripheral used, AUX_DVDD18 should connected 1.8-V power supply. ground oscillator. internal oscillator bypassed, AUX_DVSS should connected ground (VSS). When peripheral used, AUX_DVSS should connected ground (VSS). 1.2-V power supply oscillator. internal oscillator bypassed, AUX_CVDD should connected 1.2-V power supply (CVDD). When peripheral used, AUX_CVDD should connected 1.2-V power supply (CVDD). Ground oscillator. Connect crystal load capacitors. connect board ground (VSS). internal oscillator bypassed, AUX_VSS should still connected ground (VSS). When peripheral used, AUX_VSS should connected ground (VSS). 1.8-V power supply PLLs. Ground PLLs.
AUX_MXI/ AUX_CLKIN
AUX_DVDD18
AUX_MXO
AUX_DVDD18
AUX_DVDD18
AUX_DVSS
AUX_CVDD
AUX_VSS PLL1VDD18 PLL2VDD18 PLL1VSS PLL2VSS
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal more information, Recommended Operating Conditions table
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Table 2-7. Clock Generator Terminal Functions
SIGNAL NAME CLKOUT0 GP[3]/ AUDIO_CLK0 GP[2]/ AUDIO_CLK1 GP[4]/ STC_CLKIN TYPE OTHER CLOCK GENERATOR I/O/Z I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 Configurable output clock. This multiplexed between GPIO Audio Clock Selector. audio clock selector, this configurable AUDIO_CLK0 output. This multiplexed between GPIO Audio Clock Selector. audio clock selector, this configurable AUDIO_CLK1 output. This multiplexed between GPIO TSIF Clock Selector. TSIF, this STC_CLKIN which used external clock source TSIF counters TSIF output clock. DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.8.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
Table 2-8. RESET JTAG Terminal Functions
SIGNAL NAME TYPE OTHER RESET RESET DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 Device reset. Power-on reset. JTAG RTCK TRST EMU1 EMU0 I/O/Z I/O/Z JTAG test-port mode select input. proper device operation, oppose this pin. JTAG test-port data output. JTAG test-port data input. JTAG test-port clock input. JTAG test-port return clock output. JTAG test-port reset. IEEE 1149.1 JTAG compatibility, IEEE 1149.1 JTAG compatibility statement portion this data manual. Emulation Emulation DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.8.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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Table 2-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions
SIGNAL NAME TYPE OTHER EMIFA BOOT CONFIGURATION EMIFA space data width. This multiplexed between EMIFA control VPIF. reset, input state sampled EMIFA data width (boot) chip select region. 8-bit-wide EMIFA data bus, CS2BW 16-bit-wide EMIFA data bus, CS2BW After reset, this video port data output (VP_DOUT4). boot source bit. This multiplexed between boot VPIF. reset, input state sampled boot source DSPBOOT. VP_DOUT6/ DSPBOOT I/O/Z DVDD33 booted when DSPBOOT boots from EMIFA when DSPBOOT=1. After reset, this video port data output (VP_DOUT6). EMIFA FUNCTIONAL PINS: ASYNC PCI_CBE2/ HDS2/ EM_CS2 PCI_CBE3/ HR/W EM_CS3 PCI_GNT/ DACK/ GP[12]/EM_CS4 PCI_REQ/ DMARQ/ GP[11]/ EM_CS5 PCI_IDSEL/ HDDIR/ EM_R/W PCI_SERR/ HDS1/ EM_OE PCI_STOP/ HCNTL0/ EM_WE PCI_PERR/ HCS/ EM_DQM1 PCI_PAR/ HAS/ EM_DQM0 PCI_INTA/ EM_WAIT2/ (RDY2/BSY2) IORDY/ GP[21]/EM_WAIT3/ (RDY3/BSY3) DIOW/ GP[20]/EM_WAIT4/ (RDY4/BSY4) I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between PCI, HPI, EMIFA. EMIFA mode, this Chip Select output EM_CS2 (O/Z). This chip select used EMIFA boot modes. Asynchronous memories (i.e., Flash) NAND flash. This multiplexed between PCI, HPI, EMIFA. EMIFA mode, this Chip Select output EM_CS3 (O/Z). Asynchronous memories (i.e., Flash). This multiplexed between PCI, ATA, GPIO, EMIFA. EMIFA mode, this Chip Select output EM_CS4 (O/Z). Asynchronous memories (i.e., Flash). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, GPIO, EMIFA. EMIFA mode, this Chip Select output EM_CS5 (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, EMIFA. EMIFA mode, this read/write output EM_R/W (O/Z). This multiplexed between PCI, HPI, EMIFA. EMIFA mode, this output enable output EM_OE (O/Z). This multiplexed between PCI, HPI, EMIFA. EMIFA mode, this write enable output EM_WE (O/Z). DESCRIPTION
VP_DOUT4/ CS2BW
I/O/Z
DVDD33
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
These pins multiplexed between PCI, HPI, EMIFA. EMIFA mode, these pins EM_DQM[1:0] byte enables (O/Z).
I/O/Z
I/O/Z
This multiplexed between EMIFA. EMIFA mode, this wait state extension input EM_WAIT2 (I). When used EMIFA (NAND), this ready/busy input (RDY2/BSY2). This multiplexed between ATA, GPIO, EMIFA. EMIFA mode, this wait state extension input EM_WAIT3 (I). When used EMIFA (NAND), this ready/busy input (RDY3/BSY3). This multiplexed between ATA, GPIO, EMIFA. EMIFA mode, this wait state extension input EM_WAIT4 (I). When used EMIFA (NAND), this ready/busy input (RDY4/BSY4).
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.8.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal Device Overview Submit Documentation Feedback
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Table 2-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued)
SIGNAL NAME DIOR/ GP[19]/EM_WAIT5/ (RDY5/BSY5) PCI_FRAME/ HINT/ EM_BA[0] TYPE OTHER DVDD33 DESCRIPTION This multiplexed between ATA, GPIO, EMIFA. EMIFA, this wait state extension input EM_WAIT5 (I). When used EMIFA (NAND), this ready/busy input (RDY5/BSY5). This multiplexed between PCI, HPI, EMIFA. EMIFA, this Bank Address output EM_BA[0] (O/Z). When connected 16-bit asynchronous memory, this same function EMIF address (EM_A[22]). When connected 8-bit asynchronous memory, this lowest order byte address. This multiplexed between PCI, HPI, EMIFA. EMIFA, this Bank Address output EM_BA[1] (O/Z). When connected asynchronous memory this lowest order 16-bit word address. When connected 8-bit asynchronous memory, this second address. This multiplexed between ATA, GPIO, EMIFA. EMIFA mode, this reserved. This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, GPIO, EMIFA. EMIFA mode, this address output EM_A[22] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between ATA, GPIO, EMIFA. EMIFA mode, this address output EM_A[21] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between ATA, GPIO, EMIFA. EMIFA mode, this address output EM_A[20] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, GPIO, EMIFA. EMIFA mode, this address output EM_A[19] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, GPIO, EMIFA. EMIFA mode, this address output EM_A[18] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, HPI, EMIFA. EMIFA mode, this address output EM_A[17] (O/Z). When used EMIFA (NAND), this Command Latch Enable output (CLE). This multiplexed between PCI, HPI, EMIFA. EMIFA, this address output EM_A[16] (O/Z). When used EMIFA (NAND), this Address Latch Enable output (ALE). This multiplexed between PCI, ATA, HPI, EMIFA. EMIFA, this address output EM_A[15] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, HPI, EMIFA. EMIFA, this address output EM_A[14] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, HPI, EMIFA. EMIFA, this address output EM_A[13] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, HPI, EMIFA. EMIFA, this address output EM_A[12] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, HPI, EMIFA. EMIFA, this address output EM_A[11] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, HPI, EMIFA. EMIFA, this address output EM_A[10] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode).
I/O/Z
I/O/Z
DVDD33
PCI_DEVSEL/ HCNTL1/ EM_BA[1]
I/O/Z
DVDD33
INTRQ/ GP[18]/RSV PCI_RST/ DA2/ GP[13]/EM_A[22] DA1/ GP[16]/EM_A[21] DA0/ GP[17]/EM_A[20] PCI_CBE1/ ATA_CS1/ GP[32]/EM_A[19] PCI_CBE0/ ATA_CS0/ GP[33]/EM_A[18] PCI_IRDY/ HRDY/ EM_A[17]/(CLE) PCI_TRDY/ HHWIL/ EM_A[16]/(ALE) PCI_AD31/ DD15/ HD31/EM_A[15] PCI_AD30/ DD14/ HD30/EM_A[14] PCI_AD29/ DD13/ HD29/EM_A[13] PCI_AD28/ DD12/ HD28/EM_A[12] PCI_AD27/ DD11/ HD27/EM_A[11] PCI_AD26/ DD10/ HD26/EM_A[10]
I/O/Z
DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
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Table 2-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued)
SIGNAL NAME PCI_AD25/ DD9/ HD25/EM_A[9] PCI_AD24/ DD8/ HD24/EM_A[8] PCI_AD23/ DD7/ HD23/EM_A[7] PCI_AD22/ DD6/ HD22/EM_A[6] PCI_AD21/ DD5/ HD21/EM_A[5] PCI_AD20/ DD4/ HD20/EM_A[4] PCI_AD19/ DD3/ HD19/EM_A[3] PCI_AD18/ DD2/ HD18/EM_A[2] PCI_AD17/ DD1/ HD17/EM_A[1] PCI_AD16/ DD0/ HD16/EM_A[0] TYPE OTHER DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DESCRIPTION This multiplexed between PCI, ATA, HPI, EMIFA. EMIFA, this address output EM_A[9] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, HPI, EMIFA. EMIFA, this address output EM_A[8] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, HPI, EMIFA. EMIFA, this address output EM_A[7] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, HPI, EMIFA. EMIFA, this address output EM_A[6] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, HPI, EMIFA. EMIFA, this address output EM_A[5] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, HPI, EMIFA. EMIFA, this address output EM_A[4] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, HPI, EMIFA. EMIFA, this address output EM_A[3] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, HPI, EMIFA. EMIFA, this address output EM_A[2] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, HPI, EMIFA. EMIFA, this address output EM_A[1] (O/Z). This signal available when enabled (i.e., EMIF NAND Flash mode). This multiplexed between PCI, ATA, HPI, EMIFA. EMIFA, this address output EM_A[0] (O/Z), which least significant 32-bit word address. When connected 16-bit asynchronous memory, this second address. 8-bit asynchronous memory, this third address.
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
DVDD33
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TMS320DM6467 Digital Media System-on-Chip
Table 2-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued)
SIGNAL NAME PCI_AD15/ HD15/EM_D15 PCI_AD14/ HD14 /EM_D14 PCI_AD13/ HD13/EM_D13 PCI_AD12/ HD12/EM_D12 PCI_AD11/ HD11/EM_D11 PCI_AD10/ HD10/EM_D10 PCI_AD9/ HD9/EM_D9 PCI_AD8/ HD8/EM_D8 PCI_AD7/ HD7/EM_D7 PCI_AD6/ HD6/EM_D6 PCI_AD5/ HD5/EM_D5 PCI_AD4/ HD4/EM_D4 PCI_AD3/ HD3/EM_D3 PCI_AD2/ HD2/EM_D2 PCI_AD1/ HD1/EM_D1 PCI_AD0/ HD0/EM_D0 PCI_IRDY/ HRDY/ EM_A[17]/(CLE) PCI_TRDY/ HHWIL/ EM_A[16]/(ALE) PCI_INTA/ EM_WAIT2/ (RDY2/BSY2) IORDY/ GP[21]/EM_WAIT3/ (RDY3/BSY3) DIOW/ GP[20]/EM_WAIT4/ (RDY4/BSY4) DIOR/ GP[19]/EM_WAIT5/ (RDY5/BSY5) PCI_SERR/ HDS1/ EM_OE TYPE I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z OTHER DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 EMIFA FUNCTIONAL PINS: NAND I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between PCI, HPI, EMIFA. EMIFA mode, this address output EM_A[17] (O/Z). When used EMIFA (NAND), this Command Latch Enable output (CLE). This multiplexed between PCI, HPI, EMIFA. EMIFA, this address output EM_A[16] (O/Z). When used EMIFA (NAND), this Address Latch Enable output (ALE). This multiplexed between EMIFA. EMIFA mode, this wait state extension input EM_WAIT2 (I). When used EMIFA (NAND), this ready/busy input (RDY2/BSY2). This multiplexed between ATA, GPIO, EMIFA. EMIFA mode, this wait state extension input EM_WAIT3 (I). When used EMIFA (NAND), this ready/busy input (RDY3/BSY3). This multiplexed between ATA, GPIO, EMIFA. EMIFA mode, this wait state extension input EM_WAIT4 (I). When used EMIFA (NAND), this ready/busy input (RDY4/BSY4). This multiplexed between ATA, GPIO, EMIFA. EMIFA, this wait state extension input EM_WAIT5 (I). When used EMIFA (NAND), this ready/busy input (RDY5/BSY5). This multiplexed between PCI, HPI, EMIFA. EMIFA mode, this output enable output EM_OE (O/Z). These pins multiplexed between PCI, HPI, EMIFA. EMIFA mode, these pins 16-bit bidirectional data (EM_D[15:0]) [I/O/Z]. When EMIFA configured 8-bit asynchronous memory, only EM_D[7:0] pins used. DESCRIPTION
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
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TMS320DM6467 Digital Media System-on-Chip
SPRS403A DECEMBER 2007 REVISED 2008 www.ti.com
Table 2-9. Asynchronous External Memory Interface (EMIFA) Terminal Functions (continued)
SIGNAL NAME PCI_STOP/ HCNTL0/ EM_WE PCI_CBE2/ HDS2/ EM_CS2 PCI_CBE3/ HR/W EM_CS3 PCI_AD15/ HD15/EM_D15 PCI_AD14/ HD14 /EM_D14 PCI_AD13/ HD13/EM_D13 PCI_AD12/ HD12/EM_D12 PCI_AD11/ HD11/EM_D11 PCI_AD10/ HD10/EM_D10 PCI_AD9/ HD9/EM_D9 PCI_AD8/ HD8/EM_D8 PCI_AD7/ HD7/EM_D7 PCI_AD6/ HD6/EM_D6 PCI_AD5/ HD5/EM_D5 PCI_AD4/ HD4/EM_D4 PCI_AD3/ HD3/EM_D3 PCI_AD2/ HD2/EM_D2 PCI_AD1/ HD1/EM_D1 PCI_AD0/ HD0/EM_D0 TYPE OTHER DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 These pins multiplexed between PCI, HPI, EMIFA. EMIFA mode, these pins 16-bit bidirectional data (EM_D[15:0]) [I/O/Z]. When EMIFA configured 8-bit asynchronous memory, only EM_D[7:0] pins used. DESCRIPTION This multiplexed between PCI, HPI, EMIFA. EMIFA mode, this write enable output EM_WE (O/Z). This multiplexed between PCI, HPI, EMIFA. EMIFA mode, this Chip Select output EM_CS2 (O/Z). This chip select used EMIFA boot modes. Asynchronous memories (i.e., Flash) NAND flash. This multiplexed between PCI, HPI, EMIFA. EMIFA mode, this Chip Select output EM_CS3 (O/Z). Asynchronous memories (i.e., Flash).
I/O/Z
I/O/Z
I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z
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Table 2-10. DDR2 Memory Controller Terminal Functions
SIGNAL NAME DDR_CLK DDR_CLK DDR_CKE DDR_CS DDR_WE DDR_RAS DDR_CAS DDR_DQM[3] DDR_DQM[2] DDR_DQM[1] DDR_DQM[0] DDR_DQS[3] DDR_DQS[2] DDR_DQS[1] DDR_DQS[0] DDR_DQS[3] DDR_DQS[2] DDR_DQS[1] DDR_DQS[0] DDR_ODT0 DDR_BA[2] DDR_BA[1] DDR_BA[0] DDR_A[14] DDR_A[13] DDR_A[12] DDR_A[11] DDR_A[10] DDR_A[9] DDR_A[8] DDR_A[7] DDR_A[6] DDR_A[5] DDR_A[4] DDR_A[3] DDR_A[2] DDR_A[1] DDR_A[0] I/O/Z DVDDR2 DDR2 address I/O/Z DVDDR2 Bank address outputs (BA[2:0]). TYPE OTHER DDR2 Memory Controller I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DVDDR2 DDR2 Clock DDR2 Differential clock DDR2 Clock Enable DDR2 Active chip select DDR2 Active Write enable DDR2 Access Signal output DDR2 Column Access Signal output DDR2 Data mask outputs DDR_DQM[3]: upper byte data DDR_D[31:24] DDR_DQM[2]: DDR_D[23:16] DDR_DQM[1]: DDR_D[15:8] DDR_DQM[0]: lower byte DDR_D[7:0] Data strobe input/outputs each byte 32-bit data bus. They outputs DDR2 memory when writing inputs when reading. They used synchronize data transfers. DDR_DQS[3] upper byte DDR_D[31:24] DDR_DQS[2]: DDR_D[23:16] DDR_DQS[1]: DDR_D[15:8] DDR_DQS[0]: bottom byte DDR_D[7:0] Complimentary data strobe input/outputs each byte 32-bit data bus. They outputs DDR2 memory when writing inputs when reading. They used synchronize data transfers. DDR_DQS[3] upper byte DDR_D[31:24] DDR_DQS[2]: DDR_D[23:16] DDR_DQS[1]: DDR_D[15:8] DDR_DQS[0]: bottom byte DDR_D[7:0] DDR2 on-die termination control DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal more information, Recommended Operating Conditions table Device Overview
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TMS320DM6467 Digital Media System-on-Chip
SPRS403A DECEMBER 2007 REVISED 2008 www.ti.com
Table 2-10. DDR2 Memory Controller Terminal Functions (continued)
SIGNAL NAME DDR_D[31] DDR_D[30] DDR_D[29] DDR_D[28] DDR_D[27] DDR_D[26] DDR_D[25] DDR_D[24] DDR_D[23] DDR_D[22] DDR_D[21] DDR_D[20] DDR_D[19] DDR_D[18] DDR_D[17] DDR_D[16] DDR_D[15] DDR_D[14] DDR_D[13] DDR_D[12] DDR_D[11] DDR_D[10] DDR_D[9] DDR_D[8] DDR_D[7] DDR_D[6] DDR_D[5] DDR_D[4] DDR_D[3] DDR_D[2] DDR_D[1] DDR_D[0] DDR_DQGATE0 DDR_DQGATE1 DDR_DQGATE2 DDR_DQGATE3 DDR_VREF DDR_ZP DDR_ZN AA21 AB22 AA22 AA23 I/O/Z I/O/Z I/O/Z I/O/Z DVDDR2 DVDDR2 DVDDR2 DVDDR2
TYPE
OTHER
DESCRIPTION
I/O/Z
DVDDR2
DDR2 data configured bits wide bits wide.
DDR2 strobe gate signal lower-half data DDR2 strobe gate signal return lower-half data DDR2 strobe gate signal upper-half data DDR2 strobe gate signal return upper-half data Reference voltage input SSTL_18 buffers. Impedance control DDR2 outputs. This must connected 48.7- (±0.5% tolerance) resistor VSS. Impedance control DDR2 outputs. This must connected 48.7- (±0.5% tolerance) resistor DVDDR2.
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Table 2-11. Peripheral Component Interconnect (PCI) Terminal Functions
SIGNAL NAME TYPE OTHER Note: When boot mode used, proper device operation reset PCIEN must "0". functions enabled when PCIEN (PCI mode). This done external PCIEN (AC6) setting PCIEN (bit PINMUX0 register after device reset. more details PCIEN pin, Table 2-5, Boot Terminal Functions. PCI_CLK/GP[10] PCI_RST/DA2/ GP[13]/EM_A[22] PCI_IDSEL/ HDDIR/EM_R/W PCI_DEVSEL/ HCNTL1/EM_BA[1] PCI_FRAME/ HINT/EM_BA[0] PCI_IRDY/HRDY/ EM_A[17]/(CLE) PCI_ TRDY/HHWIL/ EM_A[16]/(ALE) PCI_STOP/ HCNTL0/EM_WE PCI_SERR/ HDS1/EM_OE PCI_PERR/ HCS/EM_DQM1 PCI_PAR/ HAS/EM_DQM0 PCI_INTA/ EM_WAIT2/ (RDY2/BSY2) PCI_REQ/ DMARQ/ GP[11]/EM_CS5 PCI_GNT/ DMACK/ GP[12]/EM_CS4 PCI_CBE3/ HR/W/EM_CS3 PCI_CBE2/ HDS2/EM_CS2 PCI_CBE1/ ATA_CS1/ GP[32]/EM_A[19] PCI_CBE0/ ATA_CS0/ GP[33]/EM_A[18] I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between GPIO. mode, this clock input PCI_CLK (I). This multiplexed between PCI, ATA, GPIO, EMIFA. mode, this reset PCI_RST (I). This multiplexed between PCI, ATA, EMIFA. mode, this initialization device select, PCI_IDSEL (I). This multiplexed between PCI, HPI, EMIFA. mode, this device select, PCI_DEVSEL (I/O/Z). This multiplexed between PCI, HPI, EMIFA. mode, this cycle frame, PCI_FRAME (I/O/Z). This multiplexed between PCI, HPI, EMIFA. mode, this initiator ready, PCI_IRDY (I/O/Z). This multiplexed between PCI, HPI, EMIFA. mode, this target ready, PCI_ TRDY (I/O/Z). This multiplexed between PCI, HPI, EMIFA. mode, this stop, PCI_STOP (I/O/Z). This multiplexed between PCI, HPI, EMIFA. mode, this system error, PCI_SERR (I/O/Z). This multiplexed between PCI, HPI, EMIFA. mode, this parity error, PCI_PERR (I/O/Z). This multiplexed between PCI, HPI, EMIFA. mode, this parity, PCI_PAR (I/O/Z). This multiplexed between EMIFA. mode, this interrupt PCI_INTA (O/Z). This multiplexed between PCI, ATA, GPIO, EMIFA. mode, this request, PCI_REQ (O/Z). This multiplexed between PCI, ATA, GPIO, EMIFA. mode, this grant, PCI_GNT (I). This multiplexed between PCI, HPI, EMIFA. mode, this command/byte enable PCI_CBE3 (I/O/Z). This multiplexed between PCI, HPI, EMIFA. mode, this command/byte enable PCI_CBE2 (I/O/Z). This multiplexed between PCI, ATA, GPIO, EMIFA. mode, this command/byte enable PCI_CBE1 (I/O/Z). This multiplexed between PCI, ATA, GPIO, EMIFA. mode, this command/byte enable PCI_CBE0 (I/O/Z). DESCRIPTION
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
I/O/Z
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.8.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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TMS320DM6467 Digital Media System-on-Chip
SPRS403A DECEMBER 2007 REVISED 2008 www.ti.com
Table 2-11. Peripheral Component Interconnect (PCI) Terminal Functions (continued)
SIGNAL NAME PCI_AD31/DD15/ HD31/EM_A[15] PCI_AD30/DD14/ HD30/EM_A[14] PCI_AD29/DD13/ HD29/EM_A[13] PCI_AD28/DD12/ HD28/EM_A[12] PCI_AD27/DD11/ HD27/EM_A[11] PCI_AD26/DD10/ HD26/EM_A[10] PCI_AD25/DD9/ HD25/EM_A[9] PCI_AD24/DD8/ HD24/EM_A[8] PCI_AD23/DD7/ HD23/EM_A[7] PCI_AD22/DD6/ HD22/EM_A[6] PCI_AD21/DD5/ HD21/EM_A[5] PCI_AD20/DD4/ HD20/EM_A[4] PCI_AD19/DD3/ HD19/EM_A[3] PCI_AD18/DD2/ HD18/EM_A[2] PCI_AD17/DD1/ HD17/EM_A[1] PCI_AD16/DD0/ HD16/EM_A[0] PCI_AD15/ HD15/EM_D15 PCI_AD14/ HD14/EM_D14 PCI_AD13/ HD13/EM_D13 PCI_AD12/ HD12/EM_D12 PCI_AD11/ HD11/EM_D11 PCI_AD10/ HD10/EM_D10 PCI_AD9/ HD9/EM_D9 PCI_AD8/ HD8/EM_D8 TYPE I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z OTHER DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 These pins multiplexed between PCI, HPI, EMIFA. PCI, these pins data/address bus, PCI_AD [15:0] (I/O/Z). These pins multiplexed between PCI, ATA, HPI, EMIFA. mode, these pins address/data bus, PCI_AD[31:16] (I/O/Z). DESCRIPTION
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Table 2-11. Peripheral Component Interconnect (PCI) Terminal Functions (continued)
SIGNAL NAME PCI_AD7/ HD7/EM_D7 PCI_AD6/ HD6/EM_D6 PCI_AD5/ HD5/EM_D5 PCI_AD4/ HD4/EM_D4 PCI_AD3/ HD3/EM_D3 PCI_AD2/ HD2/EM_D2 PCI_AD1/ HD1/EM_D1 PCI_AD0/ HD0/EM_D0 TYPE I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z OTHER DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 These pins multiplexed between PCI, HPI, EMIFA. PCI, these pins data/address [15:0] (I/O/Z) DESCRIPTION
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TMS320DM6467 Digital Media System-on-Chip
SPRS403A DECEMBER 2007 REVISED 2008 www.ti.com
Table 2-12. EMAC [G]MII MDIO Terminal Functions
SIGNAL NAME TYPE OTHER EMAC [G]MII RFTCLK GMTCLK MTCLK MTXD7 MTXD6 MTXD5 MTXD4 MTXD3 MTXD2 MTXD1 MTXD0 MTXEN MCOL MCRS MRCLK MRXD7 MRXD6 MRXD5 MRXD4 MRXD3 MRXD2 MRXD1 MRXD0 MRXDV MRXER DVDD33 DVDD33 DVDD33 DVDD33 [G]MII receive data valid input [G]MII receive data error input MDIO MDCLK MDIO I/O/Z Management data serial clock output Management Data DVDD33 [G]MII receive data [7:0]. 1000 GMII operation, MRXD[7:0] used. 10/100 operation, only MRXD[3:0] used. DVDD33 DVDD33 DVDD33 DVDD33 [G]MII transmit data enable output [G]MII collision detect (sense) input [G]MII carrier sense input [G]MII receive clock DVDD33 [G]MII transmit data [7:0]. 1000 GMII operation, MTXD[7:0] used. 10/100 operation, only MTXD[3:0] used. DVDD33 DVDD33 DVDD33 Gigabit (GMII) reference transmit clock (125 MHz) GMII source asynchronous transmit clock [G]MII transmit clock input DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.8.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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Table 2-13. VLYNQ Terminal Functions
SIGNAL NAME TYPE OTHER VLYNQ VLYNQ_CLOCK VLYNQ_SCRUN VLYNQ_TXD3 VLYNQ_TXD2 VLYNQ_TXD1 VLYNQ_TXD0 VLYNQ_RXD3 VLYNQ_RXD2 VLYNQ_RXD1 VLYNQ_RXD0 DVDD33 VLYNQ receive [3:0] DVDD33 VLYNQ transmit [3:0] I/O/Z I/O/Z DVDD33 DVDD33 VLYNQ serial clock VLYNQ serial clock request DESCRIPTION
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.8.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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TMS320DM6467 Digital Media System-on-Chip
SPRS403A DECEMBER 2007 REVISED 2008 www.ti.com
Table 2-14. Terminal Functions
SIGNAL NAME TYPE OTHER Host-Port Interface (HPI) enabled PINMUX0.HPIEN (and PCIEN ATAEN dependent 16-/32-bit modes). more detailed information muxing, Section 3.7.3.1, PCI, HPI, EMIFA, Muxing. PCI_PERR/ HCS/ EM_DQM1 PCI_STOP/ HCNTL0/ EM_WE PCI_DEVSEL/ HCNTL1/ EM_BA[1] PCI_PAR/HAS/ EM_DQM0 PCI_SERR/ HDS1/EM_OE PCI_CBE2/ HDS2/EM_CS2 PCI_CBE3/ HR/W/EM_CS3 PCI_TRDY/ HHWIL/ EM_A[16]/(ALE) PCI_AD31/ DD15/ HD31/EM_A[15] PCI_AD30/ DD14/ HD30/EM_A[14] PCI_AD29/ DD13/ HD29/EM_A[13] PCI_AD28/ DD12/ HD28/EM_A[12] PCI_AD27/ DD11/ HD27/EM_A[11] PCI_AD26/ DD10/ HD26/ EM_A[10] PCI_AD25/ DD9/ HD25/EM_A[9] PCI_AD24/ DD8/ HD24/EM_A[8] I/O/Z DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 This multiplexed between PCI, HPI, EMIFA. mode, this active-low chip select input, (I). This multiplexed between PCI, HPI, EMIFA. mode, this control input HCNTL0 This multiplexed between PCI, HPI, EMIFA. mode, this control input HCNTL1 (I). This multiplexed between PCI, HPI, EMIFA. mode, this address strobe, (I). NOTE: DM6467 does support feature. proper operation routed out, must pulled external resistor. This multiplexed between PCI, HPI, EMIFA. mode, this data strobe input HDS1 (I). This multiplexed between PCI, HPI, EMIFA. mode, this data strobe input HDS2 (I). This multiplexed between PCI, HPI, EMIFA. mode, this host read/write select input, HR/W (I). This multiplexed between PCI, HPI, EMIFA. mode, this half-word identification input control, HHWIL (I). DESCRIPTION
I/O/Z
I/O/Z
I/O/Z
I/O/Z I/O/Z I/O/Z I/O/Z
I/O/Z DVDD33
These pins multiplexed between PCI, ATA, HPI, EMIFA. HPI-32 mode, these pins upper data bus, HD[31:16] (I/O/Z). HPI-16 mode, HD[31:16] pins used
Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.8.1, Pullup/Pulldown Resistors. Input, Output, High impedance, Supply voltage, Ground, Analog signal Specifies operating supply voltage each signal
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Table 2-14. Terminal Functions (continued)
SIGNAL NAME PCI_AD23/ DD7/ HD23/EM_A[7] PCI_AD22/ DD6/ HD22/EM_A[6] PCI_AD21/ DD5/ HD21/EM_A[5] PCI_AD20/ DD4/ HD20/EM_A[4] PCI_AD19/ DD3/ HD19/EM_A[3] PCI_AD18/ DD2/ HD18/EM_A[2] PCI_AD17/ DD1/ HD17/EM_A[1] PCI_AD16/ DD0/ HD16/EM_A[0] PCI_AD15/ HD15/EM_D15 PCI_AD14/ HD14/EM_D14 PCI_AD13/ HD13/EM_D13 PCI_AD12/ HD12/EM_D12 PCI_AD11/ HD11/EM_D11 PCI_AD10/ HD10/EM_D10 PCI_AD9/ HD9/EM_D9 PCI_AD8/ HD8/EM_D8 PCI_AD7/ HD7/EM_D7 PCI_AD6/ HD6/EM_D6 PCI_AD5/ HD5/EM_D5 PCI_AD4/ HD4/EM_D4 PCI_AD3/ HD3/EM_D3 PCI_AD2/ HD2/EM_D2 PCI_AD1/ HD1/EM_D1 PCI_AD0/ HD0/EM_D0 TYPE OTHER DESCRIPTION
I/O/Z DVDD33
These pins multiplexed between PCI, ATA, HPI, EMIFA. HPI-32 mode, these pins upper data bus, HD[31:16] (I/O/Z). HPI-16 mode, HD[31:16] pins used
I/O/Z I/O/Z These pins multiplexed between PCI, HPI, EMIFA. HPI-16 mode, these pins data bus, HD[15:0] (I/O/Z). HPI-32 mode, these pins lower data bus, HD[15:0] (I/O/Z). These pins multiplexed between PCI, HPI, EMIFA. HPI-16 mode, these pins data bus, HD[15:0] (I/O/Z). HPI-32 mode, these pins lower data bus, HD[15:0] (I/O/Z).
DVDD33
DVDD33
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TMS320DM6467 Digital Media System-on-Chip
SPRS403A DECEMBER 2007 REVISED 2008 www.ti.com
Table 2-14. Terminal Functions (continued)
SIGNAL NAME PCI_IRDY/ HRDY/ EM_A[17]/(CLE) PCI_FRAME/ HINT/EM_BA[0] TYPE OTHER DVDD33 DVDD33 DESCRIPTION This multiplexed between PCI, HPI, EMIFA. mode, this host ready output from host, HRDY (O/Z). This multiplexed between PCI, HPI, EMIFA. mode, this host interrupt output, HINT (O/Z).
I/O/Z I/O/Z
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Table 2-15. Terminal Functions
SIGNAL NAME USB_DP USB_DN TYPE OTHER
DESCRIPTION
bidirectional Data Differential signal pair [positive/negative]. When peripheral used, USB_DP signal should pulled (high) USB_DN signal should pulled down (low) 10-k resistor. current reference output. When peripheral used, this must connected 10-k resistor USB_VSSREF. When peripheral used, this must connected 10-k resistor USB_VSSREF. This multiplexed between GPIO. When this used USB_DRVVBUS (PINMUX0.VBUSDIS Controller operating Host (USBCTL.USBID Session progress), this signal used Controler enable external VBUS charge pump. Ground reference current. This must connected 10-k resistor USB_R1. When peripheral used, USB_VSSREF signal should connected VSS. Analog power supply PHY. When peripheral used, USB_VDDA3P3 signal should connected DVDD33. 1.8-V power supply PHY. When peripheral used, USB_VDD1P8 signal should connected 1.8-V power supply. Core power supply output PHY. This must connected 1-µF capacitor VSS. When peripheral used, USB_VDDA1P2LDO signal should still connected 1-µF capacitor VSS.
USB_R1
USB_DRVVBUS/ GP[22]
I/O/Z
DVDD33
USB_VSSREF
USB_VDDA3P3
USB_VDD1P8
USB_VDDA1P2LDO
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.8.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal more information, Recommended Operating Conditions table
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TMS320DM6467 Digital Media System-on-Chip
SPRS403A DECEMBER 2007 REVISED 2008 www.ti.com
Table 2-16. Video-Port Interface (VPIF) Terminal Functions
SIGNAL NAME TYPE OTHER DESCRIPTION
VIDEO-PORT INTERFACE (VPIF) CAPTURE VP_CLKIN0 VP_CLKIN1 VP_DIN15_VP_VSYNC/ TS0_DIN7 VP_DIN14_VP_HSYNC/ TS0_DIN6 VP_DIN13_FIELD/ TS0_DIN5 VP_DIN12/ TS0_DIN4 VP_DIN11/ TS0_DIN3 VP_DIN10/ TS0_DIN2 VP_DIN9/ TS0_DIN1 VP_DIN8/ TS0_DIN0 VP_DIN7/ TS0_DOUT7/ TS1_DIN VP_DIN6/ TS0_DOUT6/ TS1_PSTIN VP_DIN5/ TS0_DOUT5/ TS1_EN_WAITO VP_DIN4/ TS0_DOUT4/ TS1_WAITO VP_DIN3/ TS0_DOUT3 VP_DIN2/ TS0_DOUT2 VP_DIN1/ TS0_DOUT1 VP_DIN0/ TS0_DOUT0 AC13 AB18 AC18 DVDD33 DVDD33 DVDD33 DVDD33 DVDD33 VPIF capture channel input clock (I). VPIF capture channel input clock (I). This multiplexed between VPIF TSIF0. When used VPIF, this capture data vertical sync input, VP_DIN15_VSYNC (I). This multiplexed between VPIF TSIF0. When used VPIF, this capture data horizontal sync input, VP_DIN14_HSYNC (I). This multiplexed between VPIF TSIF0. When used VPIF, this capture data field indicator input, VP_DIN13_FIELD (I).
AA17
AB17 AC17 AA16 AB16 AC16
DVDD33
These pins multiplexed between VPIF TSIF0. When used VPIF, these pins capture data bits, VP_DIN[12:8] (I).
AA14 I/O/Z AB14 DVDD33 These pins multiplexed between VPIF, TSIF0, TSIF1. When used VPIF, these pins capture data bits, VP_DIN[7:4] (I).
AC14 AA15 I/O/Z AB15 AC15 VIDEO-PORT INTERFACE (VPIF) DISPLAY
DVDD33
These pins multiplexed between VPIF TSIF0. When used VPIF, these pins capture data bits, VP_DIN[3:0] (I).
VP_CLKIN2 VP_CLKIN3/ TS1_CLKO VP_CLKO2
I/O/Z
DVDD33 DVDD33 DVDD33
VPIF display channel source input clock (I). This multiplexed between VPIF TSIF1. When used VPIF, this display channel source clock, VP_CLKIN3 (I). VPIF display channel output clock (O/Z).
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.8.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal Device Overview Submit Documentation Feedback
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Table 2-16. Video-Port Interface (VPIF) Terminal Functions (continued)
SIGNAL NAME VP_CLKO3/ TS0_CLKO VP_DOUT15/ TS1_DIN VP_DOUT14/ TS1_PSTIN VP_DOUT13/ TS1_EN_WAITO VP_DOUT12/ TS1_WAITO VP_DOUT11/ TS1_DOUT VP_DOUT10/ TS1_PSTO VP_DOUT9/ TS1_ENAO VP_DOUT8/ TS1_WAITIN VP_DOUT7 VP_DOUT6/ DSPBOOT VP_DOUT5/ PCIEN VP_DOUT4/ CS2BW VP_DOUT3/ BTMODE3 VP_DOUT2/ BTMODE2 VP_DOUT1/ BTMODE1 VP_DOUT0/ BTMODE0 AC10 AB10 AA10 I/O/Z DVDD33 TYPE OTHER DVDD33 DESCRIPTION This multiplexed between VPIF TSIF0. When used VPIF, this display channel output clock, VP_CLKO3 (O/Z).
I/O/Z I/O/Z I/O/Z I/O/Z
DVDD33
These pins multiplexed between VPIF TSIF1. When used VPIF, these pins display data bits, VP_DOUT[15:8] (O/Z).
These pins multiplexed between VPIF boot configuration. After reset, these pins used VPIF display data bits, VP_DOUT[7:0] (O/Z).
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TMS320DM6467 Digital Media System-on-Chip
SPRS403A DECEMBER 2007 REVISED 2008 www.ti.com
Table 2-17. Transport Stream Interface (TSIF0) Terminal Functions
SIGNAL NAME TYPE OTHER DESCRIPTION
TSIF0 PARALLEL INPUT (PINMUX0.PTSIMUX TS0_CLKIN UCTS1/USD1/ TS0_EN_WAITO/ GP[26] URTS1/UIRTX1/ TS0_WAITO/GP[25] URTS2/UIRTX2/ TS0_PSTIN/GP[41] VP_DIN15_VP_VSYNC/ TS0_DIN7 VP_DIN14_VP_HSYNC/ TS0_DIN6 VP_DIN13_FIELD/ TS0_DIN5 VP_DIN12/ TS0_DIN4 VP_DIN11/ TS0_DIN3 VP_DIN10/ TS0_DIN2 VP_DIN9/ TS0_DIN1 VP_DIN8/ TS0_DIN0 AC19 DVDD33 DVDD33 TSIF0 receive clock input (I). This multiplexed between UART1, TSIF0, GPIO. When TSIF0 input enabled (PINMUX0.PTSIMUX 1x), synchronous mode, this data enable indicator asynchronous mode, this wait output (O/Z), TS0_EN_WAITO. This multiplexed between UART1, TSIF0, GPIO. When TSIF0 input enabled (PINMUX0.PTSIMUX 1x), asynchronous mode, this wait output, TS0_WAITO (O/Z). This TSIF function used synchronous mode. This multiplexed between UART2, TSIF0, GPIO. When TSIF0 input enabled (PINMUX0.PTSIMUX 1x), this packet start input indicator, TS0_PSTIN (I).
I/O/Z
AA18
I/O/Z
DVDD33 DVDD33
AC20 AC18 AA17 AB17 AC17
I/O/Z
I/O/Z AA16 AB16 AC16
DVDD33
These pins multiplexed between VPIF TSIF0. When TSIF0 parallel input mode enabled (PINMUX0.PTSIMUX 10), these pins input data bits TS0_DIN[7:0] (I).
TSIF0 SERIAL INPUT (PINMUX0.PTSIMUX TS0_CLKIN UCTS1/USD1/ TS0_EN_WAITO/ GP[26] URTS2/UIRTX2/ TS0_PSTIN/GP[41] AC19 DVDD33 DVDD33 TSIF0 receive clock input (I). This multiplexed between UART1, TSIF0, GPIO. When TSIF0 input enabled (PINMUX0.PTSIMUX 1x), synchronous mode, this data enable indicator asynchronous mode, this wait output (O/Z), TS0_EN_WAITO. This multiplexed between UART2, TSIF0, GPIO. When TSIF0 input enabled (PINMUX0.PTSIMUX 1x), synchronous/asynchronous modes, this packet start input indicator, TS0_PSTIN (I). This multiplexed between UART1, TSIF0, GPIO. When TSIF0 serial input mode enabled (PINMUX0.PTSIMUX 11), synchronous/asynchronous modes, this serial input data (I), TS0_DIN7(I).
I/O/Z
AC20
I/O/Z
DVDD33
URXD1/ TS0_DIN7/GP[23]
I/O/Z
DVDD33
Input, Output, High impedance, Supply voltage, Ground, Analog signal Internal pulldown, Internal pullup. more detailed information pullup/pulldown resistors situations where external pullup/pulldown resistors required, Section 3.8.1, Pullup/Pulldown Resistors. Specifies operating supply voltage each signal
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TMS320DM6467 Digital Media System-on-Chip
Table 2-17. Transport Stream Interface (TSIF0) Terminal Functions (continued)
SIGNAL NAME TYPE OTHER DESCRIPTION
TSIF0 PARALLEL OUTPUT (PINMUX0.PTSIMUX VP_CLKO3/ TS0_CLKO UDTR0/ TS0_ENAO/GP[36] UDSR0/ TS0_PSTO/ GP[37] UDCD0/ TS0_WAITIN/ GP[38] VP_DIN7/ TS0_DOUT7/ TS1_DIN VP_DIN6/ TS0_DOUT6/ TS1_PSTIN VP_DIN5/ TS0_DOUT5/ TS1_EN_WAITO VP_DIN4/ TS0_DOUT4/ TS1_WAITO VP_DIN3/ TS0_DOUT3 VP_DIN2/ TS0_DOUT2 VP_DIN1/ TS0_DOUT1 VP_DIN0/ TS0_DOUT0 AC10 DVDD33 DVDD33 This multiplexed between VPIF TSIF0. When TSIF0 output enabled (PINMUX0.PTSOMUX 1x), this transmit clock output, TS0_CLKO (O/Z). This multiplexed between UART0, TSIF0, GPIO. When TSIF0 output enabled (PINMUX0.PTSOMUX 1x), this data enable indicator, TS0_ENAO (O/Z) either synchronous/asynchronous modes. This multiplexed between UART0, TSIF0, GPIO. When TSIF0 output enabled (PINMUX0.PTSOMUX 1x), this packet start output indicator, TS0_PSTO (O/Z) either synchronous/asynchronous modes. This multiplexed between UART0, TSIF0, GPIO. When TSIF0 output enabled (PINMUX0.PTSOMUX 1x), asynchronous mode, this wait input, TS0_WAITIN (I). This TSIF function used synchronous mode.
I/O/Z
AB11
I/O/Z
DVDD33
AA11
I/O/Z
DVDD33
AA14 I/O/Z AB14 DVDD33
These pins multiplexed between VPIF, TSIF0, TSIF1. When parallel TSIF0 output enabled (PINMUX0.PTSOMUX 10), TSIF1 VPIF_DIN muxing enabled (TSSI_MUX 11), these pins output data bits TS0_DOUT[7:4] (O/Z) either synchronous/asynchronous modes.
AC14 AA15 I/O/Z AB15 AC15 TSIF0 SERIAL OUTPUT (PINMUX0.PTSIMUX These pins multiplexed between VPIF TSIF0. When parallel TSIF0 output enabled (PINMUX0.PTSOMUX 10), these pins output data bits TS0_DOUT[3:0] (O/Z) either synchronous/asynchronous modes.
DVDD33
VP_CLKO3/ TS0_CLKO UDTR0/ TS0_ENAO/GP[36]
AC10
DVDD33 DVDD33
This multiplexed between VPIF TSIF0. When TSIF0 output enabled (PINMUX0.PTSOMUX 1x), this transmit clock output, TS0_CLKO (O/Z). This multiplexed between UART0, TSIF0, GPIO. When TSIF0 output enabled (PINMUX0.PTSOMUX 1x), this data enable indicator, TS0_ENAO (O/Z) either synchronous/asynchronous modes. This multiplexed between UART0, TSIF0, GPIO. When TSIF0 output enabled (PINMUX0.PTSOMUX 1x), this packet start output indicator, TS0_PSTO (O/Z) either synchronous/asynchronous modes. This multiplexed between UART0, TSIF0, GPIO. When TSIF0 output enabled (PINMUX0.PTSOMUX 1x), asynchronous mode, this wait input, TS0_WAITIN (I). This TSIF function used synchronous mode. This multiplexed between UART1, TSIF0, GPIO. When serial TSIF0 output enabled (PINMUX0.PTSOMUX 11), synchronous/asynchronous modes, this serial output data bit, TS0_DOUT[7] (O/Z).
I/O/Z
UDSR0/ TS0_PSTO/GP[37]
AB11
I/O/Z
DVDD33
UDCD0/ TS0_WAITIN/GP[38]
AA11
I/O/Z
DVDD33
UTXD1/URCTX1/ TS0_DOUT7/GP[24]
AB19
I/O/Z
DVDD33
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TMS320DM6467 Digital Media System-on-Chip
SPRS403A DECEMBER 2007 REVISED 2008 www.ti.com
Table 2-18. Transport Stream Interface (TSIF1) Terminal Functions
SIGNAL NAME TYPE OTHER DESCRIPTION
TSIF1 INPUT UART0 MUXING (PINMUX0.TSSIMUX TS1_CLKIN URXD0/ TS1_DIN URTS0/UIRTX0/ TS1_EN_WAITO UTXD0/URCTX0/ TS1_PSTIN AC11 AB13 DVDD33 DVDD33 DVDD33 DVDD33 TSIF1 receive clock input (I). This multiplexed between UART0 TSIF1. When TSIF1 input UART0 muxing enabled (PINMUX0.TSSIMUX 01), this serial data input, TS1_DIN (I). This multiplexed between UART0 TSIF1. When TSIF1 input UART0 muxing enabled (PINMUX0.TSSIMUX 01), synchronous mode, this data enable indicator asynchronous mode, this wait output, TS1_EN_WAITO (O/Z). This multiplexed between UART0 TSIF1. When TSIF1 input UART0 muxing enabled (PINUMX0.TSSIMUX 01), this packet start indicator, TS1_PSTIN (I).
AA13
I/O/Z
I/O/Z
TSIF1 INPUT VPIF DOUT MUXING (PINMUX0.TSSIMUX TS1_CLKIN VP_DOUT15/ TS1_DIN VP_DOUT13/ TS1_EN_WAITO AC11 I/O/Z DVDD33 DVDD33 DVDD33 TSIF1 receive clock input (I). This multiplexed between VPIF TSIF1. When TSIF1 input VPIF DOUT muxing enabled (PINMUX0.TSSIMUX 10), this serial data input, TS1_DIN (I). This multiplexed between VPIF TSIF1. When TSIF1 input VPIF DOUT muxing enabled (PINMUX0.TSSIMUX 10), synchronous mode, this data enable indicator asynchronous mode, this wait output, TS1_EN_WAITO (O/Z). This multiplexed between VPIF TSIF1. When TSIF1 input VPIF DOUT muxing enabled (PINMUX0.TSSIMUX 10), synchronous/asynchronous modes, this packet start indicator, TS1_PSTIN (I).
I/O/Z
VP_DOUT14/ TS1_PSTIN
I/O/Z
DVDD33
TSIF1 INPUT VPIF MUXING (PINMUX0.TSSIMUX TS1_CLKIN VP_DIN7/ TS0_DOUT7/ TS1_DIN VP_DIN5/ TS0_DOUT5/ TS1_EN_WAITO VP_DIN6/ TS0_DOUT6/ TS1_PSTIN AC11 I/O/Z DVDD33 DVDD33 DVDD33 TSIF1 receive clock input (I). This multiplexed between VPIF, TSIF0, TSIF1. When TSIF1 input VPIF muxing enabled (PINMUX0.TSSIMUX 11), synchronous/asynchronous modes, this serial data input, TS1_DIN (I). This multiplexed between VPIF, TSIF0, TSIF1. When TSIF1 input VPIF muxing enabled (PINMUX0.TSSIMUX 11), synchronous mode, this data enable indicator asynchronous mode, this wait output, TS1_EN_WAITO (O/Z). This multiplexed between VPIF, TSIF0, TSIF1. When TSIF1 input VPIF muxing enabled (PINMUX0.TSSIMUX 11), synchronous/asynchronous modes, this packet start indicator, TS
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