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Single Chip CMOS Imager with Integrated Image Signal Processor JPEG Codec
Version
Products specifications discussed herein evaluation reference purposes only subject change TransChip without notice. information this document warranty, does form part quotation contract does convey license under intellectual property rights. Copyright TransChip Israel Research Center, Ltd., 2005.
November 2005
Table Contents
INTRODUCTION FEATURES SPECIFICATIONS COMPACT 24-PIN CAMERA MODULE
FUNCTIONAL DESCRIPTION 2.10 2.11 2.12 2.13 2.14 CONT. RCLK IMGA. YUVR JPEG IMAGER ADDRESS GENERATOR. PIXEL ARRAY CONFIGURATION BAYER GRID CONFIGURATION RESOLUTIONS FRAME RATES ANALOG PROCESSING ON-CHIP MICRO CONTROLLER. BAYER TRANSLATION UNIT (YUVR). JPEG COMPRESSION UNIT (JCOR).
RESET CLOCK POWER MODES 3.1.1 Startup 3.1.2 Bypass. 3.1.3 Power Down CONFIGURATIONS DEVICE INITIALIZATION SEQUENCE
TC5747MF24L INTERFACES SERIAL INTERFACE 4.1.1 Overview 4.1.2 Mode Operation. PARALLEL VIDEO INTERFACE (PVI) 4.2.1 Parallel Mode Operation. 4.2.2 External Chip-Select 4.2.3 Qualified Clock Mode 4.2.4 VALIDH Configured WR#. 4.2.5 Frame-Rate Control. 4.2.6 Data 4.2.7 Data Markers. 4.2.8 Ancillary Data Format. 4.2.9 Serial Output Mode. SERIAL VIDEO INTERFACE
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HIGH LEVEL PROGRAMMING FIRMWARE LOADING
AC/DC SPECIFICATIONS 6.10 ABSOLUTE MAXIMUM RATINGS RECOMMENDED OPERATING CONDITIONS ELECTRICAL CHARACTERISTICS PARALLEL VIDEO OUTPUT CLOCK QUALIFIED MODE CHARACTERISTICS PARALLEL VIDEO OUTPUT CAMERA INTERFACE MODE CHARACTERISTICS PARALLEL VIDEO OUTPUT INTERFACE CHARACTERISTICS. SERIAL VIDEO OUTPUT INTERFACE CHARACTERISTICS SERIAL VIDEO OUTPUT CLOCK QUALIFIED MODE CHARACTERISTICS SERIAL VIDEO OUTPUT MODE CHARACTERISTICS. I2C-COMPATIBLE INTERFACE CHARACTERISTICS
MECHANICAL ELECTRICAL DRAWINGS TC5747MF24L 24-PIN PACKAGE LENS SPECIFICATION
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List Figures
FIGURE TC5747 FUNCTIONAL BLOCK DIAGRAM FIGURE BAYER GRID CONFIGURATION FIGURE INITIALIZATION SEQUENCE FIGURE INTERFACE START STOP CONDITIONS FIGURE PROTOCOL FIGURE HOST-WRITE ACCESS FIGURE HOST-READ ACCESS FIGURE HOST-READ MULTIPLE ACCESSES FIGURE QUALIFICATION SIGNAL TIMING FIGURE VERTICAL HORIZONTAL QUALIFY SIGNALS. FIGURE BAYER OUTPUT FORMAT FIGURE OUTPUT FORMAT FIGURE OUTPUT PARALLEL VIDEO OUTPUT INTERFACE FIGURE VALIDH WRITE SIGNAL, ACTIVE LOW. FIGURE VALIDH WRITE SIGNAL, ACTIVE HIGH FIGURE FRAME RATE CONTROL FIGURE RGB666 THREE-TRANSFERS MODE FIGURE SERIAL DATA-OUT INTERFACE X2_CLK_OUT FIGURE SERIAL DATA-OUT INTERFACE X2_CLK_OUT FIGURE SINGLE BYTE TRANSFER MODE. FIGURE PARALLEL VIDEO OUTPUT CLOCK QUALIFIED MODE FIGURE PARALLEL VIDEO OUTPUT CAMERA INTERFACE MODE FIGURE PARALLEL VIDEO OUTPUT INTERFACE SIGNALS FIGURE SERIAL VIDEO OUTPUT INTERFACE SIGNALS FIGURE SERIAL VIDEO OUTPUT CLOCK QUALIFIED MODE FIGURE SERIAL VIDEO OUTPUT MODE FIGURE I2C-COMPATIBLE INTERFACE FIGURE TC5747 24-PIN MODULE MECHANICAL DRAWING. FIGURE TC5747 24-PIN MODULE MECHANICAL DRAWING CONTINUED
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List Tables
TABLE TC5747 SPECIFICATIONS TABLE 24-PIN MODULE LIST TABLE ANALOG CLOCK RATE MODES TABLE TRANSCHIP MARKERS TABLE MARKERS. TABLE ABSOLUTE MAXIMUM RATINGS. TABLE RECOMMENDED OPERATING CONDITIONS TABLE ELECTRICAL CHARACTERISTICS TABLE PARALLEL VIDEO OUTPUT CLOCK QUALIFIED MODE CHARACTERISTICS TABLE PARALLEL VIDEO OUTPUT CAMERA INTERFACE MODE CHARACTERISTICS TABLE PARALLEL VIDEO OUTPUT INTERFACE CHARACTERISTICS TABLE SERIAL VIDEO OUTPUT CLOCK QUALIFIED MODE CHARACTERISTICS TABLE SERIAL VIDEO OUTPUT MODE CHARACTERISTICS TABLE I2C-COMPATIBLE INTERFACE CHARACTERISTICS TABLE LENS SPECIFICATIONS
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TC5747 Data Sheet Single Chip CMOS Imager
Introduction
TC5747 single chip (640 lines over pixels) color CMOS sensor with integrated color processing JPEG codec. designed meet requirements cellular devices with power consumption miniature size. embedded programmable core with dedicated hardware performs extensive color processing. embedded real-time JPEG encoder compressed frames SRAM store JPEG images chip. TC5747 flexible interfaces supports multiple video output formats easy integration into cellular phones. supports 16-bit host interface fast data access control.
Features
TC5747 features state-of-the-art architecture, allowing extremely power consumption miniature size. following product highlights. Sensor Array 1/4" optical format resolution 640x480 square pixels Integrated mosaic with micro-lens high sensitivity Double sampling fixed pattern noise reduction Separate gains Programmable frame rate QVGA Programmable window size filtered-option sub-sampling Image processing Embedded Image Signal Processor (ISP) Embedded micro controller with program memory Faulty pixel mechanism Loadable gamma correction tables Automatic white balance Automatic exposure control Despeckle function Enhanced dynamic range backlight illumination Programmable color correction matrix Programmable sharpening blurring matrix Anti flicker 50Hz Horizontal vertical inversion Digital zoom Color adjustments such brightness, contrast, saturation Digital effects, such monochrome, negative, sepia Frame stamp overlay captured image 320x240) Down sampling
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TC5747 Data Sheet Single Chip CMOS Imager
JPEG Codec Real-time JPEG encoder decoder still images M-JPEG motion video Compression format images Decompression resolution, 4:2:2, 4:1:1, 4:2:0 format images Programmable compression ratio, bits/pixel image JPEG compression done parallel with preview video Thumbnail image support Portrait images phone book Compression decompression from internal memory Compression done after scaling overlay frame stamp data Decompressed image resized re-compressed screen display screen display overlay QVGA (320x240) resolution, 4-bit data color table Support layers data. first layer used frame stamp captured image. second layer composed non-overlapping regions switching messages icons. Each window 4-bit color table. Support 32x32 pixel cursor with 4-bit color table Rotation JPEG images display 2700 Video Interface Flexible output formats including: Bayer, (666, 565, 444), YUV/YCrCb 4:2:2 JPEG bits direct interface LCD: supports 8/9/16/18 output Chip select (main sub) Camera standby mode host access Optional configuration bits camera interface Horizontal vertical sync signals CCIR656 compatible signaling markers Optional high-speed bi-directional serial interface Support simultaneous video output streams Host Interface 8/16bit bi-directional access types host interface Optional UART interface programming control Easy software Input clock frequency: 3.6MHz 32MHz Power consumption, VGA@ Power management support power modes Operation voltage Technology: 0.25 Operation temperature: degrees Celsius Packaging types: module with lens. Module have either flex cable board-to-board connector. Several pin-out options will supported provide selected interface functionality.
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
Specifications
Feature Array format Capture size Pixel size Color filter Supply Voltage Power consumption Power save modes Description 656x524 physical pixel, 648x492 active pixels 1/4" optics Configurable window size Mosaic with micro lens 2.8V ±10%, internal regulators digital analog supplies 85mW (including color processing) Sleep mode with maximum 100µA current wake less than 100msec. Power down mode with 10µA current. Input clock frequency converter Down sampling Video output format Video output interface Video synchronization Control interface Internal supports input clocks 3.6MHz 32MHz. Down sampling with filter both dimensions. YCrCb422 YUV422 RGB444 RGB565 RGB666 JPEG; 8/9/10-bit parallel camera interface 8/9/16/18 controller data interface Horizontal vertical sync signals and/or CCIR656 header 6-bit host interface compatible interface UART Used also read JPEG images Variable QVGA JPEG encoder/decoder acceleration On-chip 64Kbyte SRAM store compressed images On-chip 48Kbyte SRAM store firmware Progressive readout; vertical horizontal inversion options From line frame duration with 250ns granularity. Separate gain each three color components Enhanced dynamic range Black level, faulty pixel correction, color correction, auto white balance, auto exposure, anti-flicker, gamma correction, color suppression. Lens shading correction Digital zoom Contrast, brightness, saturation, sharpening, windowing, lookup table Camera module package with lens, optional flex cable board-toboard connector 4V/lux-sec (including gain) Table TC5747 Specifications
Frame rate JPEG JPEG frames memory Program memory Readout control Exposure control Dynamic range control Image enhancement Anti shading Zoom Image controls Camera module Sensitivity
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TC5747 Data Sheet Single Chip CMOS Imager
Compact 24-pin Camera Module
24-pin camera module option uses 8/9-bit parallel video interface.
Name SCLK AGND AVDD28 RESET# CLK_IN DGND DOUT[1]/CSDAT# DYUV[0] DYUV[1] DYUV[2] DYUV[3] DYUV[4] DYUV[5] DYUV[6] DYUV[7] DSDAT VCLKOUT/ DSCLK VALIDH DSFRM VALIDV DVDD28 SDIN Parallel video interface clock output/ Serial output clock Horizontal VALID output Write active Serial Output Frame signal Vertical VALID output signal interrupt output Frame start 2.8V digital circuits -compatible bi-directional data signal. Open-drain type. Chip operation modes [PS1, PS2]: Reset Full operation Reserved Reserved Module noise shield pin, Activates white light condition
Description I2C-compatible input clock signal generated master. Analog circuits ground. 2.8V supply analog circuits. Asynchronous reset input signal; active 16-32 clock input crystal input Digital circuits ground. data /External Chip Select data bus; active Output video data Output video data Output video data Output video data Output video data Output video data i2c_toggle Selects between addresses during RESET#
Output video data Output video data Serial Output Data signal
Reserved control
output chip select options selected through wire bonding
Table 24-pin Module List
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
Functional Description
figure below shows main functional blocks TC5747 basic signal flow.
Figure TC5747 Functional Block Diagram
CONT
CONT unit controls TC5747 units central programming bus. operation synchronized with frame image sequence through several interrupt sources. directly accessed serial interfaces
RCLK
RCLK unit generates RESET CLOCK signals various units.
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TC5747 Data Sheet Single Chip CMOS Imager
IMGA
IMGA unit controls image array analog processing unit. produces various timing controls, performs "Mirror" transformations "Fixed Pattern Noise" corrections. After receiving array pixels (the output) performing required corrections offsets, data sent YUVR unit processing, unit Bayer output.
YUVR
YUVR unit transforms Bayer data received from IMGA unit into data applying several image reconstruction correction algorithms. Demosaicing, dynamic range enhancement, digital gain, filter downscaling, sharpening blurring, color correction, gamma correction, conversion, YUV-to-RGB conversion cropping display performed YUVR unit. Resizing image done achieve target screen size with full field view.
JPEG
JPEG unit performs encoding decoding JPEG images. encode mode receives 4:2:2 data, compresses image into JPEG stream. JPEG compressed image stored that accessible CONT unit core interface. JPEG unit also configured send content output units, with optional ancillary data header checksum. decode mode, compressed code written Code memory, JPEG unit decodes into 4:2:2, 4:2:0 4:1:1 data.
4:2:0 4:1:1 formats interpolated into 4:2:2 format. data then sent YUVR unit resizing cropping. From YUVR unit decoded image sent Parallel Video Interface unit display.
Compression display ready image, after scaling overlay screen bitmap also supported. JPEG unit also output thumbnail image.
Parallel Video Interface (PVI) Serial Video Interface (SVI) units output interfaces TC5747 device. Each interface configured output several streams (Bayer, 4:2:2, RGB, JPEG). configured parallel video interface serial output interface.
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
Imager Address Generator
imager includes size pixel array, gain, double sampling, black pixel readout circuits ADC. address generator receives timing signals from control unit produces sequence signals pixel array exposure control, read reset operations. There several modes reading array content, enabling various image resolutions windowing down sampling. different modes, various modes power saving used. sized images read rate frames second. smaller images higher frame-rates, several working modes implemented.
Pixel Array Configuration
pixel array active pixels, surrounded four black columns each side black lines above black lines below active image array. This results total pixels.
Bayer Grid Configuration
Each pixel array covered color filter, create Bayer grid format: sensor operates rolling mode, which exposure readout processes linked. sampling each data performed integration time. After sampling selected-row data, reset. sampled again after reset double-sampling procedure. integration that starts again according exposure parameters. registers defines total size frame size array that read sent YUVR unit further processing. Another registers defines exposure time that required array.
Figure Bayer Grid Configuration
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TC5747 Data Sheet Single Chip CMOS Imager
2.10 Resolutions Frame Rates
following table summarizes possible resolutions frame rates that TC5747 produce. calculation modes assume input color-processing clock 32MHz. mode 16MHz clock assumed. analog clock rate varies according mode.
MODE (Full resolution) 32MHz rclk 8MHz pixel clock rclk cycles/pix Full power QVGA- down sample QVGA-down sample Table Analog Clock Rate Modes (reduced field view) (full field view) (reduced field view) MODE (MODE1with window) 32MHz rclk 8MHz pixel clock rclk cycles/pix Full power MODE (down-sample, only used) 32MHz rclk 8MHz pixel clock rclk cycles/pix Slightly reduced power MODE (down-sample with speed-up) 16MHz rclk 4MHz pixel clock rclk cycles/pix Significantly reduced power
2.11 Analog Processing
Analog processing includes separate gain control each color filtered pixel, dark pixel correction each color separately, dark black-offset correction, faulty pixel replacement 10-bit ADC.
2.12 On-chip Micro Controller
TC5747 fully controlled embedded microcontroller. Once firmware, which supplied TransChip, loaded, embedded microcontroller sets appropriate registers, runs automatic image processing algorithms. external host does need access TC5747 registers values, does need algorithm. easy (Application Programming Interface) provided adjust various camera controls. performed small host commands, which sent over serial interface (I2C UART), interpreted embedded microcontroller, perform specific camera control, other defined internal task. host commands include: Color adjustments (Brightness, contrast, saturation, etc) Image Format (size, mirror etc) Automatic algorithm enable parameters (Auto Exposure, AWB, Auto Flicker detection cancellation) concept host commands makes very useful, going forward compatible with TransChip sensor, since hardware dependent (namely need specific hardware registers.
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
TransChip supplies sample code, which shows upload firmware host commands (software API). sample includes needed header files. supplied firmware comes with preset default values various controls. Thus even single host commands performed firmware ensures that sensor running properly according preset default set. TransChip also supplies released version firmware. host commands fully detailed separate document.
2.13 Bayer Translation Unit (YUVR)
YUVR color-processing unit. unit's parameters mode registers loaded through control bus. Bayer image received from IMGA unit, processed YUVR unit, transferred unit output device. While processing image, statistics calculated YUVR unit. After completing processing image, YUVR unit produces interrupt CONT unit. YUVR thus signifies CONT that statistics current image ready, CONT read results through main control bus. YUVR unit receives Bayer grid input. each pixel, color values missing need reconstructed. input accuracy bits. YUVR unit reconstructs pixel, performs correction algorithms generates representation image. Digital color processing includes: demosaicing, dynamic range enhancement, digital gain, filter downscaling, sharpening blurring, flicker detection removal, color white balance correction, gamma correction, color suppression, zoom conversion, YUV-to-RGB conversion, down sample cropping display, formatting (6:6:6, 5:6:5, 4:4:4) performed YUVR unit. Zoom performed creating full resolution image from small region center image. small region blown target image size. missing pixels interpolated from original pixels using filter provide smooth appearance.
2.14 JPEG Compression Unit (JCOR)
JPEG unit receives 4:2:2 image data from YUVR unit, performs real-time JPEG compression. Byte memory used JPEG compression process. memory divided into Raster-to-Block operation buffer JPEG-code memory section. Bytes memory hold full VGA-sized compressed image compression ratio bits pixel. partition memory fully configurable. When higher compression ratio used, several images stored memory. example, when capturing VGA-sized image, three compressed images bits pixel stored Byte JPEG-code memory section. When capturing smaller image, smaller buffer required Raster-to-Block operation. Therefore larger JPEG-code memory section allocated support lower compression ratio.
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TC5747 Data Sheet Single Chip CMOS Imager
JPEG-compressed image transmitted either parallel video output interface serial video output interface. Alternatively, host read JPEG-compressed image from on-chip JPEGcode memory interface. JPEG unit optionally create also thumbnail image full resolution compressed image. JPEG unit also configured send contents output units, with optional ancillary data header checksum. JPEG unit also activated decompression mode. compressed code written Code memory, JPEG unit decodes into 4:2:2 data. data then sent YUVR unit resizing cropping. From YUVR unit decoded image sent Parallel Video Interface unit display.
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
Reset Clock
Power Modes
chip operation controlled bits [PS1, PS2]:
Chip operation modes [PS1, PS2]:
Startup Full operation Sleep Power
down
3.1.1
Startup
camera powers start mode Then moves full operation mode 3.1.2 Bypass
enter bypass mode, send host command power save, then provide standby mode switch input clock. Bypass mode power consumption 60µA. This minimum power consumed minimal power-supply digital regulator. Contents memories registers maintained. host access during bypass mode. return full operation from standby mode, switch input clock wait clock stability, then send host command full operation. 3.1.3 Power Down
enter power down mode, send host command power down, then provide power down mode Power down mode consumes less than 10µA. return full operation from power down mode: provide full operation mode wait clock stability, then send host command full operation load camera program.
Configurations
on-chip configured supply internal working clock signal several modes: Bypass mode internal clock identical frequency input clock.
mode, support internal clock range 24-36MHx internal clock input clock, support frequency input (3-4MHz input) internal clock input clock, support frequency input (8-9MHz input) internal clock input clock, support medium frequency input (13-16MHz input) 1.5x internal clock 1.5x input clock, support high frequency input (20-24MHz input)
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TC5747 Data Sheet Single Chip CMOS Imager
Each output units, have serial clock whose frequency multiple input clock. Each clock, rclkp rclks configured separately.
Device Initialization Sequence
PS1/2 RESET_N Bypass (Default) Active PowerDown Startup Full
Enter mode mode
CLKIN
lock time PLL_mode required working multiply
BYPASS PLL_PD RCLK
Figure Initialization Sequence
Initialization sequence includes following steps:
After system power-up, Power Save pins should into Startup mode. Clock input RESET_N should activated. After Regulators' wake time, Power Save pins should into Full-on mode.
RESET_N
deactivated.
mode should set.
After lock time, Bypass mode deactivated.
When working Bypass mode, steps skipped.
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
TC5747MF24L Interfaces
UART control interface Parallel Video Interface (PVI) Serial Video Interface (SVI)
TC5747MF24L chip following interfaces:
Serial Interface
4.1.1 Overview
interface two-wire bi-directional serial bus. TC5747 operate slave device only. Both wires (SCL SDA) connected positive supply pull-up resistor, when free both lines high. output stage device must have open-drain open collector type cell that wired-AND function between devices that connected performed. Each device recognized unique 7-bit address. address allocated TC5747-B0 0x47. When performing write operations, 0x8E. Read operation 0x8F. summarize:
Address 0x47 Write 0x8E
Read 0x8F
Note: Some operating systems automatically address. address TC5747-A0 0x47. control byte order transactions provided through setting register.
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TC5747 Data Sheet Single Chip CMOS Imager
4.1.2
Mode Operation
master, typically host DSP, initiates access TC5747 device. master activates START condition, passes address requested device along with type access (read write start byte). requested device replies with acknowledge (ACK). host then perform many transactions wishes, until host activates STOP condition. considered free after STOP condition. data must stable during high period clock (SCL) shown figure below. Only host change data while high. high-to-low transition marks START condition, low-to-high STOP condition.
Figure Interface START STOP Conditions
master device activates START condition, sends first byte data that contains 7-bit address, direction (R/W#, read, write). addressed device answers pulling down line acknowledge procedure.
Figure Protocol
TC5747 expects first bytes after address byte register address first register that read written host. Programming done host commands level which translated into series register level commands. When writing registers TC5747, following bytes data bytes. data each READ WRITE access bytes long. TC5747 performs auto increment until STOP condition identified. Auto increment performed when initial address address space that allocated On-Chip-Memories. This address space reserved tables, where multiple bytes written single address. When reading registers from TC5747, register address bytes) should followed repeated START condition, device address, R/W# equal change mode from write (address) read (data). sequence loading reading registers described figure below. colored boxes represent host-to-slave data transfer. clear boxes represent slave-to-host data transfer.
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
Figure Host-Write Access
Figure Host-Read Access
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TC5747 Data Sheet Single Chip CMOS Imager
Figure Host-Read Multiple Accesses
host should activate STOP condition direction change needed.
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
Parallel Video Interface (PVI)
generates video output TC5747. interface consists vertical frame-start signal 10-bit parallel data with clock qualify signals. supports parallel serial modes operation. 4.2.1 Parallel Mode Operation
produces clock signal (the CLK_OUT pin), 10-bit data bus, DOUT[9:0] qualifying signals that synchronous that clock. each determining edge CLK_OUT, single data byte transferred data bus, qualified VALIDH signal.
Figure Qualification Signal Timing
Valid data qualified VALIDH signal. VALIDH signal activated only when image data sent parallel interface. inactive when dark lines read, during vertical blank period. VALIDH signal configured qualify only valid image data, qualify optional Start-of-line End-of-line markers.
Figure Vertical Horizontal Qualify Signals
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TC5747 Data Sheet Single Chip CMOS Imager
DOUT[9:0] carries either Bayer grid data, 4:2:2 output data, data (RGB565, RGB666 RGB444) JPEG code according TCIF_OUTPUT_FORMAT host command. Bayer Grid data left-justified. 10-bit Bayer resides DOUT[9:0] 9-bit Bayer resides DOUT[9:1] 8-bit Bayer resides DOUT[9:2] 8-bit data resides DOUT[9:2] output pads, annotated DYUV[7:0]. 8-bit RGB565 RGB444 data resides DOUT[9:2] output pads. 9-bit RGB666 data resides DOUT[9:1] output pads.
RGB666
also transmitted using clock cycles DOUT
6-bit RGB666 (3-word mode) data resides DOUT[9:4] output pads. 8-bit JPEG data resides DOUT[9:2] output pads. 2-word output formats, RGB444, 666, data packed into words:
RGB444: RGB565: RGB666:
{Blue[3:0], 0x0} {Green[2:0], Blue[4:0]} {Green[2:0], Blue[5:0]} {Red[4:0], {Red[5:0],
{Red[3:0],Green[3:0]} Green[5:3]} Green[5:3]}
3-word output formats, data sent words:
RGB666:
Green[5:0] Blue[5:0]
Red[5:0],
active line timing depicted diagrams below. diagram below shows active data line where optional Start-of-line End-of-line markers omitted:
Figure Bayer Output Format
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
Figure Output Format
Figure Output Parallel Video Output Interface
output clock rate 2-word output double output clock rate Bayer output. output clock rate 3-word RGB666 double output clock rate output. When sending data Bayer-grid format, RED" line will always first line frame. 4.2.2 External Chip-Select
mode selected where data floated driven according external chip-select input controlled CSDAT# pin. CSDAT# active-low, i.e. when DOUT[9:1] DYUV[7:0] pins driven, when CSDAT# high these outputs tri-state position. VALIDH, VALIDV VCLKOUT pins affected CSDAT# pin. 4.2.3 Qualified Clock Mode
TC5747 supports mode where VCLKOUT active when there active data parallel interface.
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TC5747 Data Sheet Single Chip CMOS Imager
4.2.4
VALIDH Configured
VALIDH configured work WRITE signal applications requiring that video data being written into device. polarity programmable. data marked valid only when VALIDV active. data should sampled trailing edge VALIDH pin.
Figure VALIDH Write signal, Active
Figure VALIDH Write Signal, Active High
4.2.5
Frame-Rate Control
CONT unit uses c_outframe signal control frame rate. enables disables output full frame. When output disabled, VALIDH VALIDV output signals stuck inactive state. data output holds background value throughout disabled frame time.
Figure Frame Rate Control
c_outframe signal changes im_frame. decision send skip frame made clock cycle that follows im_frame signal.
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
4.2.6
4.2.6.1
Data
General
type data (Bayer, RGB, YCrCb 4:2:2 JPEG) output from TC5747 programmable through TC5747 programming registers, using host commands. type data also defines frequency TC5747's output clock signal.
4.2.6.2 Bayer Output
When Bayer output selected, data volume byte pixel. Data-Markers added, more bytes line must taken into consideration image buffer that allocated application. There types Bayer data lines: RED" lines lines that carry Green Bayer components. Green data bytes interleaved. even numbered bytes Green, numbered bytes (1,3 2n+1) Red. BLUE" lines lines that carry Blue Green Bayer components. Green Blue data bytes interleaved. even numbered bytes Blue, numbered bytes (1,3 2n+1) Green. When sending data Bayer-grid format, RED" line will always first line frame.
4.2.6.3 YCrCb 4:2:2 Output
When YCrCb 4:2:2 output selected, data volume bytes pixel. Data-Markers added, more bytes line must taken into consideration image buffer that allocated application. data YCrCb 4:2:2 output format ordered several configurations, according setting Color_order bits video output control registers:
SOL, Yn-2, Un-2, Yn-1, Vn-2, SOL, Yn-2, Vn-2, Yn-1, Un-2, SOL, Un-2, Yn-2, Vn-2, Yn-1, SOL, Vn-2, Yn-2, Un-2, Yn-1, 4.2.6.4 RGB565 Output
When RGB565 output selected, data volume bytes pixel. Output data transmitted same manner frequency YCrCb 4:2:2 output format, DOUT[9:2]. first byte each pixel carries bits color component, Green. second byte carries Green color component, bits Blue color component.
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TC5747 Data Sheet Single Chip CMOS Imager
4.2.6.5
RGB666 Output
When RGB666 output selected, data volume 9-bit words" pixel. modes selected RGB666 data.
Two-transfers Mode
When RGB666 output selected, data volume 9-bit words" pixel. extra pixels required beyond VGA/QVGA size. output data transmitted same manner frequency YCrCb 4:2:2 output format, DOUT[9:1]. first byte each pixel carries bits color component, Green. second byte carries Green color component, bits Blue color component.
Three-transfers Mode
When three-transfer RGB666 output selected, data volume three 6-bit words" pixel. extra pixels required beyond VGA/QVGA size. output data transmitted DOUT[9:4]. order transmission Red, Green Blue.
Figure RGB666 Three-transfers Mode
output data transmitted double frequency YCrCb 4:2:2 output format, consecutive clock cycles carry valid data, fourth clock cycle skipped. valid data active this clock cycle, VALIDH inactive.
4.2.6.6 RGB444 Output
When RGB444 output selected, data volume bytes pixel. output data transmitted same manner frequency YCrCb 4:2:2 output format, DOUT[9:2]. first byte each pixel carries bits color component, bits Green. second byte carries bits Blue color component DOUT[9:6], padded zeros DOUT[5:0].
4.2.6.7 JPEG Output
When JPEG output selected, compressed code sent parallel data bus, qualified VALIDH. support ancillary data format defined 1364 standards, optional ancillary data packet header added before each consecutive packet bytes JPEG code. Checksum byte added following data bytes. last packet" JPEG code contain less than packet number bytes, payload byte" packet header reflects actual size.
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
4.2.7
Data Markers
Extra optional data markers inserted beginning each image line. user select between TransChip-specific markers, markers that conform standard.
4.2.7.1 TransChip Markers
Timing signal" Marker defined standard sequence four bytes, first three bytes holding reserved values fourth byte composed collection bits whose function defined standard. TransChip markers utilize format markers defined standard, redefines bits last marker byte. There four types markers: Start First Line marker This marker precedes data first line frame. Start Line Marker This marker precedes data each line frame, except first line. When Bayer output mode selected, marker content differentiates between red" line blue" line respectively). Last Line Marker This marker immediately follows data last line frame. Line Marker This marker immediately follows data each line frame, except last line. markers bytes long. first bytes markers identical, annotate marker header. marker content where different each marker type.
Marker
SOFL SOLR (YCrCb "red" line) SOLB ("blue" line) EOLL
Marker Header 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Marker content DOUT[9:2] DYUV[7:0] 0xC7 0x80 0xAB 0xDA 0x9D
Table TransChip Markers
Bits [7:4] Marker-content byte carry marker information: Always avoid 0x00 code Special frame markers Bayer line color" Red, Blue) End/Start bit, Start-of-line marker, End-of-line Bits [3:0] Marker-content byte provide parity check capability, allowing one-bit errors corrected, two-bit errors detected, according ITU-656-4 Standard.
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TC5747 Data Sheet Single Chip CMOS Imager
4.2.7.2
Markers
Timing signal" Marker defined standard sequence four bytes, first three bytes holding reserved values fourth byte composed collection bits whose function defined standard. Bits [7:4] Marker-content byte carry marker information: Always avoid 0x00 code field field blank active video line indication active, blank) End/Start bit, Start-of-line marker, End-of-line Bits [3:0] Marker-content byte provide parity check capability, allowing one-bit errors corrected, two-bit errors detected, according ITU-656-4 Standard. When adhering bit-definition ITU-656 standard, there need distinguish between consecutive frames, either inserting markers least blank line between frames, toggling field every frame start. supports following options.
Marker
active blank active blank active blank active blank
Field
Marker Header 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0xFF 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00 0x00
Marker content DOUT[9:2] DYUV[7:0]
Table Markers
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
4.2.7.3
Avoiding Marker Emulation
When Send-Markers mode enabled, care taken avoid marker-emulation inside data itself. When YCrCb 4:2:2 output mode selected, there contention between marker header contents transmitted data, because data values limited range 16-235, data values limited 16-240 range. 0x00 0xFF values never occur inside image data values. When Bayer output selected, data modified, that 0xFF 0x00 values removed from data content, replaced their nearest allowed values (0xFE 0x01 respectively). When RGB565 output selected, data modified, case Bayer output. 0xFF 0x00 values removed from data content, replaced their nearest allowed values. first byte RGB565 replaced 0xF7 0x08. second byte RGB565 replaced 0xFE 0x01. When RGB666 output selected, data modified, case Bayer output. 0xFF 0x00 values removed from data content, replaced their nearest allowed values. When RGB444 output selected, data modified, case Bayer output. 0xFF 0x00 values removed from data content, replaced their nearest allowed values. first byte RGB444 replaced 0xEF 0x10. second byte RGB444 replaced 0xF0 0x01. JPEG code cannot modified. However, there need modification Ancillary format used JPEG transmission. 4.2.8 Ancillary Data Format
ITU-1364 defines ancillary data format that transmitted during blank lines video, defined standard. Immediately following blank line Timing signal" ancillary data packet added. ancillary data header detected instead blank video data, defined standard sequence 0x80 0x10), ancillary data extracted. ancillary data header defined sequence bytes:
0x00 0xFF 0xFF Data-SIZE/4
header followed data bytes). Check-sum byte follows data last byte packet. ancillary header checksum optionally produced JPEG unit. does differentiate between header JPEG code.
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TC5747 Data Sheet Single Chip CMOS Imager
4.2.9
Serial Output Mode
Transmitted data size Serial output mode bits transmitted word" Bayer output provides bits pixel, output provides bits pixel. bytes sent with first, last. During continuous transfer, byte immediately follows byte (N-1). TC5747 serial output interface configured work different modes: Clock-qualify mode wire interface with clock output data signals. TC5747 acts master interface. activates serial clock signal when there valid data sent out.
mode three wire interface, with clock, output data frame signals. TC5747 acts master interface, producing three signals.
Clock-Qualify Mode
4.2.9.1
serial interface consists pins: DSCLK Data Serial Clock output rate data output TC5747 generates DSCLK signal from general clock input signal.
DSDAT
Serial Data output pin.
TC5747 acts master interface. activates serial clock signal when there valid data sent out. Serial Clock Polarity Clock inactive zero Serial Clock Phase Drive data positive edge Serial clock signal (DSCLK/2), latch negative edge
Figure Serial Data-Out Interface x2_clk_out
Figure Serial Data-Out Interface x2_clk_out
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
4.2.9.2
Mode
serial interface consists three pins:
DSCLK Data DSDAT DSFRM
Serial Clock output
Serial Data output pin. Frame signal early-frame mode
TC5747 acts master interface. activates Frame signal clock period before there valid data sent out. Transfer datum size configurable. There three options: Transfer datum size single byte. Transfer datum size single line (size according output image size output mode). Transfer datum size single image. This configuration used only mode that combines SSI-mode with clock-qualify mode.
DSFRM Signal
DSFRM signal notifies transfer complete data unit. There three configurations, described below.
Single Byte Transfer Mode
bits transfer byte sent eight following effective edges DSCLK signal. When last byte sent out, DSFRM signal active again. active, following byte transfer begins next effective edge DSCLK.
Figure Single Byte Transfer Mode Image-line Transfer Mode
this mode, DSFRM activated clock before continuous transfer complete image line. Transfer size should configured receiving side according image line size, taking into consideration markers, used.
Frame Transfer Mode
this mode, DSFRM signal activated once frame, clock cycle before first byte image transferred out. DSFRM signal duration also configurable, clock cycle duration, active until last byte data transfer transmitted. second mode used generate interrupt inside receiving device, once complete data been transferred.
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TC5747 Data Sheet Single Chip CMOS Imager
DSCLK Output
DSCLK output configured continuous gated. gated option should used when DSFRM Frame-transfer mode.
Serial Video Interface
TC5747 Serial Video interface unit identical unit described above, with exceptions: Supports only serial interface Support also input data. data input controlled through I2C. addition input direction provides high speed input serial interface decompression JPEG images.
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
High Level Programming
TC5747 series products come with flexible software (Applications Program Interface) integration product interfacing wide range hosts. based defined host commands. TC5747 controlled embedded microcontroller. microcontroller runs firmware that supplied TransChip. microcontroller receives host commands, executes them perform various camera control functions.
Firmware Loading
microcontroller firmware (program) loaded through host interface. (When using UART control, firmware loaded either using interface UART interface). Once program loaded, microcontroller sets registers controls entire chip according firmware preset defaults according host commands which microcontroller receives through control interfaces.
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TC5747 Data Sheet Single Chip CMOS Imager
AC/DC Specifications
TC5747 chip excels power consumption
Absolute Maximum Ratings
Symbol
Parameter supply Voltage Storage Temperature Table Absolute Maximum Ratings
4.0V 70oC
Recommended Operating Conditions
Symbol
Parameter supply Voltage 2.8V nominal Operating Temperature Table Recommended Operating Conditions
2.52
3.08V 60oC
Electrical Characteristics
Symbol
Characteristic Input Hi-Volt Input Hi-Volt Input Low-Volt Input Low-Volt Input Hi-Volt Input Low-Volt
Condition
Specifications 2.0V
0.8V
VIL2 IDDmax II/Ioz
2.4V 0.4V 13.3mA 19.4mA 15mA 10uA
Supply current working conditions Input leakage/ Output tristate leakage
mode,
Table Electrical Characteristics
pins except clk_in clk_in
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
Parallel Video Output Clock Qualified Mode Characteristics
Figure Parallel Video Output Clock Qualified Mode Parameter
Description Data setup before effective edge VALIDH
Specifications
Units
Table Parallel Video Output Clock Qualified Mode Characteristics
Results depend device frequency mode. results this table 32MHz, clk_in.
Parallel Video Output Camera Interface Mode Characteristics
Figure Parallel Video Output Camera Interface Mode Parameter
Description Data setup before effective edge VCLKOUT
Specifications
Units
Table Parallel Video Output Camera Interface Mode Characteristics
Results depend device frequency mode. results this table 32MHz, clk_in.
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TC5747 Data Sheet Single Chip CMOS Imager
Parallel Video Output Interface Characteristics
VCLKOUT VALIDH/ VALIDV DOUT[9:0]
Figure Parallel Video Output Interface Signals
Parameter
Description Data setup before effective edge
VCLKOUT
Units nsec nsec
Table Parallel Video Output Interface Characteristics
Serial Video Output Interface Characteristics
Figure Serial Video Output Interface Signals Parameter
Tsersu Tserh
Description Data setup (DSDAT DSFRM) before negative edge DSCLK. Data hold (DSDAT DSFRM) before negative edge DSCLK.
Units nsec nsec
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
Serial Video Output Clock Qualified mode Characteristics
Figure Serial Video Output Clock Qualified mode Parameter
Tsersu Tserh
Description Data setup (DSDAT DSFRM) before negative edge DSCLK Data hold (DSDAT DSFRM) before negative edge DSCLK.
Specifications
Units
Table Serial Video Output Clock Qualified mode Characteristics
Results depend device frequency mode. results this table 32MHz, clk_in.
Serial Video Output mode Characteristics
Figure Serial Video Output mode Param
Tsersu Tserh
Description Data setup (DSDAT DSFRM) before negative edge DSCLK Data hold (DSDAT DSFRM) before negative edge DSCLK
Specifications
Units
Table Serial Video Output mode Characteristics Results depend device frequency mode. results this table 32MHz, clk_in.
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TC5747 Data Sheet Single Chip CMOS Imager
6.10 I2C-Compatible Interface Characteristics
Figure C-Compatible Interface
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
Parameter
Fmax Tcyc Tstsu Tsth Tisu Tpsu Tosu
Description Maximum SCLK frequency
SCLK cycle duration
Specifications 2500
Units
Start condition SCLK setup time Start condition SCLK hold time
SDIN input hold time SDIN input setup time
Stop condition SCLK setup time
SDIN output hold time SDIN output setup time
Table I2C-Compatible Interface Characteristics
Note: Data entered calculated 400KHz SCLK frequency.
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TC5747 Data Sheet Single Chip CMOS Imager
Mechanical Electrical Drawings
TC5747MF24L 24-pin Package
Following mechanical drawing TC5747MF24L 24-pin module.
Figure TC5747 24-pin Module Mechanical Drawing
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TC5747 Preliminary Data Sheet Single Chip CMOS Imager
Figure TC5747 24-pin Module Mechanical Drawing Continued
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TC5747 Data Sheet Single Chip CMOS Imager
Lens Specification
Characteristic Material Structure Effective Focal Length Focal Range Number Angle View (FOV) Lens module Heat resistant plastic Three element (one glass plastic) 3.72 40cm infinity Diagonal Horizontal Vertical Focus Filter Resolution (MTF) Factory fixed focused Included 0.47 cy/mm on-axis 0.40 cy/mm Vertical 0.30 cy/mm Horizontal 0.27 cy/mm Diagonal Relative Illumination 100% On-Axis Vertical Horizontal Diagonal Distortion Module Height +0.1 -0.2mm Table Lens Specifications
TransChip

Version Products specifications discussed herein evaluation refer

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