SINGLE-CHIP 8-BIT MICROCONTROLLER High performance CMOS Operation
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MX10FMAXDPC MX10FMAXDQC
SINGLE-CHIP 8-BIT MICROCONTROLLER
High performance CMOS Operation Voltage 40MHz operation (3.5MHz 40MHz) Three 16-bit timer/counters Bytes on-chip data Kbytes on-chip Flash memory Programmable lines interrupt Sources Code protection priority levels Power saving Idle power down modes external program memory space external data memory space Four 8-bit ports Full-duplex enhanced UART compatible with standard 80C51 80C52
GENERAL DESCRIPTION
single-chip 8-bit microcontroller manufactured MXIC's advanced CMOS process. This device uses same powerful instruction set, same architecture, pin-to-pin compatible with existing 80C51. added features make even more powerful microcontroller applications that require clock output, up/down counting capabilities such motor control. also more versatile serial channel that facilitates multi-processor communications.
CONFIGURATIONS
PDIP PLCC
(T2) P1.0 (T2EX) P1.1 P1.2 P1.3 P1.4 P1.5 P1.6 P1.7 RESET (RXD) P3.0 (TXD)P3.1 (INT0) P3.2 (INT1) P3.3 (T0) P3.4 (T1) P3.5 (WR) P3.6 (RD) P3.7 XTAL2 XTAL1
XTAL2
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XTAL1
P0.0 (AD0) P0.1 (AD1) P0.2 (AD2) P0.3 (AD3) P0.4 (AD4) P0.5 (AD5) P0.6 (AD6) P0.7 (AD7) PSEN P2.7 (A15) P2.6 (A14) P2.5 (A13) P2.4 (A12) P2.3 (A11) P2.2 (A10) P2.1 (A9) P2.0 (A8)
P1.4
P1.3
P1.2
P1.1
P1.0
P0.0
P0.1
P0.2
P1.5 P1.6 P1.7 P3.0 N.C. P3.1 P3.2 P3.3 P3.4 P3.5
P0.3 P0.4 P0.5 P0.6 P0.7 N.C. PSEN P2.7 P2.6 P2.5 P2.4
MX10FMAX
MX10FMAX
P3.6 P3.7
P2.0 P2.1 P2.2 P2.3 N.C.
N.C.
MX10FMAXDPC MX10FMAXDQC
BLOCK DIAGRAM
P0.0-P0.7 P2.0-P2.7
PORT DRIVERS PORT DRIVERS
ADDR. REGISTER
PORT LATCH
PORT LATCH
STACK POINTER TMP1
PROGRAM ADDR. REGISTER
TMP2 REGISTER
BUFFER
INCREMENTER T0/T1/T2 SFRs TIMERS
PROGRAM COUNTER
PSEN TIMING CONTROL
INSTRUCTION REGISTER
DPTR
PORT LATCH
PORT LATCH
OSC.
PORT DRIVERS
PORT DRIVERS
XTAL1
XTAL2
P1.0-P1.7
P3.0-P3.7
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MX10FMAXDPC MX10FMAXDQC
Port emits high-order address byte during fetches from external Program Memory during accesses external Data Memory that 16-bit addresses (MOVX @DPTR). this application uses strong internal pullups when emitting 1's. During accesses external Data Memory that 8-bit addresses (MOVX @Ri), Port emits contents Special Function Register. Port Port 8-bit bidirectional port with internal pullups. port output buffers drive inputs. Port pins that have written them pulled high internal pullups, that state used inputs. inputs, Port pins that externally pulled will source current (IIL, data sheet) because internal pullups. Port also serves function various special features 8051 Family, listed below Port P3.0 P3.1 P3.2 P3.3 P3.4 P3.5 P3.6 P3.7 Alternate Function (serial input port) (serial output port) INT0 (external interrupt INT1 (external interrupt (Timer external input) (Timer external input) (external data memory write sttobe) (external data memory read strobe)
PROCESS INFORMATION
This device manufactured MXIC CMOS process.
DESCRIPTIONS
Supply voltage. Circuit ground. Port Port 8-bit, open drain, bidirectional port. output port each sink several inputs. Port pins that have written them float, that state used high-impedance inputs. Port also multiplexed low-order address data during accesses external Program Data Memory. this application uses strong internal pullups when emitting 1's, source sink serveral inputs. Port Port 8-bit bidirectional port with internal pullups. port output buffers drive inputs. Port pins that have written them pulled high internal pullups, that state used inputs. inputs, Port pins that externally pulled will source current (IIL, data sheet) because internal pullups. additional, Port serves functions following special features MX10C805X Port P1.0 P1.1 Alternate Function (External Count Input Timer/ Counter Clock-Out T2EX (Timer/Counter Capture/Reload Trigger Direction Control)
Reset input. high this machine cycles while oscillator running resets device. port pins will driven their reset condition when minimum VIHI voltage applied whether oscillator running not. internal pulldown resistor permits power-on reset with only capacitor connected VCC. Address Latch Enable output pulse latching byte address during accesses external memory. normal operation emitted constant rate oscillator frequency, used external timing clocking purposes. Note, however, that pulse skipped during each access external Data Memory.
Port Port 8-bit bidirectional port with internal pullups. port output buffers drive inputs. Port pins that have written them pulled high internal pullups, that state used inputs. inputs, Port pins that externally pulled will source current (IIL, data sheet) because internal pullups.
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MX10FMAXDPC MX10FMAXDQC
desired, operation disabled setting location (PCON). With this set, weakly pulled high. However, disable feature will suspended during MOVX MOVC instruction, idle mode, power down mode. disable feature will terminated reset. When disable feature suspended terminated, will longer pulled weakly. Setting ALE-disable affect micrcontroller external execution mode. Throughout remainder this data sheet, will refer signal coming pin, will referred pin. PSEN Program Store Enable read strobe external Program Memory. When MX10FMAX executing code from external Program memory, PSEN activated twice each machine cycle, except that PSEN activations skipped during each access external Data memory. EA/VPP Extrernal Access enable. must strapped order enable twiceto fetch code from external Program Memory locations 0000H 0FFFFH. will internally latched reset. should strapped internal program executions. XTAL1 Input inverting oscillator amplifier. XTAL2 Output from inverting oscillator amplifier. OSCILLATOR CHARACTERISTICS XTAL1 XTAL2 input output, respectively, inverting amplifier which configured on-chip oscillator, shown Figure Either quartz crystal ceramic resonator used.
XTAL2 XTAL1
drive device from external clock source, XTAL1 should driven, while XTAL2 floats, shown Figure There requirememts duty cycle external clock signal, since input internal clocking circuitry through divide-by-two flip-flop, minimum maximum high times specified data sheet must observed. external oscillator encounter much load XTAL1 when starts This interaction between amplifer feedback capacitance. Once external signal meets specifications capacitance will exceed
XTAL2
EXTERNAL OSCILLATOR SIGNAL
XTAL1
Figure External Clock Drive Configuration
equal less than Crystal Ceramic Resonators,contact resonator manufacture. Figure Oscillator Connections
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MX10FMAXDPC MX10FMAXDQC
IDLE MODE user's software invoke Idle Mode. When microcontroller this mode, power consumption reduced. Special Function Registers onboard retain their values during Idle, processor stops executing instructions. Idle Mode will exited chip reset enabled interrupt occurs.
ABSOLUTE MAXIMUM RATING*
Ambient Temperature Under Bias Storage Temperature Voltage Other Power Dissipation 70°C -65°C +150°C -0.5V +6.5V 15mA 1.5W
(Based PACKAGE heat transfer limitations, device consumption) Table Status External Pins during Idle Power Down Mode Idle Idle Power Down Power Down Program Memory Internal External Internal External PSEN PORT0 Data Float Data Float PORT1 Data Data Data Data PORT2 Data Address Data Data PORT3 Data Data Data Data
POWER DOWN MODE
save even more power, Power Down mode invoked software. this mode, oscillator stopped instruction that invoked Power Down last instruction executed. on-chip Special Function Registers retain their values until Power Down mode terminated. MX10C805X either hardware reset external interrupt cause exit from Power Down. Reset redefines SFRs does change on-chip RAM. external interrupt allows both SFRs on-chip retain their values. properly terminate Power Down, reset external interrupt should executed before restored normal operating level, must held active long enough oscillator restart stabilize (normally less than ms). With external interrupt, INT0 INT1 must enabled configured level-sensitive. Holding restarts oscillator bringing back high completes exit. Once interrupt serviced, next instruction executed after RETI will following instruction that device into Power Down.
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PROGRAMMING SPECIFICATION
MX10FMAX programming modes, which depends P2.6 pin. P2.6 then parallel programming mode, not, then serial programming mode. Parallel Programming Mode
4.5/5/6.25V 12.5~13V,5/6.25/4.5V A[15:0] MS[2:0] PSEN P3.3 P2.7 P2.6 P3[5:4],P2[5:0],P[7:0] P3.7,P3.1, P3.0 P0[7:0] Q[7:0] XTAL2 XTAL1 4~6MHz
NAME P1.0 P1.7 P2.0 P2.5, P3.4 P3.5 P0.0 P0.7 P3.3 P2.7 P3.7, P3.1, P3.0 Notice speed progamming
SYMBOL A13, ~A15
FUNCTION Input order address bits Input high order address bits Data Input/Output Chip Enable Input Output Enable Input Write Enable Input Program Supply Voltage, 12.5 ~13Volts Flash Mode Selection Power Supply Voltage (+5V) Ground
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5.1.1 Table parallel programming modes External Standby Read Signature Program Program Verify Lock Lock Lock verify Lock bits Erase verify LOCK bits Chip Erase Erase Verify Normal Read P3.3 P2.7 P3[5:4], P2[5:0], P1[7:0] P1.0=0 P1.0=1 address address address address P3.7, P3.1, P3.0 P0[7:0]
12.5~13V 12.5~13V 12.5~13V 12.5~13V 12.5~13V 6.25V 4.5V 12.5~13V 12.5~13V
6.25V 6.25V 6.25V 6.25V 6.25V 6.25V 4.5V 6.25V 4.5V
100us pulses 100us pulses 100us pulses 100us pulses 0.5sec pulse
MftID=C2H DID=F0H DATA DATA P0[3:1]= LOCK[3:1] P0[3:1]= LOCK[3:1] DATA DATA
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5.1.2 Timing Waveform Parallel Programming Mode
READ SIGNATURE NORMAL READ WAVEFORM
ADDRESS
A0=0 A0=1
P3.3
P2.7
P3.7 P3.1,P3.0
P0.7-P0.0
ID/Device
Read Signature
Normal Read
Mim. Max. unit
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MX10FMAXDPC MX10FMAXDQC
ERASE VERIFY FLOWCHART
START
Program array zero (0~64KB) LOCK
LOCK2 apply program pulses each byte LOCK bits without verifying them
VCC=6.25V VPP=12.5V
Chip erase (0.5
VCC=4.5V VPP=4.5V
Erase-verify LOCK
fail
VCC=4.5V VPP=12.5V
erase-verify array (0~64KB) pass
fail x=x+1 x=30
Pass device
Pass device
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ERASE ERASE VERIFY WAVEFORM
ADDRESS
DON'T CARE
ADDRESS
P0.7-P0.0
VPP=12.5~13V Erase verify array; VPP=4.5V Erase verify LOCK bits
DATA
P2.7
tVPS
P3.3
tCES
P3.7, P3.1,P3.0
011/101
Erase
Erase Verify Array LOCK bits
Mim. Max. unit
tVPS
tCES
0.45 0.55
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MX10FMAXDPC MX10FMAXDQC
PROGRAM PROGRAM VERIFY FLOWCHART
START
First Address
VCC=6.25V VPP=12.5V
Program (20~100us)
Program Verify
Fail x=x+1
X=20
Increment Address
Last Address
VCC=5V VPP=5V Normal Read Fail
Fail Device
Pass
Pass Device
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PROGRAM PROGRAM VERIFY FLOWCHART
ADDRESS
P0.7~P0.0
tVPS
P2.7
P3.3
tCES
P3.7, P3.1,P3.0
Program
Program Verify
Mim. Max. unit
tVPS
tCES
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PROGRAM LOCK BITS PROGRAM VERIFY LOCK BITS FLOWCHART
START
VCC=6.25V VPP=12.5V
Program (100us) VCC=6.25V VPP=6.25V
Program Verify Apply program pulses specified LOCK
Fail x=x+1
X=20
Fail Device
Pass Device
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PROGRAM LOCK BITS PROGRAM VERIFY LOCK BITS WAVEFORM
ADDRESS
DON'T CARE
P0.7~P0.0
P0.3~P0.1= lock[3:1]
tVPS
6.25V
P2.7
P3.3
tCES
P3.7, P3.1,P3.0
111/110/100
Program Lock Bit(#1/#2/#3)
Lock Verify
Mim. Max. unit
tVPS
tCES
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MX10FMAXDPC MX10FMAXDQC
OPERATING CONDITIONS
Symbol fOSC Description Ambient Temperature Under Bias Commerical Oscillator Frequency Units
CHARACTERISTICS (Over Operating Conditions)
parameter values apply devices unless otherwise indicated.
Symbol VIL1 VIH1 VOL1 Parameter Input Voltage Input Voltage Input High Voltage (Except XTAL1, RST) Input High Voltage (XTAL1, RST) Output Voltage (Note (Ports Output Voltage (Note (Port ALE, PSEN) Output High Voltage (Port ALE, PSEN) VOH1 Output High Voltage (Port External Mode) Logical Input Current (Ports Input leakage Current (Port Logical Transition Current (Ports Industrial PRST Pulldown Resistor Capacitance Power Supply Current: Active Mode Idle Mode MHz(70°C 5.5V) Power Down Mode MHz, 25°C (Note -750 VIN=VIL VIN=2V 0.75 0.75 IOL=3.2 (Note IOH=-10 IOH=-30 IOH=-60uA IOH=-80 IOH=-300 IOH=-800 VIN=0.4V IOL=1.6 (Note VCC+0.5 -0.5 VCC+0.9 (Note VCC-0.1 VCC-0.3 VCC+0.5 Unit Test Conditions
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NOTES: Capacitive loading Ports cause noise pulses above 0.4V superimposed VOLs Ports noise external capacitance discharging into Port Port pins when these pins change from applications where capacitive loading exceeds noise pulses these signlas exceed 0.8V. desirable qualify other signals with Schmitt Triggers, CMOS-level input logic. Capacitive loading Ports cause PSEN drop below specification when address lines stabilizing. Minimum Power Down Typicals based limited number samples guaranteed. values listed room temperature Under steady state (non-transient) conditions, must externally limited follows: Maximum port pin: 10mA Maximum 8-bit port: Port 26mA Ports 15mA Maximum total output pins: 71mA exceeds test condition, exceed related specification. Pins guaranteed sink current greater than listed test conditions.
MX10FMAX
MX10FMAX
(NC) CLOCK SIGNAL
XTAL2 XTAL1
(NC) CLOCK SIGNAL
XTAL2 XTAL1
other pins disconnected TCLCH TCHCL
other pins disconnected TCLCH TCHCL
Figure Test Condition, Active Mode
Figure Test Condition Idle Mode
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MX10FMAX
(NC)
XTAL2 XTAL1
other pins disconnected Figure Test Condition, Power Down Mode VCC=2.0V 6.0V
VCC-0.5 0.45V VCC-0.1 TCHCL TCLCX TCLCL Figure Clock Signal Waveform Tests Active Idle Modes. TCLCH TCHCL TCHCX TCLCH
EXPLANATION SYMBOLS
Each timing symbol characters. first character always (stands time). other characters, depending their positions, stand name signal logical status that signal. following list characters what they stand for. Address Clock Input Data Logic level HIGH Logic level LOW, PSEN Output Data signal Time Valid signal longer valid logic level Float example, TAVLL Time from Address Valid TLLPL Time from PSEN
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CHARACTERISTICS
(Over Operating Conditions, Load Capacitance Port ALE/PROG PSEN Load Capacitance Other Outputs min. max. (maximum operating frequency); tCK=clock period SYMBOL PARAMETER UNIT
EXTERNAL PROGRAM MEMORY TLHLL PULSE DURATION TAVLL ADDRESS SET-UP TIME TLLAX ADDRESS HOLD TIME AFTER TLLIV TIME FROM VALID INSTRUCTION INPUT TLLPL TIME FROM CONTROL PULSE PSEN TPLPH CONTROL PULSE DURATION PSEN TPLIV TIME FROM PSEN VALID INSTRUCTION INPUT TPXIX INPUT INSTRUCTION HOLD TIME AFTER PSEN TPXIZ INPUT INSTRUCTION FLOAT DELAY AFTER PSEN TAVIV ADDRESS VALID INSTRUCTION INPUT TPLAZ PSEN ADDRESS FLOAT TIME EXTERNAL DATA MEMORY TLHLL PULSE DURATION TAVLL ADDRESS SET-UP TIME TLLAX ADDRESS HOLD TIME AFTER TRLRH PULSE DURATION TWLWH PULSE DURATION TRLDV VALID DATA INPUT TRHDX DATA HOLD TIME AFTER TRHDZ DATA FLOAT DELAY AFTER TLLDV TIME FROM VALID DATA INPUT TAVDV ADDRESS VALID INPUT TLLWL TIME FROM TAVWL TIME FROM ADDRESS TWHLH TIME FROM HIGH HIGH TQVWX DATA VALID TRANSITION TQVWH DATA SET-UP TIME BEFORE TWHQX DATA HOLD TIME AFTER TRLAZ ADDRESS FLOAT DELAY AFTER
NOTE: maximun operating frequency limited minimum MHz.
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MX10FMAXDPC MX10FMAXDQC
External clock drive XTAL SYMBOL fCLK tCLCL tCHCX tCLCX tCLCH tCHCL PARAMETER clock frequency clock period HIGH time time RISE time FALL time cycle time (tCY tCK) VARIABLE CLOCK tCK-tCLCX tCK-tCHCX 0.75 UNIT
SERIAL PORT CHARACTERISTICS
Serial Port Timing Shift Register Mode 5V±10%; Tamb=0°C; Load Capacitance SYMBOL tXLXL tQVXH tXHQX tXHDX tXHDV PARAMETER Serial Port clock cycle time Output data setup clock rising edge Output data hold after clock rising edge Input data hold after clock rising edge Clock rising edge input data valid OSCILLATOR UNIT
EXTERNAL CLOCK DRIVE WAVEFORM
VCC-0.5 0.45V VCC-0.1 TCLCX TCHCL TCLCL TCHCX TCLCH
TESTING INPUT, OUTPUT WAVEFORMS
VCC-0.5 0.45V VCC+0.9 VCC-0.1
FLOAT WAVEFORM
VLOAD+0.1V VLOAD VLOAD-0.1V VOH-0.1V
TIMING REFERENCE POINTS
VOL+0.1V
Inputs during testing driven VCC-0.5V Logic 0.45V Logic "0". Timing measurements made Logic Logic "0".
timing purposes port longer floating when change from load voltage occurs, begins float when 100mV change form loaded VOH/VOL level occurs. IOL/IOH
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MX10FMAXDPC MX10FMAXDQC
EXTERNAL PROGRAM MEMORY READ CYCLE
TLHLL
TLLPL TAVLL TLHIV TPLIV TPLIP
PSEN
TPLAZ TLLAX TPXIX TPXIZ
PORT
TAVIV
INSTR
PORT
EXTERNAL DATA MEMORY READ CYCLE
TLHLL TWHLH
PSEN
TLLWL
TLLDL TRLRH
TAVLL TLLAX TRLDV TRLIZ
TRHDZ TRHDX
PORT
A0-A7 FROM
TAVWL TAVDV
DATA
A0-A7 FROM
INSTR.
PORT
P2.0-P2.7 A8-A15 FROM
A8-A15 FROM
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MX10FMAXDPC MX10FMAXDQC
EXTERNAL DATA MEMORY WRITE CYCLE
TLHLL TWHLH
PSEN
TLLWL TWLWH
TAVLL TLLAX TQVWX TQVWH TWHQX
PORT
A0-A7 FROM
TAVWL
DATA
A0-A7 FROM
INSTR.
PORT
P2.0-P2.7 A8-A15 FROM
A8-A15 FROM
SHIFT REGISTER MODE TIMING WAVEFORMS
INSTRUCTION
TXLXL
CLOCK
TXHQX TQVXH
OUTPUT DATA WRITE SBUF
TXHDV
TXHDX
INPUT DATA CLEAR
VALID
VALID
VALID
VALID
VALID
VALID
VALID
VALID
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MX10FMAXDPC MX10FMAXDQC
Package Information
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MX10FMAXDPC MX10FMAXDQC
Package Information PLCC
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