Bi-CMOS LV24010LP Compact Portable Equipment 1-Chip FM+

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Bi-CMOS LV24010LP Compact Portable Equipment 1-Chip FM+

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Ordering number ENA0466
Bi-CMOS
LV24010LP
Compact Portable Equipment
1-Chip FM+RDS Tuner
LV24010LP single-chip radio with tuner that requires absolutely external components. This design achieved combining Sanyo BiCMOS process technology, Sanyo packaging technology, filtering circuit technology developed Semiconductor Ideas Market (ItoM) B.V.
Functions
stereo decoder. Tuning. Standby. RDS.
Specifications
Maximum Ratings 25°C
Parameter Maximum supply voltage Symbol Maximum input voltage VIN1 VIN2 Allowable power dissipation Storage temperature Operating temperature Tstg Topr Conditions Analog block supply voltage Digital block supply voltage Clock, Data, NR-W Extenal_clk_in Ta70°C Ratings VDD+0.3 VDD+0.3 +125 unit
With 0.8mm3, glass epoxy substrate
Operating Conditions 25°C
Parameter Recommended supply voltage Symbol Operating supply voltage range Interface voltage Note: application voltage used must either equal value less (VIO VDD). Conditions Analog block supply voltage Digital block supply voltage Ratings unit
SANYO Semiconductor products described contained herein have specifications
SANYO Semiconductor assumes responsibility equipment failures that result from using products
that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest before using SANYO Semiconductor products described contained herein such applications. values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO Semiconductor products described contained herein.
N2206 20060921-S00002 71306 20060529-S00004 No.A0466-1/18
LV24010LP
Electrical Characteristics 25°C, 3.0V, 3.0V, measuring circuit specified, Soft Mute/Stereo
Parameter Current drain operation) ICCD Current drain standby) ICCD receive band F_range ICCA Symbol ICCA Conditions Measurement with input analog block, Monaural input Measurement pins with input digital block Measurement standby mode analog block Measurement pins standby mode digital block. receive characteristics;MONO: 80MHz,fm 1kHz, 22.5kHzdev. Note that Soft_stereo,Soft_and mute functions OFF. sensitivity Practical sensitivity Practical sensitivity (Reference) Demodulation output Channel balance Signal-to-noise ratio Total harmonic distortion 1(MONO) Total harmonic distortion 2(MONO) Field intensity display level Mute attenuation Mute-Att Input level which changes 60dBµV, output THD2 60dBµV, output, 75kHdev THD1 -3dB 60dBµV, 22.5kHzdev output standard, -3dB input -3dB. Input level with 30dB, Deemphasis 75µs open display Input level with 26dB, Deemphasis 75µs, terminal display 60dBµV, output 60dBµV, output output 60dBµV, output 60dBµV, output, 22.5kHdev 1.25 dBµV dBµV Ratings unit
receive characteristics; STEREO: 80MHz, 1kHz, 60dBµV, (22.5kHz), Pilot (7.5kHzdev) Separation Total harmonic distortion (Main) characteristics RDS_center frequency -3dB bandwidth fcen BW-3dB Adjustment accuracy RDS_VCO value. (Adjustment accuracy free_run frequency) Bandwidth 57KHZ Center frequency. Block4 register Bit3-2 (RDSBW) "11" guarantee value. Just Reference value Current drain Irds current value Enable/Disable (3.0) (7.0) 56.5 57.0 57.5 THD-ST L-mod, output output Main-mod (for input), output, IHF_BPF
output level when block register control register 3,2,1,0 "0010" other cases: IF_OSC frequency must adjust 140kHz with block register 05h. IF_CENTER value (block register 03h) applies same value IF_OSC. IF_BW value (block2, register 05h) applies setting value IF_OSC value. RDS_OSC frequency must adjust 114kHz with block register 07h. RDS_FLTDAC (block register 03h) value applies setting value RDS_OSC value.
No.A0466-2/18
LV24010LP
Interface Block Allowable Operation Range +70°C,
Parameter Supply voltage Digital block input Symbol Digital block output Clock input operating frequency External clock operating frequency Note: External clock input (pin allows also input sine wave signal. fclk_ext (Pin clock frequency external input fclk High-level input voltage range Low-level input voltage range Output current level Output voltage level (Pin clock frequency 3wire_bus Conditions Ratings 0.7VDD unit
Package Dimensions
unit 3302A
View Bottom View 0.35
(0.7)
0.05
0.85max
SANYO VQLP40(5.0X5.0)
(0.7)
0.35
No.A0466-3/18
LV24010LP
Block Diagram
No.A0466-4/18
LV24010LP
Function
name FM-ANT1 FM-ANT2 LINE-OUT-L LINE-OUT-R Package-GND Package-GND Package-GND Package-GND Package-GND Package-GND Vstabi. NR_W DATA CLOCK CLK_IN Package-GND Package-GND Package-GND Package-GND Package-GND Package-GND VI/O Digital interface supply voltage Package-shied Package-shied Package-shied Package-shied Package-shied Package-shied connect. Digital supply voltage Digital interface Read/Write Digital interface DATA Digital interface Clock Reference clock-source input measurement Connect used. connect. Stabilizer voltage 2.7V connect. Analog supply voltage connect. MPX-signal output VCC-0.3V connect. Radio Line-output Radio Line-output Package-shied Package-shied Package-shied Package-shied Package-shied Package-shied connect. connect. 1.2V 1.2V Antenna input Antenna (Analog Digital GND) connect. connect. connect. connect. Connect GND. Description (Analog Digital GND) connect. connect. DC_bias Remark
No.A0466-5/18
LV24010LP
Timing Diagram
Write timing
Symbol Delay from command data
Parameter
Ratings
unit
Delay from data stable data latch time Data Hold time Clock High-level time Clock Low-level time
Read timing
Symbol
Parameter Delay from command data Data Setup time Data hold time
Ratings
unit
External clock timing (Pin
Symbol Clock High-level time Clock Low-level time
Parameter
Ratings
unit
No.A0466-6/18
LV24010LP
Digital interface specification (Interface specification: reference)
3-wire (For communication line) Access LV24010 done through 3-wire bus:
CLOCK NR_W DATA Data strobe, input LV24010 Command (Write read data), input LV24010 Bi-directional pin: input LV24010 when NR_W high, output from LV24010 when NR_W low.
LV24010 configured generate interrupt through DATA-line. When interrupt mode selected, care should taken that DATA-line connection application micro-controller also supports interrupt. When required timing window frequency measurements generated application micro-controller, external clock must connected CLK_IN LV24010 Register (For register map) LV24020 registers divided blocks:
Block Block Block Status measurement Radio Control control
access register block, block must first selected writing block number BLK_SEL register. Block selection skipped subsequent accesses other registers same block. mapping follows:
Block Address Register name CHIP_ID BLK_SEL MSRC_SEL FM_OSC SD_OSC IF_OSC CNT_CTRL IRQ_MSK FM_CAP CNT_L CNT_H CTRL_STAT RADIO_STAT IRQ_ID IRQ_OUT BLK_SEL RADIO_CTRL1 IF_CENTER IF_BW RADIO_CTRL2 RADIO_CTRL3 STEREO_CTRL AUDIO_CTRL1 AUDIO_CTRL2 PW_SCTRL BLK_SEL RDS_FLTDAC RDAT_L RDAT_H RDS_CTRL RDS_OSC RDS_INPS Access input setting Bandwidth Radio Control Radio control Stereo Control Audio Control Audio Control Power soft control Access register block control filter Demodulated data byte Demodulated data high byte control control oscillator Interrupt mask bank control RF-frequency Counter value byte Counter value high byte Control status Radio station status Interrupt identify Interrupt DATA-line Access register block Radio control Center Frequency Chip identification Block Select Measure source select control FM-RF oscillator control stereo decoder oscillator control oscillator Counter control Operation
Registers with blank colum defined should accessed.
No.A0466-7/18
LV24010LP
Register description (For each register content) Block Register BLK_SEL Block Select register (Write Only)
BN[7:0] 7-0: BN[7:0]: 8-bit block number. LV24010, following numbers valid: 01h. 02h. 04h. Note: This register accessed from block.
Block Register CHIP_ID Chip identify register (Read Only)
ID[7:0] 7-0: ID[7:0]: 8-bit chip following ID's defined: LV24010.
Block Register MSRC_SEL Measurement Source Select Register (Write-only)
MSR_O AFC_LVL AFC_SPD Reserved Reserved MSS_SD MSS_FM MSS_IF
MSR_O: Output measure source DATA-pin. Measuring source available DATA-pin (normal operation). Measuring source available DATA-pin (test mode).
AFC_LVL: trigger level. always active (trigger 0dBµV). only active when field strength above 20dBµV.
AFC_SPD: speed. adjusts with speed. adjusts with 8kHz speed (test mode).
Reserved: Must programmed with Reserved: Must programmed with MSS_SD: Stereo decoder oscillator measurement. Disable stereo decoder oscillator measurement. Enable stereo decoder oscillator measurement.
MSS_FM: oscillator measurement. Disable oscillator measurement. Enable oscillator measurement.
MSS_IF: oscillator measurement. Disable oscillator measurement. Enable oscillator measurement.
Note: Only measurement source MSS_xx bits time. frequency divided before goes measuring circuitry.
Block Register FM_OSC Oscillator Register (Write-only)
FMOSC[7:0] 7-0: Note: Positive control (i.e. frequency increases with register's value). also FM_CAP register. FMOSC[7:0]: value control oscillator (fine step)
No.A0466-8/18
LV24010LP
Block Register SD_OSC Stereo Decoder Oscillator Register (Write-only)
SDOSC[7:0] 7-0: SDOSC[7:0]: value control stereo decoder oscillator.
Note: Positive control (i.e. frequency increases with register's value)
Block Register IF_OSC Oscillator Register (Write-only)
IFOSC[7:0] 7-0: IFOSC[7:0]: value control oscillator.
Note: Positive control (i.e. frequency increases with register's value).
Block Register CNT_CTRL Counters Control Register (Write-only)
CNT1_CLR CTAB2 CTAB1 CTAB0 SWP_CNT_L CNT_EN CNT_SEL CNT_SET
CNT1_CLR: Clear counter bit. Normal mode. Clear keep counter reset mode.
6-4:
CTAB[2:0]: select counter measuring interval bits. Value 000b 001b 010b 011b 100b 101b 110b 111b Dec. Stop value Stop after counts. Stop after counts Stop after counts. Stop after counts. Stop after counts. Stop after 2048 counts. Stop after 8192 counts. Stop after 32768 counts.
SWP_CNT_L: Swap counter counter (Active low). Clock source counter clock source counter (swapping) Clock source counter clock source counter swap)
CNT_EN: Enable currently selected counter bit. Disable counter (stop counting). Enable counter (counting mode).
CNT_SEL: counter select bit. Select counter measurement. Select counter measurement.
CNT_SET: counters bit. Normal mode. both counter counter FFFFh keep them set.
No.A0466-9/18
LV24010LP
Block Register IRQ_MSK Interrupt Mask Register (Write-only)
Reserved IM_MS Reserved Reserved IRQ_LVL IM_AFC IM_FS IM_CNT2
Reserved: Must programmed with IM_MS: Mono/Stereo interrupt mask bit. Disable mono/stereo change interrupt. Enable mono/stereo change interrupt.
Reserved: Must programmed with Reserved: Must programmed with IRQ_LVL: Interrupt level select bit. Drive DATA-line from high when interrupt occurs (active high). Drive DATA-line from high when interrupt occurs (active low).
IM_AFC: range interrupt mask bit. Disable range interrupt. Enable range interrupt.
IM_FS: Field strength change interrupt mask bit. Disable field strength change interrupt. Enable field strength change interrupt.
IM_CNT2: Counter counting done interrupt mask bit. Disable counter counting done interrupt. Enable counter counting done interrupt.
Block Register FM_CAP Capacitor Bank Register (Write-only)
FMCAP[7:0] 7-0: Note: value (Bit[7:6]: Combination results same CAP-range). Negative control: frequency decreases when increasing register's value. also FM_OSC register. FMCAP[7:0]: bank value control frequency (coarse steps)
Block Register CNT_L Counter Value Register (Read-only)
CNT_LSB[7:0] 7-0: CNT_LSB[7:0]: Lower 8-bit value counter
Block Register CNT_H Counter Value High Register (Read-only)
CNT_MSB[7:0] 7-0: CNT_MSB[7:0]: Upper 8-bit value counter
Block Register CTRL_STAT Control Status Register (Read-only)
REV3 7-4: 3-1: REV2 REV1 REV0 Reserved Reserved COV_FLG AFC_FLG
REV[3:0]: should read 0Dh. Reserved[1:0]: should read COV_FLG: counter overflow flag. overflow internal counter. last counting loop causes overflow internal counter.
AFC_FLG: range within control range. control range.
Note: Reading this register will clear AFC, count done interrupt. COV_FLG clear when CLR_CNT1 CNT_CTRL register high.
No.A0466-10/18
LV24010LP
Block Register RADIO_STAT Radio Station Status Register (Read-only)
RSS_MS RSS_MS: Radio station mono/stereo state bit. Mono. Stereo. 6-0: RSS_FS[6:0]: Radio station field strength bits. 1111111b Field strength less then 10dBµV. 0111111b Field strength between 20dBµV. 0011111b Field strength between 30dBµV. 0001111b Field strength between 40dBµV. 0000111b Field strength between 50dBµV. 0000011b Field strength between 60dBµV. 0000001b Field strength between 70dBµV. 0000000b Field strength above 70dBµV. Note: Reading this register will clear field strength mono/stereo interrupt. RSS_FS
Block Register IRQ_ID Interrupt Identify Register (Read-only)
Reserved II_RDS II_CNT2 Reserved II_AFC Reserved Reserved II_FS_MS
Reserved: should read II_RDS: data available interrupt. counting counting done interrupt. Measuring with counter done.
II_CNT2: Counter counting done flag. counting counting done interrupt. Measuring with counter done.
Reserved: should read II_AFC: range interrupt bit. interrupt. fails hold RF-frequency range.
Reserved: should read Reserved: should read II_FS_MS: Field strength Mono/stereo interrupt bit. change either field strength mono/stereo mode. Change field strength bits detected mono/stereo mode changed.
Block Register IRQ_OUT Interrupt Register (Write Only)
IRQO_VAL[7:0] 7-0: IRQO_VAL[7:0]: Write value this register will select interrupt output DATA-line LV24010 (the DATA-line then used interrupt pin)
No.A0466-11/18
LV24010LP
Block Register RADIO_CTRL1 Radio Control Register (Write-only)
EN_MEAS EN_AFC Reserved Reserved DIR_AFC RST_AFC Reserved Reserved
EN_MEAS: Enable measurement bit. Normal mode. Measurement mode.
EN_AFC: Enable bit. Disable AFC. Enable AFC.
Reserved: should written with Reserved: should written with DIR_AFC: direction normal direction. reverse direction (for test purpose).
RST_AFC: Reset bit. Normal operation. Reset middle control range.
Reserved: should written with Reserved: should written with
Block Register IF_CENTER Center Frequency Register (Write-only)
IFCOSC[7:0] 7-0: IFCENT[7:0]: Value centering frequency
Block Register IF_BW Bandwidth Register (Write-only)
IFBW[7:0] 7-0: IFBW[7:0]: Value bandwidth.
Block Register RADIO_CTRL2 Radio Control Register (Write-only)
VREF2 VREF STABI_BP IF_PM_L Reserved Reserved AGCSP AM_ANT_BSW
VREF2: VREF2 control bit. VREF2 VREF2 OFF.
VREF: VREF control bit. VREF VREF OFF.
STABI_BP: Stabi Bypass bit. Internal voltage Vstabi (normal operation). Internal voltage (stabi bypassed).
IF_PM_L: mute bit. mute (presetting mode). mute (normal operation mode).
Reserved: should written with Reserved: should written with AGCSP: speed control bit. Normal speed. High speed.
Note: Turn this will speed field strength measurement (fast tuning). Reserved: should written with
No.A0466-12/18
LV24010LP
Block Register RADIO_CTRL3 Radio Control Register (Write-only)
AGC_SLVL VOLSH Reserved AMUTE_L SE_FM Reserved Reserved Reserved
AGC_SLVL: level bit. This must normal operation mode.
VOLSH: Volume level shift bit. Normal volume level. Increase volume 12dB.
Reserved: should written with AMUTE_L: Audio mute bit. Audio muted. Audio muted.
SE_FM: radio select bit. Disable radio. Enable radio.
Reserved: should written with Reserved: should written with Reserved: should written with
Block Register STEREO_CTRL Stereo Control Register (Write-only)
FRCST FMCS[2:0] FRCST: Force stereo bit. Normal mode. Force stereo mode test. 6-4: FMCS[2:0]: channel separation bits. channel separation level. AUTOSSR: Auto stereo slew rate enable bit. Disable stereo auto slew rate. Enable stereo auto slew rate. DELTA_TN: Delta tune bit. Decrease delta tune. Normal delta tune. SD_PM: Stereo decoder mute bit. Stereo decoder muted (normal operation). Stereo decoder muted (presetting mode). ST_M: stereo/mono mode bit. Stereo mode. Mono mode. AUTOSSR DELTA_TN SD_PM ST_M
Block Register AUDIO_CTRL1 Audio Control Register (Write-only)
Reserved 7-4: 3-0: Reserved Reserved Reserved VOL_LVL
Reserved: should written with VOL_LVL: volume level bits 1111b Minimum volume level. 0000b Maximum volume level. Each level about volume adjustment.
No.A0466-13/18
LV24010LP
Block Register AUDIO_CTRL2 Audio Control Register (Write-only)
Reserved 7-6: Reserved DEEMP Reserved Reserved Reserved Reserved Reserved
Reserved: should written with 11b. DEEMP: De-emphasis bit. De-emphasis 50µs. De-emphasis 75µs.
4-0:
Reserved: should written with 00000b.
Block Register PW_SCTRL Power Soft Control Register (Write-only)
SS_CTRL 7-5: SS_CTRL: Soft stereo control bits levels). 000b Minimal soft stereo (off). 111b Maximal soft stereo level. 4-2: SM_CTRL: Soft audio mute bits levels). 000b Minimal audio mute (off). 111b Maximal soft audio mute level. Reserved: should written with PW_RAD: Radio circuitry power bit. Radio circuitry switched OFF. Switch radio circuitry Note: PW_RAD power SM_CTRL Reserved PW_RAD
Block Register RDS_FLTDAC Filter Register (Write-only)
RFLTDAC[7:0] 7-0: RFLTDAC[7:0]: value filter.
Note: This register should programmed with value RDS_OSC register.
Block Register RDAT_L Data Register (Read-only)
RD_L[7:0] 7-0: RD_L[7:0]: byte data.
Note: contains first received bit.
Block Register RDAT_H Data High Register (Read-only)
RD_L[7:0] 7-0: RD_H[7:0]: High byte data.
Note: contains first received bit.
No.A0466-14/18
LV24010LP
Block Register RDS_CTRL Control Register (Write-only)
RDS_EN_L RDS_PM RDSLRG RDSITG_L RDSBW1 RDSBW0 RDCNT_EN RDCNT_RS
RDS_EN_L: Enable (active low). switched switched OFF.
RDS_PM: mute bit. un-muted (normal operation mode). muted (calibration mode).
RDSLRG: lock range. Normal lock range. Lock range
RDSITG_L: integrator. Enable integrator. Disable integrator.
3-2:
RDSBW[1:0]: Band Width Bits. Bandwidth kHz. Bandwidth kHz. Bandwidth kHz. Bandwidth kHz.
RDCNT_EN: Enable received counter. Disable counter. Enable counter (normal mode).
Note: received counter should enabled when enabled. RDCNT_RS: Reset received counter. Reset switched (normal mode). Reset switched Note: Generate counter reset making this high then low. This will flush received data FIFO.
Block Register RDS_OSC Oscillator Register (Write-only)
RDOSC[7:0] 7-0: RDOSC[7:0]: value oscillator.
Note: Positive control (i.e. frequency increases with register's value).
Block Register RDS_INPS Input Setting Register (Write-only)
Reserved 7-4: Reserved Reserved Reserved RGAIN RVREF MPXDIV EN_RNH
Reserved: Must programmed with 0000b. RDS_PM: mute bit. un-muted (normal operation mode). muted (calibration mode).
RGAIN: Gain control.
RVREF: Measure Vref. Disable. Enable (test purpose only).
MPXDIV: input divider. =1:3. =1:1.
EN_RNH: notch. Disable. Enable.
No.A0466-15/18
LV24010LP
Measurement Circuit
Application Circuit Example
Note1: vale External Component just reference. Please most suitable value under actual operation. Note2: case necessary about FM_in, Please take Consideration most suitable value. Note3: recommend R1,R2,R3,R4 interface between Note4: Please Capacitor between also, Capacitor between shown application. Note5: case using External Clock_in (pin31), Please GND.
No.A0466-16/18
LV24010LP
Recommended LV24010LP's Layout Conditions
substrate
This inductor local oscillation bottom side package. enable coverage receive frequency range 76MHz 108MHz (according receive frequency specification), requested arrange layer first layer PCB_A face directly below package bottom surface, shown figure.
Recommended substrate layout
substrate_LV24010LP
Recommended layer directly below
this SPL, receive frequency measured under above following conditions: X-value freely between 2.2mm 3.8mm (The X-value Sanyo Demo Board 3.4mm). recommended avoid provision other wiring within 0.4mm from lower layer PCB_GND much possible.
No.A0466-17/18
LV24010LP
Specifications SANYO Semiconductor products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Semiconductor Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO Semiconductor products (including technical data, services) described contained herein controlled under applicable local export control laws regulations, such products must exported without obtaining export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Semiconductor Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO Semiconductor product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO Semiconductor believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties. This catalog provides information November, 2006. Specifications information herein subject change without notice.
No.A0466-18/18

Bi-CMOS LV24010LP Compact Portable Equipment 1-Chip FM+

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