Express PCI-X Reversible Bridge 3545 North First Street, Jose, 95
|
|
|
Top Searches for this datasheet
PI7C9X130
Express PCI-X Reversible Bridge
3545 North First Street, Jose, 95134 Telephone: 1-877-PERICOM, (1-877-737-4266) Fax: 408-435-1100 Internet: http://www.pericom.com
PI7C9X130 EXPRESS PCI-X BRIDGE
LIFE SUPPORT POLICY Pericom Semiconductor Corporation's products authorized critical components life support devices systems unless specific written agreement pertaining such intended executed between manufacturer officer PSC. Life support devices system devices systems which: intended surgical implant into body Support sustain life whose failure perform, when properly used accordance with instructions provided labeling, reasonably expected result significant injury user. critical component component life support device system whose failure perform reasonably expected cause failure life support device system, affect safety effectiveness. Pericom Semiconductor Corporation reserves right make changes products specifications time, without notice, order improve design performance supply best possible product. Pericom Semiconductor does assume responsibility circuitry described other than circuitry embodied Pericom Semiconductor product. Company makes representations that circuitry described herein free from patent infringement other rights third parties which result from use. license granted implication otherwise under patent, patent rights other rights, Pericom Semiconductor Corporation.
other trademarks their respective companies.
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
REVISION HISTORY
Date
02/24/06 03/20/06
Revision Number
Description
First Draft PI7C9X130 Data Sheet Correct INTA, buffer type Update configuration registers Update JTAG chain order PCI/PCI-X selection information Update configuration register definitions. [10, 7:2] offset [31:30] offset offset [23:22] offset [7:1] offset 164h Correct typo CLKRUN_L assignment JTAG section. Absolute Maximum Ratings Correct description: REQ_L GNT_L CLKOUT [8:0] CLKOUT [6:0] Correct default setting [31:30] offset Completed non-transparent function address Configuration Register section Corrected HSEN (R3) section Miscellaneous Signals. Should read Swap used instead HIGH Revised table section Address bit[5] corrected equal Address bit[4] corrected equal GPIO[3] Revised PCIe Base Specification Compliancy from 1.0a Corrected HSSW (T3) section Miscellaneous Signals. Remove "Tied high swap function used." Corrected bit[13] offset 110h from reserved "Advisory Non-Fatal Error Status" Changed Logos some font types Corrected GNT_L[1], GNT_L[2], GNT_[3], GNT_[4], GNT_[5] Table 14-1JTAG Boundary Scan Register Definition Recommendation Pull-up Resistor PI7C9X130 Control Signals added section 16.3 PI7C9X130 Datasheets; numbers SMBCLK SMBDAT corrected under section 5.2. Added PCIX Clock Detection Chapter Clock Scheme.
04/07/06
06/07/06
06/19/06 03/26/2007 04/18/2007
05/02/2007
05/15/2007 06/08/2007 07/13/2007 08/07/2007 09/28//2007
0.91
PREFACE
datasheet PI7C9X130 will enhanced periodically when updated information available. technical information this datasheet subject change without notice. This document describes functionalities PI7C9X130 (PCI Express Bridge) provides technical information designers design their hardware using PI7C9X130.
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
This page intentionally left blank.
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
TABLE CONTENTS
INTRODUCTION EXPRESS FEATURES.13 PCI/PCI-X FEATURES GENERAL FEATURES
DEFINITION SIGNAL TYPES EXPRESS SIGNALS SIGNALS MODE SELECT STRAPPING SIGNALS.18 JTAG BOUNDARY SCAN SIGNALS.18 MISCELLANEOUS SIGNALS POWER GROUND PINS ASSIGNMENT
MODE SELECTION STRAPPING FUNCTIONAL MODE SELECTION PCI/PCI-X SELECTION.22 STRAPPING
FORWARD REVERSE BRIDGING TRANSPARENT NON-TRANSPARENT BRIDGING TRANSPARENT MODE NON-TRANSPARENT MODE
EXPRESS FUNCTIONAL OVERVIEW STRUCTURE.27 VIRTUAL ISOCHRONOUS OPERATION
CONFIGURATION REGISTERS.29 CONFIGURATION REGISTER MAP.29 EXPRESS EXTENDED CAPABILITY REGISTER MAP.34 CONTROL STATUS REGISTER CONFIGURATION REGISTERS TRANSPARENT BRIDGE MODE.37 7.4.1 VENDOR OFFSET 7.4.2 DEVICE OFFSET 00h.37 7.4.3 COMMAND REGISTER OFFSET 04h.37 7.4.4 PRIMARY STATUS REGISTER OFFSET 04h.38 7.4.5 REVISION REGISTER OFFSET 7.4.6 CLASS CODE REGISTER OFFSET 08h.40 7.4.7 CACHE LINE SIZE REGISTER OFFSET 0Ch.40 7.4.8 PRIMARY LATENCY TIMER REGISTER OFFSET 7.4.9 HEADER TYPE REGISTER OFFSET 7.4.10 RESERVED REGISTERS OFFSET 7.4.11 PRIMARY NUMBER REGISTER OFFSET 7.4.12 SECONDARY NUMBER REGISTER OFFSET 7.4.13 SUBORDINATE NUMBER REGISTER OFFSET 7.4.14 SECONDARY LATENCY TIMER REGISTER OFFSET 18h.41 7.4.15 BASE REGISTER OFFSET 1Ch.41 7.4.16 LIMIT REGISTER OFFSET 1Ch.42 Page
PERICOM SEMICONDUCTOR
September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
7.4.17 7.4.18 7.4.19 7.4.20 7.4.21 7.4.22 7.4.23 7.4.24 7.4.25 7.4.26 7.4.27 7.4.28 7.4.29 7.4.30 7.4.31 7.4.32 7.4.33 7.4.34 7.4.35 7.4.36 7.4.37 7.4.38 7.4.39 7.4.40 7.4.41 7.4.42 7.4.43 7.4.44 7.4.45 7.4.46 7.4.47 7.4.48 7.4.49 7.4.50 7.4.51 7.4.52 7.4.53 7.4.54 7.4.55 7.4.56 7.4.57 7.4.58 7.4.59 7.4.60 7.4.61 7.4.62 7.4.63 7.4.64 7.4.65 7.4.66 7.4.67 7.4.68 7.4.69 7.4.70
SECONDARY STATUS REGISTER OFFSET MEMORY BASE REGISTER OFFSET MEMORY LIMIT REGISTER OFFSET PREFETCHABLE MEMORY BASE REGISTER OFFSET 24h.43 PREFETCHABLE MEMORY LIMIT REGISTER OFFSET 24h.44 PREFETCHABLE BASE UPPER 32-BIT REGISTER OFFSET PREFETCHABLE LIMIT UPPER 32-BIT REGISTER OFFSET 2Ch.44 BASE UPPER 16-BIT REGISTER OFFSET 30h.44 BASE UPPER 16-BIT REGISTER OFFSET 30h.44 CAPABILITY POINTER OFFSET EXPANSION BASE ADDRESS REGISTER OFFSET 38h.45 INTERRUPT LINE REGISTER OFFSET 3Ch.45 INTERRUPT REGISTER OFFSET 3Ch.45 BRIDGE CONTROL REGISTER OFFSET DATA BUFFERING CONTROL REGISTER OFFSET 40h.46 CHIP CONTROL REGISTER OFFSET 40h.48 RESERVED REGISTER OFFSET ARBITER ENABLE REGISTER OFFSET 48h.49 ARBITER MODE REGISTER OFFSET 48h.50 ARBITER PRIORITY REGISTER OFFSET RESERVED REGISTERS OFFSET 64h.51 EXPRESS TRANSMITTER/RECEIVER CONTROL REGISTER OFFSET 68h.51 UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER OFFSET RESERVED REGISTER OFFSET 6Ch.52 EEPROM AUTOLOAD CONTROL/STATUS REGISTER OFFSET 70h.52 SWAP CONTROL STATUS REGISTER OFFSET GPIO DATA CONTROL REGISTER OFFSET 78h.54 RESERVED REGISTER OFFSET 7Ch.54 PCI-X CAPABILITY REGISTER OFFSET 80h.54 NEXT CAPABILITY POINTER REGISTER OFFSET PCI-X SECONDARY STATUS REGISTER OFFSET 80h.54 PCI-X BRIDGE STATUS REGISTER OFFSET 84h.55 UPSTREAM SPLIT TRANSACTION REGISTER OFFSET 88h.56 DOWNSTREAM SPLIT TRANSACTION REGISTER OFFSET 8Ch.57 POWER MANAGEMENT REGISTER OFFSET 90h.57 NEXT CAPABILITY POINTER REGISTER OFFSET POWER MANAGEMENT CAPABILITY REGISTER OFFSET POWER MANAGEMENT CONTROL STATUS REGISTER OFFSET PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER OFFSET 94h.58 RESERVED REGISTERS OFFSET 9Ch.59 CAPABILITY REGISTER OFFSET A0h.59 NEXT POINTER REGISTER OFFSET SLOT NUMBER REGISTER OFFSET CHASSIS NUMBER REGISTER OFFSET SECONDARY CLOCK CLKRUN CONTROL REGISTER OFFSET A4h.60 CAPABILITY REGISTER OFFSET A8h.61 NEXT POINTER REGISTER OFFSET RESERVED REGISTER OFFSET SUBSYSTEM VENDOR REGISTER OFFSET ACh.61 SUBSYSTEM REGISTER OFFSET EXPRESS CAPABILITY REGISTER OFFSET NEXT CAPABILITY POINTER REGISTER OFFSET B0h.62 EXPRESS CAPABILITY REGISTER OFFSET DEVICE CAPABILITY REGISTER OFFSET B4h.62 Page
PERICOM SEMICONDUCTOR
September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
7.4.71 7.4.72 7.4.73 7.4.74 7.4.75 7.4.76 7.4.77 7.4.78 7.4.79 7.4.80 7.4.81 7.4.82 7.4.83 7.4.84 7.4.85 7.4.86 7.4.87 7.4.88 7.4.89 7.4.90 7.4.91 7.4.92 7.4.93 7.4.94 7.4.95 7.4.96 7.4.97 7.4.98 7.4.99 7.4.100 7.4.101 7.4.102 7.4.103 7.4.104 7.4.105 7.4.106 7.4.107 7.4.108 7.4.109 7.4.110 7.4.111 7.4.112 7.4.113 7.4.114 7.4.115 7.4.116 7.4.117 7.4.118 7.4.119 7.4.120 7.4.121 7.4.122 7.4.123 7.4.124
DEVICE CONTROL REGISTER OFFSET DEVICE STATUS REGISTER OFFSET B8h.64 LINK CAPABILITY REGISTER OFFSET LINK CONTROL REGISTER OFFSET LINK STATUS REGISTER OFFSET C0h.66 SLOT CAPABILITY REGISTER OFFSET SLOT CONTROL REGISTER OFFSET SLOT STATUS REGISTER OFFSET XPIP CONFIGURATION REGISTER OFFSET XPIP CONFIGURATION REGISTER OFFSET D0h.68 XPIP CONFIGURATION REGISTER OFFSET D4h.68 SWAP SWITCH DEBOUNCE COUNTER OFFSET CAPABILITY REGISTER OFFSET NEXT POINTER REGISTER OFFSET REGISTER OFFSET DATA REGISTER OFFSET DCh.69 RESERVED REGISTER OFFSET ECh.69 MESSAGE SIGNALED INTERRUPTS REGISTER OFFSET NEXT CAPABILITIES POINTER REGISTER OFFSET MESSAGE CONTROL REGISTER OFFSET MESSAGE ADDRESS REGISTER OFFSET MESSAGE UPPER ADDRESS REGISTER OFFSET MESSAGE DATA REGISTER OFFSET ADVANCE ERROR REPORTING CAPABILITY REGISTER OFFSET 100h ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER OFFSET 100h NEXT CAPABILITY OFFSET REGISTER OFFSET 100h UNCORRECTABLE ERROR STATUS REGISTER OFFSET 104h UNCORRECTABLE ERROR MASK REGISTER OFFSET 108h UNCORRECTABLE ERROR SEVERITY REGISTER OFFSET 10Ch.72 CORRECTABLE ERROR STATUS REGISTER OFFSET 110h.72 CORRECTABLE ERROR MASK REGISTER OFFSET 114h.73 ADVANCED ERROR CAPABILITIES CONTROL REGISTER OFFSET 118h.73 HEADER REGISTER OFFSET 11Ch.73 HEADER REGISTER OFFSET 120h.73 HEADER REGISTER OFFSET 124h.74 HEADER REGISTER OFFSET 128h.74 SECONDARY UNCORRECTABLE ERROR STATUS REGISTER OFFSET 12Ch.74 SECONDARY UNCORRECTABLE ERROR MASK REGISTER OFFSET 130h.75 SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER OFFSET 134h.75 SECONDARY ERROR CAPABILITY CONTROL REGISTER OFFSET 138h SECONDARY HEADER REGISTER OFFSET 13Ch 148h RESERVED REGISTER OFFSET 14Ch.76 CAPABILITY REGISTER OFFSET 150h CAPABILITY VERSION REGISTER OFFSET 150h NEXT CAPABILITY OFFSET REGISTER OFFSET 150h PORT CAPABILITY REGISTER OFFSET 154h PORT CAPABILITY REGISTER OFFSET 158h PORT CONTROL REGISTER OFFSET 15Ch PORT STATUS REGISTER OFFSET 15Ch.77 RESOURCE CAPBILITY REGISTER OFFSET 160h.78 RESOURCE CONTROL REGISTER OFFSET 164h.78 RESOURCE STATUS REGISTER OFFSET 168h RESERVED REGISTERS OFFSET 16Ch 2FCh.78 EXTENDED GPIO DATA CONTROL REGISTER OFFSET 300h Page
PERICOM SEMICONDUCTOR
September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
7.4.125 EXTRA GPI/GPO DATA CONTROL REGISTER OFFSET 304h 7.4.126 RESERVED REGISTERS OFFSET 308h 30Ch.79 7.4.127 REPLAY ACKNOWLEDGE LATENCY TIMERS OFFSET 310h 7.4.128 RESERVED REGISTERS OFFSET 314h FFCh CONFIGURATION REGISTERS NON-TRANSPARENT BRIDGE MODE.80 7.5.1 VENDOR OFFSET 7.5.1 DEVICE OFFSET 00h.80 7.5.2 PRIMARY COMMAND REGISTER OFFSET 7.5.3 PRIMARY STATUS REGISTER OFFSET 04h.81 7.5.4 REVISION REGISTER OFFSET 7.5.5 CLASS CODE REGISTER OFFSET 08h.83 7.5.6 PRIMARY CACHE LINE SIZE REGISTER OFFSET 7.5.7 PRIMARY LATENCY TIMER REGISTER OFFSET 7.5.8 PRIMARY HEADER TYPE REGISTER OFFSET 7.5.9 PRIMARY MEMORY BASE ADDRESS REGISTER OFFSET 10h.84 7.5.10 PRIMARY BASE ADDRESS REGISTER OFFSET 14h.84 7.5.11 DOWNSTREAM MEMORY BASE ADDRESS REGISTER OFFSET 7.5.12 DOWNSTREAM MEMORY BASE ADDRESS REGISTER OFFSET 7.5.13 DOWNSTREAM MEMORY BASE ADDRESS REGISTER OFFSET 20h.85 7.5.14 DOWNSTREAM MEMORY UPPER BASE ADDRESS REGISTER OFFSET 7.5.15 RESERVED REGISTER OFFSET 7.5.16 SUBSYSTEM SUBSYSTEM VENDOR REGISTER OFFSET 7.5.17 RESERVED REGISTER OFFSET 7.5.18 CAPABILITY POINTER OFFSET 7.5.19 EXPANSION BASE ADDRESS REGISTER OFFSET 38h.87 7.5.20 PRIMARY INTERRUPT LINE REGISTER OFFSET 7.5.21 PRIMARY INTERRUPT REGISTER OFFSET 7.5.22 PRIMARY MINIMUM GRANT REGISTER OFFSET 7.5.23 PRIMARY MAXIMUM LATNECY TIMER OFFSET 7.5.24 DATA BUFFERING CONTROL REGISTER OFFSET 40h.88 7.5.25 CHIP CONTROL REGISTER OFFSET 40h.89 7.5.26 SECONDARY COMMAND REGISTER OFFSET 7.5.27 SECONDARY STATUS REGISTER OFFSET 44h.91 7.5.28 ARBITER ENABLE REGISTER OFFSET 48h.92 7.5.29 ARBITER MODE REGISTER OFFSET 48h.93 7.5.30 ARBITER PRIORITY REGISTER OFFSET 7.5.31 SECONDARY CACHE LINE SIZE REGISTER OFFSET 7.5.32 SECONDARY LATENCY TIMER REGISTER OFFSET 7.5.33 SECONDARY HEADER TYPE REGISTER OFFSET 7.5.34 SECONDARY MEMORY BASE ADDRESS REGISTER OFFSET 50h.95 7.5.35 SECONDARY BASE ADDRESS REGISTER OFFSET 54h.96 7.5.36 UPSTREAM MEMORY BASE ADDRESS REGISTER OFFSET 58h.96 7.5.37 UPSTREAM MEMORY BASE ADDRESS REGISTER OFFSET 7.5.38 UPSTREAM MEMORY BASE ADDRESS REGISTER OFFSET 7.5.39 UPSTREAM MEMORY UPPER BASE ADDRESS REGISTER OFFSET 64h.97 7.5.40 EXPRESS TRANSMITTER/RECEIVER CONTROL REGISTER OFFSET 68h.98 7.5.41 MEMORY ADDRESS FORWARDING CONTROL REGISTER OFFSET 68h.99 7.5.42 UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER OFFSET 7.5.43 SUBSYSTEM VENDOR REGISTER OFFSET .100 7.5.44 SUBSYSTEM REGISTER OFFSET 6Ch.100 7.5.45 EEPROM AUTOLOAD CONTROL/STATUS REGISTER OFFSET 70h.100 7.5.46 SWAP CONTROL STATUS REGISTER OFFSET .101 7.5.47 BRIDGE CONTROL STATUS REGISTER OFFSET .101 7.5.48 GPIO DATA CONTROL REGISTER OFFSET 78h.102 Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
7.5.49 7.5.50 7.5.51 7.5.52 7.5.53 7.5.54 7.5.55 7.5.56 7.5.57 7.5.58 7.5.59 7.5.60 7.5.61 7.5.62 7.5.63 7.5.64 7.5.65 7.5.66 7.5.67 7.5.68 7.5.69 7.5.70 7.5.71 7.5.72 7.5.73 7.5.74 7.5.75 7.5.76 7.5.77 7.5.78 7.5.79 7.5.80 7.5.81 7.5.82 7.5.83 7.5.84 7.5.85 7.5.86 7.5.87 7.5.88 7.5.89 7.5.90 7.5.91 7.5.92 7.5.93 7.5.94 7.5.95 7.5.96 7.5.97 7.5.98 7.5.99 7.5.100 7.5.101 7.5.102
SECONDARY INTERRUPT LINE REGISTER OFFSET .103 SECONDARY INTERRUPT REGISTER OFFSET .103 SECONDARY MINIMUM GRANT REGISTER OFFSET .103 SECONDARY MAXIMUM LATENCY TIMER OFFSET .103 PCI-X CAPABILITY REGISTER OFFSET 80h.103 NEXT CAPABILITY POINTER REGISTER OFFSET .103 PCI-X SECONDARY STATUS REGISTER OFFSET 80h.104 PCI-X BRIDGE STATUS REGISTER OFFSET 84h.104 UPSTREAM SPLIT TRANSACTION REGISTER OFFSET 88h.106 DOWNSTREAM SPLIT TRANSACTION REGISTER OFFSET 8Ch.106 POWER MANAGEMENT REGISTER OFFSET 90h.106 NEXT CAPABILITY POINTER REGISTER OFFSET .106 POWER MANAGEMENT CAPABILITY REGISTER OFFSET .107 POWER MANAGEMENT CONTROL STATUS REGISTER OFFSET .107 PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER OFFSET 94h.108 DOWNSTREAM MEMORY TRANSLATED BASE REGISTER OFFSET 98h.108 DOWNSTREAM MEMORY SETUP REGISTER OFFSET .108 CAPABILITY REGISTER OFFSET A0h.109 NEXT POINTER REGISTER OFFSET .109 SLOT NUMBER REGISTER OFFSET .109 CHASSIS NUMBER REGISTER OFFSET .109 SECONDARY CLOCK CLKRUN CONTROL REGISTER OFFSET A4h.109 DOWNSTREAM MEMORY TRANSLATED BASE REGISTER OFFSET A8h.110 DOWNSTREAM MEMORY SETUP REGISTER OFFSET .111 CAPABILITY REGISTER OFFSET B0h.111 NEXT CAPABILITY POINTER REGISTER OFFSET B0h.111 EXPRESS CAPABILITY REGISTER OFFSET .111 DEVICE CAPABILITY REGISTER OFFSET B4h.112 DEVICE CONTROL REGISTER OFFSET .113 DEVICE STATUS REGISTER OFFSET B8h.114 LINK CAPABILITY REGISTER OFFSET .114 LINK CONTROL REGISTER OFFSET .115 LINK STATUS REGISTER OFFSET C0h.115 SLOT CAPABILITY REGISTER OFFSET .116 SLOT CONTROL REGISTER OFFSET .116 SLOT STATUS REGISTER OFFSET .117 XPIP CONFIGURATION REGISTER OFFSET .117 XPIP CONFIGURATION REGISTER OFFSET D0h.117 XPIP CONFIGURATION REGISTER OFFSET D4h.118 CAPABILITY REGISTER OFFSET .118 NEXT POINTER REGISTER OFFSET .118 REGISTER OFFSET .118 DATA REGISTER OFFSET DCh.118 UPSTREAM MEMORY TRANSLATED BASE OFFSET E0h.119 UPSTREAM MEMORY SETUP REGISTER OFFSET .119 UPSTREAM MEMORY TRANSLATED BASE REGISTER OFFSET .119 UPSTREAM MEMORY SETUP REGISTER OFFSET ECh.119 MESSAGE SIGNALED INTERRUPTS REGISTER OFFSET .120 NEXT CAPABILITY POINTER REGISTER OFFSET F0h.120 MESSAGE CONTROL REGISTER OFFSET .120 MESSAGE ADDRESS REGISTER OFFSET .121 MESSAGE UPPER ADDRESS REGISTER OFFSET .121 MESSAGE DATA REGISTER OFFSET .121 ADVANCE ERROR REPORTING CAPABILITY REGISTER OFFSET 100h .121 Page
PERICOM SEMICONDUCTOR
September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
7.5.103 ADVANCE ERROR REPORTING CAPABILITY VERSION REGISTER OFFSET 100h .121 7.5.104 NEXT CAPABILITY OFFSET REGISTER OFFSET 100h .122 7.5.105 UNCORRECTABLE ERROR STATUS REGISTER OFFSET 104h .122 7.5.106 UNCORRECTABLE ERROR MASK REGISTER OFFSET 108h .122 7.5.107 UNCORRECTABLE ERROR SEVERITY REGISTER OFFSET 10Ch.123 7.5.108 CORRECTABLE ERROR STATUS REGISTER OFFSET 110h.123 7.5.109 CORRECTABLE ERROR MASK REGISTER OFFSET 114h.123 7.5.110 ADVANCED ERROR CAPABILITIES CONTROL REGISTER OFFSET 118h.124 7.5.111 HEADER REGISTER OFFSET 11Ch.124 7.5.112 HEADER REGISTER OFFSET 120h.124 7.5.113 HEADER REGISTER OFFSET 124h.124 7.5.114 HEADER REGISTER OFFSET 128h.124 7.5.115 SECONDARY UNCORRECTABLE ERROR STATUS REGISTER OFFSET 12Ch.125 7.5.116 SECONDARY UNCORRECTABLE ERROR MASK REGISTER OFFSET 130h.125 7.5.117 SECONDARY UNCORRECTABLE ERROR SEVERITY REGISTER OFFSET 134h.126 7.5.118 SECONDARY ERROR CAPABILITY CONTROL REGISTER OFFSET 138h .127 7.5.119 SECONDARY HEADER REGISTER OFFSET 13Ch 148h .127 7.5.120 RESERVED REGISTER OFFSET 14Ch.127 7.5.121 CAPABILITY REGISTER OFFSET 150h .127 7.5.122 CAPABILITY VERSION REGISTER OFFSET 150h .127 7.5.123 NEXT CAPABILITY OFFSET REGISTER OFFSET 150h .127 7.5.124 PORT CAPABILITY REGISTER OFFSET 154h .128 7.5.125 PORT CAPABILITY REGISTER OFFSET 158h .128 7.5.126 PORT CONTROL REGISTER OFFSET 15Ch .128 7.5.127 PORT STATUS REGISTER OFFSET 15Ch.128 7.5.128 RESOURCE CAPBILITY REGISTER OFFSET 160h.128 7.5.129 RESOURCE CONTROL REGISTER OFFSET 164h.129 7.5.130 RESOURCE STATUS REGISTER OFFSET 168h .129 7.5.131 RESERVED REGISTERS OFFSET 16Ch 2FCh.129 7.5.132 EXTENDED GPIO DATA CONTROL REGISTER OFFSET 300h .129 7.5.133 EXTRA GPI/GPO DATA CONTROL REGISTER OFFSET 304h .129 7.5.134 RESERVED REGISTERS OFFSET 308h 30Ch.130 7.5.135 REPLAY ACKNOWLEDGE LATENCY TIMERS OFFSET 310h .130 7.5.136 RESERVED REGISTERS OFFSET 314h FFCh .130 CONTROL STATUS REGISTERS NON-TRANSPARENT BRIDGE MODE .131 7.6.1 RESERVED REGISTERS OFFSET 000h 004h .131 7.6.2 DOWNSTREAM MEMORY TRANSLATED BASE REGISTER OFFSET 008h.131 7.6.3 DOWNSTREAM MEMORY SETUP REGISTER OFFSET 00Ch .131 7.6.4 DOWNSTREAM MEMORY TRANSLATED BASE REGISTER OFFSET 010h.132 7.6.5 DOWNSTREAM MEMORY SETUP REGISTER OFFSET 014h .132 7.6.6 DOWNSTREAM MEMORY UPPER 32-BIT SETUP REGISTER OFFSET 018h .132 7.6.7 RESERVED REGISTERS OFFSET 01Ch 030h.132 7.6.8 UPSTREAM MEMORY SETUP REGISTER OFFSET 034h .133 7.6.9 UPSTREAM MEMORY UPPER 32-BIT SETUP REGISTER OFFSET 038h.133 7.6.10 RESERVED REGISTERS OFFSET .133 7.6.11 LOOKUP TABLE OFFSET OFFSET .133 7.6.12 LOOKUP TABLE DATA OFFSET 054h .134 7.6.13 UPSTREAM PAGE BOUNDARY REQUEST REGISTER OFFSET 058h.134 7.6.14 UPSTREAM PAGE BOUNDARY REQUEST REGISTER OFFSET 05Ch .135 7.6.15 UPSTREAM PAGE BOUNDARY MASK REGISTER OFFSET 060h.135 7.6.16 UPSTREAM PAGE BOUNDARY MASK REGISTER OFFSET 064h.135 7.6.17 RESERVED REGISTER OFFSET 068C.135 7.6.18 PRIMARY CLEAR REGISTER OFFSET 070h .136 7.6.19 SECONDARY CLEAR REGISTER OFFSET 070h .136 Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
7.6.20 7.6.21 7.6.22 7.6.23 7.6.24 7.6.25 7.6.26 7.6.27 7.6.28 7.6.29 7.6.30 7.6.31 7.6.32 7.6.33 7.6.34 7.6.35 7.6.36 7.6.37 11.1 11.2 14.1 14.2 14.3 14.4 14.5 16.1 16.2 16.3
PRIMARY REGISTER OFFSET 074h.136 SECONDARY REGISTER OFFSET 074h.136 PRIMARY CLEAR MASK REGISTER OFFSET 078h.137 SECONDARY CLEAR MASK REGISTER OFFSET 078h .137 PRIMARY MASK REGISTER OFFSET 07Ch.137 SECONDARY MASK REGISTER OFFSET 07Ch.137 RESERVED REGISTERS OFFSET 080h 09Ch.138 SCRATCHPAD REGISTER OFFSET 0A0h .138 SCRATCHPAD REGISTER OFFSET 0A4h .138 SCRATCHPAD REGISTER OFFSET 0A8h .138 SCRATCHPAD REGISTER OFFSET 0ACh.138 SCRATCHPAD REGISTER OFFSET 0B0h .139 SCRATCHPAD REGISTER OFFSET 0B4h .139 SCRATCHPAD REGISTER OFFSET 0B8h .139 SCRATCHPAD REGISTER OFFSET 0BCh.139 RESERVED REGISTERS OFFSET 0C0h 0FCh.139 LOOKUP TABLE REGISTERS OFFSET 100h 1FCh .140 RESERVED REGISTERS OFFSET 200h FFCh .140
GPIO PINS ADDRESS .141 CLOCK SCHEME .142 INTERRUPTS .142 EEPROM (I2C) INTERFACE SYSTEM MANAGEMENT BUS.144 EEPROM (I2C) INTERFACE.144 SYSTEM MANAGEMENT .144 PLUG OPERATION .144 RESET SCHEME.145 IEEE 1149.1 COMPATIBLE JTAG CONTROLLER.146 INSTRUCTION REGISTER.146 BYPASS REGISTER .146 DEVICE REGISTER .146 BOUNDARY SCAN REGISTER .147 JTAG BOUNDARY SCAN REGISTER ORDER.147 POWER MANAGEMENT .152 ELECTRICAL TIMING SPECIFICATIONS .153 ABSOLUTE MAXIMUM RATINGS.153 SPECIFICATIONS .153 SPECIFICATIONS .154 PACKAGE INFORMATION.155 ORDERING INFORMATION.157
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
LIST TABLES
TABLE 14-1 JTAG BOUNDARY SCAN REGISTER DEFINITION .147 TABLE 16-1 ABSOLUTE MAXIMUM RATINGS .153 TABLE 16-2 ELECTRICAL CHARACTERISTICS.153 TABLE 16-3 TIMING PARAMETERS .154
LIST FIGURES
FIGURE PI7C9X130 TOPOLOGY FIGURE ASSIGNMENTS FIGURE FUNCTIONAL MODE SELECTION FIGURE PCI-X SELECTION FIGURE STRAPPING FIGURE FORWARD NON-TRANSPARENT MODE FIGURE REVERSE TRANSPARENT MODE FIGURE NON-TRANSPARENT REGISTERS FIGURE FORMAT FIGURE CONFIGURATION REGISTER (00H FFH) FIGURE EXPRESS EXTENDED CAPABILITY REGISTER (100H FFFH) FIGURE CONTROL STATUS REGISTER (CSR) (000H FFFH) FIGURE DEVICE STRAPPING .141 FIGURE 10-1 PCIE INTERRUPT MESSAGES INTERRUPTS MAPPING REVERSE BRIDGE MODE .143 FIGURE 10-2 INTERRUPTS PCIE INTERRUPT MESSAGES MAPPING FORWARD BRIDGE MODE .143 FIGURE 14-1 INSTRUCTION REGISTER CODES .146 FIGURE 14-2 JTAG DEVICE REGISTER .147 FIGURE 16-1 SIGNAL TIMING CONDITIONS .155 FIGURE 17-1 VIEW DRAWING .155 FIGURE 17-2 BOTTOM VIEW DRAWING .156 FIGURE 17-3 PACKAGE OUTLINE DRAWING .157
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
INTRODUCTION
PI7C9X130 PCIe-to-PCI/PCI-X bridge. PI7C9X130 compliant with Express Base Specification, Revision 1.1, Express Card Electromechnical Specification, Revision 1.1, Local Specification, Revision Express PCI/PCI-X Bridge Specification, Revision 1.0. PI7C9X130 supports transparent non-transparent mode operations. Also, PI7C9X130 supports forward reverse bridging. forward bridge mode, PI7C9X130 Express upstream port 64-bit PCI/PCI-X downstream port. 64-bit PCI-X downstream port 133MHz capable (see Figure 1-1). reverse bridge mode, PI7C9X130 64-bit PCI-X upstream port Express downstream port. PI7C9X130 configuration registers backward compatible with existing bridge software firmware. modification bridge software firmware needed original operation. Figure PI7C9X130 Topology
Express Link
PCI-X 64-bit, 133MHz
EXPRESS FEATURES
Compliant with Express Base Specification, Revision Compliant with Express Card Electromechnical Specification, Revision Compliant with Express PCI/PCI-X Bridge Specification, Revision Physical Layer interface link with 2.5Gb/s data rate) Lane polarity toggle Virtual isochronous support (upstream TC1-7 generation, downstream TC1-7 mapping) ASPM support Beacon support (16-bit), LCRC (32-bit) ECRC advanced error reporting PRBS (Pseudo Random Sequencing) generator/checker chip testing Maximum payload size bytes Page
PERICOM SEMICONDUCTOR
September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
PCI/PCI-X FEATURES
Compliant with Local Specification, Revision Compliant with PCI-to-PCI Bridge Architecture Specification, Revision Compliant with Interface Specification, Revision Compliant with Hot-Plug Specification, Revision Compliant with Mobile Design Guide, Version Compliant with PCI-X Protocol Addendum Local Specification, Revision 2.0a support 3.3V signaling with tolerance Provides level arbitration support masters 16-bit address decode Subsystem Vendor Subsystem Device support interrupt Function support
GENERAL FEATURES
Compliant with Advanced Configuration Power Interface Specification (ACPI), Revision 2.0b Compliant with System Management (SM) Bus, Version Forward bridging (PCI Express primary bus, secondary bus) Reverse bridging (PCI primary bus, Express secondary bus) Transparent mode support Non-transparent mode Support GPIO support bi-directional pins) Power Management (including ACPI, CLKRUN_L, PCI_PM) Masquerade Mode (pre-loadable vendor, device, revision IDs) EEPROM (I2C) Interface Interface Auxiliary powers (VAUX, VDDAUX, VDDCAUX) support Power consumption about Watt typical condition
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
DEFINITION
SIGNAL TYPES
TYPE SIGNAL DESCRIPTION Bi-directional Input Input with pull-up Input with pull-down Bi-directional with open drain output Open drain output Output Power Ground
"_L" signal name indicates Active signal
EXPRESS SIGNALS
NAME REFCLKP REFCLKN RREF ASSIGNMENT TYPE DESCRIPTION Reference Clock Input Connect external 100MHz differential clock. Express data input Differential data receiver input signals lane Express data input Differential data receiver input signals lane Express data input Differential data receiver input signals lane Express data input Differential data receiver input signals lane Express data outputs: Differential data transmitter output signals lane Express data outputs: Differential data transmitter output signals lane Express data outputs: Differential data transmitter output signals lane Express data outputs: Differential data transmitter output signals lane Resistor Reference: used connect external resistor (2.4K provide reference current driver equalization circuit. Express Fundamental Reset: PI7C9X130 uses this reset initialize internal state machines.
PERST_L
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
SIGNALS
NAME [31:0] ASSIGNMENT G16, G15, G14, G13, H16, H15, H14, H13, J15, J14, J13, K16, K15, K14, K13, N11, P11, R11, T11, N12, P12, R12, T12, R13, T13, P14, R14, T14, T15, R15, R16, D16, C15, C16, B16, B15, A15, C14, B14, C13, B13, A13, D12, C12, B12, A12, A10, F13, TYPE DESCRIPTION Address Data: Multiplexed address data bus. Address phase aligned with first clock FRAME_L assertion. Data phase aligned with IRDY_L TRDY_L assertion. Data transferred rising edges FBCLKIN when both IRDY_L TRDY_L asserted. During idle (both FRAME_L IRDY_L de-asserted), PI7C9X130 drives [31:0] valid logic level when arbiter parking PI7C9X130 bus.
[63:32]
Upper 32-bit Address Data: Multiplexed address data bus. Address phase aligned with first clock FRAME_L assertion. Data phase aligned with IRDY_L TRDY_L assertion. Data transferred rising edges FBCLKIN when both IRDY_L TRDY_L asserted. During idle (both FRAME_L IRDY_L deasserted), PI7C9X130 drives [63:32] valid logic level when arbiter parking PI7C9X130 bus.
[3:0]
[7:4]
P13, P15, A14,
PAR64
Command Byte Enables (Active LOW): Multiplexed command address phase byte enable data phase. During address phase, initiator drives commands [3:0] signals start transaction. command write transaction, initiator will drive byte enables during data phase. Otherwise, target will drive byte enables during data phase. During idle, PI7C9X130 drives [3:0] signals valid logic level when arbiter parking PI7C9X130 bus. Upper 4-bit Command Byte Enables (Active LOW): Multiplexed command address phase byte enable data phase. During address phase, initiator drives commands [3:0] signals start transaction. command write transaction, initiator will drive byte enables during data phase. Otherwise, target will drive byte enables during data phase. During idle, PI7C9X130 drives [7:4] signals valid logic level when arbiter parking PI7C9X130 bus. Parity Bit: Parity even parity (i.e. even number 1's), which generates based values [31:0], [3:0]. PI7C9X130 initiator with write transaction, PI7C9X130 will tri-state PAR. PI7C9X130 target write transaction, PI7C9X130 will drive clock after address data phase. PI7C9X130 target read transaction, PI7C9X130 will drive clock after address phase tri-state during data phases. tri-stated cycle after lines tri-stated. During idle, PI7C9X130 drives valid logic level when arbiter parking PI7C9X130 bus. Parity Upper 32-bit: Parity even parity (i.e. even number 1's), which generates based values [63:32], [7:4]. PI7C9X130 initiator with write transaction, PI7C9X130 will tri-state PAR64. PI7C9X130 target write transaction, PI7C9X130 will drive PAR64 clock after address data phase. PI7C9X130 target read transaction, PI7C9X130 will drive PAR64 clock after address phase tri-state PAR64 during data phases. PAR64 tri-stated cycle after lines tri-stated. During idle, PI7C9X130 drives PAR64 valid logic level when arbiter parking PI7C9X130 bus.
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
NAME FRAME_L
ASSIGNMENT
TYPE
DESCRIPTION FRAME (Active LOW): Driven initiator transaction indicate beginning duration access. de-assertion FRAME_L indicates final data phase signaled initiator burst transfers. Before being tri-stated, driven de-asserted state cycle. IRDY (Active LOW): Driven initiator transaction indicate ability complete current data phase primary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven de-asserted state cycle. TRDY (Active LOW): Driven target transaction indicate ability complete current data phase primary side. Once asserted data phase, de-asserted until data phase. Before tri-stated, driven de-asserted state cycle. Device Select (Active LOW): Asserted target indicating that device accepting transaction. master, PI7C9X130 waits assertion this signal within cycles FRAME_L assertion; otherwise, terminate with master abort. Before tri-stated, driven de-asserted state cycle. STOP (Active LOW): Asserted target indicating that target requesting initiator stop current transaction. Before tristated, driven de-asserted state cycle. LOCK (Active LOW): Asserted initiator multiple transactions complete. PI7C9X130 does support upstream LOCK transaction. Initialization Device Select: Used chip select line Type configuration access bridge's configuration space. Parity Error (Active LOW): Asserted when data parity error detected data received interface. Before being tristated, driven de-asserted state cycle. System Error (Active LOW): driven device indicate system error condition. SERR control enabled, PI7C9X130 will drive this Address parity error Posted write data parity error target Master abort during posted write transaction Target abort during posted write transaction Posted write transaction discarded Delayed write request discarded Delayed read request discarded Delayed transaction master timeout Errors reported from Express port (advanced error reporting) transparent mode. This signal open drain buffer that requires external pull-up resistor proper operation. Request (Active LOW): REQ_Ls asserted master devices request transactions bus. master devices de-assert REQ_Ls least clock cycles before asserting them again. external arbiter selected (CFN_L=1), REQ_L will grant input PI7C9X130. Also, REQ_L [5:2] will become [3:0]. Grant (Active LOW): PI7C9X130 asserts GNT_Ls release control master devices. During idle GNT_Ls deasserted arbiter parking PI7C9X130, PI7C9X130 will drive CBE, valid logic levels. external arbiter selected (CFN_L=1), GNT_L will request from PI7C9X130 external arbiter. Also, GNT_L [5:2] will become [3:0]. Request 64-bit transfer (Active LOW): PI7C9X130 asserts REQ64_L request 64-bit transactions when PI7C9X130 master. REQ64_L input when PI7C9X130 target device. Acknowledge 64-bit transfer (Active LOW): When PI7C9X130 target device drives ACK64_L signal master 64bit transfer. When PI7C9X130 master, ACK64_L input.
IRDY_L
TRDY_L
DEVSEL_L
STOP_L
LOCK_L
IDSEL PERR_L
SERR_L
REQ_L [5:0]
GNT_L [5:0]
REQ64_L
ACK64_L
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
NAME CLKOUT [6:0] RESET_L INTA_L INTB_L INTC_L INTD_L FBCLKIN
ASSIGNMENT N10,
TYPE
DESCRIPTION Clock Outputs: clock outputs derived from CLKIN provide clocking signals external Devices. RESET_L (Active LOW): When RESET_L active, signals should asynchronously tri-stated. Interrupt: Signals asserted request interrupt. After asserted, cleared device driver. INTA_L, INTB_L, INTC_L, INTD_L signals inputs asynchronous clock forward mode. reverse mode, INTA_L, INTB_L, INTC_L, INTD_L open drain buffers sending interrupts host interrupt controller. Feedback Clock Input: connects CLKOUT [6:0] Output Signals provides internal clocking PI7C9X130 interface. Clock Input: Clock Input Signal connects external clock source. Clock Outputs CLKOUT [6:0] pins derived from CLKIN Input. M66EN Input: driven high enable internal clock generator provide clock outputs CLKOUT[6:0] pins.
CLKIN M66EN
MODE SELECT STRAPPING SIGNALS
NAME ASSIGNMENT TYPE DESCRIPTION Mode Select strapping pin. When strapped normal operations strapped high testing functions. table mode selection strapping control details. Mode Select Mode Selection select EEPROM Bus. TM1=0 EEPROM (I2C) support TM1=1 support. also strapping pin. table mode selection strapping control. Mode Select Mode Selection select transparent nontransparent mode. TM0=0 transparent bridge function mode TM0=1 non-transparent bridge function mode. also strapping pin. table mode selection strapping control. Mask Input CLKOUT: MSK_IN used PI7C9X130 enable disable clock outputs. MSK_IN also strapping pin. When strapped high, hot-plug enabled. table strapping control. Forward Reverse Bridging Pin: REVRSB controls Forward (REVRSB=0) Reverse (REVRSB=1) Bridge Mode PI7C9X130. This also strapping pin. table mode selection. Central Function Control (Active Low): enable internal arbiter, CFN_L should tied low. When it's tied high, external arbiter required arbitrate bus. external arbiter mode, REQ_L re-configured secondary grant input, GNT_L reconfigured secondary request output. Also, REQ_L [5:2] GNT_L [5:2] become [3:0] [3:0] respectively external arbiter selected. CFN_L weak internal pull-down resistor. table mode selection.
MSK_IN
REVRSB
CFN_L
JTAG BOUNDARY SCAN SIGNALS
NAME ASSIGNMENT TYPE DESCRIPTION Test Clock: test clock synchronize state information data side PI7C9X130 during boundary scan operation.
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
NAME
ASSIGNMENT
TYPE
DESCRIPTION Test Mode Select: controls state Test Access Port (TAP) controller. Test Data Output: test data output connects JTAG scan chain. Test Data Input: test data input connects beginning JTAG scan chain. allows test instructions data serially shifted into side PI7C9X130. Test Reset (Active LOW): TRST_L test reset initialize Test Access Port (TAP) controller.
TRST_L
MISCELLANEOUS SIGNALS
NAME GPIO [6:0] ASSIGNMENT L15, R10, P10, TYPE DESCRIPTION General Purpose Data Pins: general-purpose signals programmable either input-only bi-directional signals writing GPIO output enable control register configuration space. chapter more information. SMBUS EEPROM Clock Pin: When EEPROM (I2C) interface selected (TM1=0), this output clock connected EEPROM clock input. When SMBUS interface selected (TM1=1), this input clock SMBUS. SMBUS EEPROM Data Pin: Data Interface EERPOM SMBUS. When EEPROM (I2C) interface selected (TM1=0), this bi-directional signal. When SMBUS interface selected (TM1=1), this open drain signal. Power Management Event Pin: Power Management Event Signal asserted request change device link power state. Clock (Active LOW): Clock signal, mobile environment, asserted de-asserted indicate status Clock. PCI-X Capability Pin: PI7C9X130 forced mode PCIXCAP tied ground with capacitor (0.1uF) parallel. PCIXCAP connected ground through capacitor (0.1uF), PI7C9X110 will 133MHz PCI-X mode. PCIXCAP connected ground through resistor (10K Ohm) with capacitor (0.1uF) parallel, PI7C9X110 will 66MHz PCI-X mode. PCIXCAP Pull-up driver: PI7C9X130 drives this PCI-X mode detection. Control 64-bit width: PI7C9X130 operates with 64-bit when DEV64=1. When DEV64=0, PI7C9X130 operates with 32-bit bus. Select 100MHz frequency: When SEL100=1, PI7C9X110 expects 100MHz clock. When SEL100=0, PI7C9X130 expects 133MHz. Swap Enable: PI7C9X130 supports swap when HSEN high. swap function used. Swap Switch: PI7C9X130 detects HSSW input monitor insertion impending extraction board. On/Off: PI7C9X130 drives illumination that signals operator extract board. ENUM_L signal: PI7C9X130 drives ENUM_L notify system host that either board been freshly inserted about extracted.
SMBCLK
SMBDAT
B/IOD
PME_L CLKRUN_L
PCIXCAP
PCIXUP DEV64 SEL100
HSEN HSSW ENUM_L
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
POWER GROUND PINS
NAME VDDA VDDP VDDAUX VDDA_PLL VDDP_PLL VDDC ASSIGNMENT M11, M12, J11, H11, E11, E10, L10, L11, M10, T16, N13, L12, K12, K11, J12, H12, G11, G12, F12, A16, D13, E12, F11, K10, J10, H10, G10, F10, TYPE DESCRIPTION Analog Voltage Supply Express Interface: Connect 1.8V Power Supply. Digital Voltage Supply Express Interface: Connect 1.8V Power Supply. Auxiliary Voltage Supply Express Interface: Connect 1.8V Power Supply. Termination Supply Voltage Express Interface: Connect 1.8V Power Supply. Analog Voltage Supply Interface: Connect 1.8V Power Supply. Digital Voltage Supply Interface: Connect 1.8V Power Supply. Core Supply Voltage: Connect 1.8V Power Supply.
VDDCAUX VD33
Auxiliary Core Supply Voltage: Connect 1.8V Power Supply. Supply Voltage Interface: Connect 3.3V Power Supply Buffers.
VAUX
Auxiliary Supply Voltage interface: Connect 3.3V Power Supply. Ground: Connect Ground.
ASSIGNMENT
Figure Assignments
Name VDDC PCIXCAP SMBDAT AD[30] AD[26] AD[23] AD[19] CBE[2] DEVSEL_L AD[33] Name VDDA VD33 VD33 VD33 VD33 VD33 VDDC VDDC VD33 Name VDDA VDDA VDDP VDDC VD33 Name VDDP REQ_L[4] GPI[2] VD33 GNT_L[2] GPO[0] RESET_L GPIO[1] CLKOUT[2] CLKOUT[6] AD[63] AD[59]
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Name AD[37] CBE[5] AD[42] VD33 VAUX PCIXUP FBCLKIN SMBCLK AD[29] AD[25] AD[22] AD[18] FRAME_L STOP_L AD[34] AD[38] AD[40] AD[43] AD[44] VDDP_PLL CLKRUN_L PME_L AD[28] AD[24] AD[21] AD[17] IRDY_L CBE[4] AD[35] AD[39] AD[41] AD[46] AD[45] REFCLKN REFCLKP VDDA_PLL AD[31] AD[27] CBE[3] AD[20] AD[16] TRDY_L AD[32] AD[36] VD33 REQ64_L PAR64 AD[47]
Name LOCK_L SEL100 DEV64 ACK64_L VDDP VDDAUX VD33 VD33 CBE[1] SERR_L PERR_L VDDP VD33 VD33 AD[12] AD[13] AD[14] AD[15] VDDA RREF VDDCAUX VDDC VD33 AD[8] AD[9] AD[10] AD[11]
Name AD[5] AD[6] AD[7] CBE[0] VDDC VD33 VD33 AD[1] AD[2] AD[3] AD[4] VDDAUX VD33 VD33 VD33 TRST_L GPIO[6] AD[0] VDDP VDDC VDDC VD33 VD33 VD33 VD33 VDDC VDDC IDSEL
Name VD33 REVRSB INTD_L MSK_IN PERST_L REQ_L[1] REQ_L[5] GPI[3] INTA_L GNT_L[3] GPO[1] ENUM_L CFN_L GPIO[0] CLKOUT[3] GPIO[4] AD[62] AD[58] CBE[7] AD[53] CBE[6] REQ_L[0] REQ_L[2] GPI[0] HSEN GNT_L[0] GNT_L[4] GPO[2] INTB_L GPIO[3] CLKOUT[0] CLKOUT[4] GPIO[5] AD[61] AD[57] AD[55] AD[52] AD[49] AD[48] VD33 REQ_L[3] GPI[1] HSSW GNT_L[1] GNT_L[5] GPO[3] CLKIN M66EN GPIO[2] CLKOUT[1] CLKOUT[5] INTC_L AD[60] AD[56] AD[54] AD[51] AD[50] VD33
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
MODE SELECTION STRAPPING
FUNCTIONAL MODE SELECTION
strapped low, PI7C9X130 uses TM1, TM0, CFN_L, REVRSB pins select different modes operations. These four input signals required stable during normal operation. sixteen combinations normal operation selected setting logic values four mode select pins. example, logic values four (TM1, TM0, CFN_L, REVRSB) pins, normal operation will have EEPROM (I2C) support transparent mode with internal arbiter forward bridge mode. designated operation with respect values TM1, TM0, CFN_L, REVRSB pins defined Table 3-1: Figure Functional Mode Selection
Strapped
CFN_L
REVRSB
Functional Mode
EEPROM (I2C) support support Transparent mode Non-Transparent mode Internal arbiter External arbiter Forward bridge mode Reverse bridge mode
PCI/PCI-X SELECTION
secondary interface capable operating either conventional mode PCI-X mode. PI7C9X130 controls mode frequency secondary utilizing pull-up circuit connected PCIXCAP. There pull-up resistors circuit recommended PCI-X addendum. first resistor weak pull-up (56K ohms) whose value selected voltage PCIXCAP below threshold when PCI-X 66MHz device attached secondary bus. second resistor strong pull-up, externally wired between PCIXCAP PCIXUP. value resistor ohm) selected voltage PCIXCAP above high threshold when devices secondary PCI-X 66MHz capable. detect mode frequency secondary bus, PCIXUP initially disabled PI7C9X130 samples value PCIXCAP. PI7C9X130 sees logic PCIXCAP, more devices secondary have either pulled signal ground (PCI-X 66MHz capable) tied ground (only capable conventional mode). differentiate between conditions, PI7C9X130 then enables PCIXUP strong pull-up into circuit node. PCIXCAP remains logic LOW, must tied ground more devices, initialized conventional mode. PCIXUP pulled more devices capable only PCI-X 66MHz operation initialized PCI-X 66MHz mode. PI7C9X130 sees logic HIGH PCIXCAP, then devices secondary capable PCI-X 100MHz 133MHz operation. PI7C9X130 then samples SEL100 distinguish between 100MHz 133MHz clock frequencies. PI7C9X130 sees logic HIGH SEL100, secondary initialized PCI-X 100MHz mode. value LOW, PCI-X 133MHz initialized. These clock frequencies allow flexibility support different loading conditions.
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
There M66EN secondary interface PI7C9X130 because internal bypassed conventional mode. CLKIN used directly, eliminating need distinguish between conventional 33MHz 66MHz. Figure PCI-X Selection
PI7C9X130
3.3v Ohms PCIXCAP Ohms Strong Pull-up 0.01uF PCIXUP Ohms 0.01uF 0.01uF Weak Pull-up
Enable During Capability Determination
3.3v
Card 3.3v Ohms SEL100 High
PCI-X 66MHz Card
PCI-X 100MHz 133MHz Card
STRAPPING
strapped high, PI7C9X130 uses TM1, TM0, MSK_IN strapping pins. strapping functions listed Table show states operations during Express PERST_L deassertion transition forward bridge mode RESET_L de-assertion transition reverse bridge mode. Figure Strapping
Strapped
Strapped
Strapped
MSK_IN Strapped
Test Functions
test Shorten initialization test with Hot-Plug enabled Functional loopback test Bridge test (PRBS, IDDQ, etc.)
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Strapped
Strapped
Strapped
MSK_IN Strapped
Test Functions
Reserved Shorten initialization test with Hot-Plug disabled Reserved Reserved
FORWARD REVERSE BRIDGING
PI7C9X130 supports forward reverse transparent non-transparent combination modes operation. example, when PI7C9X130 operating forward (REVRSB=0) non-transparent bridge mode (TM0=1) shown Figure 4-1, Express interface connected root complex PCI-X interface connected PCI-X devices. Another example, PI7C9X130 configured reverse (REVRSB=1) transparent (TM0=0) bridge shown Figure 4-2. non-transparent bridge feature PI7C9X130 allows Processor isolated from Host Processor memory which avoiding memory address conflict when both host processors needed side-by-side. PCI/PCI-X based systems peripherals ubiquitous interconnect technology market today. will tremendous effort convert existing PCI/PCI-X based products used Express systems. PI7C9X130 provides solution bridge existing PCI/PCI-X based products latest Express technology. Figure Forward Non-transparent Mode
Host Processor
System Memory
Root Complex
Other Express Subsystems
Link
Processor
PCI-X 64-bit, 133MHz
Gigabit Ethernet
Local Memory
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
reverse (REVRSB=1) transparent (TM0=0) mode shown Figure 3-2, PI7C9X130 becomes PCI-to-PCI Express bridge that PCI-X interface connected host chipset between Express link. enables legacy PCI/PCI-X Host Systems provide Express capability. PI7C9X130 provides solution convert existing PCI/PCI-X based designs adapt quickly into Express base platforms. Existing PIC/PCI-X based applications will have undergo complete rearchitecture order interface Express technology. Figure Reverse Transparent Mode
Host Processor
System Memory
Chipset
PCI-X 64-bit,
Gigabit Ethernet
link
TRANSPARENT NON-TRANSPARENT BRIDGING
TRANSPARENT MODE
transparent bridge mode, base class code PI7C9X130 (bridge device). subclass code (PCI-to-PCI bridge). Programming interface 00h. Hence, PI7C9X130 subtractive decoding bridge. PI7C9X130 type-1 configuration header (transparent bridge mode). These configuration registers same traditional transparent PCI-to-PCI Bridge. fact, backward compatible software that supporting traditional transparent PCI-to-PCI bridges. Configuration registers accessed from several different ways. Express access, Express configuration transaction forward bridge mode. access, configuration cycle mainly reverse bridge mode. However, PI7C9X130 allows configuration access forward mode secondary configuration access. access, protocol used with EEPROM selected (TM1=0). access, protocol used with selected (TM1=1).
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
NON-TRANSPARENT MODE
non-transparent bridge mode, base class code PI7C9X130 (bridge device). subclass code (other bridge). Programming interface 00h. Hence, PI7C9X130 subtractive decoding bridge. PI7C9X130 type-0 configuration header (non-transparent mode). configuration registers similar traditional device. However, there configuration registers primary interface another configuration registers secondary interface. addition, CSRs (Control Status Registers) implemented support memory transfers between primary secondary buses. CSRs accessed through memory transaction access within lowest memory range Space (bit [64:12] zeros). non-transparent configuration registers accessed through several different ways (PCI Express, PCI, I2C, bus). Express access, type-0 configuration transactions need used. access, protocol needs used through interface. access, protocol needs used through interface. hardware pins shared interface. TM1=0, pins will interface respectively. TM1=1, pins will SMBCLK SMBDAT interface respectively. non-transparent bridge mode, PI7C9X130 supports four three memory BARs (Base Address Registers) BARs (Base Address Registers) depending selection primary bus. Also, PI7C9X130 supports four three memory BARs (Base Address Registers) BARs (Base Address Registers) depending selection secondary bus. Offset defined primary downstream memory BAR. Offset defined primary downstream BAR. Offset defined downstream memory (selectable setup register). Offset defined downstream memory BAR. Offset defined downstream memory lower memory upper respectively support 64-bit decoding. direct offset translation address from primary secondary will done substituting original Base Address primary with downstream Translation Base Address Register values keeping lower address bits same form address forward transaction secondary bus. downstream memory uses direct address translation. There lookup table downstream memory address translation. Offset defined secondary upstream memory BAR. Offset defined secondary upstream BAR. Offset defined upstream memory (selectable setup register offset E4h). Offset defined upstream memory BAR. Offset defined upstream memory lower memory upper respectively support 64-bit decoding. direct offset translation address from secondary primary will done substituting original Base Address secondary with upstream Translation Base Address Register values keeping lower address bits same form address forward transaction primary bus. upstream memory uses lookup table address translation method which using original base address index select address upstream memory lookup table based page window size defined.
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Figure Non-Transparent Registers
Non-transparent Registers
Primary Memory Downstream Memory Translated Base Downstream Memory Setup Primary Downstream Memory Downstream Memroy Translated Base Donwstream Memroy Setup Downstream Memory Downstream Memory Translated Base Downstream Memory Setup Downstream Memory Downstream Memory Setup Downstream Memory Downstream Memory Setup Downstream Memory Secondary Memory Upstream Memory Translated Base Upstream Memory Setup Secondary Upstream Memory Upstream Memory Translated Base Upstream Memory Setup Upstream Memory Upstream Memory Lookup Table Offset Upstream Memory Lookup Table Data Upstream Memory Lookup Table 32-bit entries) Upstream Memory Upstream Memory Upper 32-bit Upstream Memory Setup Upstream Memory Upper 32-bit Setup
Typical Access
Configuration access offset Configuration access offset Configuration access offset Configuration access offset Configuration access offset Configuration access offset Configuration access offset Configuration access offset Lower Memory access offset 008h Lower Memory access offset 00Ch Configuration access offset Lower Memory access offset 00Ch Configuration access offset Lower Memory access offset 00Ch Configuration access offset Configuration access offset Configuration access offset Configuration access offset Configuration access offset Configuration access offset Configuration access offset Configuration access offset Configuration access offset Lower Memory access offset 050h Lower Memory access offset 054h Lower Memory access offset 100h 1FFh Configuration access offset Configuration access offset Lower Memory access offset Lower Memory access offset
EXPRESS FUNCTIONAL OVERVIEW
STRUCTURE
Express (Transaction Layer Packet) Structure comprised format, type, traffic class, attributes, digest, poison, length data payload. There four formats defined PI7C9X130 based states shown Table 6-1. Figure Format
FORMAT
double word, without data double word, without data double word, with data double word, with data
Data payload PI7C9X130 range from (1DW) (64DW) bytes. PI7C9X130 supports three routing mechanisms. They comprised Address, Implicit routings. Address routing being used Memory requests. based (bus, device, function numbers) routing being used
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
configuration requests. Implicit routing being used message routing. There message groups (baseline advanced switching). baseline message group contains INTx interrupt signaling, power management, error signaling, locked transaction support, slot power limit support, vendor defined messages, hot-plug signaling. other advanced switching support message group. advanced switching support message contains data packet signal packet messages. Advanced switching beyond scope PI7C9X130 implementation. [2:0] values "type" field will determine destination message routed. baseline messages must default traffic class zero (TC0).
VIRTUAL ISOCHRONOUS OPERATION
This section provides summary Virtual Isochronous Operation supported PI7C9X130. Virtual Isochronous support disabled default. Virtual Isochronous feature turned with setting [26] offset one. Control bits designated selecting which traffic class (TC1-7) used upstream (PCI Express-to-PCI). PI7C9X130 accepts only packets configuration, message packets downstream (PCI Express-to-PCI). configuration, message packets have traffic class other than TC0, PI7C9X130 will treat them malformed packets. PI7C9X130 maps downstream memory packets from Express transactions regardless virtual isochronous operation enabled not.
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
CONFIGURATION REGISTERS
PI7C9X130 supports Type-0 (non-transparent bridge mode) Type-1 (transparent bridge mode) configuration space headers Capability (PCI power management) (PCI Express capability structure). With REVRSB device-port type (bit [7:4]) capability register will (PCI Expressto-PCI/PIC-X bridge). When REVRSB device-port type (bit [7:4]) capability register will (PCI/PCI-X-to-PCI Express bridge). PI7C9X130 supports Express capabilities register structure with capability version (bit [3:0] offset 02h). When TM0=0, PI7C9X130 will transparent bridge mode configuration registers transparent bridge should used. When TM0=1, PI7C9X130 will non-transparent bridge mode configuration registers non-transparent bridge should used.
CONFIGURATION REGISTER
PI7C9X130 supports capability pointer with PCI-X (ID=07h), power management (ID=01h), bridge sub-system vendor (ID=0Dh), Express (ID=10h), vital product data (ID=03h), message signaled interrupt (ID=05h). swap (ID=06h) enabled setting HSEN=1. Slot identification (ID=04h) default turned through configuration programming. Figure Configuration Register (00h FFh)
Primary Configuration Access both Transparent Non-transparent mode Secondary Configuration Access Transparent Mode
Secondary Configuration Access NonTransparent Mode only
Transparent Mode (type1)
NonTransparent Mode (Type0)
EEPROM (I2C) Access
Access
Vendor Device Command Register Primary Status Register Class Code Revision Cacheline Size Register Primary Latency Timer
Vendor Device Primary Command Register Primary Status Register Class Code Revision Primary Cacheline Size Register Primary Latency Timer
Yes1 Yes1
Yes5 Yes5
Yes1
Yes5
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Primary Configuration Access both Transparent Non-transparent mode Secondary Configuration Access Transparent Mode
Secondary Configuration Access NonTransparent Mode only
Transparent Mode (type1)
NonTransparent Mode (Type0)
EEPROM (I2C) Access
Access
Header Type Register Reserved Reserved
Reserved Primary Number Register Secondary Number Register Subordinate Number Register Secondary Latency Timer Base Register Limit Register Secondary Status Register Memory Base Register Memory Limit Register Prefetchable Memory Base Register Prefetchable Memory Limit Register Prefetchable Memory Base Upper 32-bit Register Prefetchable Memory Limit Upper 32-bit Register Prefetchable Memory Limit Upper 32-bit Register Base Upper 16-bit Register Limit Upper 16-bit Register
Header Type Register Reserved Primary Memory Primary Downstream Memory Downstream Memory Downstream Memory Downstream Memory Downstream Memory Downstream Memory Downstream Memory Downstream Memory Downstream Memory Downstream Memory Upper 32-bit Downstream Memory Upper 32-bit Reserved
Subsystem Vendor
Subsystem
Reserved Reserved
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Primary Configuration Access both Transparent Non-transparent mode Secondary Configuration Access Transparent Mode
Secondary Configuration Access NonTransparent Mode only
Transparent Mode (type1)
NonTransparent Mode (Type0)
EEPROM (I2C) Access
Access
Capability Pointer Reserved Reserved Interrupt Line Interrupt Bridge Control Bridge Control Data Buffering Control Chip Control Reserved
Reserved Arbiter Mode, Enable, Priority Reserved
Reserved Reserved Reserved Reserved
Reserved Reserved Reserved Reserved Reserved
Express Control Reserved
Reserved Reserved
Capability Pointer Reserved Reserved Primary Interrupt Line Primary Interrupt Primary Min_Gnt Primary Max_Lat Data Buffering Control Chip Control Secondary Command Register Secondary Status Register Arbiter Mode, Enable, Priority Secondary Cacheline Size Register Secondary Status Register Header Type Reserved Secondary Memory Secondary Upstream Memory Upstream Memory Upstream Memory Upstream Memory Upper 32-bit Express Control Memory Address Forwarding Control Reserved Subsystem
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Primary Configuration Access both Transparent Non-transparent mode Secondary Configuration Access Transparent Mode
Secondary Configuration Access NonTransparent Mode only
Transparent Mode (type1)
NonTransparent Mode (Type0)
EEPROM (I2C) Access
Access
Reserved EEPROM (I2C) Control Status Register Swap Capability GPIO Data Control bits) Reserved bits)
Vendor Subsystem EEPROM (I2C) Control status Register Swap Capability GPIO Data Control bits) Bridge Control Status bits) Reserved bits) Secondary Interrupt Line Secondary Interrupt Secondary Min_Gnt Secondary Max_Lat PCI-X Capability PCI-X Bridge Status Upstream Split Transaction Downstream Split Transaction Power Management Capability Power Management Control Status Downstream Memory Translated Base Downstream Memory Setup Slot Capability Clock CLKRUN Control Downstream Memory Translated
Reserved Reserved Reserved Reserved PCI-X Capability PCI-X Bridge Status Upstream Split Transaction Downstream Split Transaction Power Management Capability Power Management Control Status Reserved
Reserved
Slot Capability Clock CLKRUN Control SSID SSVID Capability
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Primary Configuration Access both Transparent Non-transparent mode Secondary Configuration Access Transparent Mode
Secondary Configuration Access NonTransparent Mode only
Transparent Mode (type1)
NonTransparent Mode (Type0)
EEPROM (I2C) Access
Access
Subsystem Subsystem Vendor Express Capability Device Capability Device Control Status Link Capability Link Control Status Slot Capability Slot Control Status XPIP Configuration Register XPIP Configuration Register XPIP Configuration Register Swap Switch debounce counter Capability Register Data Register Reserved
Reserved Reserved
Reserved
Capability Register Message Address Message Upper Address Message Data
Base Downstream Memory Setup Express Capability Device Capability Device Control Status Link Capability Link Control Status Slot Capability Slot Control Status XPIP Configuration Register XPIP Configuration Register XPIP Configuration Register Swap Switch debounce counter Capability Register Data Register Upstream Memory Translated Base Upstream Memory setup Upstream Memory Translated Base Upstream Memory Setup Capability Register Message Address Message Upper Address Message Data
Yes4
Note When masquerade enabled, pre-loadable. Note When both masquerade non-transparent mode enabled, pre-loadable.
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Note When non-transparent mode enabled, pre-loadable. Note data read/write through during operation. Note Read access only.
EXPRESS EXTENDED CAPABILITY REGISTER
PI7C9X130 also supports Express Extended Capabilities with from 257-byte 4096-byte space. offset range from 100h FFFh. offset 100h defined Advance Error Reporting (ID=0001h). offset 150h defined Virtual Channel (ID=0002h). Figure Express Extended Capability Register (100h FFFh)
Primary Configuration Access both Transparent Non-transparent mode Secondary Configuration Access Transparent Mode
103h 100h
Secondary Configuration Access NonTransparent Mode only
Transparent Mode (type1)
NonTransparent Mode (Type0)
EEPROM (I2C) Access
Access
103h 100h
107h 104h 10Bh 108h 10Fh 10Ch 113h 110h 117h 114h 11Bh 118h 12Bh 11Ch 12Fh 12Ch
107h 104h 10Bh 108h 10Fh 10Ch 113h 110h 117h 114h 11Bh 118h 12Bh 11Ch 12Fh 12Ch
133h 130h
133h 130h
137h 134h
137h 134h
13Bh 138h 14Bh 13Ch
13Bh 138h 14Bh 13Ch
14Fh 14Ch 153h 150h 157h 154h 15Bh 158h
14Fh 14Ch 153h 150h 157h 154h 15Bh 158h
Advanced Error Reporting (AER) Capability Uncorrectable Error Status Uncorrectable Error Mask Uncorrectable Severity Correctable Error Status Correctable Error Mask Control Header Register Secondary Uncorrectable Error Status Secondary Uncorrectable Error Mask Secondary Uncorrectable Severity Secondary Control Secondary Header Register Reserved Capability Port Capability Port Capability
Advanced Error Reporting (AER) Capability Uncorrectable Error Status Uncorrectable Error Mask Uncorrectable Severity Correctable Error Status Correctable Error Mask Control Header Register Secondary Uncorrectable Error Status Secondary Uncorrectable Error Mask Secondary Uncorrectable Severity Secondary Control Secondary Header Register Reserved Capability Port Capability Port Capability
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Primary Configuration Access both Transparent Non-transparent mode Secondary Configuration Access Transparent Mode
15Fh 15Ch 163h 160h 167h 164h 16Bh 168h 2FFh 170h 303h 300h
Secondary Configuration Access NonTransparent Mode only
Transparent Mode (type1)
NonTransparent Mode (Type0)
EEPROM (I2C) Access
Access
15Fh 15Ch 163h 160h 167h 164h 16Bh 168h 2FFh 170h 503h 500h
307h 304h
507h 504h
30Fh 308h 310h
50Fh 508h 510h
4FFh 314h 503h 500h 504h 50Fh 505h 510h FFFh 514h
4FFh 314h 303h 300h 304h 30Fh 305h 310h FFFh 514h
Port Status Control Resource Capability Resource Control Resource Status Reserved Extended GPIO Data Control Extended GPI/GPO Data Control Reserved Replay Acknowledge Latency Timer Reserved Reserved Reserved Reserved Reserved Reserved
Port Status Control Resource Capability Resource Control Resource Status Reserved Extended GPIO Data Control Extended GPI/GPO Data Control Reserved Replay Acknowledge Latency Timer Reserved Reserved Reserved Reserved Reserved Reserved
Note Read access only.
CONTROL STATUS REGISTER
Figure Control Status Register (CSR) (000h FFFh)
Express Memory Offset
007h 000h 00Bh 008h
Offset
207h 200h 20Bh 208h
Register Name
Reserved Downstream Memory Translated Base Downstream Memory Setup Downstream Memory Translated Base Downstream Memory Setup
Reset Value
EEPROM (I2C) Access
Access
XXXX_XXXXh
00Fh 00Ch
20Fh 20Ch
0000_0000h
013h 010h
213h 210h
XXXX_XXXXh
017h 014h
217h 214h
0000_0000h
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Express Memory Offset
01Bh 018h
Offset
21Bh 218h
Register Name
Downstream Memory Upper 32-bit Setup Reserved Reserved Upstream Memory Setup Upstream Memory Upper 32-bit Setup Reserved Lookup Table Offset Register Reserved Lookup Table Data Register Upstream Page Boundary Upstream Page Boundary Upstream Page Boundary Mask Upstream Page Boundary Mask Reserved Primary Clear Register Secondary Clear Register Primary Register Secondary Register Primary Clear Mask Register Secondary Clear Mask Register Primary Mask Register Secondary Mask Register Reserved Scratch Scratch Scratch Scratch Scratch Scratch Scratch Scratch Reserved
Reset Value
EEPROM (I2C) Access
Access
0000_0000h
02Fh 01Ch 033h 030h 037h 034h
22Fh 21Ch 233h 230h 237h 234h
0000_0000h
03Bh 038h
21Bh 218h
0000_0000h
04Fh 03Ch 050h 053h 051h 057h 054h 05Bh 058h
24Fh 23Ch 250h 253h 251h 257h 254h 25Bh 258h
XXXX_XXXXh 0000_0000h
05Fh 05Ch
25Fh 25Ch
0000_0000h
063h 060h
263h 260h
FFFF_FFFFh
067h 064h
267h 264h
FFFF_FFFFh
06Fh 068h 071h 070h 073h 072h 075h 074h 077h 076h 079h 078h
26Fh 268h 271h 270h 273h 272h 275h 274h 277h 276h 279h 278h
0000h 0000h 0000h 0000h FFFFh
07Bh 07Ah
27Bh 27Ah
FFFFh
07Dh 07Ch
27Dh 27Ch
FFFFh
07Fh 07Eh
27Fh 27Eh
FFFFh
09Fh 080h 0A3h 0A0h 0A7h 0A4h 0ABh 0A8h 0AFh 0ACh 0B3h 0B0h 0B7h 0B4h 0BBh 0B8h 0BFh 0BCh 0FFh 0C0h
29Fh 280h 2A3h 2A0h 2A7h 2A4h 2ABh 2A8h 2AFh 2ACh 2B3h 2B0h 2B7h 2B4h 2BBh 2B8h 2BCh 2BFh 2FFh 2C0h
XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh XXXX_XXXXh
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Express Memory Offset
1FFh 100h
Offset
3FFh 300h
Register Name
Upstream Memory Lookup Table Reserved
Reset Value
EEPROM (I2C) Access
Access
FFFh 200h
11FFh 400h
CONFIGURATION REGISTERS TRANSPARENT BRIDGE MODE
following section describes configuration space when device transparent mode. descriptions different register type listed follow:
Register Type
RWCS
Descriptions
Read Only Read Only Sticky Read/Write Read/Write clear Read/Write Sticky Read/Write clear Sticky
7.4.1
VENDOR OFFSET
15:0
Function
Vendor
Type
Description
Identifies Pericom vendor this device. Returns 12D8h when read.
7.4.2
DEVICE OFFSET
31:16
Function
Device
Type
Description
Identifies this device PI7C9X130. Returns E130 when read.
7.4.3
COMMAND REGISTER OFFSET
Function
Space Enable
Type
Description
Ignore transactions primary interface Enable response memory transactions primary interface Reset Ignore memory read transactions primary interface Enable memory read transactions primary interface Reset initiate memory transactions primary interface disable response memory transactions secondary interface Enable bridge operate master primary interfaces memory transactions forwarded from secondary interface. primary reverse bridge PCI-X mode, bridge allowed initiate split completion transaction regardless status bit. Reset
Memory Space Enable
Master Enable
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Function
Special Cycle Enable
Type
Description
PI7C9X130 does respond target Special Cycle transactions, this defined Read-Only must return when read Reset PI7C9X130 does originate Memory Write Invalidate transaction. Implements this Read-Only returns when read (unless forwarding transaction another master). This will ignored PCI-X mode. Reset This applies reverse bridge only. Ignore palette access primary Enable positive decoding response palette writes primary interface with address bits [9:0] equal 3C6h, 3C8h, 3C9h (inclusive alias; [15:0] decoded value) Reset ignore parity error that detected take normal action This set, enables setting Master Data Parity Error Status Register when poisoned received parity error detected takes normal action Reset Wait cycle control supported Reset Disable Enable PI7C9X130 forward bridge mode report non-fatal fatal error message Root Complex. Also, reverse bridge mode assert SERR_L primary interface Reset Fast back-to-back enable supported Reset This applies reverse bridge only. INTA_L, INTB_L, INTC_L, INTD_L asserted interface Prevent INTA_L, INTB_L, INTC_L, INTD_L from being asserted interface Reset Reset 00000
Memory Write Invalidate Enable
Palette Snoop Enable
Parity Error Response Enable
Wait Cycle Control
SERR_L Enable
Fast Back-to-Back Enable Interrupt Disable
15:11
Reserved
7.4.4
PRIMARY STATUS REGISTER OFFSET
19:16
Function
Reserved Capability List Capable
Type
Description
Reset 0000 PI7C9X130 supports capability list (offset pointer data structure) Reset This applies reverse bridge only. 66MHz capable Reset when forward bridge when reverse bridge. Reset
66MHz Capable
Reserved
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Function
Fast Back-to-Back Capable
Type
Description
This applies reverse bridge only. Enable fast back-to-back transactions Reset when forward bridge when reverse bridge mode. Parity Error Enable either conditions occurs primary: FORWARD BRIDGE Receives completion marked poisoned Poisons write request REVERSE BRIDGE Detected parity error when receiving data Split Response read Observes P_PERR_L asserted when sending data receiving Split Response write Receives Split Completion Message indicating data parity error occurred non-posted write Reset These bits apply reverse bridge only. fast DEVSEL_L decoding medium DEVSEL_L decoding slow DEVSEL_L decoding reserved
Master Data Parity Error Detected
26:25
DEVSEL_L Timing (medium decode)
Signaled Target Abort
Reset when forward bridge when reverse bridge. FORWARD BRIDGE This when PI7C9X130 completes request using completer abort status primary REVERSE BRIDGE This indicate target abort primary Reset FORWARD BRIDGE This when PI7C9X130 receives completion with completer abort completion status primary REVERSE BRIDGE This when PI7C9X130 detects target abort primary Reset FORWARD BRIDGE This when PI7C9X130 receives completion with unsupported request completion status primary REVERSE BRIDGE This when PI7C9X130 detects master abort primary FORWARD BRIDGE This when PI7C9X130 sends ERR_FATAL ERR_NON_FATAL message primary REVERSE BRIDGE This when PI7C9X130 asserts SERR_L primary Reset FORWARD BRIDGE This when poisoned detected primary REVERSE BRIDGE This when address data parity error detected primary Reset
Received Target Abort
Received Master Abort
Signaled System Error
Detected Parity Error
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
7.4.5
REVISION REGISTER OFFSET
Function
Revision
Type
Description
Reset 00000000
7.4.6
CLASS CODE REGISTER OFFSET
15:8
Function
Programming Interface Sub-Class Code
Type
Description
Subtractive decoding PCI-PCI bridge supported Reset 00000000 Sub-Class Code 00000100: PCI-to-PCI bridge Reset 00000100 Base class code 00000110: Bridge Device Reset 00000110
23:16
31:24
Base Class Code
7.4.7
CACHE LINE SIZE REGISTER OFFSET
Function
Reserved
Type
Description
[1:0] supported Reset Cache line size double words Reset Cache line size double words Reset Cache line size double words Reset Cache line size double words Reset [7:6] supported Reset
Cache Line Size
Cache Line Size
Cache Line Size
Cache Line Size
Reserved
7.4.8
PRIMARY LATENCY TIMER REGISTER OFFSET
15:8
Function
Primary Latency Timer
Type
Description
bits primary latency timer PCI/PCI-X FORWARD BRIDGE with reset REVERSE BRIDGE with reset mode PCI-X mode
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
7.4.9
HEADER TYPE REGISTER OFFSET
22:16
Function
PCI-to-PCI bridge configuration Single Function Device Reserved
Type
Description
PCI-to-PCI bridge configuration 3Fh) Reset 0000001 Indicates single function device Reset Reset
31:24
7.4.10 7.4.11
RESERVED REGISTERS OFFSET PRIMARY NUMBER REGISTER OFFSET
Function
Primary Number
Type
Description
Reset
7.4.12
SECONDARY NUMBER REGISTER OFFSET
15:8
Function
Secondary Number
Type
Description
Reset
7.4.13
SUBORDINATE NUMBER REGISTER OFFSET
23:16
Function
Subordinate Number
Type
Description
Reset
7.4.14
SECONDARY LATENCY TIMER REGISTER OFFSET
31:24
Function
Secondary Latency Timer
Type
Description
Secondary latency timer PCI-X mode FORWARD BRIDGE with reset mode PCI-X mode REVERSE BRIDGE with reset
7.4.15
BASE REGISTER OFFSET
Function
32-bit Addressing Support Reserved
Type
Description
Indicates PI7C9X130 supports 32-bit addressing Reset Reset
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Function
Base
Type
Description
Indicates Base (0000_0000h) Reset 0000
7.4.16
LIMIT REGISTER OFFSET
Function
32-bit Addressing Support Reserved Base
Type
Description
Indicates PI7C9X130 supports 32-bit addressing Reset Reset Indicates Limit (0000_0FFFh) Reset 0000
11:10 15:12
7.4.17
SECONDARY STATUS REGISTER OFFSET
20:16
Function
Reserved 66MHz Capable
Type
Description
Reset 00000 Indicates PI7C9X130 66MHz capable Reset Reset FORWARD BRIDGE: reset when secondary mode (supports fast back-to-back transactions) reset when secondary PCI-X mode (does support fast back-to-back transactions) REVERSE BRIDGE: reset (does support fast back-to-back transactions) This parity error enable either conditions occur primary: FORWARD BRIDGE Detected parity error when receiving data split response read Observes S_PERR_L asserted when sending data receiving split response write Receives split completion message indicating data parity error occurred non-posted write REVERSE BRIDGE Receives completion marked poisoned Poisons write request Reset These bits apply forward bridge only. medium DEVSEL_L decoding Reset when forward mode when reverse mode. FORWARD BRIDGE when PI7C9X130 signals target abort REVERSE BRIDGE when PI7C9X130 completes request using completer abort completion status Reset
Reserved Fast Back-to-Back Capable
Master Data Parity Error Detected
26:25
DEVSEL_L Timing (medium decoding)
Signaled Target Abort
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Function
Received Target Abort
Type
Description
FORWARD BRIDGE when PI7C9X130 detects target abort secondary interface REVERSE BRIDGE when PI7C9X130 receives completion with completer abort completion status secondary interface Reset FORWARD BRIDGE when PI7C9X130 detects master abort secondary interface REVERSE BRIDGE when PI7C9X130 receives completion with unsupported request completion status primary interface Reset FORWARD BRIDGE when PI7C9X130 detects SERR_L assertion secondary interface REVERSE BRIDGE when PI7C9X130 receives ERR_FATAL ERR_NON_FATAL message secondary interface Reset FORWARD BRIDGE when PI7C9X130 detects address data parity error REVERSE BRIDGE when PI7C9X130 detects poisoned secondary interface Reset
Received Master Abort
Received System Error
Detected Parity Error
7.4.18
MEMORY BASE REGISTER OFFSET
15:4
Function
Reserved Memory Base
Type
Description
Reset 0000 Memory Base (80000000h) Reset 800h
7.4.19
MEMORY LIMIT REGISTER OFFSET
19:16 31:20
Function
Reserved Memory Limit
Type
Description
Reset 0000 Memory Limit (000FFFFFh) Reset 000h
7.4.20
PREFETCHABLE MEMORY BASE REGISTER OFFSET
Function
64-bit Addressing Support Prefetchable Memory Base
Type
Description
0001: Indicates PI7C9X130 supports 64-bit addressing Reset 0001 Prefetchable Memory Base (00000000_80000000h) Reset 800h
15:4
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
7.4.21
PREFETCHABLE MEMORY LIMIT REGISTER OFFSET
19:16
Function
64-bit Addressing Support Prefetchable Memory Limit
Type
Description
0001: Indicates PI7C9X130 supports 64-bit addressing Reset 0001 Prefetchable Memory Limit (00000000_000FFFFFh) Reset 000h
31:20
7.4.22
PREFETCHABLE BASE UPPER 32-BIT REGISTER OFFSET
31:0
Function
Prefetchable Base Upper 32-bit
Type
Description
[63:32] prefetchable base Reset 00000000h
7.4.23
PREFETCHABLE LIMIT UPPER 32-BIT REGISTER OFFSET
31:0
Function
Prefetchable Limit Upper 32-bit
Type
Description
[63:32] prefetchable limit Reset 00000000h
7.4.24
BASE UPPER 16-BIT REGISTER OFFSET
15:0
Function
Base Upper 16bit
Type
Description
[31:16] Base Reset 0000h
7.4.25
BASE UPPER 16-BIT REGISTER OFFSET
31:16
Function
Limit Upper 16bit
Type
Description
[31:16] Limit Reset 0000h
7.4.26
CAPABILITY POINTER OFFSET
31:8
Function
Reserved Capability Pointer
Type
Description
Reset Capability pointer Reset
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
7.4.27
EXPANSION BASE ADDRESS REGISTER OFFSET
31:0
Function
Expansion Base Address
Type
Description
Expansion supported. Reset 00000000h
7.4.28
INTERRUPT LINE REGISTER OFFSET
Function
Interrupt Line
Type
Description
These bits apply reverse bridge only. initialization code program tell which input interrupt controller PI7C9X130's INTA_L connected Reset 00000000
7.4.29
INTERRUPT REGISTER OFFSET
15:8
Function
Interrupt
Type
Description
These bits apply reverse bridge only. Designates interrupt INTA_L, used Reset when forward mode when reverse mode.
7.4.30
BRIDGE CONTROL REGISTER OFFSET
Function
Parity Error Response Enable
Type
Description
Ignore parity errors secondary Enable parity error detection secondary FORWARD BRIDGE Controls response uncorrectable address attribute data errors secondary REVERSE BRIDGE Controls setting master data parity error response received poisoned from secondary (PCIe link) Reset Disable forwarding SERR_L ERR_FATAL ERR_NONFATAL Enable forwarding SERR_L ERR_FATAL ERR_NONFATAL Reset (FORWARD BRIDGE) REVERSE BRIDGE Forward downstream addresses address range defined Base Limit registers Forward upstream addresses address range defined Base Limit registers that first 64KB address space (top bytes each block) Reset
SERR_L Enable
Enable
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Function
Enable
Type
Description
forward compatible memory addresses from primary secondary, unless they enabled forwarding defined memory address ranges Forward compatible memory addresses from primary secondary enable memory enable bits set), independent enable Execute 10-bit address decodes accesses Execute 16-bit address decode accesses Reset report master aborts (return FFFFFFFFh reads discards data write) Report master abort signaling target abort possible assertion SERR_L enabled). Reset force assertion RESET_L secondary forward bridge, generate reset PCIe link reverse bridge Force assertion RESET_L secondary forward bridge, generate reset PCIe link reverse bridge Reset Fast back-to-back supported Reset Primary discard timer counts clock cycles Primary discard timer counts clock cycles FORWARD BRIDGE ignored PI7C9X130 Reset Secondary discard timer counts clock cycles Secondary discard timer counts clock cycles REVERSE BRIDGE ignored PI7C9X130 Reset when discard timer expires delayed completion discarded interface forward reverse bridge Reset enable generate ERR_NONFATAL ERR_FATAL forward bridge, assert P_SERR_L reverse bridge result expiration discard timer interface. Reset Reset 0000
16-bit Decode
Master Abort Mode
Secondary Interface Reset
Fast Back-to-Back Enable Primary Master Timeout
Secondary Master Timeout
Master Timeout Status
Discard Timer SERR_L Enable
31:28
Reserved
7.4.31
DATA BUFFERING CONTROL REGISTER OFFSET
Function
Secondary Internal Arbiter's PARK Function Memory Read Prefetching Dynamic Control Disable
Type
Description
Park last master Park PI7C9X130 secondary port Reset Enable memory read prefetching dynamic control PCIe read Disable memory read prefetching dynamic control PCIe read Reset
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Function
Completion Data Prediction Control
Type
Description
Enable completion data prediction PCIe read. Disable completion data prediction Reset Reset These bits ignored PCI-X mode. cache line prefetch memory read multiple address prefetchable range interface Full prefetch address prefetchable range interface, PI7C9X130 will keep remaining data after disconnects external master during burst read with read multiple command until discard timer expires Full prefetch address prefetchable range interface Full prefetch address prefetchable range interface PI7C9X130 will keep remaining data after read multiple terminated either external master PI7C9X130, until discard time expires Reset These bits ignored PCI-X mode. Once cache line prefetch memory read address prefetchable range interface Full prefetch address prefetchable range interface PI7C9X130 will keep remaining data after disconnected external master during burst read with read line command, until discard timer expires Full prefetch memory read line address prefetchable range interface Full prefetch address prefetchable range interface PI7C9X130 will keep remaining data after read line terminated either external master PI7C9X130, until discard timer expires Reset cache line prefetch memory read address prefetchable range interface Reserved Full prefetch memory read address prefetchable range interface Disconnect first DWORD Reset Retry master that repeats transaction with command code changes. Allows master change memory command code (MR, MRL, MRM) after received retry. PI7C9X130 will complete memory read transaction return data back master address byte enables same. Reset Reset Maximum byte count used PI7C9X130 when generating memory read requests PCIe link response memory read initiated [9:8], [7:6], [5:4] "full prefetch". 000: 001: 010: 011: 100: 101: 110: 111: bytes (default) bytes bytes bytes 1024 bytes 2048 bytes 4096 bytes bytes
Reserved Read Multiple Prefetch Mode
Read Line Prefetch Mode
Read Prefetch Mode
Special Delayed Read Mode Enable
14:12
Reserved Maximum Memory Read Byte Count
Reset
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
7.4.32
CHIP CONTROL REGISTER OFFSET
Function
Flow Control Update Control
Type
Description
Flow control updated every credits available Flow control updated every credit available Reset retry counter expired since last reset retry counter expired since last reset Reset expiration limit Allow retries before expiration Allow retries before expiration Allow retries before expiration Reset Enable discard timer conjunction with [27] offset (bridge control register) Disable discard timer conjunction with [27] offset (bridge control register) Reset [24] offset forward bridge [25] offset reverse bridge indicate many clocks should allowed before discard timer expires clocks allowed before discard timer expires Reset Timer expires 25us Timer expires 0.5ms Timer expires Timer expires 25ms Reset Enable out-of-order capability between delayed transactions Disable out-of-order capability between delayed transactions Reset Timer expires 50us Timer expires 10ms Timer expires 50ms Timer disabled Reset memory transactions from PCI-X PCIe will mapped memory transactions from PCI-X PCIe will mapped Traffic Class defined [29:27] offset 40h. Reset Reset
Retry Counter Status
18:17
Retry Counter Control
Discard Timer Disable
Discard Timer Short Duration
22:21
Configuration Request Retry Timer Counter Value Control
Delayed Transaction Order Control
25:24
Completion Timer Counter Value Control
Isochronous Traffic Support Enable
29:27
Traffic Class Used Isochronous Traffic Serial Link Interface Loopback Enable
Normal mode Enable serial link interface loopback mode TM0=LOW, TM1=HIGH, TM2=HIGH, MSK_IN=HIGH, REVRSB=HIGH. transaction from will loop back forward bridge Reset
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Function
Primary Configuration Access Lockout
Type
Description
PI7C9X130 configuration space accessed from both interfaces PI7C9X130 configuration space only accessed from secondary interface. Primary accessed receives completion with status forward bridge, target retry reverse bridge Reset
7.4.33
RESERVED REGISTER OFFSET
31:0
Function
Reserved
Type
Description
Reset 00000000h
7.4.34
ARBITER ENABLE REGISTER OFFSET
Function
Enable Arbiter
Type
Description
Disable arbitration internal PI7C9X130 request Enable arbitration internal PI7C9X130 request Reset Disable arbitration master Enable arbitration master Reset Disable arbitration master Enable arbitration master Reset Disable arbitration master Enable arbitration master Reset Disable arbitration master Enable arbitration master Reset Disable arbitration master Enable arbitration master Reset Disable arbitration master Enable arbitration master Reset Disable arbitration master Enable arbitration master Reset Disable arbitration master Enable arbitration master Reset
Enable Arbiter
Enable Arbiter
Enable Arbiter
Enable Arbiter
Enable Arbiter
Enable Arbiter
Enable Arbiter
Enable Arbiter
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
7.4.35
ARBITER MODE REGISTER OFFSET
Function
External Arbiter
Type
Description
Enable internal arbiter CFN_L tied LOW) external arbiter CFN_L tied HIGH) Reset according what CFN_L tied Broken master timeout disable This enables internal arbiter count cycles while waiting FRAME_L become active when device's active idle. broken master timeout expires, device de-asserted. Reset broken master will ignored forever after de-asserting REQ_L least clock Refresh broken master state after other masters have been served once Reset 08h: These bits initialization value counter used internal arbiter. controls number cycles that arbiter holds device's active after detecting REQ_L from another device. counter reloaded whenever asserted. every GNT, counter armed decrement when detects fall FRAME_L. arbiter fairness counter 00h, arbiter will remove device's until device de-asserted REQ. Reset GNT_L de-asserted after granted master assert FRAME_L GNT_L de-asserts clock after clocks granted master asserting FRAME_L Reset Reset
Broken Master Timeout Enable
Broken Master Refresh Enable
19:12
Arbiter Fairness Counter
GNT_L Output Toggling Enable
Reserved
7.4.36
ARBITER PRIORITY REGISTER OFFSET
Function
Arbiter Priority
Type
Description
priority request internal PI7C9X130 High priority request internal PI7C9X130 Reset priority request master High priority request master Reset priority request master High priority request master Reset priority request master High priority request master Reset priority request master High priority request master Reset
Arbiter Priority
Arbiter Priority
Arbiter Priority
Arbiter Priority
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Function
Arbiter Priority
Type
Description
priority request master High priority request master Reset priority request master High priority request master Reset priority request master High priority request master Reset priority request master High priority request master Reset Reset
Arbiter Priority
Arbiter Priority
Arbiter Priority
Reserved
7.4.37 7.4.38
RESERVED REGISTERS OFFSET EXPRESS TRANSMITTER/RECEIVER CONTROL REGISTER OFFSET
Function
Nominal Driver Current Control
Type
Description
20mA 10mA 28mA Reserved Reset 0000: 1.00 nominal driver current 0001: 1.05 nominal driver current 0010: 1.10 nominal driver current 0011: 1.15 nominal driver current 0100: 1.20 nominal driver current 0101: 1.25 nominal driver current 0110: 1.30 nominal driver current 0111: 1.35 nominal driver current 1000: 1.60 nominal driver current 1001: 1.65 nominal driver current 1010: 1.70 nominal driver current 1011: 1.75 nominal driver current 1100: 1.80 nominal driver current 1101: 1.85 nominal driver current 1110: 1.90 nominal driver current 1111: 1.95 nominal driver current Reset 0000
Driver Current Scale Multiple Control
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
11:8
Function
Driver De-emphasis Level Control
Type
Description
0000: 0.00 0001: -0.35 0010: -0.72 0011: -1.11 0100: -1.51 0101: -1.94 0110: -2.38 0111: -2.85 1000: -3.35 1001: -3.88 1010: -4.44 1011: -5.04 1100: -5.68 1101: -6.38 1110: -7.13 1111: -7.96 Reset 1000 ohms ohms ohms ohms Reset ohms ohms ohms ohms Reset Reset
13:12
Transmitter Termination Control
15:14
Receiver Termination Control
29:16
Reserved
7.4.39
UPSTREAM MEMORY WRITE FRAGMENT CONTROL REGISTER OFFSET
31:30
Function
Memory Write Fragment Control
Type
Description
Upstream Memory Write Fragment Control Fragment 32-byte boundary Fragment 64-byte boundary Fragement 128-byte boundary Reset
7.4.40 7.4.41
RESERVED REGISTER OFFSET EEPROM AUTOLOAD CONTROL/STATUS REGISTER OFFSET
Function
Initiate EEPROM Read Write Cycle
Type
Description
This will reset after EEPROM operation finished. EEPROM AUTOLOAD disabled Starts EEPROM Read Write cycle Reset
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Function
Control Command EEPROM
Type
Description
Read Write Reset EEPROM acknowledge always received during EEPROM cycle EEPROM acknowledge received during EEPROM cycle Reset EEPROM autoload successfully completed EEPROM autoload successfully completed Reset Where PCLK 125MHz PCLK 4096 PCLK 2048 PCLK 1024 PCLK Reset Enable EEPROM autoload Disable EEPROM autoload Reset Normal speed EEPROM autoload Increase EEPROM autoload Reset EEPROM autoload going EEPROM autoload going Reset EEPROM word address EEPROM cycle Reset 0000000 EEPROM data written into EEPROM Reset 0000h
EEPROM Error
EPROM Autoload Complete Status
EEPROM Clock Frequency Control
EEPROM Autoload Control
Fast EEPROM Autoload Control
EEPROM Autoload Status
15:9
EEPROM Word Address EEPROM Data
31:16
7.4.42
SWAP CONTROL STATUS REGISTER OFFSET
15:8
Function
Capability Swap Next Capability Pointer Device Hiding ENUM_L signal Mask Pending Insertion Extraction
Type
Description
Reset when Sawp enable (HS_EN=1) when Swap disabled (HS_EN=0) Reset inidicate capability chain Device Hiding Armed when this Reset ENUM_L signal masked when this Reset When this armed, either value logic When this armed both have value logic Reset When this When this Reset PI=01 supports PI=00 plus device hiding pending insertion extraction bits Reset
21:20
Programming Interface
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Function
Extraction
Type
Description
indicates ENUM_L status extraction. When ENUM_L asserted Reset indicates ENUM_L status insertion. When ENUM_L asserted Reset Reset
Insertion
31:24
Reserved
7.4.43
GPIO DATA CONTROL REGISTER OFFSET
11:0 15:12 19:16 23:20 27:24 31:28
Function
Reserved GPIO Output Write1-to-Clear GPIO Output Write1-to-Set GPIO Output Enable Write-1-to-Clear GPIO Output Enable Write-1-to-Set GPIO Input Data Register
Type
Description
Reset 000h Reset Reset Reset Reset Reset
7.4.44 7.4.45
RESERVED REGISTER OFFSET PCI-X CAPABILITY REGISTER OFFSET
Function
PCI-X Capability
Type
Description
PCI-X Capability Reset
7.4.46
NEXT CAPABILITY POINTER REGISTER OFFSET
15:8
Function
Next Capability Pointer
Type
Description
Point power management Reset
7.4.47
PCI-X SECONDARY STATUS REGISTER OFFSET
Function
64-bit Device Secondary Interface 133MHz Capable
Type
Description
64-bit supported when DEV64 high Reset forward bridge mode DEV64 high reset reverse bridge mode When this PI7C9X130 133MHz capable secondary interface
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Function
Split Completion Discarded
Type
Description
Reset forward bridge mode reverse bridge mode This read-only reverse bridge mode read-write forward bridge mode When this split completion been discarded PI7C9X130 secondary because requester accept split completion transaction Reset This forward bridge mode read-write reverse bridge mode When this unexpected split completion been received with requester equaled secondary number, device number, function number PI7X9X130 secondary interface Reset When this split completion been terminated PI7C9X130 with either retry disconnect next buffer full condition Reset When this split request delayed because PI7C9X130 able forward split request transaction secondary insufficient room within limit specified split transaction commitment limit field downstream split transaction control register Reset These bits only meaningful forward bridge mode. reverse bridge mode, three bits zero. 000: Conventional mode (minimum clock period applicable) 001: 66MHz (minimum clock period 15ns) 010: 133MHz (minimum clock period 7.5ns) 011: Reserved 1xx: Reserved Reset 0000000
Unexpected Split Completion
Split Completion Overrun
Split Request Delayed
24:22
Secondary Clock Frequency
31:25
Reserved
7.4.48
PCI-X BRIDGE STATUS REGISTER OFFSET
Function
Function Number
Type
Description
Function number [10:8] type configuration transaction) Reset Device number [15:11] type configuration transaction) assigned PI7C9X130 connection system hardware. Each time PI7C9X130 addressed configuration write transaction, bridge updates this register with contents [15:11] address phase configuration transaction, regardless which register PI7C9X130 addressed transaction. PI7C9X130 addressed configuration write transaction following true: transaction uses configuration write command IDSEL asserted during address phase [1:0] (type configuration transaction) [10:8] configuration address contain appropriate function number Reset 11111
Device Number
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
15:8
Function
Number
Type
Description
Additional address from which contents primary number register type configuration space header read. PI7C9X130 uses number, device number, function number fields create completer when responding with split completion read internal PI7C9X130 register. These fields also used cases when interface conventional mode other PCI-X mode. Reset 11111111 64-bit supported when DEV64 high Reset forward bridge mode reverse bridge mode with REQ64_L high de-assertion RESET_L reset reverse bridge mode with REQ64_L de-assertion RESET_L When this PI7C9X130 133MHz capable primary interface Reset forward bridge mode reverse bridge mode This read-only reverse bridge mode read-write forward bridge mode When this split completion been discarded PI7C9X130 primary because requester accept split completion transaction Reset This forward bridge mode read-write reverse bridge mode When this unexpected split completion been received with requester equaled primary number, device number, function number PI7X9X130 primary interface Reset When this split completion been terminated PI7C9X130 with either retry disconnect next buffer full condition Reset When this split request delayed because PI7C9X130 able forward split request transaction primary insufficient room within limit specified split transaction commitment limit field downstream split transaction control register Reset 0000000000
64-bit Device Primary Interface
133MHz Capable
Split Completion Discarded
Unexpected Split Completion
Split Completion Overrun
Split Request Delayed
31:22
Reserved
7.4.49
UPSTREAM SPLIT TRANSACTION REGISTER OFFSET
15:0
Function
Upstream Split Transaction Capability
Type
Description
Upstream Split Transaction Capability specifies size buffer unit ADQs) store split completions memory read. applies requesters secondary addressing completers primary bus. 0010h value shows that buffer ADQs bytes storage Reset 0010h Upstream Split Transaction Commitment Limit indicates cumulative sequence size commitment limit units ADQs. This field programmed value equal content split capability field. example, limit FFFFh, PI7C9X130 allowed forward split requests size regardless amount buffer space available. split transaction commitment limit 0010h that same value split transaction capability. Reset 0010h
31:16
Split Transaction Commitment Limit
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
7.4.50
DOWNSTREAM SPLIT TRANSACTION REGISTER OFFSET
15:0
Function
Downstream Split Transaction Capability
Type
Description
Downstream Split Transaction Capability specifies size buffer unit ADQs) store split completions memory read. applies requesters primary addressing completers secondary bus. 0010h value shows that buffer ADQs bytes storage Reset 0010h Downstream Split Transaction Commitment Limit indicates cumulative sequence size commitment limit units ADQs. This field programmed value equal content split capability field. example, limit FFFFh, PI7C9X130 allowed forward split requests size regardless amount buffer space available. split transaction commitment limit 0010h that same value split transaction capability. Reset 0010h
31:16
Downstream Split Transaction Commitment Limit
7.4.51
POWER MANAGEMENT REGISTER OFFSET
Function
Power Management
Type
Description
Power Management Register Reset
7.4.52
NEXT CAPABILITY POINTER REGISTER OFFSET
15:8
Function
Next Pointer
Type
Description
Next pointer (point Subsystem Subsystem Vendor Reset
7.4.53
POWER MANAGEMENT CAPABILITY REGISTER OFFSET
18:16
Function
Version Number
Type
Description
Version number that complies with revision Power Management Interface specification. Reset clock required PME_L generation Reset Reset special initialization this function beyond standard configuration header required following transition un-initialized state Reset
Clock
Reserved Device Specific Initialization (DSI)
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
24:22
Function
Current
Type
Description
000: 001: 55mA 010: 100mA 011: 160mA 100: 220mA 101: 270mA 110: 320mA 111: 375mA Reset power management supported Reset power management supported Reset PME_L supported cold, hot, states. Reset 11001
Power Management Power Management PME_L Support
31:27
7.4.54
POWER MANAGEMENT CONTROL STATUS REGISTER OFFSET
Function
Power State
Type
Description
Power State used determine current power state PI7C9X130. non-implemented state written this register, PI7C9X130 will ignore write data. When present state changing state programming this register, power state change causes device reset without activating RESET_L PCI/PCI-X interface state state implemented state implemented state Reset Reset 000000 PME_L assertion disabled PME_L assertion enabled Reset Data register implemented Reset 0000 Data register implemented Reset PME_L supported Reset
Reserved Enable
12:9
Data Select
14:13
Data Scale
Status
RWCS
7.4.55
PCI-TO-PCI BRIDGE SUPPORT EXTENSION REGISTER OFFSET
21:16
Function
Reserved B2/B3 Support
Type
Description
Reset 000000 support D3hot Reset
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Function
Power/Clock Control Enable Data Register
Type
Description
Power/Clock Disabled Reset Data register implemented Reset
31:24
7.4.56 7.4.57
RESERVED REGISTERS OFFSET CAPABILITY REGISTER OFFSET
Function
Capability
Type
Description
Capability Slot Identification. default turned through EEPROM interface Reset
7.4.58
NEXT POINTER REGISTER OFFSET
15:8
Function
Next Pointer
Type
Description
Next pointer points Express capabilities register Reset
7.4.59
SLOT NUMBER REGISTER OFFSET
20:16
Function
Expansion Slot Number First Chassis
Type
Description
Expansion slot number Reset 00000 First chassis Reset Reset
23:22
Reserved
7.4.60
CHASSIS NUMBER REGISTER OFFSET
31:24
Function
Chassis Number
Type
Description
Chassis number Reset
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
7.4.61
SECONDARY CLOCK CLKRUN CONTROL REGISTER OFFSET
Function
CLKOUT0 Enable
Type
Description
CLKOUT (Slot Enable forward bridge mode only enable CLKOUT0 enable CLKOUT0 enable CLKOUT0 disable CLKOUT0 driven Reset CLKOUT (Slot Enable forward bridge mode only enable CLKOUT1 enable CLKOUT1 enable CLKOUT1 disable CLKOUT1 driven Reset CLKOUT (Slot Enable forward bridge mode only enable CLKOUT2 enable CLKOUT2 enable CLKOUT2 disable CLKOUT2 driven Reset CLKOUT (Slot Enable forward bridge mode only enable CLKOUT3 enable CLKOUT3 enable CLKOUT3 disable CLKOUT3 driven Reset CLKOUT (Device Enable forward bridge mode only enable CLKOUT4 disable CLKOUT4 driven Reset CLKOUT (Device Enable forward bridge mode only enable CLKOUT5 disable CLKOUT5 driven Reset CLKOUT (the bridge) Enable forward bridge mode only enable CLKOUT6 disable CLKOUT6 driven Reset Reset Reset Secondary clock stop status secondary clock stopped secondary clock stopped Reset
CLKOUT1 Enable
CLKOUT2 Enable
CLKOUT3 Enable
CLKOUT4 Enable
CLKOUT5 Enable
CLKOUT6 Enable
Reserved Reserved Secondary Clock Stop Status
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Function
Secondary Clkrun Protocol Enable
Type
Description
disable protocol enable protocol Reset Stop secondary clock only when bridge D3hot state Stop secondary clock whenever secondary idle there requests from primary Reset Reset 0000h
Clkrun Mode
31:16
Reserved
7.4.62
CAPABILITY REGISTER OFFSET
Function
Capability
Type
Description
Capability subsystem subsystem vendor Reset
7.4.63
NEXT POINTER REGISTER OFFSET
15:8
Function
Next Item Pointer
Type
Description
Next item pointer (point Express Capability default programmed Slot Identification Capability enabled) Reset
7.4.64
RESERVED REGISTER OFFSET
31:16
Function
Reserved
Type
Description
Reset 0000h
7.4.65
SUBSYSTEM VENDOR REGISTER OFFSET
15:0
Function
Subsystem Vendor
Type
Description
Subsystem vendor identifies particular add-in card subsystem Reset
7.4.66
SUBSYSTEM REGISTER OFFSET
31:16
Function
Subsystem
Type
Description
Subsystem identifies particular add-in card subsystem Reset
7.4.67
EXPRESS CAPABILITY REGISTER OFFSET
Function Type Description
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Function
Express Capability
Type
Description
Express capability Reset
7.4.68
NEXT CAPABILITY POINTER REGISTER OFFSET
15:8
Function
Next Item Pointer
Type
Description
Next item pointer (points register) Reset
7.4.69
EXPRESS CAPABILITY REGISTER OFFSET
19:16 23:20
Function
Capability Version Device Port Type
Type
Description
Reset 0000: Express endpoint device 0001: Legacy Express endpoint device 0100: Root port Express root complex 0101: Upstream port Express switch 0110: Downstream port Express switch 0111: Express bridge 1000: Express bridge Others: Reserved Reset Forward Bridge Reverse Bridge Reset Forward Bridge Reverse Bridge Reset Reset
29:25 31:30
Slot Implemented Interrupt Message Number Reserved
7.4.70
DEVICE CAPABILITY REGISTER OFFSET
Function
Maximum Payload Size
Type
Description
000: bytes 001: bytes 010: bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset phantom functions supported Reset 8-bit field supported Reset
Phantom Functions
8-bit Field
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Function
Endpoint L0's Latency
Type
Description
Endpoint L0's acceptable latency 000: less than 001: 010: 011: 100: 101: 110: 111: more than Reset Endpoint L1's acceptable latency 000: less than 001: 010: 011: 100: 101: 110: 111: more than Reset Plug disabled Plug enabled Forward Bridge Reset when hot-plug disabled when hot-plug enabled through strapping. Plug disabled Plug enable Forward Bridge Reset when hot-plug disabled when hot-plug enabled through strapping. Plug disabled Plug enable Forward Bridge Reset when hot-plug disabled when hot-plug enabled through strapping. Reset These bits Set_Slot_Power_Limit message Reset This value Set_Slot_Power_Limit message Reset Reset
11:9
Endpoint L1's Latency
Attention Button Present
Attention Indicator Present
Power Indicator Present
17:15 25:18
Reserved Captured Slot Power Limit Value Captured Slot Power Limit Scale Reserved
27:26
31:28
7.4.71
DEVICE CONTROL REGISTER OFFSET
Function
Correctable Error Reporting Enable Non-Fatal Error Reporting Enable Fatal Error Reporting Enable Unsupported Request Reporting Enable Relaxed Ordering Enable
Type
Description
Reset Reset Reset Reset
Relaxed Ordering disabled Reset
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
Function
Payload Size
Type
Description
This field sets maximum payload size PI7C9X130 000: bytes 001: bytes 010: bytes 011:1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset Reset Phantom functions supported Reset Auxiliary power supported Reset Bridge never sets Snoop attribute transaction initiates Reset This field sets maximum Read Request Size device requester 000: bytes 001: bytes 010: bytes 011: 1024 bytes 100: 2048 bytes 101: 4096 bytes 110: reserved 111: reserved Reset Reset
Extended Field Enable Phantom Functions Enable Auxiliary Power Enable Snoop Enable
14:12
Maximum Read Request Size
Configuration Retry Enable
7.4.72
DEVICE STATUS REGISTER OFFSET
Function
Correctable Error Detected Non-Fatal Error Detected Fatal Error Detected Unsupported Request Detected Power Detected Transaction Pending
Type
Description
Reset Reset Reset Reset Reset transaction pending transaction layer interface Transaction pending transaction layer interface Reset Reset 0000000000
31:22
Reserved
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
7.4.73
LINK CAPABILITY REGISTER OFFSET
Function
Maximum Link Speed
Type
Description
Indicates maximum speed Express link 0001: 2.5Gb/s link Reset Indicates maximum width Express link reset) 000000: reserved 000001: 000010: 000100: 001000: 001100: 010000: 100000: Reset 000100 This field indicates level Active State Power Management Support reserved L0's entry supported reserved L0's L1's supported Reset Reset Reset Reset Reset
Maximum Link Width
11:10
ASPM Support
14:12 17:15 23:18 31:24
L0's Exit Latency L1's Exit Latency Reserved Port Number
7.4.74
LINK CONTROL REGISTER OFFSET
Function
ASPM Control
Type
Description
This field controls level ASPM supported Express link disabled L0's entry enabled L1's entry enabled L0's L1's entry enabled Reset Reset Read completion boundary supported Reset Forward Bridge Reset Forward Bridge Reset Reset Reset Reset
Reserved Read Completion Boundary (RCB) Link Disable
Retrain Link
15:8
Common Clock Configuration Extended Sync Reserved
Page PERICOM SEMICONDUCTOR September 2007
PI7C9X130 EXPRESS PCI-X BRIDGE
7.4.75
LINK STATUS REGISTER OFFSET
19:16
Function
Link Speed
Type
Description
This field indicates negotiated speed Express link 001: 2.5Gb/s link Reset 000000: reserved 000001: 000010: 000100: 001000: 001100: 010000: 100000: Reset 000100 Reset Reset Reset Reset
25:20
Negotiated Link Width
31:29
Link Train Error Link Training Slot Clock Configuration Reserved
7.4.76
SLOT CAPABILITY REGISTER OFFSET
Function
Attention Button Present
Type
Description
Plug disabled Plug enabled reverse bridge Reset when hot-plug disabled when hot-plug enabled through strapping. Reset Plug disabled Plug enabled reverse bridge Reset when hot-plug disabled when hot-plug enabled through strapping. Plug disabled Plug enabled reverse bridge Reset when hot-plug disabled when hot-plug enabled through strapping. Plug disabled Plug enabled reverse bridge Reset when hot-plug disabled when hot-plug enabled through strapping. Reset Plug disabled Plug enabled reverse bridge Reset when hot-plug disabled when hot-plug enabled through strapping. Reset Reset Reset Reset
Power Controller Present Sensor Present
Attention Indicator Present
Power Indicator Present
Plug Surprise Plug Capable
14:7 16:15 18:17 31:19
Slot Power Limit Value
Other recent searches
UM10206 - UM10206 UM10206 Datasheet
SI-3018LSA - SI-3018LSA SI-3018LSA Datasheet
PS7141CL-2A - PS7141CL-2A PS7141CL-2A Datasheet
PS7141C-2A - PS7141C-2A PS7141C-2A Datasheet
PD60176-C - PD60176-C PD60176-C Datasheet
IR2172 - IR2172 IR2172 Datasheet
KK74HCT126A - KK74HCT126A KK74HCT126A Datasheet
FP5501 - FP5501 FP5501 Datasheet
FA3675F - FA3675F FA3675F Datasheet
DRV591 - DRV591 DRV591 Datasheet
2SA778 - 2SA778 2SA778 Datasheet
2SA778A - 2SA778A 2SA778A Datasheet
Privacy Policy | Disclaimer
© 2012 Datasheet Archive
