LC723661, LC723662, LC723663 Electronic tuning radio audio C
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Ordering number ENA0460A
LC723661, LC723662, LC723663
Electronic tuning radio audio
Controllers
LC723661, 723662 723663 controllers that support 64KB RAM. These 80-pin version 100-pin LC723780 series. They have built-in serial port 6-input 8-bit converter enhance communication with internal external devices.
Functions
steps subroutine area holds steps banks through LC723661-ROM 32KB, LC723662-ROM 48KB, LC723663-ROM 64KB, levels channels. These circuits support both 2-wire 3-wire 8-bit communication techniques, switched between first first operation. internally generated serial transfer clock rates selected: 12.5kHz, 37.5kHz, 187.5kHz, 281.25kHz, 375kHz, 450kHz Five interrupt inputs (pins INT0, HOLD pin) These interrupts switch between rising falling edges, although HOLD only supports falling edge detection. interrupts four internal timer interrupts, serial interrupts.
Stack Serial
External interrupts Internal interrupts
This production produced sold SANYO under license Silicon Storage Technology Inc. Specifications information herein subject change without notice.
SANYO Semiconductor products described contained herein have specifications that handle applications that require extremely high levels reliability, such life-support systems, aircraft's control systems, other applications whose failure reasonably expected result serious physical and/or material damage. Consult with your SANYO Semiconductor representative nearest before usingany SANYO Semiconductor products described contained herein such applications. SANYO Semiconductor assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO Semiconductor products described contained herein.
92006HKIM B8-9066,9070,9071 No.0460-1/12
LC723661, 723662, 723663
levels Interrupts prioritized hardware follows HOLD pin>INT0 pin>INT1 pin> INT4 pin>INT5 pin> S-I/O0>S-I/O1>Internal TMR0>Internal TMR1>Internal TMR2> Internal TMR3 Converter 8-bit resolution inputs General-purpose ports Input ports Output ports ports (These pins switched between input output 1-bit units.) block Includes sub-charge pump high-speed locking. Supports dead zone control. Built-in unlock detection circuit Twelve reference frequencies 1kHz, 3kHz, 3.125kHz, 5kHz, 6.25kHz, 9kHz, 10kHz, 12.5kHz, 25kHz, 30kHz, 50kHz, 100kHz Universal counter This 20-bit counter used either frequency period measurement supports four measurement (calculation) periods 1ms, 4ms, 8ms, 32ms Timers fixed timers programmable timers (8-bit counters) TMR0 Supports four periods 10µs, 100µs, 1ms, TMR1 Supports four periods 10µs, 100µs, 1ms, 10ms TMR2 TMR3 Programmable 8-bit counters. Input clocks with 10µs, 100µs, 125-ms timer flip-flop provided Beep circuit Provides fixed beep tones 500Hz, 1kHz, 2kHz, 2.08kHz, 2.2kHz, 2.5kHz, 3.33kHz, 3.75kHz, 4.17kHz, 7.03kHz Programmable 8-bit beep tone generator. Reference clocks with frequencies 50kHz, 15kHz, 5kHz. Reset Built-in voltage detection reset circuit External reset Cycle time 1.33µs/833ns (All instructions word), X'tal 4.5MHz/7.2MHz (4.5MHz when initialization performed. When 7.2MHz used, select 4.5MHz software.) Halt mode Stops operation clock controller. There four conditions that clear Halt mode Interrupt requests, timer flip-flop overflows, port inputs, HOLD inputs. Operating supply voltage 5.5V (Microcontroller block only 5.5V) Package QIP80E version LC72F3661 Development tools Emulator RE128V Evaluation chip LC72EV3780 Evaluation board EB-72EV3780 Interrupt nesting levels
No.0460-2/12
LC723661, 723662, 723663
Specifications
Absolute Maximum Ratings 25°C
Parameter Maximum supply voltage Input voltage Output voltage Symbol VIN1 VOUT1 VOUT2 Output current IOUT1 IOUT2 Allowable power dissipation Operating temperature Storage temperature Topr Tstg input pins PJ-PORT input pins other than VOUT1 PJ-PORT PS-PORT, EO1, Conditions Ratings -0.3 +6.5 -0.3 VDD+0.3 -0.3 -0.3 VDD+0.3 +125 Unit
Allowable Operating Range +85°C, 5.5V
Parameter Supply voltage Symbol VDD1 VDD2 VDD3 Input high-level voltage VIH2 VIH3 VIH4 Input low-level voltage VIL1 VIL2 VIL3 VIL4 Input amplitude VIN1 VIN2 VIN3 Input voltage range Input frequency VIN6 FIN1 FIN2 FIN3 FIN4 FIN5 FIN6 FIN7 FIN8 VIH1 operation Memory retention operation PS-PORT, HCTR, LCTR PK-PORT, LCTR period measurement mode), HOLD, RESET PA-PORT PS-PORT, HCTR, LCTR PK-PORT, LCTR period measurement mode), RESET HOLD FMIN FMIN, AMIN, HCTR, LCTR ADI0 ADI7 FMIN: VIN2, VDD1 FMIN: VIN3, VDD1 AMIN(H) VIN3, VDD1 AMIN(L) VIN3, VDD1 HCTR: VIN3, VDD1 LCTR: VIN3, VDD1 LCTR period measurement) VIH2, VIL2, VDD1 Pins Ratings 0.7VDD 0.8VDD 0.6VDD 0.07 0.04 0.3VDD 0.2VDD 0.4VDD Vrms Vrms Vrms
No.0460-3/12
LC723661, 723662, 723663
Electrical Characteristics allowable operating ranges
Parameter Input high-level current Symbol IIH1 IIH2 IIH3 5.0V FMIN, AMIN, HCTR, LCTR: 5.0V PS-PORT, SNS, HOLD, RESET, HCTR, LCTR: 5.0V (with ports PS-PORT input mode) Input low-level current IIL1 IIL2 IIL3 FMIN, AMIN, HCTR, LCTR: PS-PORT, SNS, HOLD, RESET, HCTR, LCTR: (with ports PS-PORT input mode) Hysteresis Output high-level voltage VOH1 VOH2 VOH3 Output low-level voltage VOL1 VOL2 VOL3 VOL4 Output leakage current IOFF2 IOFF3 conversion error Rejected pulse width Power down detection voltage Power supply current IDD1 IDD2 IDD3 IDD4 IDD5 IDD6 VDD1 FIN2 130MHz 25°C VDD1 FIN2 130MHz 25°C VDD2 Halt mode 25°C, X'tal VDD2 Halt mode 25°C, X'tal 7.2MHz Backup mode (OSC stopped) 5.5V, 25°C Backup mode (OSC stopped) 2.5V, 25°C (Fig. (Fig. (Fig. PREJ1 VDET IOFF1 PK-PORT, RESET, LCTR period measurement) PS-PORT: -1mA EO1, EO2: -500µA XOUT: -200µA PS-PORT: -1mA EO1, EO2: -500µA XOUT -200µA PJ-PORT -5mA PS-PORT EO1, PJ-PORT ADI0 ADI7 0.45 0.55 -100 -1.5 0.1VDD VDD-1.0 VDD-1.0 VDD-1.0 +100 +1.5 0.2VDD Pins Ratings unit
Twenty instruction steps executed every millisecond. PLL, universal counter, other functions stopped.
No.0460-4/12
LC723661, 723662, 723663
Test Circuits
20pF
4.5MHz
20pF
XOUT LCTR FMIN AMIN HCTR TEST
HOLD
Ports through through left open. However, ports through through left open output mode.
ILC05608
Figure HALT current test condition
20pF
20pF
4.5MHz
XOUT LCTR FMIN AMIN HCTR TEST
HOLD
Ports through left open.
ILC05609
Figure BACK current test condition
Package Dimensions
unit:mm (typ) 3174A
23.2 20.0
(0.8)
3.0max
0.35 0.15
(2.7)
SANYO QIP80E(14X20)
14.0
17.2
No.0460-5/12
LC723661, 723662, 723663
Assignment
PH0/ADI0 PH1/ADI1 VSSADC VDDPLL VSSPLL
RESET
TEST1
XOUT
HOLD
HCTR
LCTR
AMIN
FMIN
TEST2 VREG VSSCPU SI0/PG3 SO0/PG2 SCK0/PG1 SI1/PF3 SO1/PF2 SCK1/PF1 PD1/INT5 PD0/INT4
PI0/ADI4 PI1/ADI5 PI2/ADI6 PI3/ADI7 PK0/INT0 PK1/INT1 PN0/BEEP
view No.0460-6/12
VDDPORT
VSSPORT
LC723661, 723662, 723663
Block Diagram
XOUT FMIN DIVIDER SYSTEM CLOCK GENERATOR PROGRAMMBLE DIVIDER REFERENCE DIVIDER SELECTOR PHASE DETECTOR UNLOCK
AMIN HCTR LCTR UNIVERSAL COUNTER (20bits) V-DET TIMER DATA LATCH DRIVE. RESET HOLD TEST1 TEST2 ADDRESS DECODER BANK DATA LATCH DRIVE. DATA LATCH DRIVE. CONTROL INSTRUCTION DECODER ADDRESS DECODER DATA LATCH DRIVE. SKIP DATA LATCH DRIVE. STACK (PC, BANK, BEEP SNSF DATA LATCH
DRIVE. DATA LATCH DRIVE.
INT4 INT5
DATA LATCH DRIVE. INTERRUPT DATA LATCH DRIVE. PROGRAM COUNTER
SCK1
DATA LATCH DRIVE.
BEEP (PRG FIX)
LATCH LATCH
JUDGE
DATA LATCH DRIVE. DATA LATCH
INT1 INT0
SCK0 ADI0 ADI1
DATA LATCH DRIVE. DRIVE.
STATUS READ REGISTER
DRIVE. DATA LATCH DRIVE.
MPX(8ch) ADI4 ADI5 ADI6 ADI7 DRIVE.
(8bits)
INTERRUPT CONTROL
STATUS WRITE REGISTER
INTERRUPT DATA LATCH
ILC05610
No.0460-7/12
LC723661, 723662, 723663
Description
name Dedicated input ports. These ports designed with threshold voltage. Input disabled Backup mode. explanation Equivalent circuit
BACK
ILC05529
General-purpose ports. mode (input output) using IOS2 instruction. Input disabled pins high-impedance state Backup mode. These ports general-purpose input ports after power reset.
BACK
ILC05530
PD0/INT4 PD1/INT5
General-purpose external interrupt shared function ports. input formats Schmitt inputs. external interrupt function enabled when external interrupt enable flag set. When used general-purpose ports mode (input output) 1-bit units using IOS2 instruction. When used external interrupt pins external interrupt functions enabled setting corresponding external interrupt enable flag (INT4EN INT5EN). this case, pins must input mode advance. Input disabled pins high-impedance state Backup mode. These ports general-purpose input ports after power reset.
General-purpose ports input formats Schmitt inputs. mode (input output) 1-bit units using IOS1 instruction Input disabled pins high-impedance state Backup mode. These ports general-purpose input ports after power reset.
ILC05532
BACK
PF1/SCK1 PF2/SO1 PF3/SI1 PG1/SCK0 PG2/SO0 PG3/SI0
General-purpose ports with shared functions serial ports. input formats Schmitt inputs. IOS1 instruction used switch between general-purpose port serial port functions. When used general-purpose ports pins general-purpose port function using IOS1 instruction. mode (input output) 1-bit units using IOS1 instruction When used serial ports pins serial port function using IOS1 instruction. [Pin states when serial port function] PF0, General-purpose PF1, input output PF2, output PF3, input Input disabled pins high-impedance state Backup mode. These ports general-purpose input ports after power reset.
Continued next page.
No.0460-8/12
LC723661, 723662, 723663
Continued from preceding page.
name XOUT
XOUT
ILC05534
explanation Connections 4.5MHz/7.2MHz crystal oscillator element
Equivalent circuit
Main charge pump outputs. These pins output high level when frequency local oscillator divided higher than that reference frequency, they output level when that frequency lower. They high-impedance state when frequencies match. These pins high-impedance state Backup mode, after power reset, stopped state.
ILC05535
VDDPORT VDDPLL
power supply (These pins must connected VDD.) VDDPORT mainly supply power peripheral blocks. VDDPLL mainly circuits regulator.
VSSCPU VSSPORT VSSADC VSSPLL
Power supply ground (These pins must connected ground.) VSSPORT mainly supply power peripheral blocks. VSSPLL mainly circuits regulator. VSSCPU mainly used block. VSSADC mainly used block.
VREG FMIN
Internal voltage output. Connect bypass capacitor this pin. (local oscillator) input. This selected with instruction. signal input this must capacitor coupled. Input disabled Backup mode, after power reset, stopped state.
AMIN
(local oscillator) input. This selected band with (b1, instruction. Band 40MHz (SW, upconversion) 10MHz (MW,
signal input this must capacitor coupled. Input disabled Backup mode, after power reset, stopped state. HCTR Universal counter general-purpose input shared function input port. IOS1 instruction used switching between universal counter general-purpose input functions. When used frequency measurement universal counter function with IOS1 instruction. counter controlled using instructions. Since this functions amplifier this mode, input signal must input with capacitor coupling. When used general-purpose input general-purpose input function with IOS1 instruction. Data read from port using (b0) instruction. Input disabled Backup mode. (The input will pulled down.) universal counter function selected after power reset.
ILC05536
Stop instruction
Continued next page.
No.0460-9/12
LC723661, 723662, 723663
Continued from preceding page.
name LCTR explanation Universal counter (frequency period measurement) generalpurpose input shared function input port. IOS1 instruction used switching between universal counter general-purpose input functions. When used frequency measurement universal counter function with IOS1 instruction. LCTR frequency measurement mode with instruction, control operation with instruction. Since this functions amplifier this mode, input signal must input with capacitor coupling. When used period measurement universal counter function with IOS1 instruction. LCTR frequency measurement mode with instruction, control operation with instruction. Since bias feedback resistor disconnected this mode, input signal must input with coupling. When used general-purpose input general-purpose input port function with IOS1 instruction. Data read from port using (b1) instruction. Input disabled Backup mode. (The input will pulled down.) universal counter function (HCTR frequency measurement mode) selected after power reset. Voltage sense general-purpose input shared function port. This input circuit designed with input threshold voltage. When used voltage sense input used test power failures return from Backup mode. Application test this condition using internal flip-flop. flip-flop tested with instruction. (This usage requires external components, capacitors resistors. sample application circuit, user's manual.) When used general-purpose input port When used general-purpose input port state tested with instruction. Unlike other input ports, input this disabled Backup mode after power reset. result, through currents must taken into account when designing applications that this general-purpose input. HOLD Power supply monitor (with interrupt function) This designed with high input threshold voltage. This normally connected line used power detection. When power state detected, HOLDON flag hold interrupt request flag will set. enter Backup mode, execute CKSTP instruction when HOLD low. this high clear Backup mode. RESET System reset pin. When operating Halt mode, system reset when this held least machine cycle. Execution starts with pointing location this time flip-flop set. level must applied least 50ms when power first applied.
ILC05540
ILC05539
Equivalent circuit
Stop instruction
ILC05536
ILC05539
Continued next page.
No.0460-10/12
LC723661, 723662, 723663
Continued from preceding page.
name PH0/ADI0 PH1/ADI1 PI0/ADI4 PI1/ADI5 PI2/ADI6 PI3/ADI7 explanation General-purpose input converter input shared function ports. IOS1 instruction used switch between general-purpose input converter input functions. When used general-purpose input ports general-purpose input port function with IOS1 instruction. units) When used converter input pins converter input port function with IOS1 instruction. units) whose voltage converted specified with IOS1 instruction, conversion started with instruction. Note Since input disabled ports specified function, executing input instruction such port will always return level. Input disabled Backup mode. These ports general-purpose input ports after power reset. General-purpose output ports (high-voltage output) Since these open-drain output circuits, external pull-up resistors required. internal transistors turned (resulting high-level output) Backup mode after power reset. PK0/INT0 PK1/INT1 General-purpose external interrupt shared function ports. input formats Schmitt inputs. external interrupt function enabled when external interrupt enable flag set. When used general-purpose ports mode (input output) 1-bit units using IOS1 instruction. When used external interrupt pins external interrupt functions enabled setting corresponding external interrupt enable flag (INT0EN through INT3EN). Here, pins must input mode advance. Input disabled pins high-impedance state Backup mode. These ports general-purpose input ports after power reset. General-purpose ports mode switched between input output with instruction. Input disabled pins high-impedance state Backup mode. These ports general-purpose input ports after power reset. PN0/BEEP General-purpose port beep tone output shared function ports. IOS2 instruction used switch between general-purpose port beep tone output functions. When used general-purpose ports: general-purpose port function with IOS2 instruction. (Pins through dedicated general-purpose output pins.) When used beep tone output pin: beep tone output function with IOS2 instruction. frequency with BEEP instruction. When this used beep tone output pin, executing output instruction this only sets internal latch influence output. Input disabled pins high-impedance state Backup mode. These ports general-purpose input ports after power reset.
ILC05544
Equivalent circuit
BACK
converter input
ILC05541
BACK
ILC05542
BACK
ILC05543
BACK
Continued next page.
No.0460-11/12
LC723661, 723662, 723663
Continued from preceding page.
name General-purpose ports mode switched between input output with instruction. Input disabled pins high-impedance state Backup mode. These ports general-purpose input ports after power reset. General-purpose ports. mode switched between input output with instruction, data input with instruction output with OUTR instruction. SPB, RPB, TPT, instruction cannot used with these ports. Input disabled pins high-impedance state Backup mode. These ports general-purpose input ports after power reset. TEST1 TEST2 test pins. These pins must connected GND.
ILC05544
explanation
Equivalent circuit
BACK
Specifications SANYO Semiconductor products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer's products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer's products equipment. SANYO Semiconductor Co., Ltd. strives supply high-quality high-reliability products. However, semiconductor products fail with some probability. possible that these probabilistic failures could give rise accidents events that could endanger human lives, that could give rise smoke fire, that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO Semiconductor products (including technical data,services) described contained herein controlled under applicable local export control laws regulations, such products must exported without obtaining export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written permission SANYO Semiconductor Co., Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO Semiconductor product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. SANYO Semiconductor believes information herein accurate reliable, guarantees made implied regarding infringements intellectual property rights other rights third parties.
This catalog provides information September, 2006. Specifications information herein subject change without notice.
No.0460-12/12
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