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LC87F1964A CMOS FROM byte, byte on-chip 8-bit 1-chip Microco


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Ordering number ENA0496
LC87F1964A
CMOS FROM byte, byte on-chip
8-bit 1-chip Microcontroller With USB-host Controller
SANYO LC87F1964A 8-bit microcomputer that, centered around running minimum cycle time 83.3ns, integrates single chip number hardware features such 64K-byte flash (onboard programmable), 5120-byte RAM, on-chip debugger, sophisticated 16-bit timers/counters (may divided into 8-bit timers), 16-bit timers/counter (may divided into 8-bit timers/counters 8-bit PWMs), 8-bit timers with prescaler, base timer serving time-of-day clock, three synchronous interface (with automatic block transmit/ receive function), asynchronous/synchronous interface, UART interface (full duplex), Full-Speed interface (host controller), 8-bit 12-channel converter, 12-bit channels, system clock frequency divider, 32-source 10-vector address interrupt feature.
Features
Flash Capable on-board-programming with wide range, 5.5V, voltage source. Block-erasable 128-byte units Writable 2-byte units 65536 bits 5120 bits Minimum Cycle 83.3ns (CF=12MHz) Note: cycle time here refers read speed. Minimum Instruction Cycle Time 250ns (CF=12MHz)
This product licensed from Silicon Storage Technology, Inc. (USA), manufactured sold SANYO Semiconductor Co., Ltd.
SANYO Semiconductor Co.,Ltd. products described contained herein are, with regard "standard application", intended general electronics equipment (home appliances, equipment, communication device, office equipment, industrial equipment etc.). products mentioned herein shall intended "special application" (medical equipment whose purpose sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level reliability directly threaten human lives case failure malfunction product cause harm human bodies, shall they grant guarantee thereof. should intend products applications outside standard applications customer considering such and/or outside scope intended standard applications, please consult with prior intended use. there consultation inquiry before intended use, customer shall solely responsible use. Specifications SANYO Semiconductor Co.,Ltd. products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer' products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer' products equipment.
Ver.1.02
N0106HKIM 20060713-S00003 No.A0496-1/28
LC87F1964A
Ports ports Ports whose direction designated units (P10 P17, P27, P34, P73, PWM0, PWM1, XT2) Ports whose direction designated units (P00 P07) ports (UHD+, UHD-) Dedicated oscillator ports (CF1, CF2) Input-only port (also used oscillation) (XT1) Reset pins (RES) Power pins (VSS1 VDD1 Timers Timer 16-bit timer/counter with capture register. Mode 8-bit timer with 8-bit programmable prescaler (with 8-bit capture register) channels Mode 8-bit timer with 8-bit programmable prescaler (with 8-bit capture register) 8-bit counter (with 8-bit capture register) Mode 16-bit timer with 8-bit programmable prescaler (with 16-bit capture register) Mode 16-bit counter (with 16-bit capture register) Timer 16-bit timer/counter that supports PWM/toggle outputs Mode 8-bit timer with 8-bit prescaler (with toggle outputs) 8-bit timer/counter with 8-bit prescaler (with toggle outputs) Mode 8-bit with an-8bit prescaler channels Mode 16-bit timer/counter with 8-bit prescaler (with toggle outputs) (toggle outputs also possible from lower-order bits) Mode 16-bit timer with 8-bit prescaler (with toggle outputs) (The lower-order bits used PWM.) Timer 8-bit timer with 6-bit prescaler (with toggle output) Timer 8-bit timer with 6-bit prescaler (with toggle output) Base timer clock selectable from subclock (32.768kHz crystal oscillation), system clock, timer prescaler output. Interrupts programmable different time schemes SIO0: Synchronous serial interface first/MSB first mode selectable Transfer clock cycle: 512/3 tCYC Automatic continuous data transmission bits, specifiable 1-bit units, suspension resumption data transmission possible 1-byte units) SIO1: 8-bit asynchronous/synchronous serial interface Mode Synchronous 8-bit serial 3-wire configuration, tCYC transfer clocks) Mode Asynchronous serial (half-duplex, 8-data bits, stop bit, 2048 tCYC baudrates) Mode mode (start bit, 8-data bits, tCYC transfer clocks) Mode mode (start detect, 8-data bits, stop detect) SIO4: Synchronous serial interface first/MSB first mode selectable Transfer clock cycle: 1020/3 tCYC Automatic continuous data transmission 4096 bytes, specifiable 1-byte units, suspension resumption data transmission possible 1-byte 2-bytes units) Auto-start-on-falling-edge function Clock polarity selectable CRC16 calculator circuit built
Continued next page.
No.A0496-2/28
LC87F1964A
Continued from preceding page.
SIO9: Synchronous serial interface first/MSB first mode selectable Transfer clock cycle: 1020/3 tCYC Automatic continuous data transmission 4096 bytes, specifiable 1-byte units, suspension resumption data transmission possible 1-byte 2-bytes units) Auto-start-on-falling-edge function Clock polarity selectable CRC16 calculator circuit built Full duplex UART UART1 Data length: 7/8/9 bits selectable Stop bits: bits continuous transmission mode) Baud rate: 16/3 8192/3 tCYC Converter bits channels PWM: Multifrequency 12-bit channels interface (host controller) Full-Speed supported Transfer type: Control, Bulk, Interrupt, Isochronous transfer possible Watchdog Timer External watchdog timer Interrupt reset signals selectable Clock Output Function Able output selected oscillation clock 1/1, 1/2, 1/4, 1/8, 1/16, 1/32, 1/64 system clock. Able output oscillation clock clock. Interrupts sources, vector addresses Provides three levels (low (L), high (H), highest (X)) multiplex interrupt control. interrupt requests level equal lower than current interrupt accepted. When interrupt requests more vector addresses occur same time, interrupt highest level takes precedence over other interrupts. interrupts same level, interrupt into smallest vector address takes precedence.
Vector Address 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Level INT0 INT1 INT2/T0L/INT4/UHC active INT3/INT5/base timer T0H/UHC device attach/UHC device detach/UHC resume T1L/T1H/SIO9 SIO0/UART1 receive SIO1/SIO4/UART1 transmit ADC/T6/T7/UHC-ACK/UHC-NAK/UHC error/UHC STALL Port 0/PWM0/PWM1/UHC-SOF Interrupt Source
Priority levels interrupts same level, with smallest vector address takes precedence.
No.A0496-3/28
LC87F1964A
Subroutine Stack Levels 2560 levels (the stack allocated RAM) High-speed Multiplication/Division Instructions bits bits tCYC execution time) bits bits tCYC execution time) bits bits tCYC execution time) bits bits tCYC execution time) Oscillation Circuits oscillation circuit (internal): oscillation circuit: Crystal oscillation circuit: circuit (internal):
system clock system clock, interface system clock, time-of-day clock interface (see Fig.5)
Standby Function HALT mode: Halts instruction execution while allowing peripheral circuits continue operation. Oscillation halted automatically. Canceled system reset occurrence interrupt. HOLD mode: Suspends instruction execution operation peripheral circuits. base clock generator, crystal oscillators automatically stop operation. There four ways resetting HOLD mode. Setting reset lower level. Setting least INT0, INT1, INT2, INT4, INT5 pins specified level Having interrupt source established port Having active interrupt source established host controller circuit X'tal HOLD mode: Suspends instruction execution operation peripheral circuits except base timer. base clock generator, oscillator automatically stop operation. state crystal oscillation established when X'tal HOLD mode entered retained. There five ways resetting X'tal HOLD mode. Setting reset level Setting least INT0, INT1, INT2, INT4, INT5 pins specified level Having interrupt source established port Having interrupt source established base timer circuit Having active interrupt source established host controller circuit Package Form
Lead-free type Lead-free type
Development Tools On-chip debugger: TCB87 type-B LC87F1964A Flash programming boards
Package Programming boards W87F55256Q W87F55256SQ
Recommended EPROM programmer
Maker Flash Support Group, Inc. (Single) SANYO Model AF9708/AF9709/AF9709B (including product Ando Electric Co.,Ltd) (SANYO FWS) Supported version After Rev02.65 Application Version: After 1.03 Chip Data Version: After 2.01 Device LC87F1964A LC87F1964
No.A0496-4/28
LC87F1964A
Package Dimensions
unit (typ) 3163B
(0.75) 0.18
0.15
1.7max
(1.5)
SANYO SQFP48(7X7)
Package Dimensions
unit (typ) 3156A
17.2 14.0 (1.5) (2.7) 0.35 0.15 17.2 14.0
3.0max
SANYO QIP48E(14X14)
No.A0496-5/28
LC87F1964A
Assignments
P27/INT5/SCK9 P26/INT5/SI9/WR9 P25/INT5/SO9/RD9 P24/INT5/SCK4 P23/INT4/SI4/WR P22/INT4/SO4/RD P21/INT4 P20/INT4 P07/AN7/T7O P06/AN6/T6O P05/AN5/CKO P04/AN4/DBGP2 UHDUHD+ VDD3 VSS3 P34/UFILT P31/URX1 P30/UTX1 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN
LC87F1964A
P03/AN3/DBGP1 P02/AN2/DBGP0 P01/AN1 P00/AN0 VSS2 VDD2 PWM0 PWM1 P17/T1PWMH/BUZ P16/T1PWML P15/SCK1 P14/SI1/SB1
P73/INT3/T0IN XT1/AN10 XT2/AN11 VSS1 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1
view
SANYO: SANYO:
"Lead-free Type" "Lead-free Type"
No.A0496-6/28
LC87F1964A
SQFP48/QIP48 NAME P73/INT3/T0IN XT1/AN10 XT2/AN11 VSS1 VDD1 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ PWM1 PWM0 VDD2 VSS2 P00/AN0 P01/AN1 P02/AN2/DBGP0 P03/AN3/DBGP1 SQFP48/QIP48 NAME P04/AN4/DBGP2 P05/AN5/CKO P06/AN6/T6O P07/AN7/T7O P20/INT4 P21/INT4 P22/INT4/SO4/RD P23/INT4/SI4/WR P24/INT5/SCK4 P25/INT5/SO9/RD9 P26/INT5/SI9/WR9 P27/INT5/SCK9 UHDUHD+ VDD3 VSS3 P34/UFILT P31/URX1 P30/UTX1 P70/INT0/T0LCP/AN8 P71/INT1/T0HCP/AN9 P72/INT2/T0IN
No.A0496-7/28
LC87F1964A
System Block Diagram
Interrupt control
Standby control
FROM
X'tal
Clock generator
SIO0
interface Port
SIO1
register
SIO4
Port
register
SIO9
Port
Timer
Port
Timer
Port INT0 Noise filter UART1
Timer
Timer
Base timer
Stack pointer
PWM0
Watchdog timer
PWM1
On-chip debugger
host
No.A0496-8/28
LC87F1964A
Description
Name VSS1, VSS2, VSS3 VDD1, VDD2 VDD3 Port -power supply Description Option
+power supply reference voltage 8-bit port specifiable 4-bit units Pull-up resistors turned 4-bit units. HOLD reset input Port interrupt input Pins functions converter input port: (P00 P07) On-chip debugger pins: DBGP0 DBGP2 (P02 P04) P05: System Clock Output P06: Timer toggle outputs P07: Timer toggle outputs
Port
8-bit port specifiable 1-bit units Pull-up resistors turned 1-bit units. functions P10: SIO0 data output P11: SIO0 data input/bus P12: SIO0 clock P13: SIO1 data output P14: SIO1 data input/bus P15: SIO1 clock P16: Timer PWML output P17: Timer PWMH output/beeper output
Port
8-bit port specifiable 1-bit units Pull-up resistors turned 1-bit units. functions P23: INT4 input/HOLD reset input/timer event input/ timer capture input/timer capture input P27: INT5 input/HOLD reset input/timer event input/ timer capture input/ timer capture input P22: SIO4 date I/O/parallel interface output P23: SIO4 date I/O/parallel interface output P24: SIO4 clock P25: SIO9 date I/O/parallel interface output P26: SIO9 date I/O/parallel interface output P27: SIO9 clock Interrupt acknowledge type Rising INT4 INT5 enable enable Falling enable enable Rising Falling enable enable level disable disable level disable disable
Continued next page.
No.A0496-9/28
LC87F1964A
Continued from preceding page.
Name Port 5-bit port specifiable 1-bit units Pull-up resistors turned 1-bit units. functions P30: UART1 transmit P31: UART1 receive P34: interface filter (see Fig.5) Port 4-bit port specifiable 1-bit units Pull-up resistors turned 1-bit units. functions P70: INT0 input/HOLD reset input/timer capture input/watchdog timer output P71: INT1 input/HOLD reset input/timer capture input P72: INT2 input/HOLD reset input/timer event input/timer capture input/ High speed clock counter input P73: INT3 input (with noise filter) /timer event input/ timer capture input converter input port: AN8(P70), AN9(P71)Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising Falling disable disable enable enable level enable enable disable disable level enable enable disable disable Description Option
PWM0 PWM1 UHDUHD+
Input Input
PWM0 PWM1 output port General-purpose input port data General-purpose port data UHD+ General-purpose port Reset 32.768kHz crystal oscillator input functions General-purpose input port converter input port: AN10 Must connected VDD1 used.
32.768kHz crystal oscillator output functions General-purpose port converter input port: AN11 Must oscillation kept open used.
Input Output
Ceramic resonator input Ceramic resonator output
No.A0496-10/28
LC87F1964A
Port Output Types
table below lists types port outputs presence/absence pull-up resistor. Data read into input port even output mode.
Port Name Option selected units Option type PWM0, PWM1 UHD+, UHDXT1 Nch-open drain CMOS CMOS CMOS Input only 32.768kHz crystal oscillator output Programmable Programmable CMOS Nch-open drain CMOS Nch-open drain Output type Pull-up resistor Programmable (Note Programmable Programmable
Note Programmable pull-up resistors port controlled 4-bit units (P00 07).
Power Treatment
Connect shown below minimize noise input VDD1 pin. sure electrically short VSS1, VSS2, VSS3 pins. Example When microcontroller backup state HOLD mode, power sustain high level output ports supplied their backup capacitors.
backup Power supply VDD1
VDD2 VDD3
VSS1 VSS2 VSS3
Example high level output ports sustained unstable HOLD backup mode.
backup Power supply VDD1
VDD2 VDD3
VSS1 VSS2 VSS3
No.A0496-11/28
LC87F1964A
Reference Power Option
When voltage 5.5V supplied VDD1 internal reference voltage circuit activated, reference voltage port output generated. active/inactive state reference voltage circuit switched option selection. procedure marking option selection described below.
Regulator Option selection Regulator HOLD mode Regulator HALT mode Reference voltage circuit state Normal state HOLD mode HALT mode active active active NONUSE NONUSE active inactive inactive NONUSE active inactive active NONUSE NONUSE NONUSE inactive inactive inactive
When reference voltage circuit made inactive, level reference voltage port output equal VDD1. Selection used reference voltage circuit inactive HOLD HALT mode. When reference voltage circuit activated, current drain increases approximately 100µA compared with when reference voltage circuit inactive. Example VDD1=VDD2=3.3V Inactivating reference voltage circuit (selection (4)). Connecting VDD3 VDD1 VDD2.
Power supply 3.3V backup VDD1 UHD+ UHDVDD2 VDD3 UFILT VSS1 VSS2 VSS3 connector
Example VDD1=VDD2=5.0V Activating reference voltage circuit (selection (1)). Isolating VDD3 from VDD1 VDD2, connecting capacitor between VDD3 VSS.
backup Power supply VDD1 UHD+ UHDVDD2 2.2µF 0.1µF VDD3 UFILT VSS1 VSS2 VSS3 2.2µF connector
No.A0496-12/28
LC87F1964A
Absolute Maximum Ratings 25°C, VSS1 VSS2 VSS3
Parameter Maximum supply voltage Input voltage Input/output voltage Peak output current IOPH(2) IOPH(3) PWM0, PWM1 Ports Average output current (Note 1-1) IOMH(2) IOMH(3) PWM0, PWM1 Ports Total output current IOAH(1) IOAH(2) IOAH(3) IOAH(4) IOAH(5) Peak output current IOPL(2) IOPL(3) Average output current (Note 1-1) IOML(2) IOML(3) Total output current IOAL(1) IOAL(2) IOAL(3) IOAL(4) IOAL(5) Allowable power Dissipation Operating ambient Temperature Storage ambient temperature Tstg Topr IOML(1) IOPL(1) Ports Ports PWM0, PWM1 Ports PWM0, PWM1 Ports UHD+, UHDP02 Ports PWM0, PWM1 P00, Ports level output current Ports PWM0, PWM1 P00, Ports Ports Ports PWM0, PWM1 Ports PWM0, PWM1 Ports UHD+, Total applicable pins Ta=-30 +70°C Total applicable pins Total applicable pins Total applicable pins Total applicable pins applicable applicable +125 applicable applicable applicable Total applicable pins applicable Total applicable pins Total applicable pins IOMH(1) Ports IOPH(1) VI(1) VIO(1) Symbol Pin/Remarks VDD1, VDD2, VDD3 XT1, Ports PWM0, PWM1 Ports When CMOS output type selected applicable applicable When CMOS output type selected applicable High level output current When CMOS output type selected applicable applicable When CMOS output type selected applicable Total applicable pins Total applicable pins -7.5 -0.3 VDD+0.3 Conditions VDD[V] VDD1=VDD2=VDD3 -0.3 -0.3 Specification +6.5 VDD+0.3 unit
Note 1-1: mean output current mean value measured over 100ms.
No.A0496-13/28
LC87F1964A
Allowable Operating Range -30°C +70°C, VSS1 VSS2 VSS3
Parameter Operating supply voltage (Note2-1) Symbol VDD(1) Pin/Remarks VDD1=VDD2=VDD3 Conditions VDD[V] 0.245µs tCYC 200µs 0.490µs tCYC 200µs Except onboard programming Memory sustaining supply voltage High level input voltage VIH(1) Port port input/ interrupt side PWM0, PWM1 VIH(2) VIH(3) level input voltage VIL(2) VIL(3) VIL(4) VIL(5) VIL(6) Instruction cycle time (Note 2-2) External system clock frequency FEXCF(1) tCYC Except onboard programming open System clock frequency division ratio=1/1 External system clock duty= 50±5% open System clock frequency division ratio=1/1 External system clock duty= 50±5% Oscillation frequency range (Note 2-3) FmCF(2) FmRC FsX'tal XT1, CF1, FmCF(1) CF1, 12MHz ceramic oscillation Fig. 6MHz ceramic oscillation Fig. Internal oscillation 32.768kHz crystal oscillation Fig. 32.768 Port watchdog timer side XT1, XT2, CF1, VIL(1) Port watchdog timer side XT1, XT2, CF1, Port port input/ interrupt side Port PWM0, PWM1 0.9VDD 0.75VDD 0.245 0.490 0.1VDD +0.4 0.2VDD 0.15VDD +0.4 0.2VDD 0.8VDD -1.0 0.25VDD 0.3VDD +0.7 VDD1=VDD2=VDD3 register contents sustained HOLD mode. Specification unit
Note 2-1: must held greater than equal 3.0V flash onboard programming mode. Note 2-2: Relationship between tCYC oscillation frequency 3/FmCF division ratio 6/FmCF division ratio 1/2. Note 2-3: Tables oscillation constants.
No.A0496-14/28
LC87F1964A
Electrical Characteristics -30°C +70°C, VSS1 VSS2 VSS3
Parameter High level input current Symbol IIH(1) Pin/Remarks Ports Port PWM0, PWM1 UHD+, UHDIIH(2) IIH(3) level input current IIL(1) XT1, Ports Port PWM0, PWM1 UHD+, UHDIIL(2) IIL(3) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) VOH(6) PWM0, PWM1 (CK0 when using system clock output function) level output voltage VOL(1) VOL(2) VOL(3) VOL(4) VOL(5) VOL(6) VOL(7) VOL(8) Pull-up resistance Rpu(1) Rpu(2) Hysteresis voltage capacitance VHYS Ports Port Port pins pins other than that under test: VIN=VSS f=1MHz Ta=25°C Ports PWM0, PWM1 Ports P00, IOL=30mA IOL=5mA IOL=2.5mA IOL=10mA IOL=1.6mA IOL=1mA IOL=1.6mA IOL=1mA VOH=0.9VDD 0.1VDD XT1, Conditions VDD[V] Output disabled Pull-up resistor VIN=VDD (Including output Tr's leakage current) input port specification VIN=VDD VIN=VDD Output disabled Pull-up resistor VIN=VSS (Including output Tr's leakage current) input port specification VIN=VSS Ports VIN=VSS IOH=-1mA IOH=-0.4mA IOH=-0.2mA IOH=-10mA IOH=-1.6mA IOH=-1mA VDD-0.4 VDD-1 VDD-0.4 VDD-0.4 VDD-1.5 VDD-0.4 Specification unit
No.A0496-15/28
LC87F1964A
Serial Input/Output Characteristics -30°C +70°C, VSS1 VSS2 VSS3
SIO0 Serial Characteristics (Note 4-1-1)
Parameter Frequency level pulse width High level pulse width tSCKH(1) tSCKHA(1a) Continuous data transmission/reception mode USB, SIO4 SIO9 simultaneous. Fig. Input clock (Note 4-1-2) tSCKHA(1b) Continuous data transmission/reception mode simultaneous. SIO4 SIO9 simultaneous. Fig. (Note 4-1-2) tSCKHA(1c) Continuous data transmission/reception mode USB, SIO4 SIO9 simultaneous. Serial clock Fig. (Note 4-1-2) Frequency level pulse width High level pulse width tSCKH(2) tSCKHA(2a) Continuous data transmission/reception mode USB, SIO4 SIO9 simultaneous. CMOS output selected Output clock Fig. tSCKHA(2b) Continuous data transmission/reception mode simultaneous. SIO4 SIO9 simultaneous. CMOS output selected Fig. tSCKHA(2c) Continuous data transmission/reception mode USB, SIO4 SIO9 simultaneous. CMOS output selected Fig. tSCKH(2) +2tCYC tSCKH(2) +(25/3) tCYC tSCKH(2) +2tCYC tSCKH(2) +(19/3) tCYC tCYC tSCKH(2) +2tCYC tSCKH(2) +(10/3) tCYC tSCK(2) tSCKL(2) SCK0(P12) CMOS output selected Fig. tSCK tCYC Symbol tSCK(1) tSCKL(1) Pin/ Remarks SCK0(P12) Conditions VDD[V] Fig. Specification unit
Note 4-1-1: These specifications theoretical values. margin depending use. Note 4-1-2: serial-clock-input continuous trans/rec mode, time from SI0RUN being when serial clock first negative edge serial clock must longer than tSCKHA.
Continued next page.
No.A0496-16/28
LC87F1964A
Continued from preceding page.
Parameter Data setup time Serial input Symbol tsDI(1) Pin/ Remarks SB0(P11), SI0(P11) Data hold time thDI(1) Conditions VDD[V] Must specified with respect rising edge SIOCLK. Fig. Output delay Input clock time tdD0(2) tdD0(1) SO0(P10), SB0(P11) Continuous data transmission/reception mode (Note 4-1-3) Synchronous 8-bit mode (Note 4-1-3) tdD0(3) (Note 4-1-3) (1/3)tCYC +0.05 0.03 0.03 Specification unit
(1/3)tCYC +0.05 1tCYC +0.05
Serial output
Note 4-1-3: Must specified with respect falling edge SIOCLK. Must specified time beginning output state change open drain output mode. Fig. SIO1 Serial Characteristics (Note 4-2-1)
Parameter Frequency Input clock level pulse width High level pulse width Frequency Output clock level pulse width High level pulse width Data setup time Serial input tsDI(2) SB1(P14), SI1(P14) Data hold time thDI(2) Must specified with respect rising edge SIOCLK. Fig. Output delay time tdD0(4) SO1(P13), SB1(P14) Serial output Must specified with respect falling edge SIOCLK. Must specified time beginning output state change open drain output mode. Fig. (1/3)tCYC +0.05 0.03 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) CMOS output selected Fig. tSCKH(3) Symbol tSCK(3) tSCKL(3) Pin/ Remarks SCK1(P15) Conditions VDD[V] Fig. tCYC tSCK Specification unit
Note 4-2-1: These specifications theoretical values. margin depending use.
Serial clock
Output clock
No.A0496-17/28
LC87F1964A
SIO4 Serial Characteristics (Note 4-3-1)
Parameter Frequency level pulse width High level pulse width tSCKH(5) tSCKHA(5a) USB, SIO9 continuous data transmission/eception mode SIO0 simultaneous. Fig. Input clock (Note 4-3-2) tSCKHA(5b) simultaneous. SIO9 continuous data transmission/reception mode SIO0 simultaneous. Fig. (Note 4-3-2) tSCKHA(5c) USB, SIO9 continuous data transmission/eception mode SIO0 simultaneous. Serial clock Fig. (Note 4-3-2) Frequency level pulse width High level pulse width tSCKHA(6a) USB, SIO9 continuous data transmission/eception mode SIO0 simultaneous. CMOS output selected Output clock Fig. tSCKHA(6b) simultaneous. SIO9 continuous data transmission/eception mode SIO0 simultaneous. CMOS output selected Fig. tSCKHA(6c) USB, SIO9 continuous data transmission/eception mode SIO0 simultaneous. CMOS output selected Fig. Serial input Data setup time tsDI(3) SO4(P22), SI4(P23) Data hold time thDI(3) Must specified with respect rising edge SIOCLK. Fig. 0.03 0.03 tSCKH(6) +(5/3) tCYC tSCKH(6) +(34/3) tCYC tSCKH(6) +(5/3) tCYC tSCKH(6) +(19/3) tCYC tCYC tSCKH(6) +(5/3) tCYC tSCKH(6) +(10/3) tCYC tSCKH(6) tSCK(6) tSCKL(6) SCK4(P24) CMOS output selected Fig. tSCK tCYC Symbol tSCK(5) tSCKL(5) Pin/ Remarks SCK4(P24) Conditions VDD[V] Fig. Specification unit
Note 4-3-1: These specifications theoretical values. margin depending use. Note 4-3-2: serial-clock-input continuous trans/rec mode, time from SI4RUN being when serial clock first negative edge serial clock must longer than tSCKHA.
Continued next page.
No.A0496-18/28
LC87F1964A
Continued from preceding page.
Parameter Output delay time Serial output Symbol tdD0(5) Pin/ Remarks SO4(P22), SI4(P23) Conditions VDD[V] Must specified with respect rising edge SIOCLK. Must specified time beginning output state change open drain output mode. Fig. (1/3)tCYC +0.05 Specification unit
SIO9 Serial Characteristics (Note 4-4-1)
Parameter Frequency level pulse width High level pulse width tSCKH(7) tSCKHA(7a) USB, SIO4 continuous data transmission/reception mode SIO0 simultaneous. Fig. Serial clock Input clock (Note 4-4-2) tSCKHA(7b) simultaneous. SIO4 continuous data transmission/reception mode SIO0 simultaneous. Fig. (Note 4-4-2) tSCKHA(7c) USB, SIO4 continuous data transmission/reception mode SIO0 simultaneous. Fig. (Note 4-4-2) tCYC Symbol tSCK(7) tSCKL(7) Pin/ Remarks SCK9(P27) Conditions VDD[V] Fig. Specification unit
Note 4-4-1: These specifications theoretical values. margin depending use. Note 4-4-2: serial-clock-input continuous trans/rec mode, time from SI9RUN being when serial clock first negative edge serial clock must longer than tSCKHA.
Continued next page.
No.A0496-19/28
LC87F1964A
Continued from preceding page.
Parameter Frequency level pulse width High level pulse width tSCKHA(8a) USB, SIO4 continuous data transmission/reception mode SIO0 simultaneous. CMOS output selected Output clock Serial clock Fig. tSCKHA(8b) simultaneous. SIO4 continuous data transmission/reception mode SIO0 simultaneous. CMOS output selected Fig. tSCKHA(8c) USB, SIO4 continuous data transmission/reception mode SIO0 simultaneous. CMOS output selected Fig. Serial input Data setup time tsDI(4) SO9(P25), SI9(P26) Data hold time Output delay time Serial output thDI(4) tdD0(6) SO9(P25), SI9(P26) Must specified with respect rising edge SIOCLK. Fig. Must specified with respect rising edge SIOCLK. Must specified time beginning output state change open drain output mode. Fig. (1/3)tCYC +0.05 0.03 0.03 tSCKH(8) +(5/3) tCYC tSCKH(8) +(37/3) tCYC tSCKH(8) +(5/3) tCYC tSCKH(8) +(19/3) tCYC tCYC tSCKH(8) +(5/3) tCYC tSCKH(8) +(10/3) tCYC tSCKH(8) Symbol tSCK(8) tSCKL(8) Pin/ Remarks SCK9(P27) Conditions VDD[V] CMOS output selected Fig. tSCK Specification unit tCYC
No.A0496-20/28
LC87F1964A
Pulse Input Conditions -30°C +70°C, VSS1 VSS2 VSS3
Parameter High/low level pulse width Symbol tP1H(1) tP1L(1) Pin/Remarks INT0(P70), INT1(P71), INT2(P72), INT4(P20 P23), INT5(P24 P27) tPIH(2) tPIL(2) tPIH(3) tPIL(3) tPIH(4) tPIL(4) tPIL(5) INT3(P73) when noise filter time constant INT3(P73) when noise filter time constant 1/32 INT3(P73) when noise filter time constant 1/128 Interrupt source flag set. Event inputs timer enabled. Interrupt source flag set. Event inputs timer enabled. Interrupt source flag set. Event inputs timer enabled. Resetting enabled. tCYC Conditions VDD[V] Interrupt source flag set. Event inputs timer enabled. Specification unit
Converter Characteristics -30°C +70°C, VSS1 VSS2 VSS3
Parameter Resolution Absolute accuracy Conversion time TCAD Symbol Pin/Remarks AN0(P00) AN7(P07), AN8(P70), AN9(P71), AN10(XT1), AN11(XT2) conversion (when ADCR2=0) (Note 6-2) (Note 6-1) Conditions VDD[V] 15.68 (tCYC= 0.49µs) 23.52 conversion (when ADCR2=1) (Note 6-2) (tCYC= 0.735µs) 18.82 (tCYC= 294µs) 47.04 Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN (tCYC= 735µs) Specification unit
±1.5
97.92 (tCYC= 3.06µs) 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 1.53µs) 97.92 (tCYC= 1.53µs)
Note 6-1: quantization error (±1/2LSB) excluded from absolute accuracy value. Note 6-2: conversion time refers interval from time instruction starting converter issued till time complete digital value corresponding analog input value loaded required register.
No.A0496-21/28
LC87F1964A
Consumption Current Characteristics -30°C +70°C, VSS1 VSS2 VSS3
Parameter Normal mode consumption current (Note 7-1) IDDOP(2) Symbol IDDOP(1) Pin/ Remarks VDD1 =VDD2 =VDD3 Conditions VDD[V] FmCF=12MHz ceramic oscillation mode FsX'tal=32.768kHz crystal oscillation mode System clock 12MHzside Internal oscillation stopped Internal oscillation stopped frequency division ration IDDOP(3) FmCF=12MHz ceramic oscillation mode FsX'tal=32.768kHz crystal oscillation mode System clock 12MHz side IDDOP(4) Internal oscillation mode Internal oscillation stopped frequency division ration IDDOP(5) IDDOP(6) IDDOP(7) IDDOP(8) IDDOP(9) IDDOP(10) IDDOP(11) IDDOP(12) IDDOP(13) HALT mode consumption current (Note 7-1) IDDHALT(2) IDDHALT(1) FmCF=12MHz ceramic oscillation mode FsX'tal=32.768kHz crystal oscillation mode System clock 6MHz side Internal oscillation stopped frequency division ration FmCF=0MHz (oscillation stopped) FsX'tal=32.768kHz crystal oscillation mode System clock internal oscillation frequency division ration FmCF=0MHz (oscillation stopped) FsX'tal=32.768kHz crystal oscillation mode System clock 32.768kHz side Internal oscillation stopped frequency division ration HALT mode FmCF=12MHz ceramic oscillation mode FsX'tal=32.768kHz crystal oscillation mode System clock 12MHz side Internal oscillation stopped Internal oscillation stopped frequency division ration IDDHALT(3) HALT mode FmCF=12MHz ceramic oscillation mode FsX'tal=32.768kHz crystal oscillation mode IDDHALT(4) System clock 12MHz side Internal oscillation mode Internal oscillation stopped frequency division ration IDDHALT(5) IDDHALT(6) IDDHALT(7) HALT mode FmCF=12MHz ceramic oscillation mode FsX'tal=32.768kHz crystal oscillation mode System clock 6MHz side Internal oscillation stopped frequency division ration 0.68 0.36 0.30 Specification unit
Note 7-1: consumption current value includes none currents that flow into output internal pull-up resistors.
Continued next page.
No.A0496-22/28
LC87F1964A
Continued from preceding page.
Parameter HALT mode consumption current (Note 7-1) IDDHALT(9) IDDHALT(10) IDDHALT(11) IDDHALT(12) IDDHALT(13) HOLD mode consumption current Timer HOLD mode consumption current IDDHOLD(1) IDDHOLD(2) IDDHOLD(3) IDDHOLD(4) IDDHOLD(5) IDDHOLD(6) VDD1 Symbol IDDHALT(8) Pin/ Remarks VDD1 =VDD2 =VDD3 HALT mode FmCF=0MHz (oscillation stopped) FsX'tal=32.768kHz crystal oscillation mode System clock internal oscillation frequency division ration HALT mode FmCF=0MHz (oscillation stopped) FsX'tal=32.768kHz crystal oscillation mode System clock 32.768kHz side Internal oscillation stopped frequency division ration HOLD mode CF1=VDD open (External clock mode) Timer HOLD mode CF1=VDD open (External clock mode) FsX'tal=32.768kHz crystal oscillation mode 0.10 0.04 0.03 0.15 0.63 0.18 0.84 Conditions VDD[V] Specification 0.37 unit
Note 7-1: consumption current value includes none currents that flow into output internal pull-up resistors.
Characteristics Timing Ta=0 +70°C, VSS1=VSS2=VSS3=0V
Parameter High level output level output Output signal crossover voltage Differential input sensitivity Differential input common mode range High level input level input data rise time data fall time Symbol VOH(USB) VOL(USB) VCRS VIH(USB) VIL(USB) RS=33,CL=50pF RS=33,CL=50pF |(UHD+)-(UHD-)| Conditions k±5% k±5% Specification unit
F-ROM Programming Characteristics -10°C +55°C, VSS1 VSS2 VSS3
Parameter Onboard programming current Programming time tFW(1) tFW(2) Erasing Programming Symbol IDDFW(1) Pin/Remarks VDD1 Conditions VDD[V] Without current Specification unit
No.A0496-23/28
LC87F1964A
Characteristics Sample Main System Clock Oscillation Circuit
Given below characteristics sample main system clock oscillation circuit that measured using SANYO-designated oscillation characteristics evaluation board external components with circuit constant values with which oscillator vendor confirmed normal stable oscillation. Table Characteristics Sample Main System Clock Oscillator Circuit with Ceramic Oscillator
Nominal Frequency 6MHz 8MHz 10MHz 12MHz Vendor Name MURATA MURATA MURATA MURATA Circuit Constant Oscillator Name [pF] CSTCR6M00G15***-R0 CSTCE8M00G15***-R0 CSTCE10M0G15***-R0 CSTCE12M0G15***-R0 (39) (33) (33) (33) [pF] (39) (33) (33) (33) Operating Voltage Range Oscillation Stabilization Time [ms] 0.10 0.10 0.10 0.10 [ms] 0.50 0.50 0.50 0.50 Built Remarks
oscillation stabilization time refers time interval that required oscillation stabilized after goes above operating voltage lower limit (see Figure
Characteristics Sample Subsystem Clock Oscillator Circuit
Given below characteristics sample subsystem clock oscillation circuit that measured using SANYOdesignated oscillation characteristics evaluation board external components with circuit constant values with which oscillator vendor confirmed normal stable oscillation. Table Characteristics Sample Subsystem Clock Oscillator Circuit with Crystal Oscillator
Nominal Frequency Circuit Constant Vendor Name Oscillator Name [pF] 32.768kHz EPSON TOYOCOM MC-306 [pF] OPEN 510k Operating Voltage Range Oscillation Stabilization Time Applicable value= 12.5pF Remarks
oscillation stabilization time refers time interval that required oscillation stabilized after instruction starting subclock oscillation circuit executed time interval that required oscillation stabilized after HOLD mode reset (see Figure Note: components that involved oscillation should placed close another possible because they vulnerable influences circuit pattern.
X'tal
Figure Oscillator Circuit
Figure Oscillator Circuit
0.5VDD
Figure Timing Measurement Point
No.A0496-24/28
LC87F1964A
Power supply Reset time Operating lower limit
Internal oscillation tmsCF
oscillation (XT1, XT2) tmsX'tal Crystal oscillation (XT1, XT2)
State
Unpredictable
Reset
Instruction execution
Reset Time Oscillation Stabilization Time
HOLD reset signal
HOLD reset signal absen
HOLD reset signal valid
Internal oscillation tmsCF oscillation (XT1, XT2) tmsX'tal Crystal Oscillation (XT1, XT2)
State
HOLD
HALT
HOLD Reset Signal Oscillation Stabilization Time
Figure Oscillation Stabilization Times
No.A0496-25/28
LC87F1964A
P34/FILT
2.2µF
When using internal circuit generate 48MHz clock USB, necessary connect filter circuit such that shown left P34/FILT pin.
Figure Filter Circuit Internal Circuit
UHD+
Note: It's necessary adjust Circuit Constant Port Peripheral Circuit each mounting board.
UHD33
Figure Port Peripheral Circuit
RRES
CRES
Note: Determine value CRES RRES that reset signal present period 200µs after supply voltage goes beyond lower limit IC's operating voltage.
Figure Reset Circuit
No.A0496-26/28
LC87F1964A
SIOCLK:
DATAIN:
DATAOUT:
Data transfer period (SIO0, only)
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: Data transfer period (SIO0, only) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA thDI tSCKH
Figure Serial Output Waveforms
tPIL
tPIH
Figure Pulse Input Timing Signal Waveform
Vcrs
Figure Data Signal Timing Voltage Level
No.A0496-27/28
LC87F1964A
SANYO Semiconductor Co.,Ltd. assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO Semiconductor Co.,Ltd. products described contained herein. SANYO Semiconductor Co.,Ltd. strives supply high-quality high-reliability products, however, semiconductor products fail malfunction with some probability. possible that these probabilistic failures malfunction could give rise accidents events that could endanger human lives, trouble that could give rise smoke fire, accidents that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO Semiconductor Co.,Ltd. products described contained herein controlled under applicable local export control laws regulations, such products require export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written consent SANYO Semiconductor Co.,Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO Semiconductor Co.,Ltd. product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. Upon using technical information products described herein, neither warranty license shall granted with regard intellectual property rights other rights SANYO Semiconductor Co.,Ltd. third party. SANYO Semiconductor Co.,Ltd. shall liable claim suits with regard third party's intellctual property rights which resulted from technical information products mentioned above.
This catalog provides information November, 2006. Specifications information herein subject change without notice.
No.A0496-28/28

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