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LC87F06J2A CMOS FROM 192K byte, 8192 byte on-chip 8-bit 1-ch


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Ordering number ENA0432A
LC87F06J2A
CMOS FROM 192K byte, 8192 byte on-chip
8-bit 1-chip Microcontroller
SANYO LC87F06J2A 8-bit microcomputer that, centered around running minimum cycle time 66.6ns, integrate single chip number hardware features such 192K-byte flash (onboard rewritable), 8K-byte RAM, Onchip debugging function, sophisticated 16-bit timers/counters (may divided into 8-bit timers), 16-bit timer with prescaler (may divided into 8-bit timers), four 8-bit timers with prescaler, base timer serving time-of-day clock, synchronous ports (with automatic block transmission/reception capabilities), asynchronous/synchronous port, synchronous ports, UART ports (full duplex), four 12-bit channels, VPS/PDC/PAL-WSS EPG-J VBID(Video-ID) Data-slicer, universal remote control transmitter, 8-bit 16-channel converter, high-speed clock counter, system clock frequency divider, 36-source 10-vector interrupt, correction function feature.
Features
Flash Single power supply, on-board writeable Block erase byte units 196608 bits (LC87F06J2A) 8192 bits Cycle Time 66.6ns (15MHz, frequency division ratio Note: cycle time indicates speed read ROM.
This product licensed from Silicon Storage Technology, Inc. (USA), manufactured sold SANYO Semiconductor Co., Ltd.
SANYO Semiconductor Co.,Ltd. products described contained herein are, with regard "standard application", intended general electronics equipment (home appliances, equipment, communication device, office equipment, industrial equipment etc.). products mentioned herein shall intended "special application" (medical equipment whose purpose sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level reliability directly threaten human lives case failure malfunction product cause harm human bodies, shall they grant guarantee thereof. should intend products applications outside standard applications customer considering such and/or outside scope intended standard applications, please consult with prior intended use. there consultation inquiry before intended use, customer shall solely responsible use. Specifications SANYO Semiconductor Co.,Ltd. products described contained herein stipulate performance, characteristics, functions described products independent state, guarantees performance, characteristics, functions described products mounted customer' products equipment. verify symptoms states that cannot evaluated independent device, customer should always evaluate test devices mounted customer' products equipment.
Ver.1.003
31407HKIM 20070115-S00002 No.A0432-1/32
LC87F06J2A
Minimum Instruction Cycle Time (tCYC) 200ns (15MHz, frequency division ratio) Ports Normal withstand voltage ports Ports whose direction designated units: (P1n, P2n, P3n, P73, P8n, PAn, PB2, PCn, S2Pn, XT2, PWM0, PWM1, PEn, Ports whose direction designated units: (P0n) Normal withstand voltage input ports: (XT1) Dedicated oscillator ports: (CF1, CF2) Reset pin: (RES) Data slicer pins: (PB4, PB6) Power pins: (VSS1 VSS4, VDD1 VDD4, VSSVCO, VDDVCO, VDDODA) Timer Timer 16-bit timer/counter with capture register Mode 8-bit timer with 8-bit programmable prescaler (with 8-bit capture registers) channels Mode 8-bit timer with 8-bit programmable prescaler (with 8-bit capture registers) 8-bit counter (with 8-bit capture registers) Mode 16-bit timer with 8-bit programmable prescaler (with 16-bit capture registers) Mode 16-bit counter (with 16-bit capture registers) Timer 16-bit timer/counter that support PWM/ toggle output Mode 8-bit timer with 8-bit prescaler (with toggle outputs) 8-bit timer/counter (with toggle outputs) Mode 8-bit with 8-bit prescaler channels Mode 16-bit timer/counter with 8-bit prescaler (with toggle outputs) (toggle outputs also from lower-order bits) Mode 16-bit timer with 8-bit prescaler (with toggle outputs) (The lower-order bits used PWM.) Timer 8-bit timer with 6-bit prescaler Timer 8-bit timer with 6-bit prescaler Timer 8-bit timer with 6-bit prescaler (with toggle outputs) Timer 8-bit timer with 6-bit prescaler (with toggle outputs) Timer 16-bit timer with prescaler (may divided into 8-bit timers) Base timer clock selectable from subclock (32.768kHz crystal oscillator), system clock, timer prescaler output. Interrupts programmable different time schemes. Time Counter Using with base timer, used 65,000 days minute second counter. High-speed Clock Counter count clocks with maximum clock rate 20MHz main clock 10MHz). generate output real time. synchronous serial interface first/MSB first mode selectable Built-in 8-bit baudrate generator (maximum transfer clock cycle tCYC) Automatic continuous data transmission bits) asynchronous/synchronous serial interface Mode Synchronous 8-bit serial 3-wire configuration, tCYC transfer clocks) Mode Asynchronous serial (Half-duplex, data bits, stop bit, 2048 tCYC baudrates) Mode mode (start bit, data bits, tCYC transfer clocks) Mode mode (start detect, data bits, stop detect)
Continued next page.
No.A0432-2/32
LC87F06J2A
Continued from preceding page.
SIO2: synchronous serial interface first mode Built-in 8-bit baudrate generator (maximum transfer clock cycle tCYC) Automatic continuous data transmission bytes) synchronous serial interface first/MSB first mode selectable Built-in 8-bit baudrate generator (maximum transfer clock cycle tCYC) synchronous serial interface first/MSB first mode selectable Built-in 8-bit baudrate generator (maximum transfer clock cycle tCYC) UART: channels Full duplex 7/8/9 data bits selectable stop bits continuous transmission mode) Built-in baudrate generator (with baudrates 16/3 8192/3 tCYC) Converter bits channels Multifrequency 12-bit channels Remote Control Receiver Circuit (sharing pins with P73, INT3, T0IN TOHCP) Noise filtering function (noise filter time constant selectable from tCYC, tCYC, tCYC) noise filtering function available INT3, T0IN, T0HCP signal P73. When read with instruction, signal level that read regardless availability noise filtering function. Small Signal Detect Function Small Signal Detect Function available following terminals. Capable detecting pulse with certain level amplitude. Input bias circuit available. H-Counter H-counter choose following signals count-clock. HCTR signal P22/INT4/T1IN/T0LCP/T0HCP/HCTR terminal CSYNC signal PB6/CVD/CSYNC terminal Composite sync signal detected from (composite Video) signal built-in sync-separator inputted form PB6/CVD/CSYNC terminal Counter 7bit (up) 1bit (over-flow flag) Field (first/second) Detect Function Distinguishes field with following signals. CSYNC signal PB6/CVD/CSYNC terminal Composite sync signal detected from (composite Video) signal built-in sync-separator inputted form PB6/CVD/CSYNC terminal Outputs Field-Detect signal from PB0/DS1FLD terminal Watchdog Timer External watchdog timer Interrupt reset signals selectable
No.A0432-3/32
LC87F06J2A
Data-Slicer Supports XDS-1X XDS-2X (With auto-recognition) VPS/PDC/PAL-WSS Data-slicer choose following three formats Line(VBI). PDC/UDT other Teletext data PAL-WSS EPG-J Antiope VBID(VideoID) Universal Remote Control Transmitter Circuit Outputs remote control signal from PF4/IRP terminal. Interrupts sources, vector addresses Provides three levels (low (L), high (H), highest (X)) multiplex interrupt control. interrupt requests level equal lower than current interrupt accepted. When interrupt requests more vector addresses occur same time, interrupt highest level takes precedence over other interrupts. interrupts same level, interrupt into smallest vector address takes precedence.
Vector 00003H 0000BH 00013H 0001BH 00023H 0002BH 00033H 0003BH 00043H 0004BH Selectable Level INT0 INT1 INT2/T0L/INT4 INT3/INT5/Base timer0/Base timer1/Remocon transmit T0H/INT6/SIO7 T1L/T1H/INT7/SIO8 SIO0/UART1 receive/UART2 receive/T8L/T8H SIO1/SIO2/UART1 transmit/UART2 transmit ADC/T6/T7/PWM4, PWM5/ Automatic transmission Port 0/T4/T5/Data slicer /PWM0, PWM1 Interrupt signal
Priority Level: interrupts same level, with smallest vector address takes precedence. Subroutine Stack Levels 4096 levels maximum (the stack allocated RAM.) High-speed Multiplication/Division Instructions bits bits tCYC execution time) bits bits tCYC execution time) bits bits tCYC execution time) bits bits tCYC execution time) Oscillation Circuits oscillator circuit (internal): system clock oscillator circuit: system clock with internal Crystal oscillator circuit: low-speed system clock Multifrequency oscillator circuit (internal): system clock
No.A0432-4/32
LC87F06J2A
System Clock Divider Function current. minimum instruction cycle selectable from 300ns, 600ns, 1.2µs, 2.4µs, 4.8µs, 9.6µs, 19.2µs, 38.4µs, 76.8µs main clock rate 10MHz). Standby Function HALT mode: Halts instruction execution while allowing peripheral circuits continue operation. Oscillation halted automatically. Canceled system reset occurrence interrupt. HOLD mode: Suspends instruction execution operation peripheral circuits. crystal oscillators automatically stop operation. There three ways resetting HOLD mode. Setting Reset lower level Setting least INT0, INT1, INT2, INT4, INT5 pins specified level Having interrupt source established port X'tal HOLD mode: Suspends instruction execution operation peripheral circuits except base timer Day-and-time counter. oscillators automatically stop operation. state crystal oscillation established when HOLD mode entered retained. There four ways resetting X'tal HOLD mode. Setting Reset level. Setting least INT0, INT1, INT2, INT4, INT5 pins specified level. Having interrupt source established port Having interrupt source established base timer circuit. Onchip Debugging Permits software debugging with test device installed target board. Correction Function match address registers: correction: 128byte Package Form "Lead-free type" Development Tools On-chip debugger: TCB87 TypeA LC87F06J2A TCB87 TypeB LC87F06J2A Flash Programming Boards
Package Programming boards W87F05256Q
Flash Programmer
Maker Flash Support Group, Inc. (Single) Flash Support Group, Inc. (Gang) Model AF9708/AF9709/AF9709B (including product Ando Electric Co.,Ltd) AF9723(Main body) (including product Ando Electric Co.,Ltd) AF9833(Unit) (including product Ando Electric Co.,Ltd) SANYO SKK(Sanyo FWS) Application Version: After 1.03 Chip Data Version: After 2.01 LC87F06J2 Revision: After 01.86 Revision: After 02.04 LC87F06J2A FAST Supported version Revision: After 02.61 Device LC87F06J2A FAST
No.A0432-5/32
LC87F06J2A
Package Dimensions
unit (typ) 3151A
23.2
14.0
20.0
0.65 (0.58)
(2.7)
0.15
3.0max
SANYO QIP100E(14X20)
17.2
No.A0432-6/32
PC6/DBGP1
PC7/DBGP2
PC3/AN10
PC4/AN11
PC5/DGBP0
PA0/SO7
PC1/AN8
PC2/AN9
PB6/CVD/CSYNC
PC0/OCSYNC
PB4/FILTSLC
PB0/DS1FLD
PA1/SI7/SB7 VSSVCO VDDVCO VDD3 VSS3
PA2/SCK7
Assignment
PA3/SO8 VDDODA P35/URX2 P34/UTX2 P33/URX1 P32/UTX1 P31/PWM5 P30/PWM4 P27/INT5/T1IN/T0LCP/T0HCP P26/INT5/T1IN/T0LCP/T0HCP P25/INT5/T1IN/T0LCP/T0HCP
PA4/SI8/SB8
PA5/SCK8
P70/INT0/T0LCP
P71/INT1/T0HCP
P72/INT2/T0IN/T0LCP
P73/INT3/T0IN/T0HCP
VSS1 VDD1 P80/AN0 P81/AN1 P82/AN2 P83/AN3 P84/AN4 P85/AN5 P86/AN6 P87/AN7 P10/SO0 P11/SI0/SB0 P12/SCK0 P13/SO1 P14/SI1/SB1 P15/SCK1 P16/T1PWML P17/T1PWMH/BUZ
P23/INT4/T1IN/T0LCP/T0HCP P22/INT4/T1IN/T0LCP/T0HCP/HCTR P21/INT4/T1IN/T0LCP/T0HCP P07/T7O P06/T6O P05/CKO VSS2 VDD2 PWM0 PWM1 SI2P3/SCK2O SI2P2/SCK2
LC87F06J2A
LC87F06J2A
view
PE0/AN12 PE1/AN13
VSS4
VDD4
PF4/IRP
PE2/AN14
PE3/AN15
SI2P0/SO2
SI2P1/SI2/SB2
SANYO: "Lead-free Type"
No.A0432-7/32
LC87F06J2A
System Block Diagram
Interrupt Control
Flash Standby Control Xtal SIO0 Interface Clock Generator
SIO1
Port
Register
SIO2
Port
Register
SIO7 SIO8
Port Port
Timer
Timer
INT0-7 Port (Small signal detect) Port
Timer
Timer
Stack Pointer
Timer
Port Watchdog Timer
Timer
Port Onchip Debugger
Timer
Port
UART1
Port
UART2
PWM4,
PWM0,1
Port H-counter Base timer
Data slicer
Date slicer Universal remote control transmitter
time counter
No.A0432-8/32
LC87F06J2A
Description
Name VSS1, VSS2 VSS3, VSS4 VSSVCO VDD1, VDD2 VDD3, VDD4 VDDVCO, VDDODA Port 8-bit port specifiable 4-bit units Pull-up resistor turned 4-bit units HOLD release input Port interrupt input functions P05: System clock output P06: Timer toggle output P07: Timer toggle output Port 8-bit port specifiable 1-bit units Pull-up resistor turned 1-bit units functions P10: SIO0 data output P11: SIO0 data input, P12: SIO0 clock P13: SIO1 data output P14: SIO1 data input, P15: SIO1 clock P16: Timer PWML output P17: Timer PWMH output, Beeper output Port 8-bit port specifiable 1-bit units Pull-up resistor turned 1-bit units functions P20: INT4 input/HOLD reset input/timer event input/timer capture input/ timer capture input/INT6 input/timer capture input/small signal input P21, P23: INT4 input/HOLD reset input/timer event input/timer capture input/ timer capture input P22: input/HOLD reset input/timer event input/timer capture input/ timer capture input/HCTR signal input P24: INT5 input/HOLD reset input/timer event input/timer capture input/ timer capture input/INT7 input/timer capture input/small signal input P27: INT5 input/HOLD reset input/timer event input/timer capture input/ Timer capture input Interrupt acknowledge type Rising INT4 INT5 INT6 INT7 enable enable enable enable Falling enable enable enable enable Rising/ Falling enable enable enable enable level disable disable disable disable level disable disable disable disable Power supply Function description Option
Power supply
Port
7-bit port specifiable 1-bit units Pull-up resistor turned 1-bit units functions P30: PWM4 output P31: PWM5 output P32: UART1 transmit P33: UART1 receive P34: UART2 transmit P35: UART2 receive
Continued next page.
No.A0432-9/32
LC87F06J2A
Continued from preceding page.
Name Port 4-bit port specifiable 1-bit units Pull-up resistor turned 1-bit units functions P70: INT0 input/HOLD release input/Timer capture input/Output watchdog timer P71: INT1 input/HOLD release input/Timer capture input P72: INT2 input/HOLD release input/Timer event input/Timer capture input P73: INT3 input with noise filter/Timer event input/Timer capture input Interrupt acknowledge type Rising INT0 INT1 INT2 INT3 enable enable enable enable Falling enable enable enable enable Rising/ Falling disable disable enable enable level enable enable disable disable level enable enable disable disable Function description Option
Port
8-bit port specifiable 1-bit units Other functions P80-P87: converter input port
Port
6-bit port specifiable 1-bit units Pull-up resistor turned 1-bit units functions PA0: SIO7 data output PA1: SIO7 data input, PA2: SIO7 clock PA3: SIO8 data output PA4: SIO8 data input, PA5: SIO8 clock
Port PB4,
5-bit port specifiable 1-bit units Other functions PB0: Output field recognition signal PB4: connection Slicer PB6: Input CSYNC signal/CVD (Composite Video) signal
Port
8-bit port specifiable 1-bit units Pull-up resistor turned 1-bit units Other functions PC0: OCSYNC output PC4: converter input port PC7: On-chip Debugger
Port
8-bit port specifiable 1-bit units Pull-up resistor turned 1-bit units Other functions PE0-PE3: converter input port
Port
8-bit port specifiable 1-bit units Pull-up resistor turned 1-bit units Other functions PF4: Remote control signal output
Continued next page.
No.A0432-10/32
LC87F06J2A
Continued from preceding page.
Name SIO2 Port SI2P0 SI2P3 4-bit port specifiable 1-bit units Other functions: SI2P0: SIO2 data output SI2P1: SIO2 data input, input/output SI2P2: SIO2 clock input/output SI2P3: SIO2 clock output PWM0 PWM1 PWM0 output port General-purpose available PWM1 output port General-purpose available Reset Input terminal 32.768kHz X'tal oscillation Other functions: General-purpose input port Must connected VDD1 used. Output terminal 32.768kHz X'tal oscillation Other functions: General-purpose port Must oscillation kept open used. Ceramic resonator input Ceramic resonator output Function description Option
Port Output Types
table below lists types port outputs presence/absence pull-up resistor. Data read into input port even output mode.
Port Options selected units Option type PB4, SI2P0, SI2P2 SI2P3 PWM0, PWM1 SI2P1 CMOS (when selected ordinary port) N-channel open drain (when SIO2 data selected) Input only Output 32.768kHz crystal oscillator N-channel open drain (when general-purpose output mode) N-channel open drain CMOS N-channel open drain CMOS Programmable Programmable CMOS N-channel open drain CMOS Programmable CMOS N-channel open drain CMOS N-channel open drain Output type Pull-up resistor Programmable (Note Programmable Programmable
Note Programmable pull-up resistors port controlled 4-bit units (P00 P03, P07).
No.A0432-11/32
LC87F06J2A
Absolute Maximum Ratings 25°C, VSS1 VSS2 VSS3 =VSS4=VSSVCO=
Parameter Maximum Supply voltage Input voltage Input/Output Voltage VI(1) VIO(1) Symbol VDDMAX Pins/Remarks VDD1, VDD2, VDD3, VDD4, VDDVCO, VDDODA XT1, CF1, Ports Ports Ports SI2P0 SI2P3 PWM0, PWM1, Peak output current IOPH(2) IOPH(3) Average output current (Note 1-1) IOMH(2) High level output current IOMH(3) Total output current IOAH(3) IOAH(4) IOAH(1) IOAH(2) IOMH(1) IOPH(1) Ports Ports SI2P0 SI2P3 PWM0, PWM1 Ports Ports SI2P0 SI2P3 PWM0, PWM1 PWM0, PWM1 SI2P0 SI2P3 Ports Port PWM0, PWM1 SI2P0 SI2P3 IOAH(5) IOAH(6) IOAH(7) IOAH(8) IOAH(9) IOAH(10) IOAH(11) Peak output current IOPL(1) Ports Ports Port Ports Ports PB4, Ports Ports SI2P0 SI2P3 level output current PWM0, PWM1 IOPL(2) IOPL(3) Average output current (Note 1-1) IOML(1) P00, Ports Ports Ports SI2P0 SI2P3 PWM0, PWM1 IOML(2) IOML(3) P00, Ports application pin. application pin. application pin. application pin. application pin. Total applicable pins Total applicable pins Total applicable pins Total applicable pins application pin. Total applicable pins Total applicable pins Total applicable pins Total applicable pins Total applicable pins application pin. application pin. Total applicable pins Total applicable pins application pin. application pin. CMOS output select application CMOS output select application -0.3 VDD+0.3 Conditions VDD[V] VDD1=VDD2=VDD3=VDD4 =VDDVCO =VDDODA -0.3 VDD+0.3 -0.3 Specification +6.5 unit
Note 1-1: Average output current average current 100ms interval.
Continued next page.
No.A0432-12/32
LC87F06J2A
Continued from preceding page.
Specification Parameter Total output current Symbol IOAL(1) IOAL(2) IOAL(3) IOAL(4) level output current IOAL(5) IOAL(6) Pins/Remarks Port Port Ports PWM0, PWM1 SI2P0 SI2P3 Ports Ports PWM0, PWM1 SI2P0 SI2P3 IOAL(7) IOAL(8) IOAL(9) IOAL(10) IOAL(11) IOAL(12) IOAL(13) Maximum power consumption Operating temperature range Storage temperature range Tstg Topr Ports Ports Port Ports Ports PB4, Total applicable pins Total applicable pins Total applicable pins Total applicable pins Total applicable pins Total applicable pins Total applicable pins Total applicable pins Total applicable pins Conditions VDD[V] Total applicable pins Total applicable pins Total applicable pins Total applicable pins unit
Recommended Operating Range -20°C +70°C, VSS1 VSS2 VSS3 VSS4 VSSVCO
Parameter Operating supply voltage (Note 2-1, 2-2) Data-slicer Operating supply voltage Base timer time counter Operating supply voltage Memory sustaining supply voltage High level input voltage VIH(1) Ports SI2P0 SI2P3 port input /interrupt side VIH(2) Ports PB2, Ports PWM0, PWM1 VIH(3) VIH(4) VIH(5) Watchdog timer side XT1, XT2, CF1, P20, Small signal input side 0.9VDD 0.75VDD 0.75VDD 0.3VDD +0.7 0.3VDD +0.7 VDD1 register contents HOLD mode. VDD(3) VDD(2) Symbol VDD(1) Pins/Remarks VDD1=VDD2 =VDD3=VDD4 =VDDVCO=VDDODA VDD1=VDD2 =VDD3=VDD4 =VDDVCO=VDDODA VDD1 X'tal HOLD mode Base timer clock subclock. FsX'tal=32.768kHz crystal oscillation mode. Conditions VDD[V] 0.196µs tCYC 200µs 1.47µs tCYC 200µs 0.196µs tCYC 0.340µs 4.75 5.25 Specification unit
Note 2-1: must held greater than equal 4.5V flash onboard programming mode. Note 2-2: Relationship between tCYC oscillation frequency 3/FmCF division ratio 6/FmCF division ratio 1/2.
Continued next page. No.A0432-13/32
LC87F06J2A
Continued from preceding page.
Parameter level input voltage Symbol VIL(1) Pins/Remarks Ports SI2P0 SI2P3 port input /interrupt VIL(2) Ports PB2, Ports PWM0,PWM1 VIL(3) VIL(4) VIL(5) Composite video signal input voltage (Note 2-4) Instruction cycle time (Note 2-2) Oscillation frequency Range (Note 2-3) FmRC FmMRC FsX'tal XT1, FmCF(1) CF1, 15MHz ceramic oscillation Fig. Internal oscillation Frequency variable oscillation source oscillation 32.768kHz crystal oscillation. Fig. tCYC Data-slicer Operating mode 4.75 5.25 0.196 0.196 1.470 32.768 0.340 VCVD(1) VCVD(2) Port Watchdog Timer XT1, XT2, CF1, P20, Small signal input side PB6(CVD) 2Vp-p input mode 1Vp-p input mode 0.8VDD -1.0 0.25VDD 0.25VDD Vp-p 0.15VDD +0.4 0.1VDD +0.4 Conditions VDD[V] Specification unit
Note 2-2: Relationship between tCYC oscillation frequency 3/FmCF division ratio 6/FmCF division ratio 1/2. Note 2-3: Tables oscillation constants. Note 2-4: When setting DSLDACT register's bit7 bit6 diagram external circuit.
No.A0432-14/32
LC87F06J2A
Electrical Characteristics -20°C +70°C, VSS1 VSS2 VSS3 VSS4 VSSVCO
Parameter High level input current Symbol IIH(1) Pins/Remarks Ports Ports Ports SI2P0 SI2P3 PWM0, PWM1 IIH(2) IIH(3) IIH(4) level input current IIL(1) XT1, P20, Small signal input side Ports Ports Ports SI2P0 SI2P3 PWM0, PWM1 IIL(2) IIL(3) IIL(4) High level output voltage VOH(1) VOH(2) VOH(3) VOH(4) VOH(5) level output voltage VOL(1) VOL(2) XT1, P20, Small signal input side Ports Ports SI2P0 SI2P3 Ports PWM0, PWM1 P30, P31(PWM4, output mode) Ports Ports SI2P0 SI2P3 PWM0, PWM1, VOL(3) VOL(4) VOL(5) Pull-up resistation Rpu(1) Rpu(2) Hysteresis Voltage VHYS(1) Ports Ports Port Ports Ports SI2P0 SI2P3 VHYS(2) capacitance P20, Small signal input side pins pins other than that under test: VIN=VSS f=1MHz Ta=25°C Input voltage sensitivity Bias Voltage Composite video signal input clamping voltage VBIAS VCLMP Vsen P20, Small signal input side P20, Small signal input side PB6(CVD) Pedestal voltage 0.12VDD 0.5VDD Vp-p 0.1VDD 0.1VDD P00, IOL=30mA IOL=5.0mA IOL=1.6mA VOH=0.9VDD IOL=10mA IOL=1.6mA IOH=-0.4mA IOH=-10mA IOH=-1.6mA Using input port VIN=VSS VIN=VSS VIN=VBIAS+0.5 (VBIAS bias voltage) IOH=-1.0mA IOH=-0.4mA VDD-1 VDD-0.4 VDD-0.4 VDD-1.5 VDD-0.4 -8.5 -4.2 Using input port VIN=VDD VIN=VDD VIN=VBIAS+0.5 (VBIAS bias voltage) Output disable Pull-up resistor VIN=VSS (including off-leak current output Tr.) Conditions VDD[V] Output disable Pull-up resistor VIN=VDD (including off-leak current output Tr.) Specification unit
No.A0432-15/32
LC87F06J2A
Serial Characteristics -20°C +70°C, VSS1 VSS2 VSS3 VSS4 VSSVCO
SIO0 Serial Characteristics (Note 4-1-1)
Parameter Frequency level pulse width High level pulse width tSCKHA(1a) Continuous data transmission/reception mode SIO2 Input clock simultaneous. Universal remote control transmitter simultaneous. Fig. (Note 4-1-2) tSCKHA(1b) Continuous data transmission/reception mode SIO2 simultaneous. Universal remote control transmitter simultaneous. Serial clock Fig. (Note 4-1-2) Frequency level pulse idth High level pulse idth tSCKHA(2a) Continuous data transmission/reception mode SIO2 Output clock simultaneous. Universal remote control transmitter simultaneous. CMOS output selected. Fig. tSCKHA(2b) Continuous data transmission/reception mode SIO2 simultaneous. Universal remote control transmitter simultaneous. CMOS output selected. Fig. Data setup time Serial input tsDI(1) SI0(P11), SB0(P11) Data hold Time thDI(1) Must specified with respect rising edge SIOCLK fig. 0.03 0.03 tSCKH(2) +2tCYC tSCKH(2) +(25/3)tCYC tCYC tSCKH(2) +2tCYC tSCKH(2) +(10/3)tCYC tSCKH(2) tSCK(2) tSCKL(2) SCK0(P12) CMOS output selected. Fig. tSCK tCYC tSCKH(1) Symbol tSCK(1) tSCKL(1) Pins/ Remarks SCK0(P12) Conditions VDD[V] Fig. Specification unit
Note 4-1-1: These specifications theoretical values. margin depending use. Note 4-1-2: serial-clock-input continuous trans/rec mode, time from SI0RUN being when serial clock first negative edge serial clock must longer than tSCKHA.
Continued next page.
No.A0432-16/32
LC87F06J2A
Continued from preceding page.
Parameter Output delay Input clock time tdDO(2) Symbol tdDO(1) Pins/ Remarks SO0(P10), SB0(P11) Conditions VDD[V] Continuous data transmission/reception mode (Note 4-1-3) Synchronous 8-bit mode. (Note 4-1-3) Output clock tdDO(3) (Note 4-1-3) (1/3)tCYC +0.05 Specification (1/3)tCYC +0.05 1tCYC +0.05 unit
Note 4-1-3: Must specified with respect falling edge SIOCLK. Must specified time beginning output state change open drain output mode. Fig. SIO1 Serial Characteristics (Note 4-2-1)
Parameter Frequency Input clock level pulse width High level pulse width Frequency Output clock level pulse width High level pulse width Data setup time Serial input tsDI(2) SI1(P14), SB1(P14) Data hold time thDI(2) Must specified with respect rising edge SIOCLK fig. 0.03 Output delay time Serial output tdDO(4) SO1(P13), SB1(P14) Must specified with respect falling edge SIOCLK Must specified time beginning output state change open drain output mode. Fig. (1/3)tCYC +0.05 0.03 tSCKH(4) tSCK(4) tSCKL(4) SCK1(P15) CMOS output selected. Fig. tSCKH(3) Symbol tSCK(3) tSCKL(3) Pins/ Remarks SCK1(P15) Conditions VDD[V] Fig. tCYC tSCK Specification
Note 4-2-1: These specifications theoretical values. margin depending use.
Serial clock
Serial output
No.A0432-17/32
LC87F06J2A
SIO2 Serial Characteristics (Note 4-3-1)
Parameter Frequency level pulse width High level Pulse width tSCKHA(5a) Continuous data transmission/reception mode SIO0 simultaneous. Input clock Universal remote control transmitter simultaneous. Fig. (Note 4-3-2) tSCKHA(5b) Continuous data transmission/reception mode SIO0 simultaneous. Universal remote control transmitter simultaneous. Serial clock Fig. (Note 4-3-2) Frequency level pulse width High level pulse width tSCKH(6) tSCKHA(6a) tSCK(6) tSCKL(6) SCK2 (SI2P2), SCK2O (SI2P3) Continuous data transmission/reception mode SIO0 simultaneous. Universal remote control Output clock transmitter simultaneous. CMOS output selected. Fig. tSCKHA(6b) Continuous data transmission/reception mode SIO0 simultaneous. Universal remote control transmitter simultaneous. CMOS output elected. Fig. Data setup time Serial input tsDI(3) SI2(SI2P1), SB2(SI2P1) Data hold time thDI(3) Must specified with respect rising edge SIOCLK fig. 0.03 Output delay time Serial output tdDO(5) SO2(SI2P0) SB2(SI2P1) Must specified with respect falling edge SIOCLK Must specified time beginning output state change open drain output mode. Fig. (1/3)tCYC +0.05 0.03 tSCKH(6) +(5/3) tCYC tSCKH(6) +(28/3) tCYC tCYC tSCKH(6) +(5/3) tCYC tSCKH(6) +(10/3) tCYC CMOS output selected. Fig. tSCK 2.7to tCYC tSCKH(5) Symbol tSCK(5) tSCKL(5) Pins/ Remarks SCK2 (SI2P2) Conditions VDD[V] Fig. Specification unit
Note 4-3-1: These specifications theoretical values. margin depending use. Note 4-3-2: serial-clock-input time from SI2RUN being when serial clock first negative edge serial clock must longer than tSCKHA.
No.A0432-18/32
LC87F06J2A
SIO7, SIO8 Serial Characteristics (Note 4-4-1)
Parameter Frequency Input clock level pulse width High level pulse width Frequency Output clock level pulse width High level pulse width tSCKHA(8) Data setup time Serial input tsDI(4) SI7(PA1), SB7(PA1), SI8(PA4), Data hold time thDI(4) SB8(PA4) Must specified with respect rising edge SIOCLK fig. 0.03 Output delay Input clock time tdDO(6) SO7(PA0), SB7(PA1), SO8(PA3), SB8(PA4) tdDO(7) Must specified with respect falling edge SIOCLK Must specified time beginning output state change open drain output Output clock mode. Fig. (1/3)tCYC +0.05 1tCYC +0.05 0.03 tSCKH(8) tSCK(8) tSCKL(8) tSCK SCK7(PA2), SCK8(PA5) CMOS output selected. Fig. tSCKH(7) Symbol tSCK(7) tSCKL(7) Pins/ Remarks SCK7(PA2), SCK8(PA5) Conditions VDD[V] Fig. (Note 4-4-2) tCYC Specification
Note 4-4-1: These specifications theoretical values. margin depending use. Note 4-4-2: When starting transmission/reception SIO7(SIO8) using serial-clock-input, time from SI7RUN(SI8RUN) being when serial clock first negative edge serial clock must longer than 1tCYC.
Serial output
Serial clock
No.A0432-19/32
LC87F06J2A
Pulse Input Conditions -20°C +70°C, VSS1 VSS2 VSS3 VSS4 VSSVCO
Parameter High/low level pulse width Symbol tPIH(1) tPIL(1) Pins/Remarks INT0(P70), INT1(P71), INT2(P72) INT4(P20 P23), INT5(P24 P27), INT6(P20), INT7(P24) tPIH(2) tPIL(2) tPIH(3) tPIL(3) INT3(P73) when noise filter time constant 1/1. INT3(P73) (The noise rejection clock selected 1/32.) tPIH(4) tPIL(4) INT3(P73) (The noise rejection clock selected 1/128.) tPIH(5) tPIL(5) tPIL(6) HCTR(P22) CSYNC(PB6) Count clock inputs H-counter enabled. Reset acceptable Interrupt source flag set. Event inputs timer enabled. Interrupt source flag set. Event inputs timer enabled. Interrupt source flag set. Event inputs timer enabled. tCYC Conditions VDD[V] Interrupt source flag set. Event inputs timer enabled. Specification unit
Converter Characteristics -20°C +70°C, VSS1 VSS2 VSS3 VSS4 VSSVCO
Parameter Resolution Absolute precision Conversion time TCAD Symbol Pins/Remarks AN0(P80) AN7(P87), AN8(PC1), AN9(PC2), AN10(PC3), AN11(PC4), AN12(PE0), AN13(PE1), AN14(PE2), AN15(PE3) conversion time=64 tCYC (when ADCR2=1) Analog input voltage range Analog port input current IAINH IAINL VAIN=VDD VAIN=VSS VAIN (Note 6-2) conversion time=32 tCYC (when ADCR2=0) (Note 6-2) (Note 6-1) Conditions VDD[V] 12.54 (tCYC= 0.396µs) 47.04 (tCYC= 1.47µs) 12.54 (tCYC= 0.198µs) Specification ±1.5 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 3.06µs) 97.92 (tCYC= 1.53µs) unit
Note 6-1: quantization error (±1/2 LSB) excluded from absolute accuracy value. Note 6-2: conversion time refers interval from time instruction starting converter issued till complete digital value corresponding analog input value loaded required register.
No.A0432-20/32
LC87F06J2A
Consumption Current Characteristics -20°C +70°C, VSS1 VSS2 VSS3 VSS4 VSSVCO
Parameter Normal mode consumption current (Note 7-1) Symbol IDDOP(1) Pins/ Remarks VDD1 =VDD2 =VDD3 =VDD4 =VDDODA =VDDVCO Conditions VDD[V] FmCF=15MHz ceramic oscillation mode FsX'tal=32.768kHz crystal oscillation mode System clock 15MHz side Internal oscillation stopped frequency variable oscillation stopped frequency division ratio. Slicer running. Slicer oscillation running. Data Slicer running. IDDOP(2) FmCF=15MHz ceramic oscillation mode FsX'tal=32.768kHz crystal oscillation mode System clock 15MHz side Internal oscillation stopped frequency variable oscillation stopped frequency division ratio. IDDOP(3) FmCF=0Hz(oscillation stopped) FsX'tal=32.768kHz crystal oscillation mode IDDOP(4) System clock internal oscillation frequency variable oscillation stopped frequency division ratio. IDDOP(5) FmCF=0Hz(oscillation stopped) FsX'tal=32.768kHz crystal oscillation mode. IDDOP(6) System clock 1MHz with frequency variable oscillation Internal oscillation stopped frequency division ratio. IDDOP(7) FmCF=0Hz(oscillation stopped) FsX'tal=32.768kHz crystal oscillation mode. IDDOP(8) System clock 32.768kHz side. Internal oscillation stopped frequency variable oscillation stopped frequency division ratio. 4.75 5.25 Specification unit
Note 7-1: consumption current value includes none currents that flow into output internal pull-up resistors
Continued next page.
No.A0432-21/32
LC87F06J2A
Continued from preceding page.
Parameter HALT mode consumption current (Note 7-1) Symbol IDDHALT(1) Pins/ Remarks VDD1 =VDD2 =VDD3 =VDD4 =VDDVCO =VDDODA HALT mode FmCF=15MHz ceramic oscillation mode FsX'tal=32.768kHz crystal oscillation mode System clock 15MHz side Internal oscillation stopped frequency variable oscillation stopped frequency division ratio. IDDHALT(2) HALT mode FmCF=0Hz(oscillation stopped) FsX'tal=32.768kHz crystal IDDHALT(3) oscillation mode System clock internal oscillation frequency variable oscillation stopped frequency division ratio. IDDHALT(4) HALT mode FmCF=0Hz(oscillation stopped) FsX'tal=32.768kHz crystal oscillation mode. IDDHALT(5) System clock 1MHz with frequency variable oscillation Internal oscillation stopped frequency division ratio. IDDHALT(6) HALT mode FmCF=0Hz(oscillation stopped) FsX'tal=32.768kHz crystal oscillation mode. IDDHALT(7) System clock 32.768kHz side. Internal oscillation stopped frequency variable oscillation stopped frequency division ratio. Current drain during HOLD mode Current drain during timebase clock HOLD mode IDDHOLD(4) IDDHOLD(2) IDDHOLD(3) VDD1 IDDHOLD(1) VDD1 HOLD mode CF1=VDD open (External clock mode) Timer HOLD mode CF1=VDD open (External clock mode) FsX'tal=32.768kHz crystal oscillation mode 0.02 0.085 Conditions VDD[V] Specification unit
Note 7-1: consumption current value includes none currents that flow into output internal pull-up resistors
F-ROM Write Characteristics +10°C +55°C, VSS1 VSS2 VSS3 VSS4 VSSVCO
Parameter Onboard programming current Programming time tFW(1) 128-byte programming Erasing current including Time setting byte data excluded. Symbol IDDFW(1) Pins/ Remarks VDD1 Conditions VDD[V] 128-byte programming Erasing current including Specification unit
No.A0432-22/32
LC87F06J2A
UART(Full Duplex) Operating Conditions -20°C +70°C, VSS1 VSS2 VSS3 VSS4 VSSVCO
Parameter Clock rate Symbol UBR,UBR2 Pins/Remarks UTX1(P32), URX1(P33), UTX2(P34), URX2(P35) 16/3 8192/3 tCYC Conditions VDD[V] Specification unit
Data length: 7,8,and bits (LSB first) Stop bits: (2-bit continuous data transmission) Parity bits: Example Continuous 8-bit Data Transmission Mode Processing (First Transmit Data 55H)
Start Start transmission Transmit data (LSB first) Stop transmission
UBR, UBR2
Example Continuous 8-bit Data Reception Mode Processing (First Receive Data 55H)
Stop Received data (LSB first) reception
Start Start reception
UBR, UBR2
No.A0432-23/32
LC87F06J2A
Automatic transmission output characteristics -20°C +70°C, VSS1 VSS2 VSS3 VSS4 VSSVCO
Parameter Frequency level pulse width tSCKLA(9) High level pulse width tSCKHA(9) tBLKSEP(9a) fig. Transfer continuous data blocks (Note10-1) tBLKSEP(9b) fig. Transfer continuous data blocks with skipping S-number data blocks (Note10-1) Frequency Output clock level pulse width High level pulse width Output delay Serial output time tSCK(10) tSCKL(10) tSCKLA(10) tSCKH(10) tSCKHA(10) tdDO(8) SB7(PA1) Must specified with respect falling edge SIOCLK Must specified time beginning output state change open drain output mode. fig. 1tCYC +0.05 SCK7(PA2), CMOS output selected fig. (Note10-1) 26/3 tSCK (2/3) tSCKH(9) Symbol tSCK(9) tSCKL(9) Pins/ Remarks SCK7(PA2), fig. (Note10-1) Conditions VDD[V] tCYC Specification unit
Note10-1: When starting transmission, time from ECST begin when serial clock first negative edge serial clock must longer than following. (2/3) tCYC Skipping number data block when starting transmission.
Serial clock
Input clock
No.A0432-24/32
LC87F06J2A
VDD1, VSS1 Terminal condition
necessary place capacitors between VDD1 VSS1 describe below. Place capacitors close VDD1 VSS1 possible. Place capacitors that length each terminal each capacitor equal L1', L2'). Place high capacitance capacitor capacitance capacitor parallel. Capacitance must more than 0.05µF. thicker pattern VDD1 VSS1.
VSS1
VDD1
VDDVCO, VSSVCO Terminal condition
necessary place capacitors between VDDVCO VSSVCO describe below. Place capacitors close VDDVCO VSSVCO possible. Place capacitors that length each terminal each capacitor equal L3', L4'). Place high capacitance capacitor capacitance capacitor parallel. Capacitance must more than 0.05µF. thicker pattern VDDVCO VSSVCO.
VSSVCO
VDDVCO
No.A0432-25/32
LC87F06J2A
Characteristics Sample Main System Clock Oscillation Circuit
Given below characteristics sample main system clock oscillation circuit that measured using SANYO-designated oscillation characteristics evaluation board external components with circuit constant values with which oscillator vendor confirmed normal stable oscillation Table Characteristics Sample Main System Clock Oscillator Circuit with Ceramic Oscillator
Nominal Frequency Vendor Name Circuit Constant Oscillator Name [pF] 15MHz MURATA CSTCE15M0V53-R0 (15) [pF] (15) Operating Voltage Range Oscillation Stabilization Time [ms] [ms] Internal SMD-type Remarks
oscillation stabilization time refers time interval that required oscillation stabilized follwing cases (see Figure time interval that required oscillation stabilized after goes above operating voltage lower limit. time interval that required oscillation stabilized after instruction starting mainclock oscillation circuit executed. time interval that required oscillation stabilized after HOLD mode reset ocsillation started. time interval that required oscillation stabilized after X'tal Hold mode, under state which CFSTOP (bit register) reset ocsillation started.
Characteristics Sample Subsystem Clock Oscillator Circuit
Given below characteristics sample subsystem clock oscillation circuit that measured using SANYOdesignated oscillation characteristics evaluation board external components with circuit constant values with which oscillator vendor confirmed normal stable oscillation. Table Characteristics Sample Subsystem Clock Oscillator Circuit with Crystal Oscillator
Nominal Frequency Vendor Name Oscillator Name [pF] 32.768kHz EPSON TOYOCOM MC-306 Circuit Constant [pF] OPEN 560k Operating Voltage Range Oscillation Stabilization Time Applicable value 12.5pF SMD-type Remarks
oscillation stabilization time refers time interval that required oscillation stabilized follwing cases (see Figure time interval that required oscillation stabilized after goes above operating voltage lower limit. time interval that required oscillation stabilized after instruction starting subclock oscillation circuit executed. time interval that required oscillation stabilized after Hold mode, under state which EXTOSC (bit register) reset ocsillation started. time interval that required oscillation stabilized after Hold mode, under state which DMSRUN (bit DMSCNT register) reset ocsillation started.
No.A0432-26/32
LC87F06J2A
Note: components that involved oscillation should placed close another possible because they vulnerable influences circuit pattern.
X'tal
Figure Ceramic Oscillation Circuit
Figure Crystal Oscillation Circuit
0.5VDD
Figure Timing Point
No.A0432-27/32
LC87F06J2A
Power Supply limit Reset time
Internal Resonator tmsCF
CF1, tmsX'tal
XT1,
Operating mode
Unfixed
Reset
Instruction execution mode
Reset Time Oscillation Stabilization Time
HOLD release signal
HOLD release signal VALID
Internal Resonator tmsCF
CF1, tmsX'tal
XT1,
Operation mode
HOLD
HALT
HOLD Reset Signal Oscillation Stabilization Time
Figure Oscillation Stabilization Time
No.A0432-28/32
LC87F06J2A
RRES
CRES
Note Select CRES RRES value assure that least 200µs reset time generated after becomes higher than minimum operating voltage.
Figure Reset Circuit
SIOCLK:
DATAIN:
DATAOUT:
Data transmission period (only SIO0,2) Continuous trans/rec interval (only SIO7,8)
tSCK tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKH
Data transmission period (only SIO0,2) Continuous trans/rec interval (only SIO7,8) tSCKL SIOCLK: tsDI DATAIN: tdDO DATAOUT: thDI tSCKHA
Figure Serial Waveforms
tPIL
tPIH
Figure Pulse Input Timing Condition
No.A0432-29/32
LC87F06J2A
SIOCLK:
DATAOUT:
tSCK tSCKL SIOCLK: tdDO DATAOUT: tSCKH
tSCKLA SIOCLK: tdDO DATAOUT:
tSCKHA
SIOCLK:
DATAOUT:
Transmission interval over blocks
tSCKLA SIOCLK: tdDO DATAOUT:
tBLKSEP
Figure Automatic Transmission Output Waveforms
No.A0432-30/32
LC87F06J2A
Table Cfcvd constants
Cfcvd VPS/PDC/PAL-WSS Antiope EPG-J VBID XDS-1X XDS-2X 820pF OPEN
Composite Video Signal
C-Video Video Buffer PB6/CVD/CSYNC
Cfcvd
Figure Recommended Circuit
PB4/FILTSLC 2.2µF VSSVCO Cfs=OPEN
Figure Recommended FILTSLC Circuit
No.A0432-31/32
LC87F06J2A
SANYO Semiconductor Co.,Ltd. assumes responsibility equipment failures that result from using products values that exceed, even momentarily, rated values (such maximum ratings, operating condition ranges, other parameters) listed products specifications SANYO Semiconductor Co.,Ltd. products described contained herein. SANYO Semiconductor Co.,Ltd. strives supply high-quality high-reliability products, however, semiconductor products fail malfunction with some probability. possible that these probabilistic failures malfunction could give rise accidents events that could endanger human lives, trouble that could give rise smoke fire, accidents that could cause damage other property. When designing equipment, adopt safety measures that these kinds accidents events cannot occur. Such measures include limited protective circuits error prevention circuits safe design, redundant design, structural design. event that SANYO Semiconductor Co.,Ltd. products described contained herein controlled under applicable local export control laws regulations, such products require export license from authorities concerned accordance with above law. part this publication reproduced transmitted form means, electronic mechanical, including photocopying recording, information storage retrieval system, otherwise, without prior written consent SANYO Semiconductor Co.,Ltd. information described contained herein subject change without notice product/technology improvement, etc. When designing equipment, refer "Delivery Specification" SANYO Semiconductor Co.,Ltd. product that intend use. Information (including circuit diagrams circuit parameters) herein example only; guaranteed volume production. Upon using technical information products described herein, neither warranty license shall granted with regard intellectual property rights other rights SANYO Semiconductor Co.,Ltd. third party. SANYO Semiconductor Co.,Ltd. shall liable claim suits with regard third party's intellctual property rights which resulted from technical information products mentioned above.
This catalog provides information January, 2007. Specifications information herein subject change without notice.
No.A0432-32/32

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