Channel ACPI Regulator with Step-Down DC/DC Controller RT9643 com

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Channel ACPI Regulator with Step-Down DC/DC Controller RT9643 com

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RT9643
Channel ACPI Regulator with Step-Down DC/DC Controller
RT9643 combo regulator which compliant ACPI specification desktop/motherboard power management system application. part features switch regulator memory VDDQ power; three linear regulators including 1.5Amp peak sourcing/sinking capability regulator VTT, 1.2V ultra-low-dropout linear controller chipset miscellaneous power, 3.3VSB power with 1.25Amp peak current capability; dual power control including 5VDL, 3.3VDL control system power. part totally feature sets power which compliant ACPI specification into single small footprint package VQFN-24L 5x5. part generally operated conform ACPI specification, state, there only VDDQ 3.3VSB regulators remain while ULDO regulators off. transition from external capacitor attached linear regulators control slew rates respectively avoid inrush current induced. Moreover, PGOOD signal raises high stage while regulators stable. stage there only 3.3VSB remain while other regulators powered down. VDDQ regulator voltage mode implementation with external compensation provide high load transient response. regulated follow VDDQ capable sourcing sinking 1.5A peak currents.
Features
Integrated Channels Power Regulator DC/DC Buck Regulator VDDQ (2.5V 1.8V) Linear Regulator Supports 1.5Amp Peak Sinking/ Sourcing Capability 1.2V Ultra-Low-Dropout Linear Controller GMCH Power 3.3VSB Linear Regulator Supports 1.25A Capability 5VDL Switch Control 3VDL Switch Control Conform ACPI Specification Support Power Management State 300kHz Fixed Frequency Switching RDS(ON) Current Sensing Optional Current Sense Resistor Precision Over-Current Detect Embedded Synchronous Boot-Strapped Diode Power Good Signal Indication Voltages Thermal Shutdown 24-Lead VQFN Package RoHS Compliant 100% Lead (Pb)-Free
Applications
VDDQ Voltage Generator with ACPI Support Desktop System Power Servers System Power
Ordering Information
RT9643 Package Type VQFN-24L (V-Type) Operating Temperature Range Free with Commercial Standard Green (Halogen Free with Commercial Standard)
Configurations
(TOP VIEW)
REF_IN COMP
1.2V_DRV 1.2V_FB 5VSB_DRV 5V_MAIN VTT_SNS VTT_OUT
ILIM
S3#I VCC_EN 3VSB_OUT PGOOD
Note Richtek Pb-free Green products RoHS compliant compatible with current requirements IPC/JEDEC J-STD-020. Suitable SnPb Pb-free soldering processes. 100% matte (Sn) plating. DS9643-03 August 2007
BOOT
UGATE
ISNS
VDDQ_IN
VQFN-24L www.richtek.com
PHASE
LGATE
RT9643
Typical Application Circuit
5V_MAIN
RT9643
DUAL 5VSB MAIN DUAL VDDQ 5VSB 5VSB_DRV VCC_EN 5V_MAIN UGATE
PHASE ISNS LGATE Exposed (25)
S3#I 3VSB_OUT
1.2V_FB 1.2V_DRV
BOOT COMP
Chip Enable
ILIM PGOOD
VDDQ_IN VTT_SNS REF_IN VTT_OUT
Operation
RT9643 provides functions: general purpose regulator, used generate VDDQ power memory. source-sink linear regulator capable sinking sourcing 1.5A peak(minimum). adjustable Drop controller which, conjunction with external N-Channel power MOSFET, provides programmable voltage output. normally provides 1.2V termination voltage. Generating DUAL voltage using external N-channel supply power from MAIN external P-Channel provide power from Standby (5VSB) 5.An internal which regulates DUAL" mode from VCC(VSB). this regulator capable 1.25A peak currents with current limit protection typ.). 100k pull resistor VOUT obtain output voltage. When output voltage arrive normal value power good will output voltage with delay time. When output voltage falling arrive normal value power good will turn with less than delay time. But, there exceptions. enable pull power good will turn quickly. second falling arrive value typ.) power good also will turn quickly.
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RT9643
Table While
State
S3#I
EN(S5#)
VCC_EN 5VSB_DRV
VDDQ
VTT_OUT
Dual
Dual +5VSB +5VMAIN
Start Sequencing provides power logic analog control functions regulator including After above UVLO, start-up sequence begins shown Figure
UVLO 5VSB 2.5V 1.5V 2.0V
Dual VDDQ VTT_OUT/
Figure After initial power-up, will ignore logic inputs time period (T3-T0) about
Dual regulation. 3.3V LDO' slew rate limited discharge slope CSS. MAIN come prior this time, DUAL node will already pre-charged through body diode (see Figure waits about 100s before initiating soft-start VDDQ allow time fully discharged. "SLEEP" state when low. only 3.3V will held While First time enter will start VDDQ only 5V_MAIN above UVLO threshold (5V_MAIN o.k.) S3#I high. After VDDQ stabilized (when above about 1.5V) which will allow 1.2V soft start. ensure that VDDQ output subjected large transient currents during transition, 1.2V slew rates limited slew rate until regulation. addition, regulator current limited. Dropping S3#I signal. When this occurs, VCC_EN goes low, 3.3V turns 1.2V turned off, discharged 5VSB_DRV pulls turn P-Channel DUAL switch.
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RT9643
system signals this transition raising S3#I signal. mode entered until 5V_MAIN o.k. Then following occurs VCC_EN releases pull high external resistor. 5VSB_DRV pulls high turn P-Channel switch. 3.3V turns off. 1.2V turned allowed charge most systems, power supply enabled when S3#I goes high. that point, 5V_MAIN MAIN will start rise. RT9643 waits until 5V_MAIN above 4.5V turn This cause about "bump" both DUAL 3.3V DUAL when turn since that point, 5V_MAIN MAIN their regulation value.
Dual 4.4V
5V_MAIN VCC_EN S3#I
Figure Transition DUAL) eliminate "bump" delay 5V_MAIN shown below. 5V_MAIN RT9643 does supply power only used monitor voltage level 5V_MAIN supply.
5V_MAIN RT9643 5V_MAIN from
Figure Adding Delay 5V_MAIN Another method eliminate potential this "bump" PWR_OK drive 5V_MAIN pin. Some systems cannot tolerate long delay PWR_OK (>100ms) assert, hence solution figure preferable. During transition, will pull 5VSB_DRV with 500nA current sink limit inrush MAIN below UVLO threshold. that time, Dual charged. limited gate drive controls inrush current through charges (Capacitance Dual). Depending current available from 5VSB, size omitted. IQ4(INRUSH) GD(Q4)
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RT9643
Table B.O.M Application Circuit
Component Description notes below notes below Capacitor 1uF, 10%, 16VDC, X7R, 0603 Capacitor 10nF, 10%, 50VDC, X7R, 0603 Capacitor 10nF, 10%, 16V, X7R, 0603 Capacitor 220pF, 10%, 50VDC, NPO, 0603 Capacitor 10nF, 10%, 50VDC, X7R, 0603 Capacitor 220nF,10%, 10VDC, X7R, 0603 Capacitor 100nF, 10%, 25VDC, X7R, 0603 Inductor 1.8uH, 3.24m?16 Amps Inductor 0.39uH, 2.8m, Amps MOSFET N-CH, 8.8m, 30V, 50A, D-PAK, FSID: FDD6296 MOSFET N-CH, 30V, 75A, D-PAK, FSID: FDD6606 MOSFET N-CH, 32m, 20V, 21A, D-PAK, FSID: FDD6530A MOSFET P-CH, 35m, -20V, -5.5A, SSOT-6, FSID DC602P Resistor 1.82k, 0805 Resistor 56k, 0805 Resistor 11.8k, 0805 Resistor 3.01k, 0603 Resistor 9.09k, 0603 Resistor 10k, 0805 Resistor 0805 RT9643 Cout C1,C12,C17 C2,C4 C10, Q3,Q5,Q6 R1,R2,R9,R10 WALSIN WALSIN WALSIN WALSIN Inter-Technical Inter-Technical Fairchild Fairchild Fairchild Fairchild Yageo RichTek Vendor
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RT9643
Function Block Diagram
S3#I VCC_EN 5VSB_DRV 5V_MAIN BOOT
VTT_SNS FB1.2
Gate Control
UGATE PHASE LGATE ISNS COMP
PGOOD
PGOOD
Soft-Start Control Circuit
1.2V_DRV 1.2V_FB
VDDQ_IN
Oscillator
VTT_OT
3VSB_OUT
ILIM
REF_IN
VTT_SNS
Functional Description
1.2V_DRV (Pin1) Gate drive 1.2V linear controller. will turned (low) state. 1.2V_FB (Pin2) Feedback 1.2V linear controller. applied 1.2V output regulation sense. voltage disabled pulling higher than 0.9V. 5VSB_DRV (Pin3) 5VSB Control Switch. applied drive external P-Channel MOSFET switch 5VDL power 5VSB stage. goes high 5V_Main (Pin4) main power. When this below 4.5V, transition from inhibited. UGATE (Pin9) High-Side Drive. High-side MOSFET driver output VDDQ PWM. Connect gate high-side MOSFET.
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VTT_SNS (Pin5) Remote sense VTT. applied remote sense output voltage VTT. VTT_OUT (Pin6) Output VTT. Regulator power output. VDDQ_IN (Pin7) Input external VDDQ. Input power VTT, implemented tracking VDDQ. BOOT (Pin8) Boot. applied VDDQ bootstrapped power embedded driver power.
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RT9643
PHASE (Pin10) Phase node VDDQ PWM. applied sense phase node VDDQ gates switch control. ISNS (Pin11) Current Sense input. Monitors voltage drop across low-side MOSFET external sense resistor over current control. LGATE (Pin12) Low-Side Drive. low-side MOSFET driver output. Connect gate low-side MOSFET. PGOOD (Pin13) Power Good Indication Signal. open-drain output signal that will pull outside ±10% range 0.9V reference outputs 110% reference. PGOOD goes when high. power good signal from regulator enables regulator controller. (Pin14) VCC. 5VSB generally applied bias power logics gate driver control. stays standby until this higher than 4.35V. 3VSB_OUT (Pin15) 3.3VSB Output. Internal linear regulator capable drive 1.25Amp peak current. power Turned state, stage. VCC_EN (Pin16) enable signal dual power. applied control power 3.3VDL 5VDL, signal open drain output which pulls gate NChannel blocking MOSFETs This goes high (open) S3#I (Pin17) Input. When LOW, 1.2V regulators turned 3.3VSB regulator turned the. PGOOD when S3#I LOW. REF_IN (Pin24) voltage setting. regulator tracks voltage pin, typically, should 1/2VDDQ (Pin23) VDDQ Feedback. output feedback VDDQ PWM. applied voltage regulation, PGOOD, under-voltage, over-voltage protection monitoring. COMP (Pin22) Compensation VDDQ PWM. Output error amplifier. Connect compensation network between this (Pin21) Soft Start. external capacitor attached control slew rate converter during initialization well sets initial slew rate controllers when transitioning from This charged/discharged with internal current source during initialization, charged with 50uA during soft-start. ILIM (Pin20) Current Limit setting pin. external resistor attached current limit value. [Pin19, Exposed (25)] GROUND. ground power whole chip. exposed must soldered large connected maximum power dissipation. (Pin18) Chip ENABLE. Typically tied S5#. When this low, operated standby mode, regulators VCC_EN low.
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RT9643
Absolute Maximum Ratings
(Note Supply Input Voltage, 6.5V PHASE Voltage UGATE Voltage VPHASE 0.3V VBOOT 0.3V LGATE Voltage 0.3V 0.3V BOOT VCC_EN BOOT PHASE 6.5V BOOT UGATE 6.5V UGATE PHASE 6.5V Input, Output Voltage 0.3V 0.3V Storage Temperature Range -65°C 150°C Lead Temperature (Soldering, sec.) 260°C Junction Temperature Range -20°C 125°C Power Dissipation, 25°C VQFN-24L 1.923W Package Thermal Resistance (Note VQFN-24L 5x5, 52°C/W Susceptibility (Note (Human Body Mode) (Machine Mode) 200V
Recommended Operating Conditions
(Note
Supply Voltage, Ambient Temperature Range -10°C 85°C
Electrical Characteristics
(Rocommended Operating Conditions, unless otherwise specification)
Parameter Converter
Symbol
Test Condition LGATE, UGATE open, 0.9, I(VTT) S3#I S3#I=LOW, I(3.3)< 10mA I(3.3) Rising
Units
-4.0 -4.3
4.05
-4.6
Current
IVCC
UVLO Threshold
Falling Hysteresis Rising
5V_MainUVLO Threshold
Falling Hysteresis
continued
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RT9643
Parameter Oscillator Frequency Ramp Amplitude pk-pk Ramp offset Reference Soft Start Internal Reference voltage Soft Start Current discharge resistance Converter Load Regulation Bias Current Under Voltage shutdown Isns over-current threshold Over voltage threshold Output Driver UGATE Output Resistance LGATE Output Resistance Sourcing Sinking Sourcing Sinking -1.8 noise filter RILIM IOUT from 0.75 1.25 Initial ramp after power-up During PWM/LOD soft start 0.891 -0.900 0.909 FOSC -300 -kHz Symbol Test Condition Units
PGOOD (Power good Output) control pins, VDDQ output Lower threshold Upper threshold PGOOD Output Leakage Current Regulator VDDQ Current VREF Differential Output Voltage Internal Divider Gain Current Limit Leakage Current input resistance PGOOD Drop-Out Voltage mode, IVTT IVTT 25°C IVTT ±1.25A (pulsed) EN=0 Pulse(300ms MAX), 25°C S3#I 0.9V Measured ±1.5A 0.493 ±1.5 -0.8 -0.498 -110 0.503 -110 noise filter noise filter IPGOOD Pull
continued
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RT9643
Parameter 1.2V Regulation Drop-Out Voltage External Gate Drive Gate Drive Source Current Gate Drive Sink Current 1.2V PGOOD Threshold 3.3V Regulation Drop-Out Voltage Control Function S3#I, input threshold S3#I, input Current Over-Temperature Shutdown Over-Temperature Hysteresis VCC_EN Output RDS(ON) VCC_EN Output High Leakage 5VSB_DRV Output resistance 5VSB_DRV Sink Current 5VSB_DRVOutput High -VVCC_EN 5V_MAIN 5V_MAIN UVLO -1.25 -150 1.55 -300 -1200 I(3.3) from 1.25A, 4.75V I(3.3) 1.25A -3.3 -3.4 I(1.2) from I(1.2) RDS(ON) 4.75V 1.17 -1.2 -1.2 -1.23 -0.8 Symbol Test Condition Units
Note Stresses listed above "Absolute Maximum Ratings" cause permanent damage device. These stress ratings. Functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods remain possibility affect device reliability. Note Devices sensitive. Handling precaution highly recommended. Note operating conditions beyond recommended range guaranteed. Note measured natural convection 25°C effective thermal conductivity test board (single-layer, JEDEC 51-3 thermal measurement standard.
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RT9643
Application Information
Regulator
RT9643 combines single-phase synchronous buck controller designed drive N-Channel MOSFETs. provides highly accurate, programmable output voltage precisely regulated voltage requirement with internal 0.9V reference. Setting output voltage output voltage regulator range 0.9V power input external resistor divider. internal reference 0.9V. output divided down external voltage divider (for example, Typical Application Circuit). There also precision (±5%) current sourced ensure that open, VDDQ will remain low. output voltage therefore 0.9V VOUT 0.9V minimize noise pickup this node, keep resistor (R2) below selected 1.82k solved
ILIM det.
source. output voltage starts when VCSS larger than 0.4V. prevent large duty cycles high currents during beginning soft-start, Once charged 1.3V, output voltage will regulation. time takes reach 1.3V T1.3 where T1.3 regulator' latched faults enabled until charges 1.5V. When reaches 2.5V, 1.2V will begin their soft-start ramps. After 1.2V regulators regulation, PGOOD then allowed HIGH (open). UVLO will discharge reset Current Sensing Section
ISNS RSENSE Current Sense 2.5V ILIM ILIM Mirror 0.9V ILIM RILIM PGND
(VOUT 0.9) 1.816k 1.82k
Figure Current Sense Limit following discussion refers Figure current through RSENSE resistor (ISNS) sensed shortly after side MOSFET turned Setting Current Limit ISNS compared current established when internal reference drives ILIM pin. RILIM, RDS(ON) RSENSE determine current limit
synchronous buck converter optimized operation. Oscillator internal oscillator frequency 300kHz. internal ramp reset rising clock edge. Soft Start When regulator enabled circuit will wait until VDDQ_IN below 100mV ensure that soft-start cycle does begin with large residual voltage regulator output. When regulator disabled, turned from VDDQ_IN PGND discharge output. voltage positive input error amplifier limited VCSS which charged with current
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RILIM
RSENSE ILIMIT RDS(ON)
Where ILIMIT peak inductor current. Since tolerance current limit largely dependent ratio external resistors fairly accurate voltage drop Switching Node side RSENSE accurate representation load current.
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RT9643
When using MOSFET sensing element, variation RDS(ON) causes proportional variation ISNS. This value only varies from device device, also typical junction temperature coefficient about 0.4%/°C (consult MOSFET datasheet actual values), actual current limit point will decrease proportional increasing MOSFET temperature. factor current limit point should compensate MOSFET DS(ON) variations, assuming MOSFET' heat sinking will keep operating temperature below 125°C. Current limit (ILIMIT) should sufficiently high allow inductor current rise response output load transient. Typically, factor sufficient. addition, since ILIMIT peak current cut-off value, will need multiply ILOAD(MAX) inductor ripple current (20% chosen). ILIMIT ILOAD(MAX)
Frequency Loop Compensation loop compensated using feedback network around error amplifier, which voltage output Amp. Figure shows complete type3 compensation network. type2 compensation configuration eliminates shown typical application circuit. Type2 compensation used most applications. critical applications that require wide loop-bandwidth, very output capacitors, type3 compensation required.
COMP
VOUT
Gate Driver Section adaptive gate control logic translates internal control signal into MOSFET gate drive signals providing necessary amplification, level shifting shoot-through protection. Also, functions that help optimize performance over wide range operating conditions. Since MOSFET switching time vary dramatically from type type with input voltage, gate control logic provides adaptive dead time monitoring gate source voltages both upper lower MOSFETs. lower MOSFET drive turned until PHASE decreased less than approximately (~0.6volt). Similarly, upper MOSFET turned until gate-to-source voltage lower MOSFET decreased less than approximately (~0.6 volt). This allows wide variety upper lower MOSFETs used without concern simultaneous conduction, shoot-through. There must low-resistance, low-inductance path between driver MOSFET gate adaptive dead-time circuit work properly. delay along that path will subtract from delay generated adaptive dead-time circuit shoot-through occur. Figure Compensation Network PGOOD Signal PGOOD monitors status output well 1.2V regulators. PGOOD remains unless conditions below S3#I HIGH above Fault latch cleared between 110% VREF 1.2V regulators regulation Protection converter output monitored protected against extreme overload, short circuit, over-voltage undervoltage conditions. internal "Fault Latch" fault intended shut down When "Fault Latch" set, will discharge VDDQ_IN driving GATE high until VDDQ_IN 0.5V. LGATE will then until VDDQ_IN 0.8V. This behavior will discharge output without causing undershoot (negative output voltage).
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RT9643
discharge output capacitors, load resistor switched from VDDQ_IN PGND whenever fault condition, when low. After latched fault, operation restored recycling power toggling pin. Under-Voltage Shutdown stays below under-voltage threshold "Fault latch" set. This fault prevented from setting fault latch during soft-start 1.5V). Over-Current Sensing circuit' current limit signal ("ILIM det" shown Figure high beginning clock cycle, pulse skipping circuit activated UGATE inhibited. circuit continues pulse skip this manner next clock cycles. time from 16th clock cycle, "ILIM det" again reached, fault latch set. "ILIM det" does occur between cycle normal operation restored over-current circuit resets itself. This fault prevented from setting fault latch during soft-start 1.5V). VDDQ_IN (PWM output voltage) 100mV these faults will fault latch. These faults fault latch during time 1.5V). ensure that open will cause destructive condition, current source ensures that will high open. This will cause regulator keep output low, eventually result Under-voltage fault shutdown (after complete). Over-Temperature Protection RT9643 incorporates internal over temperature circuit designed protect device during overload conditions. junction temperature reaches nominal temperature 150°C, over temperature circuit will shut chip. Normal operation restored when temperature falls below 125°C with internal Power Reset asserted, resulting full soft-start cycle. accomplish this, over temperature comparator should discharge pin. Regulator regulator simple high-speed linear regulator designed generate termination voltage double data rate (DDR) memory system. regulator capable actively sinking sourcing 1.25A while regulating output voltage within 40mV. output termination voltage tightly regulated track 1/2VDDQ_IN internal voltage divider resistors (50k each resistor) external voltage divider resistors from output regulator. regulator also incorporates high-speed differential amplifier provide ultra-fast response line/ load transient. Other features include extremely initial offset voltage, excellent load regulation, current limiting bi-directions. regulator enabled when S3#I HIGH regulator's internal PGOOD signal true. regulator also includes PGOOD signal which high when VTT_SNS REF_IN. Controller controller combined with external N-Channel MOSFET pass element used provide 1.2V
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PGOOD (5V/Div)
(10A/Div)
UGATE (10V/Div) LGATE (5V/Div)
Time (10s/Div)
Figure Over Current Protection Waveform Fault short detection: Fault detected when there more than 0.5V from PHASE PGND 350ns after LGATE reaches (same time current sampling time). Fault Detection occurs 115% VREF clock cycles. During soft-start, output voltage could potentially "run away" either shorted open. This fault will detected following condition persists more than during soft-start.
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RT9643
Front-side termination. driving voltage gate drive pull within 0.5V VCC. MOSFET assure RDS(ON) small enough full load operation. soft start accomplished clamping input voltage smooth up-going ramp. final input reference voltage after soft start 0.9V. Component Selection Components should appropriately selected ensure stable operation, fast transient response, high efficiency, minimum cost maximum reliability. Output Inductor Selection selection output inductor based considerations efficiency, output power operating frequency. synchronous buck converter, ripple current inductor (IL) calculated follows (VIN VOUT) VOUT fOSC current from input capacitor during time upper MOSFET. value ripple current flowing through input capacitor described
IIN(RMS) IOUT
input bulk capacitor must cable handling this ripple current. Sometime, higher efficiency capacitor necessarily. Appropriate high frequency ceramic capacitors physically near MOSFETs effectively reduce switching voltage spikes. MOSFET Selection selection MOSFETs based upon considerations RDS(ON), gate driving requirements, thermal management requirements. power loss upper MOSFET consists conduction loss switching loss expressed PUPPER PCOND _UPPER PSW_UPPER IOUT RDS(ON) IOUT (TRISE TFALL fOSC
Generally, inductor that limits ripple current between output current appropriate. Make sure that output inductor could handle maximum output current would saturate over operation temperature range. Output Capacitor Selection output capacitors determine output ripple voltage (VOUT) initial voltage drop after high slew-rate load transient. selection output capacitor depends output ripple requirement. output ripple voltage described follows VOUT VOUT fOSC electrolytic capacitor application, typically 90~95% output voltage ripple contributed output capacitors. Paralleling lower ceramic capacitor with bulk capacitors could dramatically reduce equivalent consequently ripple voltage. Input Capacitor Selection mixed types input bypass capacitors control input voltage ripple switching voltage spike across MOSFETs. buck converter draws pulsewise
where TRISE TFALL rising falling time upper MOSFET respectively. RDS(ON) should simultaneously considered minimize power loss upper MOSFET. power loss lower MOSFET consists conduction loss, reverse recovery loss body diode, conduction loss body diode express
PLOWER PCOND _LOWER PDIODE IOUT RDS(ON) fOSC IOUT TDIODE fOSC
where TDIODE conducting time lower body diode. Special control scheme adopted minimize body diode conducting time. result, RDS(ON) loss dominates power loss lower MOSFET. MOSFET with adequate RDS(ON) minimize power loss satisfy thermal requirements. Bypass Capacitor Notes Input capacitor typically chosen based ripple current requirements. COUT typically selected based both current ripple rating requirement.
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RT9643
selection will largely determined load transient response requirements. Layout Considerations MOSFETs switch very fast efficiently. speed with which current transitions from device another causes voltage spikes across interconnecting impedances parasitic circuit elements. voltage spikes degrade efficiency radiate noise, that results over-voltage stress devices. Careful component placement layout printed circuit design minimize voltage spikes induced converter. Consider, example, turn-off transition upper MOSFET prior turn-off, upper MOSFET carrying full load current. During turn-off, current stops flowing upper MOSFET picked side MOSFET schottky diode. inductance switched current path generates large voltage spike during switching interval. Careful component selections, layout critical components, shorter wider traces help minimizing magnitude voltage spikes. There sets critical components DC-DC converter using RT9643. switching power components most critical because they switch large amounts energy, such, they tend generate equally large amounts noise. critical small signal components those connected sensitive nodes those supplying critical bypass current. power components controller should placed firstly. Place input capacitors, especially high-frequency ceramic decoupling capacitors, close power switches. Place output inductor output capacitors between MOSFETs load. Also locate controller near MOSFETs. multi-layer printed circuit board recommended. Figure shows connections critical components converter. Note that capacitors COUT each them represents numerous physical capacitors. dedicated grounding plane vias ground critical components this layer. Apply another solid layer power plane this plane into smaller islands common voltage levels. power plane should support input power output power nodes. copper filled polygons bottom circuit layers PHASE node, necessary oversize this particular island. Since PHASE node subjected very high dV/dt voltages, stray capacitance formed between these island surrounding circuitry will tend couple switching noise. remaining printed circuit layers small signal routing. traces between controller gate MOSFET also traces connecting source MOSFETs should sized carry peak currents. Below gerber files test board your reference
Figure Component Side
Figure
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RT9643
Figure Power
Figure Bottom
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RT9643
Outline Dimension
DETAIL
DETAIL Mark Options Note configuration identifier optional, must located within zone indicated.
Symbol
Dimensions Millimeters 0.800 0.000 0.175 0.250 4.950 3.100 4.950 3.100 0.650 0.350 0.450 1.000 0.050 0.250 0.350 5.050 3.400 5.050 3.400
Dimensions Inches 0.031 0.000 0.007 0.010 0.195 0.122 0.195 0.122 0.026 0.014 0.018 0.039 0.002 0.010 0.014 0.199 0.134 0.199 0.134
V-Type Package
Richtek Technology Corporation
Headquarter Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
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Channel ACPI Regulator with Step-Down DC/DC Controller RT9643 com

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