Triple Linear Regulator Controller Support ACPI Control Interface

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Triple Linear Regulator Controller Support ACPI Control Interface

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RT9641A/B
Triple Linear Regulator Controller Support ACPI Control Interface
RT9641A/B, paired with either RT9230 RT9231 simplifies implementation ACPI-compliant designs microprocessor computer applications. integrates linear controllers low-current pass transistor, well monitoring control functions into 16-pin SOIC package. linear controller generates 3.3VDUAL voltage plane from power supply's 5VSB output during sleep states (S3,S4/S5), powering slots through external pass transistor, instructed status 3.3VDUAL enable pin. additional pass transistor used switch 3.3V output operation during (active) operating states. second linear controller supplies computer system's 2.5V/3.3V memory power through external pass transistor active states. During state, integrated pass transistor supplies 2.5V/ 3.3V sleep-state power. third controller powers 5VDUAL plane switching output active states, 5VSB sleep states. RT9641A/B's operating mode (active-state outputs sleep-state outputs) selectable through control pins: Further control logic governing activation different power modes offered through enabling pins: EN3VDL EN5VDL. active states, 3.3VDUAL linear regulator uses external N-channel pass MOSFET connect output (VOUT1) directly 3.3V input supplied equivalent) power supply, while incurring minimal losses. sleep state, 3.3VDUAL output supplied from 5VSB through transistor, also external controller. Active state power delivery 2.5V/3.3V 2.6V/3.43V VMEM output done through external NMOS transistor. sleep states, conduction this output transferred internal pass transistor. 5VDUAL output powered through external transistors. sleep states, PMOS PNP) transistor conducts current from 5VSB output, while active states, current flow transferred NMOS transistor connected output. Similar 3.3VDUAL output, operation 5VDUAL output dictated only status pins, that EN5VDL well.
DS9641A/B-11 March 2007
Features
Provides ACPI-Controlled Voltages Active/Sleep(5VDUAL) 3.3V Active/Sleep(3.3VDUAL) 2.5V/3.3V Active/Sleep(VMEM) with RT9641A 2V/3.43V Active 2.5V/3.3V Sleep(VMEM) with RT9641B Simple Control Design Compensation Required Excellent Output Voltage Accuracy 3.3VDUALOutput 2.0% Sleep States Only 2.5V/3.3V (2.6V/3.43V) Output 2.0% Both Operational States Fixed Output Voltages Require Precision External Resistors Small Size Small External Component Count Selectable 2.5V/3.3V (2.6/3.43) V(MEM) Output Voltage FAULT/MSEL 2.5V/2.6V RDRAM Memory 3.3V/3.43V SDRAM Memory Under-Voltage Monitoring Outputs with Centralized FAULT Reporting Adjustable Soft-start Function Eliminates 5VSB Perturbations RoHS Compliant 100% Lead (Pb)-Free
Ordering Information
RT9641A/B Package Type SOP-16 Operating Temperature Range Free with Commercial Standard Green (Halogen Free with Commercial Standard) Voltage 2.5V/3.3V 2.6V/3.43V
Note RichTek Pb-free Green products RoHS compliant compatible with current requirements IPC/JEDEC J-STD-020. Suitable SnPb Pb-free soldering processes. 100%matte (Sn) plating. www.richtek.com
RT9641A/B
Configurations
(T0P VIEW)
5VSB EN3VDL 3V3DLSB 3V3DL EN5VDL VSEN2 DRV2 5VDL 5VDLSB FAULT/MSEL
SOP-16
Typical Application Circuit
+5VIN +12VIN +3.3VIN +5VSB 2SD1802 UF76113DK8 VOUT1 3.3VDUAL
10uF
470uF 220uF 5VSB
3V3DLSB DRV2 RT9641A/B 3V3DL VSEN2 FAULT/MSEL 5VDLSB EN5VDL EN3VDL 5VDL 2X150uF HUF7613DK8 180k VOUT3 5VDUAL
2SD1802
2X150uF
VOUT2 3.3/3.43VMEM VOUT2 2.5VMEM MMBT2907A
200uF
EN5VDL EN3VDL SHUTDOWN (From Open-drain N-MOS) 0.1uF
150uF
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DS9641A/B-11 March 2007
RT9641A/B
Function Block Diagram
3V3DLSB 3V3DL 5VSB
Bias Monitor 10.5V/9.5V
5VSB
FAULT/MSEL
Detector
5VDLSB Monitor Control Temperature Monitor (TMON) 1.265V DRV2
40uA
Voltage Select COMP 0.2V Enable 5VDLSB Mode Compartor 3.75V
Detector
VSEN2
5VDL
EN3VDL EN5VDL
Simplified Power System Diagram
5VIN 12VIN 5VSB 3.3VIN Linear Controller Linear Controller 3.3VDUAL FAULT RT9641A/B Control Logic DUAL SHUTDOWN EN5VLD EN3VDL VMEM
DS9641A/B-11 March 2007
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RT9641A/B
Absolute Maximum Ratings
Supply Voltage (V5VSB) -12V -DLA, DRV2 -All Other Pins -Package Thermal Resistance SOP-16, -Maximum Junction Temperature -Maximum Storage Temperature Range -Maximum Lead Temperature (Soldering, sec.) -+7.0V GND-0.3V +14.5V GND-0.3V V12V+0.3V GND-0.3V 5VSB+0.3V 100°C/W 150°C -65°C 150°C 260°C
Recommended Operating Conditions
Supply Voltage (V5VSB) -Secondary Bias Voltage (V12V) -Digital Inputs (VS3, VS5, VEN3VDL, VEN5VDL) -Junction Temperature Range -Ambient Temperature Range -CAUTION: Stresses beyond ratings specified "Absolute Maximum Ratings" cause permanent damage device. This stress only rating operation device these other conditions above those indicated operational sections this specification implied. +12V ±10% +5.5V 125°C 70°C
Electrical Characteristics
(VCC (12VIN) 12V, 25°C, unless otherwise specified)
Parameter Supply Current Operating Supply Current Shutdown Supply Current
Symbol
Test Conditions
Units
I5VSB
-VSS
I5VSB(OFF)
Power-on Reset, Soft-start, Monitor Rising 5VSB Threshold Rising Threshold Soft-start Current Shutdown Soft-start Voltage -2.5 10.5
continued
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DS9641A/B-11 March 2007
RT9641A/B
Parameter Symbol Test Conditions Units 2.5V/3.3V (2.6V/3.43V) Linear Regulator (VOUT2) Regulation VSEN2 Nominal Voltage Level VSEN2 Nominal Voltage Level VSEN2 Under-voltage Falling Threshold VSEN2 Under-voltage Hysteresis VSEN2 Output Current DRV2 Output Drive Current DRV2 Output Impedance 3.3V Dual Linear Regulator (VOUT1) Sleep-mode Regulation 3V3DL Nominal Voltage Level 3V3DL Under-voltage Falling Threshold 3V3DL Under-voltage Hysteresis 3V3DLSB Output Drive Current Output Impedance Dual Switch Controller (VOUT3) 5VDL Under-voltage Falling Threshold 5VDL Under-voltage Hysteresis 5VDLSB Output Drive Current Timing Intervals Active Sleep, Input Switching Delay Sleep Active, Input Switching Delay 0.1F
-VVSEN VVSEN2 RSEL RSEL -IVSEN2 IDRV2 5VSB 5VSB RSEL RSEL
-2.5/2.6 3.3/3.4
-V3V3DL -I3V3DLSB 5VSB
-3.3 2.24
3.40
I5VDLSB
5VDLSB
Control (S3, EN3VDL, EN5VDL, FAULT) High Level Threshold Level Threshold Internal Pull-up Impedance 5VSB FAULT Output Impedance Temperature Monitor Fault-level Threshold Shutdown-level Threshold
-FAULT high
-0.8
Note:
50ms with 0.1F Soft-start capacitor. delay time adjustable with 500xCSS (ms).
DS9641A/B-11 March 2007
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RT9641A/B
Functional Description
5VSB (Pin Provide bias supply this connecting 5VSB output. This also provides base bias current external transistors controlled voltage this monitored power-on reset (POR) purposes. EN3VDLand EN5VDL (Pin Pin5) These pins control logic governing output behavior response S4/S5 requests. These digital inputs whose status only changed during active states operation during chip shutdown grounded external open-drain device). input information latched-in when entering sleep state, well following 5VSB release exit from shutdown. 3V3DLSB (Pin Connect this base suitable transistor. sleep states, this transistor used regulate voltage 3V3DL 3.3V. 3V3DL (Pin Connect this 3.3V dual output (VOUT1). sleep states, voltage this regulated 3.3V; active states, 3.3V output delivered this node through fully N-MOS transistor. During operating states, this monitored under-voltage events. (Pin Pin7) These pins switch IC's operating state from active (S0, S4/S5 sleep states. Connect SLP_S3 SLP_S5. These digital inputs featuring internal 50k(typical) resistor pull-up 5VSB. Internal circuitry de-glitches disturbances. (Pin Signal ground voltage levels measured with respect this pin. FAULT/MSEL (Pin This multiplexed function allowing setting memory output voltage either 2.5V(2.6V) 3.3V(3.43V) (for RDRAM SDRAM memory systems). memory voltage setting latched-in when DRV2 (Pin 2.5V RDRAM systems, connect this base suitable transistor. This pass transistor regulates 2.5V(2.6V) output from 3.3V during active states operation. 3.3V SDRAM systems connect 5VDL (Pin Connect this through 180k resistor distinguishing state from S3/S5. (Pin Connect small ceramic capacitor (0.1F recommended) from this GND. internal Soft-start (SS) current source along with external capacitor creates voltage ramp used control ramp-up output voltages. Pulling this with open-drain device shuts down output well forces FAULT low. capacitor also used provide controlled S4/S5 active transition delay time. (Pin Connect this equivalent) output. This used monitor status power supply well provide bias NMOS-compatible output drivers. presence chip absence bias voltage, severe brownout during active states (S0, operation lead chip misbehavior. RT9641A/B refuses entering active state before power ready. voltage goes 0.8V (typically after POR). case under-voltage outputs over temperature event, this used report fault condition being pulled 5VSB. (Pin Connect this gates suitable N-MOSFETs, which active states, used switch 3.3V outputs into 3.3VDUAL 5VDUAL outputs, respectively. 5VDLSB (Pin Connect this gate suitable P-MOSFET bipolar PNP. sleep states, this transistor switched connecting 5VSB output 5VDUAL regulator output. When used, recommanded base resistor base current limiting.
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DS9641A/B-11 March 2007
RT9641A/B
this gate suitable N-MOS transistor base suitable transistor. VSEN2 (Pin Connect this memory output (VOUT2). sleep states, this regulated 2.5V(2.6V) 3.3V(3.43V) (based SEL) through internal pass transistor capable delivering 300mA (Typically). active-state voltage this regulated through external NMOS transistor connected DRV2 both 2.5V(2.6V) 3.3V(3.43V) setting. During operating states, voltage this monitored under-voltage events. Operational Truth Tables EN3VDL EN5VDL pins offer host choices terms overall system architecture supported features. Tables describe truth combinations pertaining each three outputs.
Table 3.3VDUAL Output (VOUT1) Truth Table
EN3VDL 3V3DL 3.3V 3.3V Note 3.3V 3.3V 3.3V Note Comments States (Active) Maintains Previous State S4/S5 States (Active) Maintains Previous State S4/S5
Application Information
Operation RT9641A/B controls output voltages. designed microprocessor computer applications with 3.3V, 5VSB, outputs from power supply. composed linear controllers supplying slots' 3.3VAUX power (3.3VDUAL, VOUT1) 2.5V RDRAM 3.3V SDRAM memory power (2.5V/3.3V (2.6V/3.43V) VMEM, VOUT2), dual switch controller supplying 5VDUAL voltage (VOUT3). addition, control monitoring functions necessary complete ACPI implementation integrated into RT9641A/B. Initialization RT9641A/B automatically initializes upon receipt input power. Power-On Reset (POR) function continually monitors 5VSB input supply voltage, initiating soft-start operation after exceeds threshold S4/S5 states). 5VSB trip event also used lock memory voltage setting based RSEL. RT9641A/B forces operation mode start from S4/S5 states releasing with 3.3VDUAL 5VDUAL voltages under control EN3VDL EN5VDL input signals.
Note: Combination allowed. seen Table EN3VDLsimply controls whether 3.3VDUAL plane remains powered during S4/S5 sleep state. Table 5VDUAL Output (VOUT3) Truth Table
EN5VDL 5VDL Note Note Comments States(Active) Maintains Previous State S4/S5 States(Active) Maintains Previous State S4/S5
Note: Combination allowed. Very similarly, Table details fact that EN5VDL status controls whether 5VDUAL plane supports sleeps states.
DS9641A/B-11 March 2007
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RT9641A/B
Table 2.5V/3.3V(2.6V/3.43V) VMEM Output (VOUT2) Truth Table
RSEL 2.5V/3.3V 2.5V/2.6V 2.5V Note Comments States(Active) Maintains Previous State S4/S5
Another condition that could FAULT flag chip over-temperature. RT9641A/B reaches internal temperature 145°C (typical), FAULT flag (FAULT/MSEL pulled high), chip continues operate until temperature reaches 155°C (typical), when unconditional shutdown outputs takes place. thermal shutdown released with re-soft-start when chip cools down. Shutdown case FAULT condition that might endanger computer system, other time, RT9641A/B shut down pulling below specified shutdown level (typically 0.8V) with open drain open collector device capable sinking minimum 2mA. Pulling effectively shuts down pass elements. Upon release pin, RT9641A/B undergoes soft-start cycle resumes normal operation accordance supply control pins status. Layout Considerations typical application employing RT9641A/B fairly straight-forward implementation. Similar other linear regulators, attention paid potentially sensitive small signal components, such those connected high-impedance nodes those supplying critical by-pass currents. power components (pass transistors) controller should placed first. controller should placed central position motherboard, closer memory load possible. Ensure VSEN2 connection properly sized carry 300mA without significant resistive losses. pass transistors should placed pads capable heatsinking, matching device's power dissipation. Where applicable, multiple corrections large internal plane significantly lower localized device temperature rise.
3.3V/3.43V States(Active) 3.3V Note Maintains Previous State S4/S5
Note: Combination allowed. seen Table 2.5V/3.3V(2.6V/3.43V) VMEM output maintained (Suspend-To-RAM), S4/S5 state. dual-voltage support accommodates both SDRAM well RDRAM type memories. Fault Protection outputs monitored against under-voltage events. serve over-current caused failed load outputs, would, turn, cause that specific output suddenly drop. output voltages drop below their value, such event reported having FAULT/MSEL pulled Additionally, 2.5V/ 3.3V(2.6V/3.43V) memory regulator internally current limited while sleep state. Exceeding maximum current rating this output sleep state lead output voltage drooping. excessive, this droop ultimately trip under-voltage detector send FAULT signal computer system. However, FAULT condition will only FAULT flag, will shut latch part circuit. shutdown latch circuit desired, this achieved externally pulling latching low. Pulling will also force FAULT low. Under-voltage sensing disabled disabled outputs during soft-start ramp-up intervals.
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DS9641A/B-11 March 2007
RT9641A/B
+12VIN +5VSB C12V 5VSB 5VDLSB 5VDL 3V3DLSB 3V3DL VSEN2 DRV2 C5VSB
CHF1 VOUT1 LOAD CBULK1 +3.3VIN
VOUT3 CBULK2 VOUT2 CHF2 LOAD CHF3 LOAD
solid layer power plane break this plane into smaller islands common voltage levels. Ideally, power plane should support both input power output power nodes. copper filled polygons bottom circuit layers create power islands connecting filtering components (output capacitors) loads. remaining printed circuit layers small signal wiring.
RT9641A/B
Component Selection Guidelines
Output Capacitors Selection output capacitors outputs should selected allow output voltage meet dynamic regulation requirements active state operation (S0, S1). load transient various microprocessor system's components require high quality capacitors supply high slew rate (di/dt) current demands. Thus, recommended that capacitors COUT1 COUT2 should selected transient load regulation. Also, during transition between active sleep states, there short interval time during which none power pass elements conducting-during this time output capacitors have supply output current. output voltage drop during this brief period time approximated with following formula:
CBULK2
ISLAND POWAR PLANE LAYER ISLAND CIRCUIT/POWER PLANE LAYER CONNECTION GROUND PLANE
Figure Printed Circuit Board Islands Placement decoupling bulk capacitors should follow placement reflecting their purpose. such, high-frequency decoupling capacitors (CHF) should placed close possible load they decoupling; ones decoupling controller (C12V, C5VSB) close controller pins, decoupling load close load connector load itself embedded). bulk capacitance (aluminum electrolytic tantalum capacitors) placement critical highfrequency capacitor placement, having these capacitors close load they serve preferable. only critical small signal component soft-start capacitor, CSS. Locate component close control connect ground though vias placed close capacitor's ground pad. Minimize leakage current paths from node, since internal current source only multi-layer printed circuit board recommended. Figure1 shows connections most components converter. Note that each individual capacitor could represent numerous physical capacitors. Dedicate solid layer ground plane make critical component ground connections through vias placed close component possible. Dedicate another
DS9641A/B-11 March 2007
VOUT IOUT (ESROUT COUT), where VOUT :output voltage drop
ESROUT output capacitor bank IOUT output current during transition COUT output capacitor bank capacitance active-to-sleep sleep-to-active transition time typical) Since output voltage drop heavily dependent (equivalent series resistance) output capacitor bank, capacitors should chosen maintain output voltage above lowest allowable regulation level. Input Capacitors Selection input capacitors RT9641A/B application must have sufficiently that input voltage does excessively when energy transferred output capacitors.
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RT9641A/B
Transistor Selection/Considerations
RT9641A/B typically requires P-channel transistor N-Channel power MOSFETs bipolar transistors. general requirement selection transistors linear regulators/switching elements package selection efficient removal heat. power dissipated linear regulator/switching element PLINEAR (VIN VOUT) Select package heatsink that maintains junction temperature below rating with maximum expected ambient temperature. active element 2.5V/3.3V (2.6V/3.43V) V(MEM) output different requirements each voltage settings. 2.5V systems utilizing RDRAM voltagecompatible) memory, better bipolar capable conducting maximum required output current must have minimum current gain (hfe) 100~150 this current 0.7V VCE. such systems, 2.5V(2.6V) output regulated from 3.3V output while active state. 3.3V systems (SDRAM compatible) suggested N-channel MOSFET, then MOSFET serves like switch when connected ATX3.3V during active states (S0, S1). main criteria selection this transistor output voltage budgeting. maximum RDS(ON) allowed highest junction temperature expressed with following equation: RDS(ON) (VIN(MIN)-VOUT (MIN))/ IOUT( MAX), where VIN(MIN) minimum input voltage VOUT(MIN) minimum output voltage allowed. IOUT(MAX) maximum output current gate bias available this MOEFET approximately logic level MOSFET prefered. 3.3V(3.43V) V(MEM) power also regulated from order have high quality (MEM), such configuration, either MOSFET transistors used. While heat dissipation should carefully handled. P-Chanel MOSFET used switch 5VSB output supply into 5VDUAL output during S4/S5 states dictated EN5VDL status), then, similar situation where MOSFET, selection criteria this device also proper voltage budgeting. maximum (ON), however, achieved with only 4.5V VGS, logic level MOSFET needs selected. device chosen perform this function, have saturation voltage while providing maximum sleep-state current have current gain sufficiently high saturated using minimum drive current (typically 20mA). resistor recommended inserted between 5VDLSB Base node transistor limiting base current. N-Channel MOSFETs used switch 3.3V inputs provided supply into 3.3VDUAL 5VDUAL outputs, respectively, while active (S0, state. Similar RDS(ON) criteria apply these cases well, unlike PMOS, however, these NMOS transistors benefit increased drive (approximately respectively). transistor used sleep-state pass element 3.3VDUAL output must have minimum current gain 1.5V 500mA throughout incircuit operating temperature range.
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DS9641A/B-11 March 2007
RT9641A/B
Outline Dimension
Symbol
Dimensions Millimeters 9.804 3.810 1.346 0.330 1.194 0.178 0.102 5.791 0.406 10.008 3.988 1.753 0.508 1.346 0.254 0.254 6.198 1.270
Dimensions Inches 0.386 0.150 0.053 0.013 0.047 0.007 0.004 0.228 0.016 0.394 0.157 0.069 0.020 0.053 0.010 0.010 0.244 0.050
16-Lead Plastic Package
Richtek Technology Corporation
Headquarter Taiyuen Street, Chupei City Hsinchu, Taiwan, R.O.C. Tel: (8863)5526789 Fax: (8863)5526611
Richtek Technology Corporation
Taipei Office (Marketing) 137, Lane 235, Paochiao Road, Hsintien City Taipei County, Taiwan, R.O.C. Tel: (8862)89191466 Fax: (8862)89191465 Email: marketing@richtek.com
DS9641A/B-11 March 2007
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Triple Linear Regulator Controller Support ACPI Control Interface

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