Programmable Radio Chip Power PRoCLP Features Single Device,
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CYRF69213
Programmable Radio Chip Power
PRoCLP Features
Single Device, Functions 8-bit, Flash based peripheral function radio transceiver function single device Flash-based Microcontroller Function based 8-bit CPU, optimized Human Interface Devices (HID) applications Bytes SRAM Kbytes Flash memory with EEPROM emulation In-System reprogrammable through D+/D- pins. 16-bit free running timer power wake timer 12-bit Programmable Interval Timer with interrupts Watchdog timer Industry-Leading Radio Transceiver Function Operates unlicensed worldwide Industrial, Scientific Medical (ISM) band (2.4 GHz-2.483 GHz) DSSS data rates Kbps GFSK data rate Mbps receive sensitivity Programmable output power Auto Transaction Sequencer (ATS) Framing Auto Received Signal Strength Indication (RSSI) Automatic Gain Control (AGC) Component Reduction Integrated 3.3V regulator Integrated pull GPIOs that require external components Operates single crystal Flexible High current drive GPIO pins. Configurable 8-mA 50-mA/pin current sink designated pins Each GPIO supports high-impedance inputs, configurable pull open-drain output, CMOS/TTL inputs CMOS output Maskable intrrupts pins Specification Compliance Conforms Specification Version Conforms Specification Version Supports Speed device address Supports control endpoint data points Integrated Transceiver Operating voltage from 4.0V 5.5V Operating temperature from 70°C Lead-free 40-lead package Advanced development tools based Cypress's PSoC® Tools
PRoCLP CYRF69213 Block Diagram
Vbus MOSI 4.7uF 470nF
VBat1
VBat3
VBat2
VReg
VCC1
VCC2
VDD_MICRO
P1.2 VReg
VCC3
RFbias
P0_2:4,7 P1_6:7 P2_0:1 D+/D2
Microcontroller Function
P1.5/MOSI P1.4/SCK P1.3/nSS RESV
Radio Function
IRQ/GPIO MISO/GPIO XOUT/GPIO PACTL/GPIO
12MHz
Xtal
Cypress Semiconductor Corporation Document 001-07552 Rev.
Champion Court
Jose, 95134-1709 408-943-2600 Revised February 2007
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470nF
CYRF69213
Applications
CYRF69213 PRoC Speed targeted following applications: Bridge Human Interface Devices (HID) Wireless mice Wireless keyboards Remote controls Gaming applications Bridge General Purpose Applications Consumer electronics Industrial applications White goods Home automation Personal health
Data Transmission Modes radio supports four different data transmission modes: GFSK mode, data transmitted Mbps without DSSS mode, byte encoded each code symbol transmitted mode, bits encoded each code symbol transmitted mode, single encoded each code symbol transmitted Both 64-chip 32-chip data codes supported. four data transmission modes apply data after Start Packet (SOP). particular, packet length, data sent same mode. Microcontroller Function microcontroller function based powerful CYRF69213 microcontroller. 8-bit Flash programmable microcontroller with integrated speed interface. microcontroller GPIO pins support USB, PS/2 other applications. Each GPIO port supports high-impedance inputs, configurable pull open drain output, CMOS/TTL inputs CMOS output. pins support programmable drive strength Additionally each used generate GPIO interrupt microcontroller. Each GPIO port GPIO interrupt vector with exception GPIO Port microcontroller features internal oscillator. With presence traffic, internal oscillator precisely tune timing requirements 1.5%). PRoC Kbytes Flash user's firmware code bytes stack space user variables. PRoC includes Watchdog timer, vectored interrupt controller, 12-bit programmable interval timer with configurable 1-ms interrupt 16-bit free running timer with capture registers.
Functional Description
PRoC devices integrated radio microcontroller functions same package provide dual-role single-chip solution. Communication between microcontroller radio interface between both functions.
Functional Overview
CYRF69213 complete Radio System-on-Chip device, providing complete system solution with single device discrete components. CYRF69213 designed implement low-cost wireless systems operating worldwide 2.4-GHz Industrial, Scientific, Medical (ISM) frequency band (2.400 GHz-2.4835 GHz). Radio Function radio meets following world-wide regulatory requirements: Europe ETSI 489-1 V1.4.1 ETSI 328-1 V1.3.1 North America Part Japan ARIB STD-T66
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Pinout
Name P0.4 Xtal_in P0.3 P0.1 Vbat P2.1 Bias P2.0 RESV VDD_micro P1.2 VREG P1.3 P1.4 P1.5 MOSI MISO XOUT PACTL P1.6 Reset GPIO. Port Reserved. Must connect Low-speed Low-speed 4.0-5.5 CPU/4.75-5.5 Must configured 3.3V output. must have output capacitor Slave select Serial Clock from function radio function Interrupt output, configure high/low GPIO Master Slave Master Slave Out, from radio function.Can configured GPIO Bufferd CLK, PACTL_n GPIO Control external GPIO GPIO. Port interface voltage. Connected 0.047 Radio Reset. Connected 0.47 Capacitor microcontroller GPIO pin. Must have RESET HIGH event very first time power applied radio otherwise state radio function control registers unknown. GPIO. Port Regulated logic bypass. Connected 0.47 Connected GPIO. Port Connected Connected Individually configured GPIO Crystal. External Clock Connected 0.047-µF Capacitor. Individually configured GPIO Individually configured GPIO Connected 0.047-µFshunt capacitor GPIO. Port voltage reference Differential input to/from antenna Ground Differential to/from antenna Function
P1.7 VDD_1.8 P0.7 Vreg E-pad
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Pinout Diagram
Figure Pinout 40-Lead LF48A
PACTL GPIO
VDD_1.8
VREG
P1.7
P0.7
P1.6
VBAT
Corner tabs
P0.4 XTAL P0.3 P0.1 VBAT P2.1 VBAT
E-PAD Bottom Side
XOUT GPIO MISO GPIO
CYRF69213 WirelessUSB
P1.5 MOSI GPIO P1.4 P1.3 P1.2 VREG VDD_Micro
RFBIAS P2.0 RESV
PRoC Functional Overview
designed implement wireless device links operating worldwide 2.4-GHz frequency band. intended systems compliant with world-wide regulations covered ETSI 489-1 V1.41, ETSI 328-1 V1.3.1 (Europe), Part (USA Industry Canada) TELEC ARIB_T66_March, 2003 (Japan). contains 2.4-GHz 1-Mbps GFSK radio transceiver, packet data buffering, packet framer, DSSS baseband controller, Received Signal Strength Indication (RSSI), interface data transfer device configuration. radio supports discrete 1-MHz channels (regulations limit some these channels certain jurisdictions). DSSS modes baseband performs DSSS spreading/despreading, while GFSK Mode Mb/s GFSK) baseband performs Start Frame (SOF), Frame (EOF) detection CRC16 generation checking. baseband also configured automatically transmit Acknowledge (ACK) handshake packets whenever valid packet received. When receive mode, with packet framing enabled, device always ready receive data transmitted supported rates, except SDR, enabling implementation mixed-rate systems which different devices different data rates. This also enables implementation dynamic data rate systems, which high data rates shorter distances and/or low-moderate interference environment,
change lower data rates longer distances and/or high interference environments. function 8-bit Flash-programmable microcontroller with integrated low-speed interface. instruction been optimized specifically operations, although used variety other embedded applications. function eight Kbytes Flash user's code bytes stack space user variables. addition, function includes Watchdog timer, vectored interrupt controller, 16-bit Free-Running Timer, 12-bit Programmable Interrupt Timer. function supports in-system programming using pins serial programming mode interface. programming protocol USB. Backward Compatibility CYRF69213 fully interoperable with main modes other Cypress radios CYWUSB6934 CYRF6936. 62.5-kbps mode supported selecting 32-chip DATA_CODE_ADR codes, mode, disabling SOP, length, CRC16 fields. Similarly, 15.675-kHz mode supported selecting 64-chip DATA_CODE_ADR codes mode. this way, suitably configured CYRF69213 device transmit data and/or receive data from first generation device.
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Functional Block Overview
blocks that make PRoC presented here. 2.4-GHz Radio radio transceiver dual conversion architecture optimized power range/robustness. radio employs channel-matched filters achieve high performance presence interference. integrated Power Amplifier (PA) provides transmit power, with output power control range steps. supply current device reduced output power reduced. Table Internal Output Power Step Table Setting Frequency Synthesizer Before transmission reception commence, necessary frequency synthesizer settle. settling time varies depending channel; fast channels provided with maximum settling time `fast channels' (<100-µs settling time) every third frequency, starting 2400 including 2472 (for example, 0,3,6,9.69 72). Baseband Framer baseband framer blocks provide DSSS encoding decoding, generation reception CRC16 generation checking, well detection length field. Data Rates Data Transmission Modes supports four different data transmission modes: GFSK mode, data transmitted Mbps, without DSSS. mode, bits encoded each DATA_CODE_ADR derived code symbol transmitted. mode, 2-bits encoded each DATA_CODE_ADR derived code symbol transmitted. CYWUSB6934 mode). mode, encoded each DATA_CODE_ADR derived code symbol transmitted. CYWUSB6934 standard modes.) Both 64-chip 32-chip DATA_CODE_ADR codes supported. four data transmission modes apply data after SOP. particular length, data, CRC16 Typical Output Power (dBm)
sent same mode. general, lower data rates reduces packet error rate given environment. combining DATA_CODE_ADR code lengths data transmission modes described above, CYRF69213 supports following data rates: 1000-kbps (GFSK) 250-kbps (32-chip 8DR) 125-kbps (64-chip 8DR) 62.5-kbps (32-chip DDR) 31.25-kbps (64-chip DDR) 15.625-kbps (64-chip SDR) Lower data rates typically provide longer range and/or more robust link. Link Layer Modes CYRF69213 device supports following data packet framing features: Packets begin with 2-symbol Start Packet (SOP) marker. This required GFSK modes, optional mode supported mode; framing disabled then event inferred whenever successive correlations detected. SOP_CODE_ADR code used different from that used `body' packet, desired different length. must configured same length both sides link. There options detecting packet. enabled, then packet length field enabled. GFSK must enable length field. This first bits after symbol, transmitted payload data rate. length field enabled, Packet (EOP) condition inferred after reception number bytes defined length field, plus bytes CRC16 enabled-see below). alternative using length field infer condition from configurable number successive non-correlations; this option available GFSK mode only recommended when using mode. CRC16 device configured append 16-bit CRC16 each packet. CRC16 uses polynomial with added programmability seed. enabled, receiver will verify calculated CRC16 payload data against received value CRC16 field. starting value CRC16 calculation configurable, CRC16 transmitted calculated using either loaded seed value zero seed; received data CRC16 will checked against both configured zero CRC16 seeds. CRC16 detects following errors: error bits error matter apart, which column, number bits error matter where they are) error burst wide checksum itself Figure shows example packet with SOP, CRC16 lengths fields enabled.
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Figure Example Default Packet Format
Preamble 16us Framing Symbol*
Framing Symbol*
Length
Packet length Byte Period
Payload Data
*Note:32 64us
Packet Buffers Packet data configuration registers accessed through interface. configuration registers directly addressed through address field packet. Configuration registers provided allow configuration DSSS codes, data rate, operating mode, interrupt masks, interrupt status, others. Packet Buffers data transmission reception uses 16-byte packet buffers-one transmission reception. transmit buffer allows complete packet bytes payload data loaded burst transaction, then transmitted with further intervention. Similarly, receive buffer allows entire packet payload data bytes received with firmware intervention required until packet reception complete. CYRF69213 supports packet length bytes; interrupts provided allow transmit receive buffers FIFOs. When transmitting packet longer than bytes, load bytes initially, further bytes transmit buffer transmission data creates space buffer. Similarly, when receiving packets longer than bytes, function must fetch received data from FIFO periodically during packet reception prevent from overflowing. Auto Transaction Sequencer (ATS) CYRF69213 provides automated support transmission reception acknowledged data packets. When transmitting data packet, device automatically starts crystal synthesizer, enters transmit mode, transmits packet transmit buffer, then automatically switches receive mode waits handshake packet-and then automatically reverts sleep mode idle mode when either packet received, timeout period expires. Similarly, when receiving transaction mode, device waits receive mode valid packet received, then automatically transitions transmit mode, transmits packet, then switches back receive mode await next packet. contents packet buffers affected transmission reception packets. each case, entire packet transaction takes place without need firmware action; transmit data simply needs load data packet transmitted, length, bit. Similarly, when receiving packets transaction mode, firmware simply needs retrieve Below requirements crystal directly Document 001-07552 Rev.
fully received packet response interrupt request indicating reception packet. Interrupts radio function provides interrupt (IRQ) output, which configurable indicate occurrence various different events. programmed either active high active low, either CMOS open drain output. multiplexed routed external pin. radio function features three sets interrupts: transmit, receive, system interrupts. These interrupts share single (IRQ), independently enabled/disabled. transmit mode, receive interrupts automatically disabled, receive mode transmit interrupts automatically disabled. However, contents enable registers preserved when switching between transmit receive modes. more than radio interrupt enabled time, necessary read relevant status register determine which event caused assert. Even when given interrupt source disabled, status condition that would otherwise cause interrupt determined reading appropriate status register. therefore possible devices without making polling status register(s) wait event, rather than using pin. microcontroller function supports maskable interrupts vectored interrupt controller. Interrupt sources include reset, LVR/POR, programmable interval timer, 1.024-ms output from Free Running Timer, three endpoints, capture timers, five GPIO Ports, three GPIO pins, SPI, 16-bit free running timer wrap, internal wake-up timer, active interrupt. wake-up timer causes periodic interrupts when enabled. endpoints interrupt after transaction complete bus. capture timers interrupt whenever timer value saved selected GPIO edge event. total eight GPIO interrupts support both CMOS thresholds. additional flexibility, edge sensitive GPIO pins, interrupt polarity programmable either rising falling. Clocks radio function 12-MHz crystal (30-ppm better) directly connected between XTAL without need external capacitors. digital clock function provided, with selectable output frequencies 0.75, 1.5, MHz. This output used clock external microcontroller (MCU) ASIC. This output enabled default, disabled. connected XTAL GND: Page
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Nominal Frequency: Operating Mode: Fundamental Mode Resonance Mode: Parallel Resonant Frequency Initial Stability: Series Resistance: ohms Load Capacitance: Drive Level: µW-100
Figure Power Management From Internal Regulator
0.047µF
0.047µF 0.047µF
0.047µF 0.047µF 0.047µF 0.047µF 0.047µF
VBat2
VBat3
VCC1
VCC2
VBat1
GPIO Interface function features general-purpose (GPIO) pins support USB, PS/2, other applications. pins grouped into five ports (Port pins Port Port each configured individually while pins Ports only configured group. Each GPIO port supports high-impedance inputs, configurable pull open drain output, CMOS/TTL inputs, CMOS output with five pins that support programmable drive strength 50-mA sink current. GPIO Port features four pins that interface voltage level volts. Additionally, each used generate GPIO interrupt microcontroller. Each GPIO port GPIO interrupt vector with exception GPIO Port GPIO Port three dedicated pins that have independent interrupt vectors (P0.2-P0.4). Power-On Reset/Low-Voltage Detect power-on reset circuit detects logic when power applied device, resets logic known state, begins executing instructions Flash address 0x0000. When power falls below programmable trip voltage, generates reset configured generate interrupt. There low-voltage detect circuit that detects when drops below programmable trip voltage. configurable generate interrupt inform processor about low-voltage event. share same interrupt. There separate interrupt each. Watchdog timer used ensure firmware never gets stalled infinite loop. Power Management device draws power supply from Vbus line. Vbus supplies power function, which internal regulator. This supplied radio function P1.2/VREG after proper filtering shown Figure
P1.2 VReg
VBUS VDD_MICRO
PRoC
0.1µF
Timers free-running 16-bit timer provides interrupt sources: programmable interval timer with 1-µs resolution 1.024-ms outputs. timer used measure duration event under firmware control reading timer start event, then calculating difference between values. Interface function includes integrated serial interface engine (SIE) that allows chip easily interface host. hardware supports device address with three endpoints. Noise Amplifier (LNA) Received Signal Strength Indication (RSSI) gain receiver controlled directly clearing writing Noise Amplifier (LNA) RX_CFG_ADR register. When cleared, receiver gain reduced approximately allowing accurate reception very strong received signals (for example when operating receiver very close transmitter). additional receiver attenuation added setting Attenuation (ATT) bit; this allows data reception limited devices very short ranges. Disabling enabling recommended unless receiving from device using external RSSI register returns relative signal strength on-channel signal power. When receiving, device configured automatically measure store relative strength signal being received 5-bit value. When enabled, RSSI reading taken read through interface.
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VCC3
VReg
function features internal oscillator. With presence traffic, internal oscillator precisely tune timing requirements ±1.5%). clock generator provides 12-MHz 24-MHz clocks that remain internal microcontroller.
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RSSI reading taken automatically when start packet detected. addition, RSSI reading taken every time previous reading read from RSSI register, allowing background energy level given channel easily measured when RSSI read when signal being received. reading occur fast once every
Interface
interface between function radio function 3-wire Interface. three pins MOSI (Master Slave In), (Serial Clock), (Slave Select). There alternate 4-wire MISO Interface that requires connection external pins. interface controlled configuring Configure Register (SICR Address: 0x3D). 3-Wire Interface radio function receives clock from function pin. MOSI multiplexed with MISO pin. Bidirectional data transfer takes place between function radio function through this multiplexed MOSI pin. When using this mode user firmware should ensure that MOSI function high impedance state, except when actively transmitting data. Firmware must also control direction data flow switch directions between function radio function setting SWAP [Bit Configure Register. asserted prior initiating data transfer between function radio function. function optionally multiplexed with MOSI pin; when this option enabled function available while low. When using this configuration, user firmware should ensure that MOSI function function high-impedance state whenever high. Figure 3-Wire Mode
MOSI
device receives from function pin. Data from function shifted MOSI pin. Data function shifted MISO pin. active must asserted functions communicate. function optionally multiplexed with MOSI pin; when this option enabled function available while low. When using this configuration, user firmware should ensure that MOSI function function high-impedance state whenever high. Figure 4-WIRE Mode
MOSI
Function
Radio Function
P1.5/MOSI
MOSI
P1.6/MISO
P1.4/SCK
MISO
P1.3/nSS
This connection external PRoC Chip
Communication Transactions transactions single byte multi-byte. function initiates data transfer through Command/Address byte. following bytes data bytes. transaction format shown Figure specifies direction data transfer. Master reads from slave. Master writes slave. helps read write consecutive bytes from contiguous memory locations single burst mode operation.
Function
P1.5/MOSI
MOSI/MISO multiplexed MOSI
Radio Function
MOSI
Slave Select asserted then master function reads byte from radio, address incremented byte location, then byte that location read, Slave Select asserted then function reads/writes bytes same register burst mode, register file then reads/writes bytes that register file. interface between radio function dependent internal 12-MHz oscillator radio. Therefore, radio function registers read from written into while radio sleep mode. Voltage References interfaces between function radio have separate voltage reference VIO, enabling radio function directly interface with Page
P1.4/SCK
P1.3/nSS
4-Wire Interface 4-wire communications interface consists MOSI, MISO, SCK,
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function, which operates higher supply voltage. internal SPIO pins between function radio function should connected with regulated voltage 3.3V setting [bit4] Registers P13CR, P14CR, P15CR, P16CR function) internal 3.3V regulator function should turned
Connects External Devices three wires, MOSI, SCK, also drawn package external pins allow user interface their external devices (such optical sensors others) through SPI. radio function also wires MISO IRQ, which used send data back function send interrupt request function. They also configured GPIO pins.
Figure Transaction Format
Byte Bit# Name [5:0] Address Byte [7:0] Data
Architecture
This family microcontrollers based high-performance, 8-bit, Harvard-architecture microprocessor. Five registers control primary operation core. These registers affected various instructions, directly accessible through register space user. Table Registers Register Names Register Flags Program Counter Accumulator Stack Pointer Index Register Name CPU_F CPU_PC CPU_A CPU_SP CPU_X
Accumulator Register (CPU_A) general-purpose register that holds results instructions that specify source addressing modes. Index Register (CPU_X) holds offset value that used indexed addressing modes. Typically, this used address block data within data memory space. Stack Pointer Register (CPU_SP) holds address current top-of-stack data memory space. affected PUSH, POP, LCALL, CALL, RETI, instructions, which manage software stack. also affected SWAP instructions. Flag Register (CPU_F) three status bits: Zero Flag [1]; Carry Flag [2]; Supervisory State [3]. Global Interrupt Enable used globally enable disable interrupts. user cannot manipulate Supervisory State status [3]. flags affected arithmetic, logic, shift operations. manner which each flag changed dependent upon instruction being executed (for example, AND, XOR). Table
16-bit Program Counter Register (CPU_PC) allows direct addressing full eight Kbytes program memory space.
Registers
Flags Register
Flags Register only reset with logical instruction. Table Flags Register (CPU_F) [R/W]
Field Read/Write Default
Reserved
Super
Carry
Zero
Global
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Table Flags Register (CPU_F) [R/W]
Bits Reserved user select between register banks Bank Bank Super Indicates whether executing user code Supervisor Code. (This code cannot accessed directly user.) User Code Supervisor Code Carry indicate whether there been carry previous logical/arithmetic operation Carry Carry Zero indicate whether there been zero result previous logical/arithmetic operation Equal Zero Equal Zero Global Determines whether interrupts enabled disabled Disabled Enabled
Note CPU_F register only readable with explicit register address 0xF7. expr expr instructions must used clear CPU_F bits
Accumulator Register Table Accumulator Register (CPU_A)
Field Read/Write Default
Accumulator [7:0]
Bits Accumulator [7:0] 8-bit data value holds result logical/arithmetic instruction that uses source addressing mode
Index Register Table Register (CPU_X)
Field Read/Write Default [7:0]
Bits [7:0] 8-bit data value holds index instruction that uses indexed addressing mode
Stack Pointer Register Table Stack Pointer Register (CPU_SP)
Field Read/Write Default
Stack Pointer [7:0]
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Table Stack Pointer Register (CPU_SP)
Bits Stack Pointer [7:0] 8-bit data value holds pointer current top-of-stack
Program Counter High Register Table Program Counter High Register (CPU_PCH)
Field Read/Write Default
Program Counter [15:8]
Bits Program Counter [15:8] 8-bit data value holds higher byte program counter
Program Counter Register Table Program Counter Register (CPU_PCL)
Field Read/Write Default
Program Counter [7:0]
Bits Program Counter [7:0] 8-bit data value holds lower byte program counter
Addressing Modes
Examples different addressing modes discussed this section example code given. Source Immediate result instruction using this addressing mode placed register, register, register, register, which specified part instruction opcode. Operand immediate value that serves source instruction. Arithmetic instructions require sources. Instructions using this addressing mode bytes length. Table Source Immediate Opcode Instruction Examples
this case, immediate value added with Accumulator, ;and result placed ;Accumulator. this case, immediate value moved register. this case, immediate value logically ANDed with ;register result placed register.
Source Direct result instruction using this addressing mode placed either register register, which specified part instruction opcode. Operand address that points location either memory space register space that source instruction. Arithmetic instructions require sources; second source register register specified opcode. Instructions using this addressing mode bytes length. Table 10.Source Direct Opcode Instruction Operand Immediate Value Examples
this case, value ;the memory location ;address added with ;Accumulator, result placed Accumulator. this case, value ;the register space address moved register.
Operand Source Address
REG[8]
Source Indexed result instruction using this addressing mode placed either register register, which
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specified part instruction opcode. Operand added register forming address that points location either memory space register space that source instruction. Arithmetic instructions require sources; second source register register specified opcode. Instructions using this addressing mode bytes length. Table 11.Source Indexed Opcode Instruction Examples
[X+7] this case, value ;the memory location ;address added with ;the Accumulator, ;result placed ;Accumulator. this case, value ;the register space ;address moved ;the register.
instruction register. Arithmetic instructions require sources; second source location specified Operand added with register. Instructions using this addressing mode bytes length. Table 13.Destination Indexed Opcode Instruction Operand Destination Index
Operand Source Index Example
[X+7], this case, value ;memory location address added with Accumulator, ;and result placed ;the memory location address ;x+7. Accumulator ;unchanged.
Destination Direct Source Immediate result instruction using this addressing mode placed within either memory space register space. Operand address result. source instruction Operand which immediate value. Arithmetic instructions require sources; second source location specified Operand Instructions using this addressing mode three bytes length. Table 14.Destination Direct Immediate Opcode Instruction Examples
[7], this case, value mem;ory location address ;added immediate value result placed ;the memory location address this case, immediate ;value moved into ;register space location ;address
REG[X+8]
Destination Direct result instruction using this addressing mode placed within either memory space register space. Operand address that points location result. source instruction either register register, which specified part instruction opcode. Arithmetic instructions require sources; second source location specified Operand Instructions using this addressing mode bytes length. Table 12.Destination Direct Opcode Instruction Examples
[7], this case, value ;the memory location ;address added with ;Accumulator, result placed memory ;location address ;Accumulator unchanged. this case, Accumula;tor moved regis;ter space location ;address Accumulator unchanged.
Operand Destination Address
Operand Immediate Value
Operand Destination Address
REG[8],
Destination Indexed Source Immediate result instruction using this addressing mode placed within either memory space register space. Operand added register form address result. source instruction Operand which immediate value. Arithmetic instructions require sources; second source location specified Operand added with register. Instructions using this addressing mode three bytes length. Table 15.Destination Indexed Immediate Opcode Instruction Operand Destination Index Operand Immediate Value
REG[8],
Destination Indexed result instruction using this addressing mode placed within either memory space register space. Operand added register forming address that points location result. source
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Examples
[X+7], this case, value ;the memory location ;address added with ;the immediate value ;and result placed memory location ;address X+7. this case, immedi;ate value moved ;into location ;register space ;address X+8.
bytes length. Refer PSoC Designer: Assembly Language User Guide further details instruction. Table 17.Source Indirect Post Increment Opcode Instruction Example
this case, value ;memory location address indirect address. memory ;location pointed indi;rect address moved into ;Accumulator. indirect ;address then incremented.
Operand Source Address Address
REG[X+8],
Destination Direct Source Direct result instruction using this addressing mode placed within memory. Operand address result. Operand address that points location memory that source instruction. This addressing mode only valid instruction. instruction using this addressing mode three bytes length. Table 16.Destination Direct Source Direct Opcode Instruction Example
[7], this case, value ;memory location address ;moved memory location ;address
Destination Indirect Post Increment result instruction using this addressing mode placed within memory space. Operand address pointing location within memory space, which contains address (the indirect address) destination instruction. indirect address incremented part instruction execution. source instruction Accumulator. This addressing mode only valid instruction. instruction using this addressing mode bytes length. Table 18.Destination Indirect Post Increment Opcode Instruction Example Operand Destination Address Address
Operand Destination Address
Operand Source Address
Source Indirect Post Increment result instruction using this addressing mode placed Accumulator. Operand address pointing location within memory space, which contains address (the indirect address) source instruction. indirect address incremented part instruction execution. This addressing mode only valid instruction. instruction using this addressing mode
[8],
this case, value ;the memory location ;address indirect ;address. Accumulator ;moved into memory loca;tion pointed indi;rect address. indirect ;address then incremented.
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Instruction Summary
instruction summarized Table numerically serves quick reference. more information needed,
Opcode Opcode
Instruction Summary tables described detail PSoC Designer Assembly Language User Guide (available www.cypress.com site).
Table 19.Instruction Summary Sorted Numerically Opcode Order[1,
Opcode Cycles Cycles Cycles Bytes Bytes Instruction Format Flags Instruction Format Flags Bytes Instruction Format Flags
expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr PUSH expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr PUSH expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr ROMX expr [expr] [X+expr] [expr],
[X+expr], [expr], expr [X+expr], expr HALT expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr expr [expr] [X+expr] [expr], expr [X+expr], expr [expr]++ [expr]++ reg[expr], expr reg[X+expr], expr reg[expr], expr reg[X+expr], expr reg[expr], expr reg[X+expr], expr [expr], expr [X+expr], expr reg[expr], expr reg[X+expr], expr SWAP SWAP [expr] SWAP [expr] SWAP expr [expr] [X+expr] [expr], [X+expr], [expr], expr [X+expr], expr expr [expr] [X+expr]
[expr], reg[expr] reg[X+expr] [expr], [expr] reg[expr], reg[X+expr], reg[expr], expr reg[X+expr], expr [expr] [X+expr] [expr] [X+expr] [expr] [X+expr] [expr] [X+expr] expr expr expr [expr] [X+expr] [expr] [X+expr] LCALL LJMP RETI CALL JACC INDEX
(A=B) (A<B)
Notes Interrupt routines take cycles before execution resumes interrupt vector table. number cycles required instruction increased instructions that span 256-byte boundaries Flash memory space.
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Memory Organization
Flash Program Memory Organization Figure Program Memory Space with Interrupt Vector Table after reset 16-bit Address 0x0000 0x0004 0x0008 0x000C 0x0010 0x0014 0x0018 0x001C 0x0020 0x0024 0x0028 0x002C 0x0030 0x0034 0x0038 0x003C 0x0040 0x0044 0x0048 0x004C 0x0050 0x0054 0x0058 0x005C 0x0060 0x0064 0x0068 Program execution begins here after reset POR/LVD INT0 Transmitter Empty Receiver Full GPIO Port GPIO Port INT1 Reset Active 1-ms Interval Timer Programmable Interval Timer Reserved Reserved 16-bit Free Running Timer Wrap INT2 Reserved GPIO Port Reserved Reserved Reserved Reserved Sleep Timer Program Memory begins here below interrupts used, program memory start lower)
0x1FFF
ends here
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Data Memory Organization function bytes data Figure Data Memory Organization after reset 8-bit Address 0x00 Stack begins here grows upward.
Memory Flash
0xFF SROM SROM holds code that used boot part, calibrate circuitry, perform Flash operations. (Table lists SROM functions.) functions SROM accessed normal user code operating from Flash. SROM exists separate memory space from user code. SROM functions accessed executing Supervisory System Call instruction (SSC), which opcode 00h. Prior executing SSC, M8C's accumulator needs loaded with desired SROM function code from Table Undefined functions will cause HALT called from user code. SROM functions executing code with calls; therefore, functions require stack space. With exception Reset, SROM functions have parameter block SRAM that must configured before executing SSC. Table lists possible parameter block variables. meaning each parameter, with regards specific SROM function, described later this section. Table 20.SROM Function Codes Function Code Function Name SWBootReset ReadBlock WriteBlock EraseBlock EraseAll TableRead CheckSum Stack Space
This section describes Flash block CYRF69213. Much user-visible Flash functionality, including programming security, implemented Supervisory Read Only Memory (SROM). CYRF69213 Flash endurance 1000 cycles 10-year data retention. Flash Programming Security Flash programming performed code SROM. registers that control Flash programming only visible when executing SROM. This makes impossible read, write, erase Flash bypassing security mechanisms implemented SROM. Customer firmware only program Flash SROM calls. data code images sourced interface with appropriate support firmware. This type programming requires `boot-loader'-a piece firmware resident Flash. safety reasons this boot-loader should overwritten during firmware rewrites. Flash provides four auxiliary rows that used hold Flash block protection flags, boot time calibration values, configuration tables, device values. routines accessing these auxiliary rows documented SROM section. auxiliary rows affected device erase function. In-System Programming Most designs that include CYRF69213 part will have connector attached D+/D- pins device. These designs require ability program reprogram part through these pins alone. CYRF69213 device enables this type in-system programming using pins serial programming mode interface. This allows external controller cause CYRF69213 part enter serial programming mode then test queue issue Flash access functions SROM. programming protocol USB.
important variables that used functions KEY1 KEY2. These variables used help discriminate between valid SSCs inadvertent SSCs. KEY1 must always have value 3Ah, while KEY2 must have same value stack pointer when SROM function begins execution. This would Stack Pointer value when opcode executed, plus three. either keys
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match expected values, will halt (with exception SWBootReset function). following code puts correct value KEY1 KEY2. code starts with halt, force program jump directly into setup code into halt SSCOP: [KEY1], [KEY2], Table 21.SROM Function Parameters Variable Name Key1/Counter/Return Code Key2/TMP BlockID Pointer Clock Mode Delay SRAM Address 0,F8h 0,F9h 0,FAh 0,FBh 0,FCh 0,FDh 0,FEh 0,FFh
SWBootReset Function SROM function, SWBootReset, function that responsible transitioning device from reset state running user code. SWBootReset function executed whenever SROM entered with accumulator value 00h; SRAM parameter block used input function. This will happen, design, after hardware reset, because M8C's accumulator reset when user code executes instruction with accumulator value 00h. SWBootReset function will execute when instruction executed with value nonzero function code. CYRF69213 device will execute HALT instruction value given either KEY1 KEY2. SWBootReset function verifies integrity calibration data 16-bit checksum, before releasing user code. ReadBlock Function ReadBlock function used read contiguous bytes from Flash-a block. first thing this function does check protection bits determine desired BLOCKID readable. read protection turned ReadBlock function will exit, setting accumulator KEY2 back 00h. KEY1 will have value 01h, indicating read failure. read protection enabled, function will read bytes from Flash using ROMX instruction store results SRAM using instruction. first bytes will stored SRAM address indicated value POINTER parameter. When ReadBlock completes successfully, accumulator, KEY1, KEY2 will have value 00h. Table 23.ReadBlock Parameters Name KEY1 KEY2 Address 0,F8h 0,F9h 0,FAh 0,FBh Stack Pointer value, when executed Flash block number First addresses SRAM where returned data should stored Description
SROM also features Return Codes Lockouts. Return Codes Return codes determination success failure particular function. return code stored KEY1's position parameter block. CheckSum TableRead functions have return codes because KEY1's position parameter block used return other data. Table 22.SROM Return Codes Return Code Success Function allowed level protection block Software reset without hardware reset Fatal error, SROM halted Description
BLOCKID POINTER
WriteBlock Function Read, write, erase operations fail target block read write protected. Block protection levels during device programming. EraseAll function overwrites data addition leaving entire user Flash erase state. EraseAll function loops through number Flash macros product, executing following sequence: erase, bulk program zeros, erase. After user space Flash macros erased, second loop erases then programs each protection block with zeros. SROM Function Descriptions SROM functions described following sections. WriteBlock function used store data Flash. Data moved bytes time from SRAM Flash using this function. first thing WriteBlock function does check protection bits determine desired BLOCKID writable. write protection turned WriteBlock function will exit, setting accumulator KEY2 back 00h. KEY1 will have value 01h, indicating write failure. configuration WriteBlock function straightforward. BLOCKID Flash block, where data stored, must determined stored SRAM address FAh. SRAM address first bytes stored Flash must indicated using POINTER variable parameter block (SRAM address FBh). Finally, CLOCK
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DELAY values must correctly. CLOCK value determines length write pulse that will used store data Flash. CLOCK DELAY values dependent speed. Refer `Clocking' Section additional information. Table 24.WriteBlock Parameters Name KEY1 KEY2 Address 0,F8h 0,F9h Stack Pointer value, when executed 8-KB Flash block number (00h-7Fh) 4-KB Flash block number (00h-3Fh) 3-KB Flash block number (00h-2Fh) First addresses SRAM, where data stored Flash located prior calling WriteBlock Clock divider used write pulse width speed Description
ability perform external reads writes. internal writes, used. Internal reading always permitted ROMX instruction. ability read SROM ReadBlock function indicated protection level stored bits according Table These bits packed into bytes protection block. Therefore, each protection block byte stores protection level four Flash blocks. bits packed into byte, with lowest numbered block's protection level stored lowest numbered bits. first address protection block contains protection level blocks through second address blocks through 64th byte will store protection level blocks through 255. Table 26.Protection Modes Mode Settings Description Marketing Unprotected Factory upgrade
BLOCKID 0,FAh
POINTER 0,FBh
Unprotected Read protect
CLOCK DELAY
0,FCh 0,FEh
Disable external Field upgrade write Disable internal write Full protection
EraseBlock Function EraseBlock function used erase block contiguous bytes Flash. first thing EraseBlock function does check protection bits determine desired BLOCKID writable. write protection turned EraseBlock function will exit, setting accumulator KEY2 back 00h. KEY1 will have value 01h, indicating write failure. EraseBlock function only useful first step programming. Erasing block will cause data block hundred percent unreadable. objective obliterate data block, best method perform EraseBlock followed WriteBlock zeros. parameter block EraseBlock function, correct values must stored KEY1 KEY2. block number erased must stored BLOCKID variable CLOCK DELAY values must based current speed. Table 25.EraseBlock Parameters Name KEY1 KEY2 Address 0,F8h 0,F9h Stack Pointer value when executed Flash block number (00h-7Fh) Clock divider used erase pulse width speed Description
Block
Block
Block
Block
level protection only decreased EraseAll, which places zeros locations protection block. level protection, ProtectBlock function used. This function takes data from SRAM, starting address 80h, with current values protection block. result operation then stored protection block. EraseBlock function does change protection level block. Because SRAM location protection data fixed there only protection block Flash macro, ProtectBlock function expects very variables parameter block prior calling function. parameter block values that must set, besides keys, CLOCK DELAY values. Table 27.ProtectBlock Parameters Name KEY1 KEY2 CLOCK DELAY Address 0,F8h 0,F9h 0,FCh 0,FEh Stack Pointer value when executed Clock divider used write pulse width speed Description
BLOCKID 0,FAh CLOCK DELAY 0,FCh 0,FEh
EraseAll Function ProtectBlock Function CYRF69213 device offers Flash protection block-by-block basis. Table lists protection modes available. table, used indicate EraseAll function performs series steps that destroy user data Flash macros resets protection block each Flash macro zeros (the unprotected state). EraseAll function does affect three hidden blocks above protection block each Flash macro. first Page
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these four hidden blocks used store protection table eight Kbytes user data. EraseAll function begins erasing user space Flash macro with highest address range. bulk program zeros then performed same Flash macro, destroy traces previous contents. bulk program followed second erase that leaves Flash macro state ready writing. erase, program, erase sequence then performed next lowest Flash macro address space exists. Following erase user space, protection block Flash macro with highest address range erased. Following erase protection block, zeros written into every protection table. next lowest Flash macro address space then protection block erased filled with zeros. result EraseAll function that user data Flash destroyed Flash left unprogrammed state, ready accept various write commands. protection bits user data also reset zero state. parameter block values that must set, besides keys, CLOCK DELAY values. Table 28.EraseAll Parameters Name KEY1 KEY2 CLOCK DELAY Address 0,F8h 0,F9h 0,FCh 0,FEh Stack Pointer value when executed Clock divider used write pulse width speed Description
Revision hard coded into SROM. Revision discussed more detail later this section. internal table holds alternate trim values device returns one-byte internal revision counter. internal revision counter starts with value zero incremented each time other revision numbers incremented. reset zero each time other revision numbers incremented. internal revision count returned CPU_A register. CPU_X register will always when trim values read. BLOCKID value, parameter block, used indicate which table should returned user. Only three least significant bits BLOCKID parameter used TableRead function CYRF69213. upper five bits ignored. When function called, transfers bytes from table SRAM addresses F8h-FFh. M8C's registers used TableRead function return die's Revision Revision 16-bit value hard coded into SROM that uniquely identifies die's design. Checksum Function Checksum function calculates 16-bit checksum over user specifiable number blocks, within single Flash macro (Bank) starting from block zero. BLOCKID parameter used pass number blocks calculate checksum over. BLOCKID value will calculate checksum only block while BLOCKID value will calculate checksum user blocks. 16-bit checksum returned KEY1 KEY2. parameter KEY1 holds lower eight bits checksum parameter KEY2 holds upper eight bits checksum. checksum algorithm executes following sequence three instructions over number blocks times checksummed. romx [KEY1], [KEY2], Table 30.Checksum Parameters Name KEY1 KEY2 BLOCKID Address 0,F8h 0,F9h 0,FAh Stack Pointer value when executed Number Flash blocks calculate checksum Description
TableRead Function TableRead function gives user access part-specific data stored Flash during manufacturing. also returns Revision (not confused with Silicon ID). Table 29.Table Read Parameters Name KEY1 KEY2 Address 0,F8h 0,F9h Stack Pointer value when executed Table number read Description
BLOCKID 0,FAh
Clocking
CYRF69213 internal oscillator outputs frequencies, Internal 24-MHz Oscillator 32-KHz Low-power Oscillator. Internal 24-MHz Oscillator designed such that trimmed output frequency over temperature voltage variation. With presence traffic, Internal 24-MHz Oscillator precisely tune timing requirements 1.5%). Without traffic, Internal 24-MHz Oscillator accuracy (between
table space CYRF69213 simply 64-byte broken into eight tables eight bytes. tables numbered zero through seven. user hidden blocks CYRF69213 parts consist bytes. internal table holds Silicon returns Revision Silicon returned SRAM, while Revision returned CPU_A CPU_X registers. Silicon value placed table programming Flash controlled Cypress Semiconductor Product Engineering.
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0°-70°C). external components required achieve this level accuracy. internal low-speed oscillator nominally provides slow clock source CYRF69213 suspend mode, particularly generate periodic wake-up interrupt also provide clock sequential logic during power-up power-down events when main clock stopped. addition, this oscillator also used clocking source Interval Timer clock (ITMRCLK) Capture Timer clock (TCAPCLK). 32-KHz Low-power Oscillator operate low-power mode provide more accurate clock normal mode. Internal 32-KHz Low-power Oscillator accuracy ranges (between follows: Normal mode: mode: +12% When using 32-KHz oscillator PITMRL/H should read until consecutive readings match before sending/receiving data. following firmware example assumes developer interested lower byte PIT.
Read_PIT_counter: reg[PITMRL] [57h], reg[PITMRL] [58h], [59h], reg{PITMRL] [60h], ;;;Start comparison [60h] [59h] [59h] done [59h] [58h] [58h] done [57h] ;;;correct data memory location done: [57h],
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Figure Clock Block Diagram
CPUCLK
CLK_EXT CLK_24MHz SCALE (divide 0-5,7) CPU_CLK
CLK_USB
SCALE
SCALE
EXT/2
CLK_32
Clock Architecture Description CYRF69213 clock selection circuitry allows selection independent clocks CPU, USB, Interval Timers, Capture Timers. clock, CPUCLK, sourced from external crystal oscillator Internal 24-MHz Oscillator. selected clock source optionally divided where 0-5,7 (see Table 34). USBCLK, which must function properly, sourced Internal 24-MHz Oscillator external crystal oscillator. optional divide-by-two allows 24-MHz source. Interval Timer clock (ITMRCLK), sourced from external crystal oscillator, Internal 24-MHz Oscillator, Document 001-07552 Rev.
Internal 32-KHz Low-power Oscillator, from timer capture clock (TCAPCLK). programmable prescaler then divides selected source. Timer Capture clock (TCAPCLK) sourced from external crystal oscillator, Internal 24-MHz Oscillator, Internal 32-KHz Low-power Oscillator. When being used external crystal oscillator, CLKOUT driven from many sources. This used test also used some applications. sources that drive CLKOUT are: CLKIN after optional EFTB filter Internal 24-MHz Oscillator Internal 32-KHz Low-power Oscillator CPUCLK after programmable divider Page
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Table 31.IOSC Trim (IOSCTR) [0x34] [R/W]
Field Read/Write Default foffset[2:0] Gain[4:0]
IOSC Calibrate register used calibrate internal oscillator. reset value undefined, during boot SROM writes calibration value that determined during manufacturing test. This value should require change during normal use. This meaning Default field Bits foffset [2:0] This value used trim frequency internal oscillator. These bits used factory calibration will zero. Setting each these bits causes appropriate fine offset oscillator frequency foffset foffset foffset Bits Gain [4:0] effective frequency change offset input controlled through gain input. lower value gain setting increases gain offset input. This value sets size each offset step internal oscillator. Nominal gain change (KHz/offsetStep) each bit, typical conditions (24-MHz operation): Gain -1.5 Gain -3.0 Gain Gain Gain
Table 32.LPOSC Trim (LPOSCTR) [0x36] [R/W]
Field Read/Write Default 32-KHz Power Reserved
32-KHz Bias Trim [1:0]
32-KHz Freq Trim [3:0]
This register used calibrate 32-KHz Low-speed Oscillator. reset value undefined, during boot SROM writes calibration value that determined during manufacturing test. This value should require change during normal use. This meaning Default field. 32-KHz Low-power needs written, care should taken disturb 32-KHz Bias Trim 32-KHz Freq Trim fields from their factory calibrated values 32-KHz Power 32-KHz Low-speed Oscillator operates normal mode 32-KHz Low-speed Oscillator operates low-power mode. oscillator continues function normally with reduced accuracy Bits Reserved 32-KHz Bias Trim [1:0] These bits control bias current low-power oscillator. bias High bias Reserved Reserved
Important Note program 32-KHz Bias Trim [1:0] field with reserved value, oscillator does oscillate corner conditions with this setting Bits 32-KHz Freq Trim [3:0] These bits used trim frequency low-power oscillator
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Table 33.CPU/USB Clock Config CPUCLKCR) [0x30] [R/W]
Field Read/Write Default Reserved CLK/2 Disable This only affects USBCLK when source external crystal oscillator. When USBCLK source Internal 24-MHz Oscillator, divide always enabled USBCLK source divided two. This correct setting when Internal 24-MHz Oscillator used, when external source used with 24-MHz clock USBCLK undivided. this setting only with 12-MHz external clock Select This controls clock source Internal 24-MHz Oscillator. With presence traffic, Internal 24-MHz Oscillator trimmed meet requirement 1.5% tolerance (see Table External clock-Internal Oscillator trimmed traffic. Proper operation requires 12-MHz 24-MHz clock accurate <1.5% Reserved Reserved CLK/2 Disable Select Reserved CPUCLK Select
Bits
Select Internal 24-MHz Oscillator External clock-External clock CLKIN (P0.0) Note speed selection configured using OSC_CR0 Register (Table
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Table 34.OSC Control (OSC_CR0) [0x1E0] [R/W]
Field Read/Write Default
Reserved Reserved
Buzz
Speed [2:0]
Sleep Timer [1:0]
Bits
Buzz During sleep (the Sleep CPU_SCR Register-Table 38), detection circuit turned periodically detect events (the Sleep Duty Cycle bits ECO_TR used control duty
cycle-Table 42). facilitate detection events, Buzz used force detection circuit continuously enabled during sleep. This results faster response event during sleep expense slightly higher than average sleep current detection circuit turned periodically configured Sleep Duty Cycle Sleep Duty Cycle value overridden. detection circuit always enabled Note periodic Sleep Duty Cycle enabling independent with sleep interval shown Sleep [1:0] bits below Bits Sleep Timer [1:0]
Sleep Timer Clock Frequency (Nominal) Sleep Period (Nominal) 1.95 15.6 Watchdog Period (Nominal)
Sleep Timer [1:0]
Note Sleep intervals approximate Bits Speed [2:0] CYRF69213 operate over range clock speeds. reset value Speed bits zero; therefore, default speed one-eighth internal MHz, Regardless Speed bit's setting, actual speed greater than MHz, 24-MHz operating requirements apply. example this scenario device that configured external clock, which supplying frequency MHz. speed register's value 0b011, clock will MHz. Therefore supply voltage requirements device same part operating MHz. operating voltage requirements relaxed until speed less
when Internal Oscillator selected (Default) Reserved External Clock Clock In/8 Clock In/4 Clock In/2 Clock In/1 Clock In/16 Clock In/32 Clock In/128 Reserved
Speed [2:0]
Important Note Correct operations require clock speed least less than clock/8. clocks have same source then clock divider should divide more than clocks have different sources, care must taken ensure that maximum ratio Clock/CPU Clock never exceed across full specification range both clock sources
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Table 35.USB Osclock Clock Configuration (OSCLCKCR) [0x39] [R/W]
Field Read/Write Default Reserved Fine Tune Only Osclock Disable
This register used trim Internal 24-MHz Oscillator using received low-speed packets timing reference. Osclock circuit active when Internal 24-MHz Oscillator provides clock Bits Reserved Fine Tune Only Enable Disable oscillator lock from performing course-tune portion retuning. oscillator lock must allowed perform course tuning order tune oscillator correct operation. After oscillator properly tuned this reduce variance internal oscillator frequency that would caused course tuning Osclock Disable Enable. With presence traffic, Internal 24-MHz Oscillator precisely tunes 1.5% Disable. Internal 24-MHz Oscillator trimmed based packets. This setting useful when internal oscillator sourcing USBSIE clock
Table 36.Timer Clock Config (TMRCLKCR) [0x31] [R/W]
Field Read/Write Default Bits
TCAPCL Divider
TCAPCLK Select
ITMRCLK Divider
ITMRCLK Select
TCAPCLK Divider TCAPCLK Divider controls TCAPCLK divisor Divide Divide Divide Divide TCAPCLK Select TCAPCLK Select field controls source TCAPCLK Internal 24-MHz Oscillator External crystal oscillator-external crystal oscillator CLKIN CLKOUT external crystal oscillator enabled, CLKIN input external crystal oscillator disabled (the XOSC Enable CLKIOCR Register cleared-Table Internal 32-KHz Low-power Oscillator TCAPCLK Disabled
Bits
Note 1024-µs interval timer based assumption that TCAPCLK running MHz. Changes TCAPCLK frequency will cause corresponding change 1024-µs interval timer frequency Bits ITMRCLK Divider ITMRCLK Divider controls ITMRCLK divisor. Divider value Divider value Divider value Divider value Bits ITMRCLK Select Internal 24-MHz Oscillator External crystal oscillator external crystal oscillator CLKIN CLKOUT external crystal oscillator enabled, CLKIN input external crystal oscillator disabled Internal 32-KHz Low-power Oscillator TCAPCLK
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Interval Timer Clock (ITMRCLK) Interval Timer Clock (ITMRCLK) sourced from external crystal oscillator, Internal 24-MHz oscillator, internal 32-KHz low-power oscillator, timer capture clock. programmable prescaler then divides selected source. 12-bit Programmable Interval Timer simple down counter with programmable reload value. provides 1-µs resolution default. When down counter reaches zero, next clock spent reloading. reload value read written while counter running, care should taken ensure that counter does unintentionally reload while 12-bit reload value only partially stored-for example, between writes 12-bit value. programmable interval timer generates interrupt each reload. parameters will appear device editor view PSoC Designer once place CYRF69213 Timer User Module. parameters PITIMER_Source PITIMER_Divider. PITIMER_Source clock
timer PITMER_Divider value clock divided interval register (PITMR) holds value that loaded into counter terminal count. counter down counter. Programmable Interval Timer resolution configurable. example: TCAPCLK divide clock (for example TCAPCLK divide 24-MHz clock will give frequency MHz) ITMRCLK divide TCAPCLK (for example, ITMRCLK divide TCAPCLK resolution 0.25 Timer Capture Clock (TCAPCLK) Timer Capture clock sourced from external crystal oscillator, internal 24-MHz oscillator Internal 332-KHz low-power oscillator. programmable prescaler then divides selected source.
Figure Programmable Interval Timer Block Diagram
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Figure Timer Capture Block Diagram
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Table 37.Clock Config (CLKIOCR) [0x32] [R/W]
Field Read/Write Default Bits Bits Reserved CLKOUT Select Internal 24-MHz Oscillator External crystal oscillator external crystal oscillator CLKIN CLKOUT external crystal oscillator enabled, CLKIN input external oscillator disabled Internal 32-KHz Low-power Oscillator CPUCLK Reserved
CLKOUT Select
Clock During Sleep Mode When enters sleep mode CPUCLK Select (Bit [0], Table forced internal oscillator, oscillator stopped. When comes sleep mode running internal oscillator. internal oscillator recovery time three clock cycles Internal 32-KHz Low-power Oscillator. system requires external clock after awakening from sleep mode, firmware will need switch clock source CPU.
initiated, registers restored their default states interrupts disabled. occurrence reset recorded System Status Control Register (CPU_SCR). Bits within this register record occurrence Reset respectively. firmware interrogate these bits determine cause reset. microcontroller resumes execution from Flash address 0x0000 after reset. internal clocking mode active after reset, until changed user firmware. Note clock defaults (Internal 24-MHz Oscillator divide-by-8 mode) guarantee operation that might present during supply ramp.
Reset
microcontroller supports types resets: Power-on Reset (POR) Watchdog Reset (WDR). When reset
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Table 38.System Status Control Register (CPU_SCR) [0xFF] [R/W]
Field Read/Write Default GIES Reserved WDRS R/C[3] PORS R/C[3] Sleep Reserved Stop
bits CPU_SCR register used convey status control events various functions CYRF69213 device GIES Global Interrupt Enable Status read only status discouraged. GIES legacy bit, which used provide ability read CPU_F register. However, CPU_F register readable. When this set, indicates that CPU_F register also which, turn, indicates that microprocessor will service interrupts Global interrupts disabled Global interrupt enabled Reserved WDRS WDRS indicate that event occurred. user read this determine type reset that occurred. user clear this event occurred PORS PORS indicate that event occurred. user read this determine type reset that occurred. user clear this event occurred. (Note that events will occur until this cleared) SLEEP user enable sleep state. will remain sleep mode until interrupt pending. Sleep covered more detail Sleep Mode section Normal operation Sleep Reserved STOP This user halt CPU. will remain halted until reset (WDR, POR, external reset) taken place. application wants stop code execution until reset, preferred method would HALT instruction rather than writing this Normal operation halted (not recommended)
Power-on Reset occurs every time power device switched released when supply typically 2.6V upward supply transition, with typically hysteresis during power-on transient. System Status Control Register (CPU_SCR) record this event (the register contents 00010000 POR). After POR, microprocessor held approximately supply stabilize before executing first instruction address 0x00 Flash. voltage drops below downward supply trip point, reasserted. supply needs ramp linearly from Important PORS status only cleared user. cannot firmware. Watchdog Timer Reset user option enable WDT. enabled clearing PORS bit. Once PORS
cleared, cannot disabled. only exception this event takes place, which will disable WDT. sleep timer used generate sleep time period Watchdog time period. sleep timer clocked Internal 32-KHz Low-power Oscillator system clock. user program sleep time period using Sleep Timer bits OSC_CR0 Register (Table 34). When sleep time elapses (sleep timer overflows), interrupt Sleep Timer Interrupt Vector will generated. Watchdog Timer period automatically three counts Sleep Timer overflows. This represents between three sleep intervals depending count Sleep Timer previous clear. When this timer reaches three, generated. user either clear WDT, Sleep Timer. Whenever user writes Reset Register (RES_WDT), will cleared. data that written value 0x38, Sleep Timer will also cleared same time.
Note Clear. This only cleared user cannot firmware
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Table 39.Reset Watchdog Timer (RESWDT) [0xE3]
Field Read/Write Default Bits Reset Watchdog Timer [7:0]
write this register will clear Watchdog Timer, write 0x38 will also clear Sleep Timer Reset Watchdog Timer [7:0]
Sleep Mode
only sleep firmware. This accomplished setting Sleep System Status Control Register (CPU_SCR). This stops from executing instructions, will remain asleep until interrupt comes pending, there reset event (either Power-on Reset, Watchdog Timer Reset). Low-voltage Detection circuit (LVD) drops into fully functional power-reduced states, latency increased. actual latency traded against power consumption changing Sleep Duty Cycle field ECO_TR Register. Internal 32-KHz Low-speed Oscillator remains running. Prior entering suspend mode, firmware optionally configure 32-KHz Low-speed Oscillator operate low-power mode help reduce overall power consumption (using Table 32). This will help save approximately however, trade that 32-KHz Low-speed Oscillator will less accurate. interrupts remain active. Only occurrence interrupt will wake part from sleep. Stop System Status Control Register (CPU_SCR) must cleared part resume sleep. Global Interrupt Enable Flags Register (CPU_F) does have effect. unmasked interrupt will wake system result, interrupts intended waking must disabled through Interrupt Mask Registers. When enters sleep mode CPUCLK Select (Bit Table forced Internal Oscillator. internal oscillator recovery time three clock cycles Internal 32-KHz Low-power Oscillator. Internal 24-MHz Oscillator restarts immediately exiting Sleep mode. external clock used, firmware will need switch clock source CPU. exiting sleep mode, once clock stable delay time expired, instruction immediately following
sleep instruction executed before interrupt service routine enabled). Sleep interrupt allows microcontroller wake periodically poll system components while maintaining very average power consumption. Sleep interrupt also used provide periodic interrupts during non-sleep modes. Sleep Sequence SLEEP input into sleep logic circuit. This circuit designed sequence device into hardware sleep state. hardware sequence device sleep shown Figure defined follows. Firmware sets SLEEP CPU_SCR0 register. Request (BRQ) signal immediately asserted. This request system halt operation instruction boundary. samples positive edge CPUCLK. specific timing register write, issues Request Acknowledge (BRA) following positive edge clock. sleep logic waits following negative edge clock then asserts system-wide Power Down (PD) signal. Figure halted system-wide power down signal asserted. system-wide (power down) signal controls several major circuit blocks: Flash memory module, internal 24-MHz oscillator, EFTB filter bandgap voltage reference. These circuits transition into zero power state. only operational circuits chip Power oscillator, bandgap refresh circuit, supply voltage monitor (POR/LVD) circuit. Note achieve lowest possible power consumption during suspend/sleep, following conditions must observed addition considerations sleep timer. GPIOs must outputs driven pins P1.0 P1.1 should configured inputs with their pull enabled.
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Figure Sleep Timing
Firmware write SLEEP causes immediate
captures next CPUCLK edge
responds with
falling edge CPUCLK, asserted. 24/48 system clock halted; Flash bandgap powered down
CPUCLK SLEEP
Wakeup Sequence Once asleep, only event that wake system interrupt. global interrupt enable flag register does need set. unmasked interrupt will wake system optional actually take interrupt after wakeup sequence. wakeup sequence synchronized 32-KHz clock purposes sequencing startup delay, allow Flash memory module enough time power before asserts first read access. Another reason delay allow oscillator, Bandgap, LVD/POR circuits time settle before actually being used system. shown Figure wakeup sequence follows: wakeup interrupt occurs synchronized negative edge 32-KHz clock. following positive edge 32-KHz clock, system-wide signal negated. Flash memory module, internal oscillator, EFTB, bandgap circuit powered normal operating state. following positive edge 32-KHz clock, current values precision have settled sampled. following negative edge 32-KHz clock (after about nominal), signal negated sleep logic circuit. following CPUCLK, negated instruction execution resumes. Note that Figure fixed function blocks, such Flash, internal oscillator, EFTB, bandgap, have about start wakeup times (interrupt operational) will range from
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Figure Wakeup Timing
Sleep Timer GPIO interrupt occurs
Interrupt double sampled clock negated system
restarted after (nominal)
CLK32K SLEEP BANDGAP PPOR ENABLE SAMPLE SAMPLE LVD/POR CPUCLK/ 24MHz (Not Scale)
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Low-Voltage Detect Control
Table 40.Low-voltage Control Register (LVDCR) [0x1E3] [R/W]
Field Read/Write Default Bits Bits Reserved PORLEV[1:0] This field controls level below which precision power-on-reset (PPOR) detector generates reset 2.7V Range (trip near 2.6V) Range (trip near 2.9V) Range, >4.75V (trip near 4.65V) PPOR will generate reset, values read from Voltage Monitor Comparators Register (Table give internal PPOR comparator state with trip point range setting Reserved VM[2:0] This field controls level below which low-voltage-detect trips-possibly generating interrupt level which Flash enabled operation. Trip Point VM[2:0]
Reserved
PORLEV[1:0]
Reserved
VM[2:0]
This register controls configuration Power-on Reset/Low-voltage Detection block
Bits
Min.
2.681 2.892 2.991 3.102 4.439 4.597 4.680 4.766
Typical
2.70 2.92 3.02 3.13 4.48 4.64 4.73 4.82
Max.
2.735 2.950 3.053 3.164 4.528 4.689 4.774 4.862
Compare State Table 41.Voltage Monitor Comparators Register (VLTCMP) [0x1E4]
Field Read/Write Default Bits Reserved This indicate that low-voltage-detect comparator tripped, indicating that supply voltage gone below trip point VM[2:0] (See Table low-voltage-detect event low-voltage-detect tripped PPOR This indicate that precision-power-on-reset comparator tripped, indicating that supply voltage below trip point PORLEV[1:0] precision-power-on-reset event precision-power-on-reset event tripped Reserved PPOR
This read-only register allows reading current state Low-voltage-Detection Precision-Power-On-Reset comparators
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Trim Register Table 42.ECO (ECO_TR) [0x1EB] [R/W]
Field Read/Write Default Bits Reserved
Sleep Duty Cycle [1:0]
This register controls ratios numbers 32-KHz clock periods) `on' time versus `off' time detection circuit Sleep Duty Cycle [1:0] periods Internal 32-KHz Low-speed Oscillator periods Internal 32-KHz Low-speed Oscillator periods Internal 32-KHz Low-speed Oscillator periods Internal 32-KHz Low-speed Oscillator
General-Purpose Ports
general-purpose ports discussed following sections. Port Data Registers Table 43.P0 Data Register (P0DATA)[0x00] [R/W]
Field Read/Write Default P0.7 Reserved Reserved P0.4/INT2 P0.3/INT1 P0.2/INT0 Reserved Reserved
This register contains data Port Writing this register sets values output output enabled pins. Reading from this register returns current state Port pins P0.7 Data Bits Bits Reserved pins P0.6-P0.5 GPIOs alternative functions exist CYRF69213 P0.4-P0.2 Data/INT2 INT0 addition their P0.4-P0.2 GPIOs, these pins also used alternative functions Interrupt pins (INT0-INT2). configure P0.4-P0.2 pins, refer P0.2/INT0-P0.4/INT2 Configuration Register (Table pins P0.4-P0.2 GPIOs alternative functions exist CYRF69213 Reserved Reserved
Table 44.P1 Data Register (P1DATA) [0x01] [R/W]
Field Read/Write Default P1.7 P1.6/SMISO P1.5/SMOSI P1.4/SCLK P1.3/SSEL P1.2/VREG P1.1/D- P1.0/D+
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Table 44.P1 Data Register (P1DATA) [0x01] [R/W]
This register contains data Port Writing this register sets values output output enabled pins. Reading from this register returns current state Port pins P1.7 Data Bits P1.6-P1.3 Data/SPI Pins (SMISO, SMOSI, SCLK, SSEL) addition their P1.6-P1.3 GPIOs, these pins also used alternative function interface pins. configure P1.6-P1.3 pins, refer P1.3-P1.6 Configuration Register (Table pins P1.6-P1.3 GPIOs alternative functions exist CYRF69213 parts P1.2/VREG 1-µF min, 2-µF capacitor required VREG output. P1.1-P1.0/D- When mode disabled (Bit Table clear), P1.1 P1.0 bits used control state P1.0 P1.1 pins. When mode enabled, P1.1 P1.0 pins used pins, respectively. Force State (Bit Table set, state pins controlled writing bits
Bits
Table 45.P2 Data Register (P2DATA) [0x02] [R/W]
Field Read/Write Default Reserved P2.1-P2.0
This register contains data Port Writing this register sets values output output enabled pins. Reading from this register returns current state Port pins Bits Reserved Data [7:2] Bits Data [1:0]
GPIO Port Configuration GPIO configuration registers have common configuration controls. following definitions GPIO configuration registers. Enable When set, Enable allows GPIO generate interrupts. Interrupt generate occur regardless whether configured input output. interrupts edge sensitive, however interrupt that shared multiple sources (that Ports inputs must deasserted before interrupt occur. When clear, corresponding interrupt disabled pin. possible configure GPIOs outputs, enable interrupt then generate interrupt driving appropriate state. This useful test have value applications well. When set, corresponding interrupt active falling edge. When clear, corresponding interrupt active rising edge. Thresh When set, input threshold. When clear, input standard CMOS threshold. High Sink When set, output sink
When clear, output sink CYRF69213, only P1.7-P1.3 have 50-mA sink drive capability. Other pins have 8-mA sink drive capability. Open Drain When set, output determined Port Data Register. corresponding Port Data Register set, high-impedance state. corresponding Port Data Register clear, driven low. When clear, output driven HIGH. Pull-up Enable When pull VREG ports with V3.3 enabled). When clear, pull disabled. Output Enable When set, output driver enabled. When clear, output driver disabled. pins with shared functions there some special cases. VREG Output/SPI P1.2 (VREG), P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI) P1.6 (SMISO) pins used their dedicated functions GPIO. enable GPIO, clear corresponding VREG Output bit. function controls output enable dedicated function pins when their GPIO enable clear.
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3.3V Drive P1.3 (SSEL), P1.4 (SCLK), P1.5 (SMOSI) P1.6 (SMISO) pins have alternate voltage source from voltage regulator. 3.3V Drive high level driven from voltage regulator instead from VCC.
Setting 3.3V Drive does enable voltage regulator. That must done explicitly setting VREG Enable VREGCR Register (Table 75).
Figure Block Diagram GPIO
3.3V rive
ull-U nable utput nable rain
hreshold
Table 46.P0.2/INT0-P0.4/INT2 Configuration (P02CR-P04CR) [0x07-0x09] [R/W]
Field Read/Write Default Reserved Thresh Reserved
Open Drain
Pull-up Enable Output Enable
These registers control operation pins P0.2-P0.4, respectively. These pins shared between P0.2-P0.4 GPIOs INT0-INT2. These registers exist CYRF69213 parts. INT0-INT2 interrupts different than other GPIO interrupts. These pins connected directly interrupt controller provide three edge-sensitive interrupts with independent interrupt vectors. These interrupts occur rising edge when clear falling edge when set. These pins enabled interrupt sources interrupt controller registers (Table Table these pins interrupt inputs configure them inputs clearing corresponding Output Enable. INT0-INT2 pins configured outputs with interrupts enabled, firmware generate interrupt writing appropriate value P0.2, P0.3 P0.4 data bits Data Register Regardless whether pins used Interrupt GPIO pins Enable, Low, Threshold, Open Drain, Pull-up Enable bits control behavior P0.2/INT0-P0.4/INT2 pins individually configured with P02CR (0x07), P03CR (0x08), P04CR (0x09), respectively. Note Changing state cause unintentional interrupt generated. When configuring these interrupt sources, best follow following procedure: Disable interrupt source Configure interrupt source Clear pending interrupts from source Enable interrupt source
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Table 47.P0.7 Configuration (P07CR) [0x0C] [R/W]
Field Read/Write Default Reserved Enable Thresh Reserved Open Drain
Pull-up Enable Output Enable
This register controls operation P0.7.
Table 48.P1.0/D+ Configuration (P10CR) [0x0D] [R/W]
Field Read/Write Default Reserved Enable Reserved Reserved Output Enable
This register controls operation P1.0 (D+) when interface enabled, allowing used interface GPIO. Table information enabling USB. When enabled, none controls this register have effect P1.0 Note P1.0 open drain only output. actively drive signal low, cannot actively drive signal high PS/2 Pull-up Enable Disable 5K-ohm pull-up resistors Enable 5K-ohm pull-up resistors both P1.0 P1.1. Enable P1.0 (D+) P1.1 (D-) pins style interface
Table 49.P1.1/D- Configuration (P11CR) [0x0E] [R/W]
Field Read/Write Default Reserved Enable Reserved Open Drain Reserved Output Enable
This register controls operation P1.1 (D-) when interface enabled, allowing used interface GPIO. Table information enabling USB. When enabled, none controls this register have effect P1.1 pin. When disabled, 5-Kohm pull-up resistor this enabled PS/2 Pull-up Enable P10CR Register (Table Note There 2-mA sourcing capability this pin. only sink VOL3
Table 50.P1.2 Configuration (P12CR) [0x0F] [R/W]
Field Read/Write Default Output Enable Threshold Reserved Open Drain
Pull-up Enable Output Enable
This register controls operation P1.2 Output internally selected clock sent onto P1.2 When Output set, internally selected clock sent onto P1.2
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Table 51.P1.3 Configuration (P13CR) [0x10] [R/W]
Field Read/Write Default Reserved Enable 3.3V Drive High Sink Open Drain
Pull-up Enable Output Enable
This register controls operation P1.3 pin. This register exists CYRF69213 parts P1.3 GPIO's threshold always When hardware enabled, output enable output state controlled circuitry. When hardware disabled, controlled Output Enable corresponding data register Regardless whether used GPIO Enable, Low, 3.3V Drive, High Sink, Open Drain, Pull-up Enable control behavior 50-mA sink drive capability only available CY7C638xx.
Table 52.P1.4-P1.6 Configuration (P14CR-P16CR) [0x11-0x13] [R/W]
Field Read/Write Default Enable 3.3V Drive High Sink Open Drain
Pull-up Enable Output Enable
These registers control operation pins P1.4-P1.6, respectively P1.4-P1.6 GPIO's threshold always When hardware enabled, pins that configured have their output enable output state controlled circuitry. When hardware disabled clear, controlled Output Enable corresponding data register Regardless whether used GPIO Enable, Low, 3.3V Drive, High Sink, Open Drain, Pull-up Enable control behavior Disable alternate function. used GPIO Enable function. circuitry controls output Important Note Comm Modes (SPI Master Slave, Table When configured (SPI Comm Modes [1:0] Master Slave mode), input/output direction pins P1.3, P1.5, P1.6 automatically logic. However, P1.4's input/output direction automatically set; must explicitly firmware. Master mode, P1.4 must configured output; Slave mode, P1.4 must configured input
Table P1.7 Configuration (P17CR) [0x14] [R/W]
Field Read/Write Default Reserved Enable Thresh High Sink Open Drain
Pull-up Enable Output Enable
This register controls operation P1.7. This register only exists CY7C638xx 50-mA sink drive capability only available CY7C638xx. P1.7 GPIO's threshold always
Table 54.P2 Configuration (P2CR) [0x15] [R/W]
Field Read/Write Default Reserved Enable Thresh High Sink Open Drain
Pull-up Enable Output Enable
This register only exists CY7C638xx. This register controls operation pins P2.0-P2.1. CY7C638xx, only 8-mA sink drive capability available this regardless setting High Sink
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Serial Peripheral Interface (SPI)
Master/Slave Interface core logic runs clock domain, making functionality independent system clock speed. four serial interface comprised clock, enable data pins. Figure Block Diagram
Register Block Speed Clock Generation
Master/Slave
Clock Select
SCK_OE
Polarity Phase
Clock Phase/Polarity Select
Little Endian
LE_SEL GPIO Block SS_N SS_N
State Machine SS_N Data bit) Load Empty Master/Slave LE_SEL Shift Buffer MISO/MOSI Crossbar Output Shift Buffer
SS_N_OE
MISO_OE
MISO
MOSI_OE
MOSI Data bit) Load Full Input Shift Buffer
Sclk Output Enable Slave Select Output Enable Master Slave Master Out, Slave
SCK_OE SS_N_OE MISO_OE MOSI_OE
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Data Register Table 55.SPI Data Register (SPIDATA) [0x3C] [R/W]
Field Read/Write Default Bits Data [7:0] SPIData[7:0]
When read, this register returns contents receive buffer. When written, loads transmit holding register
When interrupt occurs indicate firmware that byte receive data available, transmitter holding register empty, firmware clocks manage buffers-to empty receiver buffer, refill transmit holding register. Failure meet this timing requirement will result incorrect data transfer. Configure Register Table 56.SPI Configure Register (SPICR) [0x3D] [R/W]
Field Read/Write Default Swap First Comm Mode CPOL CPHA SCLK Select
Swap Swap function disabled block swaps SMOSI SMISO. Among other things, this useful implementing single wire SPI-like communications First transmits receives (Most Significant Bit) first transmits receives (Least Significant Bit) first. Comm Mode [1:0] communication disabled master mode slave mode Reserved CPOL This controls clock (SCLK) idle polarity SCLK idles SCLK idles high CPHA Clock Phase controls phase clock which data sampled. Table shows timing various combinations First, CPOL, CPHA SCLK Select This field selects speed master SCLK. When master mode, SCLK generated dividing base CPUCLK
Bits
Bits
Important Note Comm Modes (SPI Master Slave): When configured SPI, (SPI 1-Table 52), input/output direction pins P1.3, P1.5, P1.6 automatically logic. However, P1.4's input/output direction automatically set; must explicitly firmware. Master mode, P1.4 must configured output; Slave mode, P1.4 must configured input
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Table 57.SPI Mode Timing First, CPOL CPHA First CPHA CPOL
SCLK SSEL
Diagram
SSEL
SSEL
SSEL
SCLK SSEL
SCLK SSEL
SCLK SSEL
SSEL
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Table 58.SPI SCLK Frequency SCLK Select CPUCLK Divisor SCLK Frequency when CPUCLK
Registers Free-Running Counter 16-bit free-running counter clocked 4/6-MHz source. read software general-purpose time base. When order byte read, high order byte registered. Reading high order byte reads this register allowing read 16-bit value atomically (loads bits time). free-running timer generates interrupt 1024-µs rate. also generate interrupt when free-running counter overflow occurs-every 16.384 This allows extending length timer software.
Timer Registers
timer functions CYRF69213 provided single timer block. timer block asynchronous from clock.
Figure 16-Bit Free-Running Counter Block Diagram
verflow Interrupt
apture lock
16-bit unning ounter
1024-µs Interrupt
Table 59.Free-Running Timer Low-Order Byte (FRTMRL) [0x20] [R/W]
Field Read/Write Default Bits
Free-running Timer [7:0]
Free-running Timer [7:0]
This register holds low-order byte 16-bit free-running timer. Reading this register causes high-order byte moved into holding register allowing automatic read bits simultaneously. reads, actual read occurs cycle when order read. writes, actual time write occurs cycle when high order written When reading free-running timer, low-order byte should read first high-order second. When writing, low-order byte should written first then high-order byte
Table 60.Free-Running Timer High-Order Byte (FRTMRH) [0x21] [R/W]
Field Read/Write Default Bits
Free-running Timer [15:8]
Free-running Timer [15:8]
When reading free-running timer, low-order byte should read first high-order second. When writing, low-order byte should written first then high-order byte
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Table 61.Programmable Interval Timer (PITMRL) [0x26]
Field Read/Write Default Bits
Prog Interval Timer [7:0]
`Prog Interval Timer [7:0]
This register holds low-order byte 12-bit programmable interval timer. Reading this register causes high-order byte moved into holding register allowing automatic read bits simultaneously
Table 62.Programmable Interval Timer High (PITMRH) [0x27]
Field Read/Write Default Bits Bits Reserved Prog Internal Timer [11:8] Reserved
Prog Interval Timer [11:8]
This register holds high-order nibble 12-bit programmable interval timer. Reading this register returns high-order nibble 12-bit timer instant that low-order byte last read
Table 63.Programmable Interval Reload (PIRL) [0x28] [R/W]
Field Read/Write Default Bits Prog Interval [7:0]
Prog Interval [7:0]
This register holds lower bits timer. While writing into 12-bit reload register, write lower byte first then higher nibble
Table 64.Programmable Interval Reload High (PIRH) [0x29] [R/W]
Field Read/Write Default Bits Bits Reserved Prog Interval [11:8] Reserved
Prog Interval[11:8]
This register holds higher bits timer. While writing into 12-bit reload register, write lower byte first then higher nibble
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Figure 16-Bit Free-Running Counter Loading Timing Diagram
clk_sys write
valid addr write data reload ready Timer Prog Timer reload interrupt 12-bit programmable timer load timing Capture timer free running counter load free running counter
00A0 00A1 00A2 00A3 00A4 00A5 00A6 00A7 00A8 00A9 00AB 00AC 00AD 00AE 00AF 00B0 00B1 00B2 ACBE ACBF ACC0
16-bit free running counter loading timing
Figure Memory Mapped Registers Read/Write Timing Diagram
clk_sys rd_wrn
Valid Addr rdata wdata Memory mapped registers Read/Write timing diagram
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Interrupt Controller
interrupt controller associated registers allow user's code respond interrupt from almost every functional block CYRF69213 devices. registers associated with interrupt controller allow interrupts disabled either globally individually. registers also provide mechanism which user clear pending posted interrupts, clear individual posted pending interrupts. following table lists interrupts priorities that available CYRF69213. Table 65.Interrupt Numbers, Priorities, Vectors Interrupt Priority Interrupt Address 0000h 0004h 0008h 000Ch 0010h 0014h 0018h 001Ch 0020h 0024h 0028h 002Ch 0030h 0034h 0038h 003Ch 0040h Reset POR/LVD INT0 Transmitter Empty Receiver Full GPIO Port GPIO Port INT1 Reset Active 1-ms Interval timer Programmable Interval Timer Reserved Reserved Name
Table 65.Interrupt Numbers, Priorities, Vectors (continued) Interrupt Priority Interrupt Address 0044h 0048h 004Ch 0050h 0054h 0058h 005Ch 0060h 0064h INT2 Reserved GPIO Port Reserved Reserved Reserved Reserved Sleep Timer Name 16-bit Free Running Timer Wrap
Architectural Description interrupt posted when interrupt conditions occur. This results flip-flop Figure clocking `1'. interrupt will remain posted until interrupt taken until cleared writing appropriate INT_CLRx register. posted interrupt pending unless enabled setting interrupt mask appropriate INT_MSKx register). pending interrupts processed Priority Encoder determine highest priority interrupt which will taken Global Interrupt Enable CPU_F register. Disabling interrupt clearing interrupt mask INT_MSKx register) does clear posted interrupt, does prevent interrupt from being posted. simply prevents posted interrupt from becoming pending. Nested interrupts accomplished re-enabling interrupts inside interrupt service routine. this, Flag Register. block diagram CYRF69213 Interrupt Controller shown Figure
Figure Interrupt Controller Block Diagram
Interrupt Taken INT_CLRx Write Posted Interrupt Pending Interrupt
Priority Encoder
Interrupt Vector
Interrupt Request Core
Interrupt Source (Timer, GPIO, etc.) INT_MSKx Mask Setting
CPU_F[0]
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Interrupt Processing sequence events that occur during interrupt processing follows: interrupt becomes active, either because: interrupt condition occurs (for example, timer expires). previously posted interrupt enabled through update interrupt mask register. interrupt pending from Flag register. current executing instruction finishes. internal interrupt dispatched, taking cycles. During this time, following actions occur: Program Counter Flag registers (CPU_PC CPU_F) stored onto program stack automatic CALL instruction cycles) generated during interrupt acknowledge process. PCH, PCL, Flag register (CPU_F) stored onto program stack that order) automatic CALL instruction cycles) generated during interrupt acknowledge process. CPU_F register then cleared. Since this clears additional interrupts temporarily disabled (PC[15:8]) cleared zero. interrupt vector read from interrupt controller value placed into (PC[7:0]). This sets program counter point appropriate address interrupt table (for example, 0004h POR/LVD interrupt). Program execution vectors interrupt table. Typically, LJMP instruction interrupt table sends execution user's Interrupt Service Routine (ISR) this interrupt. executes. Note that interrupts disabled since ISR, interrupts re-enabled desired Table Interrupt Clear (INT_CLR0) [0xDA] [R/W]
Field Read/Write Default GPIO Port Sleep Timer INT1
setting (care must taken avoid stack overflow). ends with RETI instruction which restores Program Counter Flag registers (CPU_PC CPU_F). restored Flag register re-enables interrupts, since again. Execution resumes next instruction, after that occurred before interrupt. However, there more pending interrupts, subsequent interrupts will processed before next normal program instruction. Interrupt Latency time between assertion enabled interrupt start calculated from following equation. Latency Time current instruction finish Time internal interrupt routine execute Time LJMP instruction interrupt table execute. example, 5-cycle instruction executing when interrupt becomes active, total number clock cycles before begins would follows: cycles finish) cycles interrupt routine) cycles LJMP) cycles. example above, MHz, clock cycles take 1.042 Interrupt Registers Interrupt Registers discussed following sections. Interrupt Clear Register Interrupt Clear Registers (INT_CLRx) used enable individual interrupt sources' ability clear posted interrupts. When INT_CLRx register read, bits that indicates interrupt been posted that hardware resource. Therefore, reading these registers gives user ability determine posted interrupts.
Receive
Transmit
INT0
POR/LVD
GPIO Port
When reading this register, There's posted interrupt corresponding hardware Posted interrupt corresponding hardware present Writing bits will clear posted interrupts corresponding hardware. Writing bits ENSWINT (Bit INT_MSK3 Register) will post corresponding hardware interrupt
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Table Interrupt Clear (INT_CLR1) [0xDB] [R/W]
Field Read/Write Default Reserved Prog Interval Timer 1-ms Timer Active Reset
When reading this register, There's posted interrupt corresponding hardware Posted interrupt corresponding hardware present Writing bits will clear posted interrupts corresponding hardware. Writing bits ENSWINT (Bit INT_MSK3 Register) will post corresponding hardware interrupt Reserved
Table 68.Interrupt Clear (INT_CLR2) [0xDC] [R/W]
Field Read/Write Default Reserved Reserved Reserved GPIO Port Reserved INT2 16-bit Counter Wrap Reserved
When reading this register, There's posted interrupt corresponding hardware Posted interrupt corresponding hardware present Writing bits will clear posted interrupts corresponding hardware. Writing bits ENSWINT (Bit INT_MSK3 Register) will post corresponding hardware interrupt Bits 7,6,5,3,0 Reserved
Interrupt Mask Registers Interrupt Mask Registers (INT_MSKx) used enable individual interrupt sources' ability create pending interrupts. There four Interrupt Mask Registers (INT_MSK0, INT_MSK1, INT_MSK2, INT_MSK3), which referred general INT_MSKx. cleared, each INT_MSKx register prevents posted interrupt from becoming pending interrupt (input priority encoder). However, interrupt still post even mask zero. INT_MSKx bits independent other INT_MSKx bits. INT_MSKx set, interrupt source associated with that mask generate interrupt that will become pending interrupt. Table 69.Interrupt Mask (INT_MSK3) [0xDE] [R/W]
Field Read/Write Default ENSWINT
Enable Software Interrupt (ENSWINT) INT_MSK3[7] determines individual value written INT_CLRx register interpreted. When cleared, writing INT_CLRx register effect. However, writing INT_CLRx register, when ENSWINT cleared, will cause corresponding interrupt clear. ENSWINT set, written INT_CLRx registers ignored. However, written INT_CLRx register, while ENSWINT set, will cause interrupt post corresponding interrupt. Software interrupts debugging interrupt service routines eliminating need create system level interactions that sometimes necessary create hardware-only interrupt.
Reserved
Enable Software Interrupt (ENSWINT) Disable. Writing INT_CLRx register, when ENSWINT cleared, will cause corresponding interrupt clear Enable. Writing INT_CLRx register, when ENSWINT set, will cause corresponding interrupt post Reserved
Bits
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Table 70.Interrupt Mask (INT_MSK2) [0xDF] [R/W]
Reserved Field Read/Write Default Reserved Reserved Reserved GPIO Port Interrupt Enable Mask GPIO Port interrupt Unmask GPIO Port interrupt Reserved INT2 Interrupt Enable Mask INT2 interrupt Unmask INT2 interrupt 16-bit Counter Wrap Interrupt Enable Mask 16-bit Counter Wrap interrupt Unmask 16-bit Counter Wrap interrupt Reserved Reserved Reserved GPIO Port Enable Reserved INT2 Enable 16-bit Counter Wrap Enable Reserved
Table 71.Interrupt Mask (INT_MSK1) [0xE1] [R/W]
Reserved Field Read/Write Default Reserved Prog Interval Timer Interrupt Enable Mask Prog Interval Timer interrupt Unmask Prog Interval Timer interrupt 1-ms Timer Interrupt Enable Mask 1-ms interrupt Unmask 1-ms interrupt Active Interrupt Enable Mask Active interrupt Unmask Active interrupt Reset Interrupt Enable Mask Reset interrupt Unmask Reset interrupt Interrupt Enable Mask interrupt Unmask interrupt Interrupt Enable Mask interrupt Unmask interrupt Interrupt Enable Mask interrupt Unmask interrupt Prog Interval Timer Enable 1-ms Timer Enable Active Enable Reset Enable Enable Enable Enable
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Table Interrupt Mask (INT_MSK0) [0xE0] [R/W]
Field Read/Write Default GPIO Port Enable Sleep Timer Enable INT1 Enable GPIO Port Enable Receive Enable Transmit Enable INT0 Enable POR/LVD Enable
GPIO Port Interrupt Enable Mask GPIO Port interrupt Unmask GPIO Port interrupt Sleep Timer Interrupt Enable Mask Sleep Timer interrupt Unmask Sleep Timer interrupt INT1 Interrupt Enable Mask INT1 interrupt Unmask INT1 interrupt GPIO Port Interrupt Enable Mask GPIO Port interrupt Unmask GPIO Port interrupt Receive Interrupt Enable Mask Receive interrupt Unmask Receive interrupt Transmit Interrupt Enable Mask Transmit interrupt Unmask Transmit interrupt INT0 Interrupt Enable Mask INT0 interrupt Unmask INT0 interrupt POR/LVD Interrupt Enable Mask POR/LVD interrupt Unmask POR/LVD interrupt
Interrupt Vector Clear Register Table 73.Interrupt Vector Clear Register (INT_VC) [0xE2] [R/W]
Field Read/Write Default
Pending Interrupt [7:0]
Interrupt Vector Clear Register (INT_VC) holds interrupt vector highest priority pending interrupt when read, when written will clear pending interrupts Bits Pending Interrupt [7:0] 8-bit data value holds interrupt vector highest priority pending interrupt. Writing this register will clear pending interrupts
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Transceiver
Transceiver Configuration Table 74.USB Transceiver Configure Register (USBXCR) [0x74] [R/W]
Field Read/Write Default Pull-up Enable Reserved Force State
Pull-up Enable Disable pull-up resistor Enable pull-up resistor This pull-up VREG enabled internally generated 3.3V when VREG enabled Reserved Force State This allows state pins forced state while enabled Disable Force State Enable Force State. Allows pins controlled P1.1 P1.0 respectively when USBIO mode. Refer Table more information
Bits
Note transceiver dedicated 3.3V regulator signalling purposes provide 1.5K pull Unlike other 3.3V regulator, this regulator cannot controlled/accessed firmware. When device suspended, this regulator disabled along with bandgap (which provides reference voltage regulator) line pulled through alternate 6.5K resistor. During wakeup following suspend, band regulator switched order. Under extremely rare case when device wakes following reset condition voltage regulator band turn that particular order, there possibility glitch/low pulse occurring line. host misinterpret this deattach condition. This condition, although rare, avoided keeping bandgap circuitry enabled during sleep. This achieved setting Buzz' bit, bit[5] OSC_CR0 register. This issue only device sleep during reset condition
VREG Control Table 75.VREG Control Register (VREGCR) [0x73] [R/W]
Field Read/Write Default Bits Reserved Keep Alive Keep Alive when allows voltage regulator source current when voltage regulator disabled, P12CR[0],P12CR[7] should cleared. Disabled Enabled VREG Enable This turns 3.3V voltage regulator. voltage regulator only functions within specifications when above 4.35V. This block should enabled when below 4.35V-although damage irregularities will occur enabled below 4.35V Disable 3.3V voltage regulator output VREG/P1.2 Enable 3.3V voltage regulator output VREG/P1.2 pin. GPIO functionality P1.2 disabled Reserved Keep Alive VREG Enable
Note alternate drive pins P1.3-P1.6 requires that VREG Enable enable regulator provide alternate voltage
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Serial Interface Engine (SIE)
allows microcontroller communicate with host low-speed data rates (1.5 Mbps). simplifies interface between microcontroller incorporating hardware that handles following activity independently microcontroller: Translating encoded received data formatting data transmitted checking generation. Flagging microcontroller errors exist during transmission Address checking. Ignoring transactions addressed device Sending appropriate ACK/NAK/STALL handshakes
Identifying token type (SETUP, OUT). Setting appropriate token once valid token received Placing valid received data appropriate endpoint FIFOs Sending updating data toggle (Data1/0) stuffing/unstuffing. Firmware required handle rest interface with following tasks: Coordinate enumeration decoding device requests Fill empty FIFOs Suspend/Resume coordination Verify select Data toggle values
Device
Table 76.USB Device Address (USBCR) [0x40] [R/W]
Field Read/Write Default Enable Device Address[6:0]
content this register cleared when Reset condition occurs Enable This must enabled firmware before serial interface engine (SIE) will respond traffic address specified Device Address [6:0]. When this cleared, transceiver enters power-down state. User's firmware should clear this prior entering sleep mode save power Disable device address transceiver into power-down state Enable device address transceiver into normal operating mode Device Address [6:0] These bits must firmware during enumeration process (for example, SetAddress) non-zero address assigned host
Bits
Table 77.Endpoint Count (EP0CNT-EP2CNT) [0x41, 0x43, 0x45] [R/W]
Field Read/Write Default Data Toggle Data Valid Reserved
Byte Count[3:0]
Data Toggle This selects DATA packet's toggle state. transactions, firmware must this select transmitted Data Toggle. SETUP transactions, hardware sets this state received Data Toggle bit. DATA0 DATA1 Data Valid This used SETUP tokens only. This cleared CRC, bitstuff, errors have occurred. This does update some endpoint mode settings Data invalid. enabled, endpoint interrupt will occur even invalid data received Data valid Reserved Byte Count [3:0] Byte Count Bits indicate number data bytes transaction: transactions, firmware loads count with number bytes transmitted host from endpoint FIFO. Valid values inclusive. SETUP transactions, count updated hardware number data bytes received, plus bytes. Valid values 2-10 inclusive.
Bits Bits
Endpoint Count Register, whenever count updates from SETUP transaction, count register locks cannot written CPU. Reading register unlocks This prevents firmware from overwriting status update
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Endpoint Mode Because both firmware allowed write Endpoint Mode Count Registers provides interlocking mechanism prevent accidental overwriting data. Table 78.Endpoint Mode (EP0MODE) [0x44] [R/W]
Field Read/Write Default Setup Received R/C[3] Received R/C[3]
When writes these registers they locked processor cannot write them until after read them. Writing this register clears upper four bits regardless value written.
Mode[3:0]
Received ACK'd Trans R/C[3] R/C[3]
SETUP Received This hardware when valid SETUP packet received. forced HIGH from start data packet phase SETUP transactions until data phase control write transfer cannot cleared during this interval. While this `1', cannot write FIFO. This prevents firmware from overwriting incoming SETUP transaction before firmware chance read SETUP data This cleared non-locked writes register SETUP received SETUP received Received This bit, when set, indicates valid packet been received. This updated after host acknowledges data packet.When clear, indicates that either been received that host didn't acknowledge data sending handshake This cleared non-locked writes register. received received Received This bit, when set, indicates valid packet been received ACKed. This updated after last received packet transaction. When clear, indicates received This cleared non-locked writes register received received ACK'd Transaction ACK'd transaction whenever engages transaction register's endpoint that completes with packet This cleared non-locked writes register transaction completes with transaction does complete with Mode [3:0] endpoint modes determine responds traffic that host sends endpoint. mode controls responds traffic will change mode that endpoint result host packets endpoint
Bits
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Table 79.Endpoint Mode (EP1MODE EP2MODE) [0x45, 0x46] [R/W]
Field Read/Write Default Stall Reserved Enable ACK'd Transaction (Note Mode[3:0]
Stall When this will stall packet Mode Bits ACK-OUT, will stall packet mode bits ACK-IN. This must clear other modes Reserved Enable This bit, when set, causes endpoint interrupt generated even when transfer completes with NAK. Unlike enCoRe, CYRF69213 family members generate endpoint interrupt under these conditions unless this Disable interrupt NAK'd transactions Enable interrupt NAK'd transaction ACK'd Transaction ACK'd transaction whenever engages transaction register's endpoint that completes with packet This cleared writes register transaction does complete with transaction completes with Mode [3:0] endpoint modes determine responds traffic that host sends endpoint. mode controls responds traffic will change mode that endpoint result host packets endpoint.
Bits
Note When writes EP1MODE EP2MODE register blocks firmware writes EP2MODE EP1MODE registers, respectively both writes occur same clock cycle). This because design employs only common `update' signal both EP1MODE EP2MODE registers. Thus, when writes EP1MODE register, update signal this prevents firmware writes EP2MODE register. writes endpoint mode registers have higher priority than firmware writes. This mode register write block situation endpoints incorrect modes. Firmware must read EP1/2MODE registers immediately following firmware write rewrite value read incorrect
Endpoint Data Buffers three data buffers used hold data both transactions. Each data buffer bytes long. reset values Endpoint Data Registers unknown. Unlike past enCoRe parts data buffers only accessible space processor. Table 80.Endpoint Data (EP0DATA) [0x50-0x57] [R/W]
Field Read/Write Default Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown
Endpoint Data Buffer [7:0]
Endpoint buffer comprised bytes located address 0x50 0x57
Table 81.Endpoint Data (EP1DATA) [0x58-0x5F] [R/W]
Field Read/Write Default Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown
Endpoint Data Buffer [7:0]
Endpoint 1buffer comprised bytes located address 0x58 0x5F
Document 001-07552 Rev.
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CYRF69213
Table 82.Endpoint Data (EP2DATA) [0x60-0x67] [R/W]
Field Read/Write Default Unknown Unknown Unknown Unknown Unknown Unknown Unknown Unknown
Endpoint Data Buffer [7:0]
Endpoint buffer comprised bytes located address 0x60 0x67
Mode Tables
Mode DISABLE IN/OUT STATUS ONLY STALL IN/OUT STATUS ONLY STATUS STATUS (STALL (STALL (STALL (STALL Reserved Reserved Reserved Reserved Reserved Encoding 0000 0001 0010 0011 0110 1011 1111 SETUP Ignore Accept Accept Accept Accept Accept Accept Ignore STALL STALL byte byte Count Ignore Check STALL STALL Check Comments Ignore traffic this endpoint. Used Data Control endpoints token. Control endpoint only STALL zero byte OUT. Control endpoint only STALL token. Control endpoint only STALL send zero byte data token. Control endpoint only token send zero byte data token. Control endpoint only Respond data Status OUT. Control endpoint only
1000 1001 1001 1100 1101 1101 0101 0111 1010 0100 1110
Ignore Ignore Ignore Ignore Ignore Ignore Ignore Ignore Ignore Ignore Ignore
Ignore Ignore Ignore Count STALL Ignore Ignore Ignore Ignore Ignore
STALL Ignore Ignore Ignore Ignore Ignore Ignore Ignore Ignore
Send handshake token. Data endpoint only This mode changed mode 1000 issuance handshake OUT. Data endpoint only STALL transfer Send handshake token. Data endpoint only This mode changed mode 1100 after receiving handshake data. Data endpoint only STALL transfer. Data endpoint only These modes supported SIE. Firmware should this mode Control Data endpoints
Mode Column 'Mode' column contains mnemonic names given mode
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