AFETG core Internal regulator charge pump circuitry Compatibility with
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12-Bit Signal Processor with Precision TimingGenerator AD9992
AFETG core Internal regulator charge pump circuitry Compatibility with systems programmable vertical clock outputs Correlated double sampler (CDS) with gain 10-bit variable gain amplifier (VGA) 12-bit, Black level clamp with variable level control Complete on-chip timing generator Precision Timing core with resolution On-chip horizontal drivers General-purpose outputs (GPOs) shutter system support On-chip driver external crystal On-chip sync generator with external sync input 105-lead CSP_BGA package, 0.65 pitch
AD9992 highly integrated signal processor digital still camera applications. includes complete analog front with conversion combined with full-function programmable timing generator. timing generator capable supporting vertical clock signals control advanced CCDs. Precision Timing core allows adjustment high speed clocks with approximately resolution operation. AD9992 also contains eight generalpurpose input/outputs, which used shutter system functions. AD9992 specified pixel rates MHz. analog front includes black level clamping, CDS, VGA, 12-bit analog-to-digital converter (ADC). timing generator provides necessary clocks: H-clocks, V-clocks, sensor gate pulses, substrate clock, substrate bias control. Operation programmed using 3-wire serial interface. AD9992 specified over operating temperature range -25°C +85°C.
APPLICATIONS
Digital still cameras
FUNCTIONAL BLOCK DIAGRAM
REFT REFB
AD9992
42dB CCDIN -3dB, 0dB, +3dB, +6dB INPUT 1.8V OUTPUT 1.8V INPUT OUTPUT XV24 XSUBCK VERTICAL TIMING CONTROL
05891-001
VREF 12-BIT
DOUT
CLAMP
CHARGE PUMP
INTERNAL CLOCKS
HORIZONTAL DRIVERS
PRECISION TIMING GENERATOR
INTERNAL REGISTERS SDATA
SYNC GENERATOR
GPO1 GPO8
SYNC
Figure
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
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AD9992 TABLE CONTENTS
Features Applications. General Description Functional Block Diagram Specifications. Digital Specifications Analog Specifications. Timing Specifications Absolute Maximum Ratings. Package Thermal Characteristics Caution. Configuration Function Descriptions. Terminology Typical Performance Characteristics Equivalent Circuits System Overview High Speed Precision Timing Core. Horizontal Clamping Blanking. Horizontal Timing Sequence Example. Vertical Timing Generation Vertical Sequences (VSEQ) Vertical Timing Example. Shutter Timing Control Substrate Clock Operation (SUBCK) Field Counters. General-Purpose Outputs (GPOS) Look-Up Tables (LUT). Complete Exposure/Readout Operation Using Primary Counter Signals Manual Shutter Operation Using Enhanced SYNC Modes Analog Front-End Description Operation. Power-Up Sequence Master Mode. Standby Mode Operation Frequency Change. Circuit Layout Information. Serial Interface Timing Layout Internal Registers Updating Register Values Complete Register Listing Outline Dimensions Ordering Guide
REVISION HISTORY
1/06-Revision Initial Version
Rev. Page
AD9992 SPECIFICATIONS
Table
Parameter TEMPERATURE RANGE Operating Storage POWER SUPPLY VOLTAGE INPUTS AVDD (AFE Analog Supply) TCVDD (Timing Core Supply) CLIVDD (CLI Input Supply) RGVDD (RG, Driver) HVDD Drivers) DVDD (Digital Logic) DRVDD (Parallel Data Output Drivers) IOVDD (Digital I/O) XVVDD (Vertical Output Drivers) CP1P8 Supply Input) LDOIN (LDO Supply Input) POWER SUPPLY CURRENTS-40 OPERATION AVDD (1.8 TCVDD (1.8 CLIVDD RGVDD (3.3 Load, Load) HVDD (3.3 Total Load DVDD (1.8 DRVDD Load Each DOUT Pin) IOVDD Depends Load Output Frequency Digital I/O) XVVDD Depends Load Output Frequency Signals) POWER SUPPLY CURRENTS-STANDBY MODE OPERATION Standby1 Mode Standby2 Mode Standby3 Mode MAXIMUM CLOCK RATE (CLI)
2.25
+150
Unit
total power dissipated HVDD RGVDD) supply approximated using equation Total HVDD Power HVDD Pixel Frequency] HVDD Reducing capacitive load and/or reducing HVDD supply reduces power dissipation. total capacitance seen H-outputs.
Rev. Page
AD9992
DIGITAL SPECIFICATIONS
IOVDD RGVDD HVDD TMIN TMAX, unless otherwise noted. Table
Parameter LOGIC INPUTS (IOVDD) High Level Input Voltage Level Input Voltage High Level Input Current Level Input Current Input Capacitance LOGIC OUTPUTS (IOVDD, XVDD) High Level Output Voltage Level Output Voltage H-DRIVER OUTPUTS (HVDD, RGVDD) High Level Output Voltage Maximum Current Level Output Voltage Maximum Current Maximum Output Current (Programmable) Maximum Load Capacitance (for Each Output) Symbol Unit
Rev. Page
AD9992
ANALOG SPECIFICATIONS
AVDD fCLI MHz, typical timing specifications, TMIN TMAX, unless otherwise noted. Table
Parameter Allowable Reset Transient Gain Accuracy -3.0 Gain Gain Gain Gain Maximum Input Range Before Saturation Gain Gain Gain Gain Allowable Pixel Amplitude1 Gain (Default) Gain VARIABLE GAIN AMPLIFIER (VGA) Gain Control Resolution Gain Monotonicity Gain Range Gain (VGA Code Default) Maximum Gain (VGA Code 1023) BLACK LEVEL CLAMP Clamp Level Resolution Clamp Level Minimum Clamp Level (Code Maximum Clamp Level (Code 1023) Resolution Differential Nonlinearity (DNL) Missing Codes Integral Nonlinearity (INL) Full-Scale Input Voltage VOLTAGE REFERENCE Reference Voltage (REFT) Reference Bottom Voltage (REFB) SYSTEM PERFORMANCE Gain Accuracy Gain (VGA Code Maximum Gain (VGA Code 1023) Peak Nonlinearity, Input Signal Total Output Noise Power Supply Rejection (PSR)
-2.3 +0.5
Unit
Notes
gain (Code default value) -3.3 -0.5 -2.8 -100 +200 +100 1024 Guaranteed 42.4 1024 -1.0 gain (Code default value) Steps
Steps Measured output Bits Includes entire signal chain gain Gain (0.0358 Code) 5.76 gain, gain applied AC-grounded input, gain applied Measured with step change supply
±0.5 +1.0 Guaranteed
41.9
42.4
42.9
Input signal characteristics defined follows:
05891-002
500mV RESET TRANSIENT 200mV OPTICAL BLACK PIXEL
INPUT SIGNAL RANGE (0dB GAIN)
Rev. Page
AD9992
TIMING SPECIFICATIONS
AVDD DVDD TCVDD DRVDD fCLI MHz, unless otherwise noted. Table
Parameter MASTER CLOCK (See Figure Clock Period High/Low Pulse Width Delay from Rising Edge Internal Pixel Position FALLING EDGE FALLING EDGE SLAVE MODE (See Figure CLPOB PULSE WIDTH (See Figure Figure SAMPLE LOCATION (See Figure Figure 18)1 Sample Edge Sample Edge DATA OUTPUTS (See Figure Figure Output Delay from DCLK Rising Edge Inhibited Area DOUTPHASE Edge Location Pipeline Delay from SHP/SHD Sampling DOUT SERIAL INTERFACE (See Figure Maximum Frequency (Must Exceed Frequency) Setup Time Hold Time SDATA Valid Rising Edge Setup Falling Edge SDATA Valid Hold
Symbol tCONV tCLIDLY tVDHD
Unit Pixels Edge location Cycles
12.5 12.5
period tCONV
tDOUTINH
SHDLOC
SHDLOC
fSCLK
Parameter programmable. Minimum CLPOB pulse width functional operation only. Wider typical pulses recommended achieve good clamp performance.
Rev. Page
AD9992 ABSOLUTE MAXIMUM RATINGS
Table
Parameter AVDD TCVDD HVDD RGVDD DVDD DRVDD IOVDD XVVDD CLIVDD CP1P8 Output Output Digital Outputs Digital Inputs SCK, SDATA REFT, REFB, CCDIN Junction Temperature Lead Temperature, With Respect AVSS TCVSS HVSS RGVSS DVSS DRVSS DVSS DVSS TCVSS CPVSS RGVSS HVSS DVSS DVSS DVSS AVSS Rating -0.3 +2.0 -0.3 +2.0 -0.3 +3.9 -0.3 +3.9 -0.3 +2.0 -0.3 +3.9 -0.3 +3.9 -0.3 +3.9 -0.3 +3.9 -0.3 +2.0 -0.3 RGVDD -0.3 HVDD -0.3 IOVDD -0.3 IOVDD -0.3 IOVDD -0.3 AVDD 150°C 350°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
PACKAGE THERMAL CHARACTERISTICS
Thermal Resistance CSP_BGA package: 40.3°C/W
CAUTION
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this product features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Rev. Page
AD9992 CONFIGURATION FUNCTION DESCRIPTIONS
CORNER INDEX AREA VIEW (Not Scale)
05891-003
AD9992
Figure Configuration
Table Function Descriptions
Mnemonic GPO8 GPO7 GPO6 GPO5 GPO4 GPO3 GPO2 GPO1 SYNC Type Description General-Purpose Output General-Purpose Output General-Purpose Output General-Purpose Output General-Purpose Output General-Purpose Output General-Purpose Output General-Purpose Output External System Sync Input Vertical Sync Pulse (input slave mode, output master mode) Horizontal Sync Pulse (input slave mode, output master mode) External Reset Input (active pulse reset, internal pull-up resistor) Digital Supply: (GPO, SUBCK, HD/VD, SCK, SDATA, SYNC, RSTB) Digital Ground Output Supply: Substrate Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Mnemonic XV11 XV12 XV13 XV14 XV15 XV16 XV17 XV18 XV19 XV20 XV21 XV22 XV23 XV24 DVDD DVSS DCLK DRVSS Type Description Vertical Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Vertical Clock Digital Logic Supply: Digital Logic Ground Internally Connected Internally Connected Data Output (LSB) Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output Data Output (MSB) Data Clock Output Data Driver Ground
RSTB
IOVDD
IOVSS XVVDD XSUBCK XV10
Rev. Page
AD9992
Mnemonic DRVDD CP3P3 CPFCT CPFCB CPVSS CP1P8 CPCLI LDO3P2EN LDOVSS LDO1P8EN SENSE LDOOUT LDOIN HVSS1 HVDD1 HVSS2 HVDD2 Type Description Data Driver Supply: Charge Pump Output Charge Pump Flying Capacitor Charge Pump Flying Capacitor Bottom Charge Pump Ground Charge Pump Input Charge Pump Clock Input Output Enable Ground Output Enable Output Sense Output Voltage Input Horizontal Clock Horizontal Clock H-Driver Ground H-Driver Supply Horizontal Clock Horizontal Clock Horizontal Clock Horizontal Clock H-Driver Ground H-Driver Supply Horizontal Clock G10, Mnemonic RGVSS RGVDD TCVSS TCVDD CLIVDD AVDD CCDIN AVSS REFT REFB SDATA Type Description Horizontal Clock Last Horizontal Clock Driver Ground Driver Supply: Reset Gate Clock Analog Ground Timing Core Timing Core Supply: Input Supply: 3.3.V Clock Output Crystal Reference Clock Input Supply: Signal Input Analog Supply Ground Voltage Reference Bypass Voltage Reference Bottom Bypass 3-Wire Serial Load Pulse (internal pull-up resistor) 3-Wire Serial Data Input 3-Wire Serial Clock Internally Connected
Rev. Page
AD9992 TERMINOLOGY
Differential Nonlinearity (DNL) ideal exhibits code transitions that exactly apart. deviation from this ideal value. Therefore, every code must have finite width. missing codes guaranteed 12-bit resolution indicates that 4096 codes must present over operating conditions. Peak Nonlinearity Peak nonlinearity, full signal chain specification, refers peak deviation output AD9992 from true straight line. point used zero scale occurs before first code transition. Positive full scale defined level beyond last code transition. deviation measured from middle each particular output code true straight line. error then expressed percentage full-scale signal. input signal always appropriately gained fill ADC's full-scale range. Total Output Noise output noise measured using histogram techniques. standard deviation output codes calculated represents noise level total signal chain specified gain setting. output noise converted equivalent voltage using relationship (ADC Full Scale/2n Codes) where resolution ADC. AD9992, 0.488 Power Supply Rejection (PSR) measured with step change applied supply pins. specification calculated from change data outputs given step change supply voltage.
Rev. Page
AD9992 TYPICAL PERFORMANCE CHARACTERISTICS
POWER (mW)
+3dB
3.0V/1.8V
OUTPUT NOISE (LSB)
3.3V/1.8V
-3dB
FREQUENCY (MHz) 2.7V/1.8V
GAIN (dB)
Figure Power Frequency (AVDD TCVDD DVDD Other Supplies
Figure Output Noise Total Gain (CDS VGA)
(LSB)
-0.2 -0.4 -0.6 -0.8
05891-089
(LSB)
1000
1500
2000 2500 CODE
3000
3500
4000
1000
1500
2000 2500 CODE
3000
3500
4000
Figure Typical Differential Nonlinearity (DNL) Performance
Figure Typical Integral Nonlinearity (INL) Performance
Rev. Page
05891-090
-1.0
05891-006
05891-004
AD9992 EQUIVALENT CIRCUITS
IOVDD
AVDD
05891-008
AVSS
AVSS
IOVSS
Figure CCDIN
Figure Digital Inputs
DVDD
DRVDD
HVDD RGVDD
DATA
05891-010
THREESTATE
DOUT
THREE-STATE
OUTPUT
05891-009
DVSS
DRVSS
HVSS RGVSS
Figure Digital Data Outputs
Figure Drivers
Rev. Page
05891-011
AD9992 SYSTEM OVERVIEW
Figure shows typical system block diagram AD9992 master mode. output processed AD9992's circuitry, which consists CDS, VGA, black level clamp, ADC. digitized pixel information sent digital image processor chip, which performs postprocessing compression. operate CCD, timing parameters programmed into AD9992 from system microprocessor through 3-wire serial interface. From master clock, CLI, provided image processor external crystal, AD9992 generates CCD's horizontal vertical clocks internal clocks. External synchronization provided sync pulse from microprocessor, which resets internal counters resyncs outputs.
V-DRIVER VSUB DOUT
CCDIN
Alternatively, AD9992 operated slave mode. this mode, provided externally from image processor, AD9992 timing synchronized with H-drivers included AD9992, allowing these clocks directly connected CCD. H-driver voltage supported. external V-driver required vertical transfer clocks, sensor gate pulses, substrate clock. AD9992 includes programmable general-purpose outputs (GPO), which trigger mechanical shutter strobe (flash) circuitry. Figure Figure show maximum horizontal vertical counter dimensions AD9992. internal horizontal vertical clocking controlled these counters, which specify line pixel locations. Maximum length 8192 pixels line, maximum length 8192 lines field.
MAXIMUM COUNTER DIMENSIONS
XV24, SUBCK
AD9992
AFETG
DCLK
GPO1 GPO8
DIGITAL IMAGE PROCESSING ASIC
SERIAL INTERFACE
05891-012
SYNC
13-BIT HORIZONTAL 8192 PIXELS
Figure Typical System Block Diagram, Master Mode
13-BIT VERTICAL 8192 LINES
Figure Vertical Horizontal Counters
LENGTH 8192 LINES
LENGTH 8192 PIXELS
Figure Maximum VD/HD Dimensions
Rev. Page
05891-014
05891-013
AD9992
HIGH SPEED PRECISION TIMING CORE
AD9992 generates high speed timing signals using flexible Precision Timing core. This core foundation generating timing used both AFE; includes reset gate horizontal drivers SHP/SHD sample clocks. unique architecture makes routine system designer optimize image quality providing precise control over horizontal readout correlated double sampling. high speed timing AD9992 operates same either master slave mode configuration. more information synchronization pipeline delays, Power-Up Sequence Master Mode section. clock programming CLIDIVIDE register (AFE Register Address 0x0D). AD9992 then internally divides frequency AD9992 includes master clock output, CLO, which inverse CLI. This output should used crystal driver. crystal placed between pins generate master clock AD9992.
High Speed Clock Programmability
Figure shows when high speed clocks SHP, generated. pulse programmable rising falling edges inverted using polarity control. Horizontal Clock programmable rising falling edges polarity control. HCLK Mode equal always inverses edge location registers each bits wide, allowing selection edge locations. Figure shows default timing locations high speed clock signals.
Timing Resolution
Precision Timing core uses master clock input reference (CLI). This clock should same pixel clock frequency. Figure illustrates internal timing core divides master clock period into steps edge positions. Using frequency, edge resolution Precision Timing core approximately system clock available, possible reference
POSITION P[0] P[16] P[32]
P[48]
P[64] P[0]
tCLIDLY
PIXEL PERIOD
Figure High Speed Clock Resolution from CLI, Master Clock Input
SIGNAL
PROGRAMMABLE CLOCK POSITIONS:
Figure High Speed Clock Programmable Locations (HCLKMODE 001)
Rev. Page
05891-016
1SHP SAMPLE LOCATION. 2SHD SAMPLE LOCATION. RISING EDGE. FALLING EDGE. RISING EDGE. FALLING EDGE. RISING EDGE. FALLING EDGE.
05891-015
NOTES PIXEL CLOCK PERIOD DIVIDED INTO POSITIONS, PROVIDING FINE EDGE RESOLUTION HIGH SPEED CLOCKS. THERE FIXED DELAY FROM INPUT INTERNAL PIXEL PERIOD POSITION (tCLIDLY).
AD9992
H-Driver Outputs
addition programmable timing positions, AD9992 features on-chip output drivers outputs. These drivers powerful enough drive inputs directly. H-driver current adjusted optimum rise/fall time particular load using drive strength control registers (Addresses 0x35 0x36). 3-bit drive setting each output adjustable increments: three-state; 12.9 17.2 shown Figure when HCLK Mode used, outputs inverses outputs, respectively. Using HCLKMODE register (Address 0x23, Bits [9:7]), possible select different configuration. Table shows comparison different programmable settings each HCLK mode. Figure Figure show settings HCLK Mode HCLK Mode respectively. Note that recommended that outputs AD9992 used together maximum flexibility drive strength settings. typical with inputs should only have AD9992's outputs connected together drive CCD's outputs connected together drive CCD's Similarly, with inputs should have connected CCD's connected CCD's connected CCD's connected CCD's
Table Timing Core Register Parameters SHP,
Parameter Polarity Positive Edge Negative Edge Sampling Location Drive Strength Length Range High/low edge location edge location edge location current steps Description Polarity control inversion, inversion) Positive edge location Negative edge location Sampling location internal signals Drive current outputs (4.3 step)
Table HCLK Modes, Selected Address 0x23, Bits [9:7]
HCLKMODE Mode Mode Mode Invalid Selection Register Value 000, 011, 101, 110, Description edges programmable, with inverse edges programmable, with edges programmable, with edges programmable, with inverse edges programmable, with inverse Invalid register settings
Figure HCLK Mode Operation
Rev. Page
05891-017
PROGRAMMABLE LOCATIONS: RISING EDGE. FALLING EDGE. RISING EDGE. FALLING EDGE.
AD9992
PROGRAMMABLE EDGES: RISING EDGE. FALLING EDGE. RISING EDGE. FALLING EDGE.
Figure HCLK Mode Operation
POSITION P[0] P[16] P[32] P[48] P[64] P[0]
PIXEL PERIOD RGr[0] RGf[16]
HLr[0] H1r[0]
HLf[32]
H1f[32]
SHP[32] SIGNAL
SHD[0]
Figure High Speed Timing Default Locations
Digital Data Outputs
AD9992 data output DCLK phase programmable using DOUTPHASE registers (Address 0x38, Bits [11:0]). DOUTPHASEP (Bits [5:0]) selects edge location from shown Figure DOUTPHASEN (Bits [11:6]) does actually program phase data outputs used internally should always programmed value DOUTPHASEP plus edges. example, DOUTPHASEP DOUTPHASEN should (0x20).
Normally, DOUT DCLK signals track phase, based contents DOUTPHASE registers. DCLK output phase also held fixed with respect data outputs changing DCLKMODE register high (Address 0x38, [12]). this mode, DCLK output remains fixed phase equal delayed version while data output phase still programmable. pipeline delay through AD9992 shown Figure After input sampled SHD, there 16-cycle delay until data available.
Rev. Page
05891-019
NOTES SIGNAL EDGES FULLY PROGRAMMABLE POSITIONS WITHIN PIXEL PERIOD. DEFAULT POSITIONS EACH SIGNAL SHOWN. HCLK MODE SHOWN. CONNECT TOGETHER TOGETHER MAXIMUM DRIVE STRENGTH.
05891-018
AD9992
P[0] PIXEL PERIOD P[16] P[32] P[48] P[64] P[0]
DCLK
DOUT
Figure Digital Output Phase Adjustment Using DOUTPHASEP Register
tCLIDLY CCDIN
SAMPLE PIXEL (INTERNAL)
DOUT (INTERNAL)
05891-020
NOTES DATA OUTPUT (DOUT) DCLK PHASE ADJUSTABLE WITH RESPECT PIXEL PERIOD. WITHIN CLOCK PERIOD, DATA TRANSITION PROGRAMMED DIFFERENT LOCATIONS. DCLK INVERTED WITH RESPECT DOUT USING DCLKINV REGISTER.
tDOUTINH
DCLK PIPELINE LATENCY CYCLES DOUT
Figure Digital Data Output Pipeline Delay
Rev. Page
05891-021
NOTES TIMING VALUES SHOWN SHDLOC WITH DCLKMODE HIGHER VALUES AND/OR DOUT PHASE SHIFTS DOUT TRANSITION RIGHT, WITH RESPECT LOCATION. RECOMMENDED VALUE DOUT PHASE SHPLOC EDGES FOLLOWING SHPLOC.
AD9992
HORIZONTAL CLAMPING BLANKING
AD9992's horizontal clamping blanking pulses fully programmable suit variety applications. Individual control provided CLPOB, PBLK, HBLK different regions each field. This allows dark pixel clamping blanking patterns changed each stage readout order accommodate different image transfer timing high speed line shifts.
CLPOB PBLK Masking Areas
Additionally, AD9992 allows CLPOB PBLK signals disabled certain lines field without changing existing CLPOB pattern settings. CLPOB PBLK) masking, CLPMASKSTART (PBLKMASKSTART) CLPMASKEND (PBLKMASKEND) registers programmed specify start lines field where CLPOB (PBLK) patterns ignored. three sets start registers allow three CLPOB (PBLK) masking areas created. CLPOB PBLK masking registers specific certain V-sequence; they always active existing field timing. During operation, disable CLPOB masking feature, these registers must maximum value 0x1FFF value greater than programmed length. Note that disable CLPOB (and PBLK) masking during power-up, recommended CLPMASKSTART (PBLKMASKSTART) 8191 CLPMASKEND (PBLKMASKEND) This prevents accidental masking caused register update events.
Individual CLPOB PBLK Patterns
horizontal timing consists CLPOB PBLK, shown Figure These signals programmed independently using registers Table start polarity CLPOB (and PBLK) signal CLPOBPOL (PBLKPOL), first second toggle positions pulse CLPOBTOG1 (PBLKTOG1) CLPOBTOG2 (PBLKTOG2). Both signals active should programmed accordingly. separate pattern CLPOB PBLK programmed each vertical sequence. described Vertical Timing Generation section, several V-sequences created, each containing unique pulse pattern CLPOB PBLK. Figure shows sequence change positions divide readout field into different regions. assigning different V-sequence each region, CLPOB PBLK signals change with each change vertical timing.
Table CLPOB PBLK Pattern Registers
Register CLPOBPOL PBLKPOL CLPOBTOG1 CLPOBTOG2 PBLKTOG1 PBLKBTOG2 CLPMASKSTART CLPMASKEND PBLKMASKSTART PBLKMASKEND Length Range High/low High/low 8191 pixel location 8191 pixel location 8191 pixel location 8191 pixel location 8191 line location 8191 line location 8191 line location 8191 line location Description Starting polarity CLPOB each V-sequence. Starting polarity PBLK each V-sequence. First CLPOB toggle position within line each V-sequence. Second CLPOB toggle position within line each V-sequence. First PBLK toggle position within line each V-sequence. Second PBLK toggle position within line each V-sequence. CLPOB masking area-starting line within field (maximum three areas). CLPOB masking area-ending line within field (maximum three areas). PBLK masking area-starting line within field (maximum three areas). PBLK masking area-ending line within field (maximum three areas).
Rev. Page
AD9992
CLPOB PBLK ACTIVE
ACTIVE
05891-022
PROGRAMMABLE SETTINGS: 1START POLARITY (CLAMP BLANK REGION ACTIVE LOW). 2FIRST TOGGLE POSITION. 3SECOND TOGGLE POSITION.
Figure Clamp Preblank Pulse Placement
CLPOB SIGNAL LINES
CLPOB SIGNAL LINE
CLPOB
05891-023
CLPMASKSTART1
CLPMASKEND1
CLPMASKSTART2 CLPMASKEND2
Figure CLPOB Masking Example
Rev. Page
AD9992
Individual HBLK Patterns
HBLK programmable timing shown Figure similar CLPOB PBLK; however, there start polarity control. Only toggle positions used designate start stop positions blanking period. Additionally, there separate masking polarity controls that designate polarity horizontal clock signals during blanking period. Setting HBLKMASK_H1 high sets therefore during blanking, shown Figure with CLPOB PBLK signals, HBLK registers available each V-sequence, allowing different blanking signals used with different vertical timing sequences. AD9992 supports three modes HBLK operation. HBLK Mode supports basic operation some support special HBLK patterns. HBLK Mode supports pixel mixing HBLK operation. HBLK Mode supports advanced HBLK operation. following sections describe each mode detail. Register parameters described detail Table
HBLK Mode Operation
There toggle positions available HBLK. Normally, only toggle positions used generate standard HBLK interval. However, additional toggle positions used generate special HBLK patterns, shown Figure pattern this example uses toggle positions generate extra groups pulses during HBLK interval. changing toggle positions, different patterns created. Separate toggle positions available even lines. alternation needed, same values should loaded into registers even (HBLKTOGE) (HBLKTOGO) lines.
HBLKTOGE1 HBLKTOGE2
BASIC HBLK PULSE GENERATED USING HBLKTOGE1 HBLKTOGE2 REGISTERS (HBLKALT
Figure Typical Horizontal Blanking Pulse Placement (HBLKMODE
HBLK
H1/H3/H5/H7
POLARITY H1/H3/H5/H7 DURING BLANKING PROGRAMMABLE (H2/H4/H6/H8 SEPARATELY PROGRAMMABLE) H1/H3/H5/H7
05891-025
H2/H4/H6/H8
Figure HBLK Masking Polarity Control
HBLKTOGE2 HBLKTOGE1 HBLKTOGE4 HBLKTOGE3 HBLKTOGE6 HBLKTOGE5
HBLK
H1/H3
H2/H4
SPECIAL H-BLANK PATTERN CREATED USING MULTIPLE HBLK TOGGLE POSITIONS (HBLKALT
Figure Using Multiple Toggle Positions HBLK (HBLKMODE
Rev. Page
05891-026
05891-024
HBLK
BLANK
BLANK
AD9992
Table HBLK Pattern Registers
Register HBLKMODE Length Range HBLK modes Description Enables different HBLK toggle position operation. normal mode. toggle positions available even lines. even/odd alternation needed, toggles even/odd same. pixel mixing mode. addition toggle positions, HBLKSTART, HBLKEND, HBLKLEN, HBLKREP registers used generate HBLK patterns. even/odd alternation need, toggles even/odd same. advanced HBLK mode. Divides HBLK interval into repeat areas. Uses HBLKSTARTA/B/C RA*H*REPA/B/C registers. test mode only. access. Start location HBLK HBLK Mode HBLK Mode location HBLK HBLK Mode HBLK Mode HBLK length HBLK Mode HBLK Mode Number HBLK repetitions HBLK Mode HBLK Mode Masking polarity during HBLK. Masking polarity during HBLK. Masking polarity during HBLK. First HBLK toggle position lines HBLK Mode HBLK Mode Second HBLK toggle position lines HBLK Mode HBLK Mode Third HBLK toggle position lines HBLK Mode HBLK Mode Fourth HBLK toggle position lines HBLK Mode HBLK Mode Fifth HBLK toggle position lines HBLK Mode HBLK Mode Sixth HBLK toggle position lines HBLK Mode HBLK Mode First HBLK toggle position even lines HBLK Mode HBLK Mode Second HBLK toggle position even lines HBLK Mode HBLK Mode Third HBLK toggle position even lines HBLK Mode HBLK Mode Fourth HBLK toggle position even lines HBLK Mode HBLK Mode Fifth HBLK toggle position even lines HBLK Mode HBLK Mode Sixth HBLK toggle position even lines HBLK Mode HBLK Mode HBLK Repeat Area Number repetitions HBLKSTARTA/B/C HBLK Mode even lines; lines defined using HBLKALT_PAT. [3:0] RA0H1REPA. Number pulses following HBLKSTARTA. [7:4] RA0H1REPB. Number pulses following HBLKSTARTB. [11:8] RA0H1REPC. Number pulses following HBLKSTARTC. HBLK Repeat Area Number repetitions HBLKSTARTA/B/C. HBLK Repeat Area Number repetitions HBLKSTARTA/B/C. HBLK Repeat Area Number repetitions HBLKSTARTA/B/C. HBLK Repeat Area Number repetitions HBLKSTARTA/B/C. HBLK Repeat Area Number repetitions HBLKSTARTA/B/C. HBLK Repeat Area Number repetitions HBLKSTARTA/B/C HBLK Mode even lines; lines defined using HBLKALT_PAT. [3:0] RA0H2REPA. Number pulses following HBLKSTARTA. [7:4] RA0H2REPB. Number pulses following HBLKSTARTB. [11:8] RA0H2REPC. Number pulses following HBLKSTARTC. HBLK Repeat Area Number repetitions HBLKSTARTA/B/C. HBLK Repeat Area Number repetitions HBLKSTARTA/B/C. HBLK Repeat Area Number repetitions HBLKSTARTA/B/C. HBLK Repeat Area Number repetitions HBLKSTARTA/B/C. HBLK Repeat Area Number repetitions HBLKSTARTA/B/C. HBLK Repeat Area Start Position HBLK Mode 8191 used. HBLK Repeat Area Start Position HBLK Mode 8191 used. HBLK Repeat Area Start Position HBLK Mode 8191 used.
HBLKSTART HBLKEND HBLKLEN HBLKREP HBLKMASK_H1 HBLKMASK_H2 HBLKMASK_HL HBLKTOGO1 HBLKTOGO2 HBLKTOGO3 HBLKTOGO4 HBLKTOGO5 HBLKTOGO6 HBLKTOGE1 HBLKTOGE2 HBLKTOGE3 HBLKTOGE4 HBLKTOGE5 HBLKTOGE6 RA0H1REPA/B/C
8191 pixel location 8191 pixel location 8191 pixels 8191 repetitions High/low High/low High/low 8191 pixel location 8191 pixel location 8191 pixel location 8191 pixel location 8191 pixel location 8191 pixel location 8191 pixel location 8191 pixel location 8191 pixel location 8191 pixel location 8191 pixel location 8191 pixel location HCLK pulses each
RA1H1REPA/B/C RA2H1REPA/B/C RA3H1REPA/B/C RA4H1REPA/B/C RA5H1REPA/B/C RA0H2REPA/B/C
HCLK pulses HCLK pulses HCLK pulses HCLK pulses HCLK pulses HCLK pulses each
RA1H2REPA/B/C RA2H2REPA/B/C RA3H2REPA/B/C RA4H2REPA/B/C RA5H2REPA/B/C HBLKSTARTA HBLKSTARTB HBLKSTARTC
HCLK pulses HCLK pulses HCLK pulses HCLK pulses HCLK pulses 8191 pixel location 8191 pixel location 8191 pixel location
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AD9992
Register HBLKALT_PAT1 HBLKALT_PAT2 HBLKALT_PAT3 HBLKALT_PAT4 HBLKALT_PAT5 HBLKALT_PAT6 Length Range even repeat area even repeat area even repeat area even repeat area even repeat area even repeat area Description HBLK Mode Field Repeat Area pattern, selected from even field repeat areas previously defined. HBLK Mode Field Repeat Area pattern. HBLK Mode Field Repeat Area pattern. HBLK Mode Field Repeat Area pattern. HBLK Mode Field Repeat Area pattern. HBLK Mode Field Repeat Area pattern.
HBLKTOGE2 HBLKSTART HBLKTOGE1 HBLKTOGE3
HBLKTOGE4 HBLKEND
HBLK HBLKLEN HBLKREP H1/H3
H2/H4
05891-027
HBLKREP NUMBER
HBLKREP NUMBER
HBLKREP NUMBER
H-BLANK REPEATING PATTERN CREATED USING HBLKLEN HBLKREP REGISTERS
Figure HBLK Repeating Pattern Using HBLKMODE
HBLK Mode Operation
Multiple repeats HBLK signal enabled setting HBLKMODE this mode, HBLK pattern generated using different registers: HBLKSTART, HBLKEND, HBLKLEN, HBLKREP, along with toggle positions (see Figure 26). Separate toggle positions available even lines. alternation needed, same values should loaded into registers even (HBLKTOGE) (HBLKTOGO) lines.
Bits [7:4]) value between When this register wide HCLK feature disabled. reduced frequency occurs only pulses that located within HBLK area. HCLK_WIDTH register generally used conjunction with special HBLK patterns generate vertical horizontal mixing CCD. Note that wide HCLK feature available only HBLK Mode HBLK Mode HBLK Mode does support wide HCLKs. Table HCLK Width Register
Register HCLK_WIDTH Length Description Controls width during HBLK fraction pixel rate same frequency pixel rate pixel frequency, that doubles HCLK pulse width pixel frequency pixel frequency pixel frequency 1/10 pixel frequency 1/30 pixel frequency
Generating HBLK Line Alternation
HBLK Mode HBLK Mode provide ability alternate different HBLK toggle positions even lines. HBLK line alternation used conjunction with V-pattern odd/even alternation own. Separate toggle positions available even lines. even/odd line alternation required, same values should loaded into registers even (HBLKTOGE) (HBLKTOGO) lines.
Increasing H-Clock Width During HBLK
HBLK Mode HBLK Mode allow pulse width increased during HBLK interval. shown Figure H-clock frequency reduced factor 1/2, 1/4, 1/6, 1/8, 1/10, 1/12, 1/30. enable this feature, HCLK_WIDTH register (Address 0x34,
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AD9992
HBLK
H1/H3 1/FPIX H2/H4
05891-028
(1/FPIX)
H-CLOCK FREQUENCY REDUCED DURING HBLK SHOWN), 1/4, 1/6, 1/8, 1/10, 1/12, 1/30 USING HBLKWIDTH REGISTER
Figure Generating Wide H-Clock Pulses During HBLK Interval
CREATE GROUPS TOGGLES COMMON REPEAT AREAS
MASK PULSES REPEAT AREA SETTING RA*H*REP*
CHANGE NUMBER PULSES REPEAT AREA USING RA*H*REP* REGISTERS
REPEAT AREA HBLKSTART
REPEAT AREA REPEAT AREA
REPEAT AREA
REPEAT AREA REPEAT AREA HBLKEND
Figure HBLK Mode Operation
HBLKLEN HBLK HBLKSTARTA HBLKSTARTB HBLKSTARTC RA*H*REPA/B/C REGISTERS CREATE HCLK PULSES
RA0H1REPA RA0H1REPB
RA0H1REPC
RA1H1REPA RA1H1REPB
RA1H1REPC
HBLKSTART
RA0H2REPA RA0H2REPB
RA0H2REPC
RA1H2REPA RA1H2REPB
RA1H2REPC
HBLKEND
05891-030
REPEAT AREA HBLKREP CREATE REPEAT AREAS
REPEAT AREA
Figure HBLK Mode Registers
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AD9992
HBLK Mode Operation
HBLK Mode allows more advanced HBLK pattern operation. multiple areas HCLK pulses that unevenly spaced apart from another needed, HBLK Mode used. Using separate registers, HBLK Mode divide HBLK region into repeat areas (see Table 10). shown Figure each repeat area shares common group toggle positions, HBLKSTARTA, HBLKSTARTB, HBLKSTARTC. However, number toggles following each start position unique each repeat area using RAH1REP RAH2REP registers. shown Figure setting RAH1REPA/RAH1REPB/RAH1REPC RAH2REPA/ RAH2REPB/RAH2REPC registers masks HCLK groups from appearing particular repeat area. Figure shows only repeat areas being used, although available. possible program separate number repeat area repetitions generally same value used both Figure shows example RA0H1REPA/RA0H1REPB/ RA0H1REPC RA0H2REPA/RA0H2REPB/RA0H2REPC RA1H1REPA/RA1H1REPB/RA1H1REPC RA1H2REPA/ RA1H2REPB/RA1H2REPC Furthermore, HBLK Mode allows different HBLK pattern even lines. HBLKSTARTA, HBLKSTARTB, HBLKSTARTC registers, well RAH1REPA/RAH1REPB/ RAH1REPC RAH2REPA/RAH2REPB/RAH2REPC registers, define operation even lines. separate control lines, HBLKALT_PAT registers specify repeat areas lines reordering repeat areas used even lines. patterns available, order previously defined repeat areas even lines changed lines accommodate advanced operation.
HORIZONTAL TIMING SEQUENCE EXAMPLE
Figure shows example layout. horizontal register contains dummy pixels, which occur each line clocked from CCD. vertical direction, there optical black (OB) lines front readout back readout. horizontal direction four pixels front back. Figure shows basic sequence layout used during effective pixel readout. pixels each line used CLPOB signals. PBLK optional often used blank digital outputs during HBLK time. HBLK used during vertical shift interval. Because PBLK used isolate input (see Analog Preblanking section), PBLK signal should used during CLPOB operation. change offset behavior that occurs during PBLK impacts accuracy CLPOB circuitry. HBLK, CLPOB, PBLK parameters programmed V-sequence registers. More elaborate clamping schemes, such adding separate sequence clamp entire shield lines, used. This requires configuring separate V-sequence clocking lines. CLPMASK registers also useful disabling CLPOB lines without affecting setup clamping sequences. important that CLPOB used only during valid pixels. During other portions frame timing, such vertical blanking line timing, does output valid pixels. CLPOB pulse that occurs during this time causes errors clamping operation changes black level image.
VERTICAL LINES EFFECTIVE IMAGE AREA VERTICAL LINES
PIXELS HORIZONTAL REGISTER
05891-031
PIXELS
DUMMY PIXELS
Figure Example Configuration
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AD9992
OPTICAL BLACK OPTICAL BLACK
OUTPUT H1/H3/H5/H7 H2/H4/H6/H8 HBLK PBLK CLPOB
VERTICAL SHIFT
DUMMY
EFFECTIVE PIXELS
OPTICAL BLACK
VERT. SHIFT
NOTES PBLK ACTIVE (LOW) SHOULD USED DURING CLPOB ACTIVE (LOW).
Figure Horizontal Sequence Example
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AD9992
VERTICAL TIMING GENERATION
AD9992 provides flexible solution generating vertical timing support multiple CCDs different system architectures. vertical transfer clocks used shift each line pixels into horizontal output register CCD. AD9992 allows these outputs individually programmed into various readout configurations using 4-step process. Figure shows overview vertical timing generated four steps. individual pulse patterns created using vertical pattern group registers. V-pattern groups used build sequences, which where additional information added. readout entire field constructed dividing field into different regions then assigning sequence each region. Each field contain nine different regions accommodate different steps readout, such high speed line shifts unique vertical line transfers. total number V-patterns, V-sequences, fields programmable, limited number registers. MODE registers allow different fields combined order various readout configurations.
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CREATE VERTICAL PATTERN GROUPS, FOUR TOGGLE POSITIONS EACH OUTPUT. VPAT0 V-SEQUENCE (VPAT0, REP)
BUILD V-SEQUENCES ADDING START POLARITY, LINE START POSITION, NUMBER REPEATS, ALTERNATION, GROUP A/B/C/D INFORMATION, HBLK/CLPOB PULSES.
VPAT1 V-SEQUENCE (VPAT1, REP)
V-SEQUENCE (VPAT1, REP)
MODE REGISTERS CONTROL WHICH FIELDS USED, WHAT ORDER (MAXIMUM SEVEN FIELDS COMBINED ORDER).
BUILD EACH FIELD DIVIDING INTO DIFFERENT REGIONS ASSIGNING DIFFERENT V-SEQUENCE EACH (MAXIMUM NINE REGIONS EACH FIELD).
FIELD FIELD0 FIELD1 FIELD2 REGION V-SEQUENCE REGION V-SEQUENCE REGION V-SEQUENCE REGION V-SEQUENCE REGION V-SEQUENCE REGION V-SEQUENCE REGION V-SEQUENCE FIELD3 FIELD4
REGION V-SEQUENCE REGION V-SEQUENCE FIELD5 FIELD1 FIELD4 FIELD2 REGION V-SEQUENCE REGION V-SEQUENCE FIELD1 FIELD2
05891-033
Figure Summary Vertical Timing Generation
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AD9992
Vertical Pattern Groups (VPAT)
vertical pattern groups define individual pulse patterns each output signal. Table summarizes registers available generating each V-pattern groups. first, second, third, fourth toggle positions (VTOG1, VTOG2, VTOG3, VTOG4) pixel locations within line where pulse transitions. toggle positions 13-bit values, allowing their placement anywhere horizontal line. More registers included vertical sequence registers specify output pulses. VPOL specifies start polarity each signal; VSTART specifies start position V-pattern group within line; VLEN designates total length V-pattern group, which determines number pixels between each pattern repetitions when repetitions used. VSTART position actually offset value each toggle position. actual pixel location each toggle, measured from falling edge (Pixel equal VSTART value plus toggle position. When selected V-output designated pulse, either VTOG1/VTOG2 VTOG3/VTOG4 pair selected using V-Sequence Address 0x02, VSGPATSEL. four toggle positions simultaneously available pulses. unused V-channels must have their toggle positions programmed either maximum value. This prevents unpredictable behavior because default values V-pattern group registers unknown.
Table Vertical Pattern Group Registers
Register VTOG1 VTOG2 VTOG3 VTOG4 Length Description First toggle position within line each output, relative VSTART value Second toggle position, relative VSTART value Third toggle position, relative VSTART value Fourth toggle position, relative VSTART value
START POSITION VERTICAL PATTERN GROUP PROGRAMMABLE VERTICAL SEQUENCE REGISTERS.
Figure Vertical Pattern Group Programmability
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PROGRAMMABLE SETTINGS: 1START POLARITY (LOCATED V-SEQUENCE REGISTERS). 2FIRST TOGGLE POSITION. 3SECOND TOGGLE POSITION (THIRD FOURTH TOGGLE POSITIONS ALSO AVAILABLE MORE COMPLEX PATTERNS). 4TOTAL PATTERN LENGTH VERTICAL OUTPUTS (LOCATED VERTICAL SEQUENCE REGISTERS).
AD9992
VERTICAL SEQUENCES (VSEQ)
vertical sequences created selecting V-pattern groups adding repeats, start position, horizontal clamping, blanking information. V-sequences programmed using registers shown Table Figure shows different registers used generate each V-sequence. VPATSELA, VPATSELB, VPATSELC, VPATSELD registers select which V-pattern used given V-sequence. Having four groups available allows different vertical outputs mapped different V-patterns. selected V-pattern group have repetitions added high speed line shifts line binning using VREP registers even lines. Generally, same number repetitions programmed into both registers. different number repetitions required even lines, separate values used each register (see Generating Line Alternation VSequences HBLK section). VSTARTA VSTARTB registers specify where line V-pattern group starts. VMASK_EN register used conjunction with FREEZE/RESUME registers enable optional masking V-outputs. Either both FREEZE1/RESUME1 FREEZE2/RESUME2 registers enabled. line length pixels) programmable using HDLEN registers. Each V-sequence have different line length accommodate various image readout techniques. maximum number pixels line 8192. last line field programmed separately using HDLASTLEN register, which located field register section.
V-PATTERN GROUP VREP VREP
CLPOB
HBLK
PROGRAMMABLE SETTINGS EACH VERTICAL SEQUENCE: 1START POSITION LINE SELECTED V-PATTERN GROUP. LINE LENGTH. 3V-PATTERN SELECT (VPATSEL) SELECT V-PATTERN GROUP. 4NUMBER REPETITIONS V-PATTERN GROUP NEEDED). 5START POLARITY TOGGLE POSITIONS CLPOB PBLK SIGNALS. 6MASKING POLARITY TOGGLE POSITIONS HBLK SIGNAL.
Figure V-Sequence Programmability
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AD9992
Table Summary V-Sequence Registers (see Table Table HBLK, CLPOB, PBLK Register Summary)
Register HOLD VMASK_EN CONCAT_GRP Length Description conjunction with VMASK_EN. HOLD function instead FREEZE/RESUME function. Enables masking outputs locations specified FREEZE/RESUME registers. enable masking groups. each Freeze Resume Positions Combines toggle positions Groups A/B/C/D when enabled. Only Group settings start, polarity, length, repetition used when this mode selected. disable. enable addition toggle positions from VPATSELA/B/C/D. test mode only. use. test mode only. use. Selects line alternation V-output repetitions. Note separate control Group Groups B/C/D. disable alternation. Group uses VREPA_1, Groups B/C/D VREP _EVEN lines. 2-line. Group alternates VREPA_1 VREPA_2. Groups B/C/D alternate VREP_EVEN VREP_ODD. 3-line. Group alternates VREPA_1, VREPA_2, VREPA_3. Groups B/C/D follow VREP_EVEN, VREP_ODD, VREP_ODD, VREP_EVEN, VREP_ODD, VREP_ODD pattern. 4-line. Group alternates VREPA_1, VREPA_2, VREPA_3, VREPA_4. Groups B/C/D follow 2-line alternation. Enables separate pattern length used during last repetition V-sequence. each group high enable. Group LSB. Recommended value enabled. Enables final toggle position added V-sequence. toggle position shared V-outputs same group. each group. high enable. Group LSB. line length even lines V-sequence. line length lines V-sequence. Group start polarity bits each output. Group start polarity bits each output. Group start polarity bits each output. Group start polarity bits each output. Assigns each output either Group A/B/C/D. bits each signal. Bits [1:0] Bits [3:2] Bits [23:22] V12. assign Group Group Group Group Assigns each output either Group A/B/C/D. bits each signal. Bits [1:0] V13, Bits [3:2] Bits [23:22] V24. assign Group Group Group Group Selected V-pattern Group Selected V-pattern Group Selected V-pattern Group Selected V-pattern Group Start position selected V-pattern Group Start position selected V-pattern Group Start position selected V-pattern Group Start position selected V-pattern Group Length selected V-pattern Group Length selected V-pattern Group Length selected V-pattern Group Length selected V-pattern Group Number repetitions V-Pattern Group first lines (even). Number repetitions V-Pattern Group second lines (odd). Number repetitions V-Pattern Group third lines. Number repetitions V-Pattern Group fourth lines. Number repetitions V-Pattern Group lines. Number repetitions V-Pattern Group lines.
VREP_MODE
LASTREPLEN_EN LASTTOG_EN HDLENE HDLEN0 VPOL_A VPOL_B VPOL_C VPOL_D GROUPSEL_0
GROUPSEL_1
VPATSELA VPATSELB VPATSELC VPATSELD VSTARTA VSTARTB VSTARTC VSTARTD VLENA VLENB VLENC VLEND VREPA_1 VREPA_2 VREPA_3 VREPA_4 VREPB_ODD VREPC_ODD
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Register VREPD_ODD VREPB_EVEN VREPC_EVEN VREPD_EVEN FREEZE1 FREEZE2 FREEZE3 FREEZE4 RESUME1 RESUME RESUME3 RESUME4 LASTREPLEN_A LASTREPLEN_B LASTREPLEN_C LASTREPLEN_D LASTTOG_A LASTTOG_B LASTTOG_C LASTTOG_D VSEQALT_EN VALT_MAP VALTSEL0_EVEN VALTSEL1_EVEN VALTSEL0_ODD VALTSEL1_ODD SPC_PAT_EN Length Description Number repetitions V-Pattern Group lines. Number repetitions V-Pattern Group even lines. Number repetitions V-Pattern Group even lines. Number repetitions V-Pattern Group even lines. Pixel location where V-outputs freeze hold (see VMASK_EN). Also used VALTSEL0_EVEN [12:0] register when Special VSEQALT_EN mode enabled. Pixel location where V-outputs freeze hold (see VMASK_EN). Also used VALTSEL1_EVEN [12:0] register when Special VSEQALT_EN mode enabled. Pixel location where V-outputs freeze hold (see VMASK_EN). Also used VALTSEL0_ODD [12:0] register when Special VSEQALT_EN mode enabled. Pixel location where V-outputs freeze hold (see VMASK_EN). Also used VALTSEL1_ODD [12:0] register when Special VSEQALT_EN mode enabled. Pixel location where V-outputs resume operation (see VMASK_EN). Also used VALTSEL0_EVEN [17:13] register when Special VSEQALT_EN mode enabled. Pixel location where V-outputs resume operation (see VMASK_EN). Also used VALTSEL1_EVEN [17:13] register when Special VSEQALT_EN mode enabled. Pixel location where V-outputs resume operation (see VMASK_EN). Also used VALTSEL0_ODD [17:13] register when Special VSEQALT_EN mode enabled. Pixel location where V-outputs resume operation (see VMASK_EN). Also used VALTSEL1_ODD [17:13] register when Special VSEQALT_EN mode enabled. Separate length last repetition vertical pulses. Must enabled using LASTREPLEN_EN. Should programmed value equal VLENA register. Separate length last repetition vertical pulses. Must enabled using LASTREPLEN_EN. Should programmed value equal VLENB register. Separate length last repetition vertical pulses. Must enabled using LASTREPLEN_EN. Should programmed value equal VLENC register. Separate length last repetition vertical pulses. Must enabled using LASTREPLEN_EN. Should programmed value equal VLEND register. Optional fifth toggle position vertical signals. Must enabled using LASTTOG_EN. Note that toggle position common vertical signals. Optional fifth toggle position vertical signals. Must enabled using LASTTOG_EN. Note that toggle position common vertical signals. Optional fifth toggle position vertical signals. Must enabled using LASTTOG_EN. Note that toggle position common vertical signals. Optional fifth toggle position vertical signals. Must enabled using LASTTOG_EN. Note that toggle position common vertical signals. Special V-sequence alternation mode enabled when this register programmed high. Enables FREEZE/RESUME register locations specify VALTSEL0 VALTSEL1 registers. Must enabled VSEQALT mode enabled. Select lines special V-sequence alternation mode even lines. Used concatenate VPAT Groups A/B/C/D into unique merged patterns. Setting used specify segment, with maximum segments. Select lines special V-sequence alternation mode even lines. Used concatenate VPAT Groups A/B/C/D into unique merged patterns. Setting used specify segment, with maximum segments. Select lines special V-sequence alternation mode lines. Used concatenate VPAT Groups A/B/C/D into unique merged patterns. Setting used specify segment, with maximum segments. Select lines special V-sequence alternation mode lines. Used concatenate VPAT Groups A/B/C/D into unique merged patterns. Setting used specify segment, with maximum segments. Enable special V-pattern inserted into repetition VPATA series. SPC_PAT_EN [0]: enable VPATB used special pattern insertion. SPC_PAT_EN [1]: enable VPATC used special pattern insertion. SPC_PAT_EN [2]: enable VPATD used special pattern insertion.
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V-PATTERN GROUP
V-PATTERN GROUP
Figure Using Separate Group Group Patterns
V-PATTERN GROUP V-PATTERN GROUP V-PATTERN GROUP V-PATTERN GROUP
Figure Combining Multiple V-Patterns Using CONCAT_GRP
V-PATTERN GROUP V-PATTERN GROUP
05891-038
GROUP
GROUP
GROUP
Figure Combining Group Group Patterns with Repetition
Group A/Group B/Group C/Group Selection
AD9992 flexibility four different V-pattern groups vertical sequence. general, vertical outputs same V-pattern group during particular sequence. possible assign some outputs different V-pattern group, which useful certain readout modes. GROUPSEL registers used select Group Group Group Group each V-output. general, only single V-pattern group needed vertical outputs; therefore, Group should selected outputs default (GROUPSEL_0, GROUPSEL_1 0x00). this configuration, outputs V-pattern group specified VPATSELA register.
additional flexibility needed, some outputs Group Group Group GROUPSEL registers. this case, those selected outputs V-pattern group specified VPATSELB, VPATSELC, VPATSELD registers. Figure shows example where outputs using separate V-Pattern Group perform special timing. Another application Group Group Group Group registers combine four different V-pattern groups together more complex patterns. This accomplished setting CONCAT_GRP register (Address 0x00, Bits [13:10]) equal 0x01. This setting combines toggle positions from V-pattern groups specified registers VPATSELA, VPATSELB, VPATSELC, VPATSELD
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05891-036
AD9992
maximum toggle positions. Example timing CONCAT_GRP feature shown Figure only groups needed eight toggle positions) specified timing, VPATSELB, VPATSELC, VPATSELD registers programmed same value. only three groups needed, VPATSELC VPATSELD programmed same value. Following this approach conserves register memory four separate V-patterns needed. Note that when CONCAT_GRP enabled, Group settings used only start position, polarity, length, repetitions. toggle positions Group Group Group Group combined together applied using settings VSTARTA, VPOL_A, VLENA, VREPA registers. Table VALTSEL Settings Even Lines
Parameter VALTSEL0_EVEN VALTSEL1_EVEN VALTSEL0_ODD VALTSEL1_ODD Resulting pattern even lines Resulting pattern lines VALTSEL SETTINGS
When entire pattern divided, program VALTSEL0 (even odd) [17:0] VALTSEL1 (even odd) [17:0] that segments will concatenated desired order. separate even lines required, even registers same value. Figure illustrates process using vertical pattern segments that have been concatenated into small, merged pattern. Program register VREPA_1 specify number segments that will concatenated into each merged pattern. maximum number segments that concatenated create merged pattern Program VLENA, VLENB, VLENC, VLEND equal length. Finally, program HBLK generate proper H-clock timing using procedure HBLK Mode described HBLK Mode Operation section. important note that because FREEZE/RESUME registers used specify VALTSEL registers, VALT_MAP register must enabled when using special VALT mode. Table VALTSEL Register Locations1
Register Function When VSEQALT_EN VALTSEL0_EVEN [12:0] VALTSEL0_EVEN [17:13] VALTSEL1_EVEN [12:0] VALTSEL1_EVEN [17:13] VALTSEL0_ODD [12:0] VALTSEL0_ [17:13] VALTSEL1_ [12:0] VALTSEL1_ [17:13]
Special Vertical Sequence Alternation (SVSA) Mode
AD9992 additional flexibility combining four different V-pattern groups random sequence that programmed specific requirements. This mode operation allows custom vertical sequences CCDs that require more complex vertical timing patterns. example, using special vertical sequence alternation mode, possible support random pattern concatenation, with additional support odd/even line alternation. Figure illustrates four common repetitive vertical pattern segments, through that derived from complete vertical pattern. Figure illustrates each group concatenated together arbitrary order. enable SVSA mode, write VSEQALT_EN bit, Address 0x20 [13], equal 0x01. location VALTSEL registers shared with VPAT registers V24. When SVSA mode enabled, VALTSEL register function selected. create SVSA timing, divide complete vertical timing pattern into four common repetitive segments. Identify related segments VPATA, VPATB, VPATC, VPATD. four toggle positions each segment programmed using V-pattern registers. Table shows segments specified using 2-bit representation. Each from VALTSEL0 VALTSEL1 combined produce four values, corresponding patterns
Register Location VSEQ register FREEZE1 [12:0] VSEQ register RESUME1 [17:13] VSEQ register FREEZE2 [12:0] VSEQ register RESUME2 [17:13] VSEQ register FREEZE3 [12:0] VSEQ register RESUME3 [17:13] VSEQ register FREEZE4 [12:0] VSEQ register RESUME4 [17:13]
VALT_MAP register must enable VALTSEL registers.
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AD9992
V-PATTERN V-PATTERN V-PATTERN V-PATTERN
VLENA
VLENB
VLENC
VLEND
05891-039
NOTES EACH SEGMENT MUST SAME LENGTH. VLENA VLENB VLENC VLEND.
Figure Vertical Timing Divided Into Four Segments: VPATA, VPATB, VPATC, VPATD
COMBINED V-PATTERN
Figure Concatenating Each VPAT Group Arbitrary Order
SEGMENT
SEGMENT
SEGMENT
SEGMENT4
SEGMENT
SEGMENT
VPATA VALTSEL0_EVEN VALTSEL1_EVEN VPATC VPATB VPATD VPATD VPATA
05891-041
NOTES V-PATTERN SEGMENTS CONCATENATED INTO MERGED PATTERN. COMMON REPETITIVE SEGMENTS DERIVED FROM COMPLETE PATTERN. VALTSEL REGISTERS SPECIFY SEGMENT ORDER CREATE CONCATENATED MERGED PATTERN.
Figure Example Special V-Sequence Alternation Mode Using VALTSEL Registers Specify Segment Order
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NOTES ABLE CONCATENATE PATTERNS TOGETHER ARBITRARILY. EACH PATTERN HAVE FOUR TOGGLES PROGRAMMED. CONCATENATE PATTERNS INTO MERGED PATTERN. EVEN LINES HAVE DIFFERENT PATTERN CONCATENATION SPECIFIED VALTSEL EVEN REGISTERS.
AD9992
Using LASTREPLEN_EN
LASTREPLEN_EN register (Address 0x00, Bits [19:16] sequence registers) used enable separate pattern length used final repetition several pulse repetitions. recommended that LASTREPLEN_EN register bits high (enabled) LASTREPLEN_A, LASTREPLEN_B, LASTREPLEN_C, LASTREPLEN_D registers value equal VLENA, VLENB, VLENC, VLEND register values, respectively. even lines. Only number repeats different even lines, while V-pattern group remains same. There separate controls assigned Group Group Group Group patterns. groups support even line alternation. Group uses VREPA_1 VREPA_2 registers; Group Group Group corresponding VREP_ODD VREP_EVEN registers. With additional VREPA_3 VREPA_4 registers, Group also support 3-line 4-line alternation. discussed Generating HBLK Line Alternation section, HBLK signal alternated even lines. Figure shows example V-pattern group repetition alternation HBLK Mode alternation used together.
Generating Line Alternation V-Sequences HBLK
During resolution readout, some CCDs require different number vertical clocks alternate lines. AD9992 support this using VREP registers. This allows different number V-pattern group repetitions programmed
VREPA_1 VREPB/C/D_EVEN VREPA_2 VREPB/C/D_ODD VREPA_1 VREPB/C/D_EVEN
TOGE1 HBLK
TOGE2
TOGO1
TOGO2
TOGE1
TOGE2
Figure Odd/Even Line Alternation V-Pattern Group Repetitions HBLK Toggle Positions
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NOTES NUMBER REPEATS V-PATTERN GROUPS A/B/C/D ALTERNATED EVEN LINES. GROUP ALSO SUPPORTS 4-LINE ALTERNATION USING ADDITIONAL VREPA_3 VREPA_4 REGISTERS. HBLK TOGGLE POSITIONS ALTERNATED BETWEEN EVEN LINES GENERATE DIFFERENT HBLK PATTERNS.
AD9992
Vertical Masking Using FREEZE/RESUME Registers
shown Figure Figure FREEZE/RESUME registers used temporarily mask V-outputs. pixel locations begin masking (FREEZE) masking (RESUME) create area which vertical toggle positions ignored. pixel location specified FREEZE register, V-outputs held static their current state, high low. V-outputs held until pixel location specified RESUME register reached, which point signals continue with remaining toggle positions, exist. Four sets FREEZE/RESUME registers provided, allowing vertical outputs interrupted four times same line. FREEZE RESUME Positions enabled independently applied groups (Group Group Group Group using VMASK_EN register. Note that when masking enabled, each group (Group Group Group Group uses same FREEZE/ RESUME positions. Note that FREEZE/RESUME registers also used VALTSEL0 VALTSEL1 registers during special vertical alternation mode.
MASKING AREA
Figure FREEZE/RESUME
V-MASKING AREA FREEZE RESUME
NOTES TOGGLE POSITIONS WITHIN FREEZE/RESUME MASKING AREA IGNORED. H-COUNTER CONTINUES COUNT DURING MASKING. FOUR SEPARATE MASKING AREAS AVAILABLE, USING FREEZE1/RESUME1, FREEZE2/RESUME2, FREEZE3/RESUME3, FREEZE4/RESUME4 REGISTERS.
Figure Using FREEZE/RESUME
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AD9992
Hold Area Using FREEZE/RESUME Registers
FREEZE/RESUME registers also used create hold area which V-outputs temporarily held later continued, starting point where they were held. shown Figure this different than VMASK_EN register because V-outputs continue from where they stopped rather than continuing from where they would have been. hold area temporarily stops pixel counter V-outputs, while V-masking allows counter continue masking area.
FREEZE
HOLD AREA GROUP
RESUME
NOTES WHEN HOLD V-SEQUENCE GROUP, FREEZE RESUME REGISTERS USED SPECIFY HOLD AREA. ABOVE EXAMPLE: ASSIGNED GROUP HOLD GROUP H-COUNTER GROUP V10) STOPS DURING HOLD AREA.
Figure Hold Area Group
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AD9992
Special Pattern Insertion
Additional flexibility available using SPC_PAT_EN registers, which allows Group pattern inserted into series Group repetitions. This feature useful when different pattern needed start, end, middle sequence. Figure shows example sweep region using VPATA with multiple repetitions where single repetition VPATB been added into middle sequence. Figure shows more detail registers achieve desired timing. Note that VREPB used specify which repetition number special pattern inserted instead VPATA. VPATB always priority over VPATC VPATD more than SPC_PAT_EN enabled (SPC_PAT_EN priority).
SCP1
SCP2
LINE
LINE
LINE
LINE
LINE
REGION REGION SWEEP REGION REGION
05891-046
PATTERN INSERTED DURING PATTERN REPETITIONS
Figure Example Special Pattern Insertion
V-PATTERN REGISTER SETTINGS: SPC_PAT_EN[0] VREPA VREPB
V-PATTERN
V-PATTERN
DESCRIPTION: V-PATTERN USED SPECIAL PATTERN TOTAL NUMBER REPS USED SEQUENCE REPS) USES V-PATTERN INSTEAD V-PATTERN
05891-047
NOTES VSTARTB MUST EQUAL VSTARTA.
Figure Example Special Pattern Insertion, Detail
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AD9992
Complete Field: Combining V-Sequences
After V-sequences created, they combined create different readout fields. field consists nine regions, within each region, different V-sequence selected. Figure shows sequence change positions (SCP) designate line boundary each region registers then select which V-sequence used each region. Registers control outputs also included field registers. Table summarizes registers used create different fields. registers, each region, select which V-sequences active each region. MULT_SWEEP registers, each region, used enable sweep mode and/or multiplier mode region. registers create line boundaries each region. VDLEN register specifies total number lines field. HDLEN registers specifies total number pixels line, Table Field Registers (CLPOB, PBLK Masking Shown Table
Register SEQx MULT_SWEEP Length Range V-sequence Description Selected V-sequence each region field. Enables multiplier mode and/or sweep mode each region. multiplier off, sweep off. multiplier off, sweep multiplier sweep off. multiplier sweep Sequence change position each region. Total number lines each field. Length pixels last line each field. VSGPATSEL selects which V-pattern toggle positions used. When Toggle Toggle used. When Toggle Toggle used. [0]: selection TOG1, TOG2; TOG3, TOG4). [23]: XV24 selection. high mask each individual output. [0]: mask. [23]: XV24 mask. Selects line field where signals active. Selects second line field repeat signals. used, this equal SGACTLINE1 maximum value.
HDLASTLEN register specifies number pixels last line field. VPATSECOND register used second V-pattern group outputs vertical sensor gate (VSG) line. SGMASK register used enable disable each individual output. There bits each output enable separate masking SGACTLINE1 SGACTLINE2. Setting masking high masks output; setting enables output. VSGPATSEL register assigns eight patterns each output. individual patterns created separately using pattern registers. SGACTLINE1 register specifies which line field contains outputs. optional SGACTLINE2 register allows same pulses repeated different line. Separate masking available SGACTLINE1 SGACTLINE2.
VDLEN HDLASTLEN VSGPATSEL
8191 line 8191 lines 8191 pixels High/low
SGMASK
High/low, each
SGACTLINE1 SGACTLINE2
8191 line 8191 line
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AD9992
SCP0 SCP1 SCP2 SCP3 SCP4 SCP5 SCP8
REGION REGION REGION REGION REGION REGION
SEQ0
SEQ1 SGACTLINE1
SEQ2
SEQ3
SEQ4
SEQ8
FIELD SETTINGS: SEQUENCE CHANGE POSITIONS (SCP0 SCP8) DEFINE EACH NINE AVAILABLE REGIONS FIELD. SEQ0 SEQ8 SELECT DESIRED V-SEQUENCE EACH REGION. SGACTLINE1 REGISTER SELECTS WHICH LINE FIELD CONTAINS SENSOR GATE PULSE(S).
Figure Complete Field Divided into Regions
SCP1
SCP2
LINE
LINE
LINE
LINE
LINE
REGION REGION SWEEP REGION REGION
05891-049
Figure Example Sweep Region High Speed Vertical Shift
Sweep Mode Operation
AD9992 contains additional mode vertical timing operation called sweep mode. This mode used generate large number repetitive pulses that span across multiple lines. example where this mode needed start readout operation. image exposure before image transferred sensor gate pulses, vertical interline registers should free charge. This accomplished quickly shifting charge using long series pulses from vertical outputs. Depending vertical resolution CCD, 3000 clock cycles might needed shift charge each vertical line. This operation spans across multiple line lengths. Normally, AD9992 vertical timing must contained within line length, when sweep mode enabled, boundaries ignored until region finished. enable sweep mode within region, program appropriate SWEEP register high.
Figure shows example sweep mode operation. number vertical pulses needed depends vertical resolution CCD. toggle positions signals generated using V-pattern registers (shown Table 12). single pulse created using polarity toggle position registers. number repetitions then programmed match number vertical shifts required CCD. Repetitions programmed into V-sequence registers (shown Table using VREP registers. This produces pulse train appropriate length. Normally, pulse train truncated line length, when sweep mode enabled this region, boundaries ignored. Figure sweep region occupies lines. After sweep mode region complete, normal sequence operation resumes next region. When using sweep mode, sure region boundaries (using sequence change positions) appropriate lines prevent sweep operation from overlapping next V-sequence.
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05891-048
AD9992
Multiplier Mode
generate very wide vertical timing pulses, vertical region configured into multiplier region. This mode uses V-pattern registers slightly different manner. Multiplier mode used support unusual timing requirements, such vertical pulses that wider than 13-bit V-pattern toggle position counter. general, 13-bit toggle position counter used with sweep mode feature support very wide pulses; however, multiplier mode used generate even wider pulses. start polarity toggle positions still used same manner standard V-pattern group programming, VLEN used differently. Instead using pixel counter counter) specify toggle position locations (VTOG1, VTOG VTOG VTOG V-pattern group, VLEN multiplied with VTOG position allow very long pulses generated. calculate exact toggle position, which counted pixels after start position, following equation: Because VTOG register multiplied VLEN, resolution toggle position placement reduced. VLEN toggle position precision reduced 4-pixel increments instead single-pixel increments. Table summarizes V-pattern group registers used multiplier mode operation. multiplier mode, VREP registers must always programmed same value highest toggle position. Figure illustrates this operation. first toggle position second toggle position nonmultiplier mode, this causes V-sequence toggle Pixel then Pixel within single line. However, multiplier mode toggle positions multiplied value VLEN this case, therefore, first toggle occurs Pixel second toggle occurs Pixel Sweep mode also been enabled allow toggle positions cross line boundaries.
Multiplier Mode Toggle Position VTOG VLEN
Table Multiplier Mode Register Parameters
Register MULTI VPOL VTOG VLEN VREP Length Range High/low High/low 8191 pixel location 8191 pixels 8191 pixel location Description High enables multiplier mode. Starting polarity signals each V-pattern group. Toggle positions signals each V-pattern group. Used multiplier factor toggle position counter. VREP_EVEN/VREP_ODD must same value highest VTOG value.
START POSITION VPAT GROUP STILL PROGRAMMED V-SEQUENCE REGISTERS
VLEN
PIXEL NUMBER
MULTIPLIER MODE V-PATTERN GROUP PROPERTIES: 1START POLARITY (STARTPOL 2FIRST, SECOND, THIRD TOGGLE POSITIONS (VTOG1 VTOG2 3LENGTH VPAT COUNTER (VLEN THIS MINIMUM RESOLUTION TOGGLE POSITION CHANGES. 4TOGGLE POSITIONS OCCUR LOCATION EQUAL (VTOG VLEN). SWEEP REGION ENABLED, V-PULSES ALSO CROSS BOUNDRIES, SHOWN ABOVE.
Figure Example Multiplier Region Wide Vertical Pulse Timing
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05891-050
AD9992
Vertical Sensor Gate (Shift Gate) Patterns
interline CCD, vertical sensor gate (VSG) pulses used transfer pixel charges from light-sensitive image area into light-shielded vertical registers. From lightshielded vertical registers, image clocked line-by-line using vertical transfer pulses signals) conjunction with high speed horizontal clocks. AD9992 vertical signals, each signal assigned pulse instead pulse. Table summarizes control registers, which mostly located field registers space (see Table 16). VSGSELECT register (Address 0x1C fixed address space) determines which vertical outputs assigned pulses. When signal selected pulse, only starting polarity V-pattern toggle positions used. VSGPATSEL register sequence registers used assign either TOG1 TOG2 TOG3 TOG4 signal. Table Control Registers (also Field Registers Table
Register VSGSELECT (Located Fixed Address Space, 0x1C) Length Range High/low Description Selection signals from signals. make signal VSG. [0]: selection pulse; pulse). [1]: selection. [23]: XV24 selection. When signal selected using VSGSELECT register, VSGPATSEL selects which V-pattern toggle positions used. When Toggle Toggle used. When Toggle Toggle used. [0]: selection TOG1, TOG2; TOG3, TOG4). [1]: selection. [23]: XV24 selection. high mask each individual output. [0]: mask. [23]: XV24 mask. Selects line field where signals active. Selects second line field repeat signals. used, this equal SGACTLINE1 maximum value.
Note that only four V-pattern toggle positions available when vertical signal selected pulse. SGACTLINE1 SGACTLINE2 registers used select which line field line. active line location used reference when substrate clocking (SUBCK) signal begins operate each field. more information, Substrate Clock Operation (SUBCK) section. Also located field registers, SGMASK register selects which individual pulses active given field. Therefore, patterns preprogrammed into V-pattern registers appropriate pulses different fields enabled separately.
VSGPATSEL
High/low
SGMASK
High/low, each
SGACTLINE1 SGACTLINE2
8191 line 8191 line
PATTERN
PROGRAMMABLE SETTINGS EACH PATTERN: 1START POLARITY PULSE (FROM VPOL SEQUENCE REGISTERS). 2FIRST TOGGLE POSITION (FROM V-PATTERN REGISTERS). 3SECOND TOGGLE POSITION (FROM V-PATTERN REGISTERS). 4ACTIVE LINE PULSES WITHIN FIELD (FROM FIELD REGISTERS).
Figure Vertical Sensor Gate Pulse Placement
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05891-051
AD9992
MODE Registers
MODE registers used select field timing AD9992. Typically, field, V-sequence, V-pattern information programmed into AD9992 startup. During operation, MODE registers allow user select combination field timing meet requirements system. advantage using MODE registers conjunction with preprogrammed timing that greatly reduces system programming requirements during camera operation. Only register writes required when camera operating mode changed, rather than having program vertical timing information with each camera mode change. basic still camera application require fields vertical timing-one draft mode operation, autofocusing, four still image readout. register timing information fields loaded startup. Then, during camera operation, MODE registers select which field timing active, depending camera being used. Table shows MODE registers used. MODE register (Address 0x2A) specifies many total fields used. value from selected using these three bits. other registers (0x2B 0x2C) used select Table MODE Registers-VD Updated
Address Name MODE FIELD0 FIELD1 FIELD2 FIELD3 FIELD4 FIELD5 FIELD6 Length Description Total number fields cycle through. from Selected FIELD (from FIELD registers configurable memory) first field cycle through. Selected FIELD (from FIELD registers configurable memory) second field cycle through. Selected FIELD (from FIELD registers configurable memory) third field cycle through. Selected FIELD (from FIELD registers configurable memory) fourth field cycle through. Selected FIELD (from FIELD registers configurable memory) fifth field cycle through. Selected FIELD (from FIELD registers configurable memory) sixth field cycle through. Selected FIELD (from FIELD registers configurable memory) seventh field cycle through.
which programmed fields used which order. seven fields used single MODE write. AD9992 starts with field timing specified FIELD0, next switches timing specified FIELD1, After completing total number fields specified MODE, AD9992 repeats starting first field. This continues until write MODE register occurs. Figure shows example MODE register settings different field configurations. Note that only write Address 0x2C properly resets field counter. Therefore, when changing values mode registers, recommended that three registers updated together same field period).
Caution
MODE registers updated default. they configured VD-updated registers writing Address 0xB4 0x03FF Address 0xB5 0xFC00, MODE information updated second falling edge after write occurs, rather than first falling edge. Figure example.
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AD9992
MODE WRITE REGISTER WRITE MODE UPDATE
MODE FIELD NUMBER
(DRAFT)
(DRAFT)
(STILL FIELD)
(STILL FIELD)
EXAMPLE MODE REGISTER CHANGE: REGISTER WRITE A--WRITE MODE REGISTERS 0x2A, 0x2B, 0x2C SPECIFY CHANGE FROM DRAFT MODE (FIELD4) STILL MODE (FIELD0/1/2/3). REGISTER WRITE B--WRITE GAIN REGISTER VALUES NEEDED STILL FRAME OPERATION, SUCH FIELD INFORMATION.
05891-053
NOTES MODE INFORMATION UPDATED SECOND FALLING EDGE AFTER SERIAL WRITE
Figure Update MODE Register, Updated (Default Setting)
MODE WRITE REGISTER WRITE MODE UPDATE
MODE FIELD NUMBER
(DRAFT)
(DRAFT)
(STILL FIELD)
(STILL FIELD)
EXAMPLE MODE REGISTER CHANGE: REGISTER WRITE A--WRITE MODE REGISTERS 0x2A, 0x2B, 0x2C SPECIFY CHANGE FROM DRAFT MODE (FIELD4) STILL MODE (FIELD0/1/2/3). REG. WRITE B--WRITE GAIN REGISTER VALUES NEEDED STILL FRAME OPERATION, SUCH FIELD INFORMATION.
05891-053
NOTES MODE INFORMATION UPDATED SECOND FALLING EDGE AFTER SERIAL WRITE
Figure Update MODE Register Changed VD-Updated Register
EXAMPLE TOTAL FIELDS FIRST FIELD FIELD0, SECOND FIELD FIELD1, THIRD FIELD FIELD2 MODE SETTINGS: 0x2A 0x2B 0x820 0x2C FIELD0 FIELD1 FIELD2
EXAMPLE TOTAL FIELDS FIRST FIELD FIELD3 MODE SETTINGS: 0x2A 0x2B 0x2C FIELD3
EXAMPLE TOTAL FIELDS FIRST FIELD FIELD5, SECOND FIELD FIELD1, THIRD FIELD FIELD4, FOURTH FIELD FIELD2 MODE SETTINGS: 0x2A 0x2B 0x11025 0x2C FIELD5 FIELD1 FIELD4 FIELD2
05891-054
Figure Using MODE Registers Select Field Timing
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AD9992
VERTICAL TIMING EXAMPLE
better understand AD9992 vertical timing generation used, consider example timing chart Figure This example illustrates using general 3-field readout technique. described previous field section, each readout field must divided into separate regions perform each step readout. sequence change positions (SCP) determine line boundaries each region, SEQx registers assign particular V-sequence each region. V-sequences contain specific timing information required each region: pulses (using Vpattern groups), HBLK/CLPOB timing, patterns active lines. This timing example requires four regions each three fields, labeled Region Region Region Region Because AD9992 allows many individual fields programmed, FIELD0, FIELD1, FIELD2 used meet requirements this timing example. four regions each field very similar this example, individual registers each field allow flexibility accommodate other timing charts. Region high speed, vertical shift region. Sweep mode used generate this timing operation with desired number high speed vertical pulses needed clear charge from CCD's vertical registers. Region consists only lines uses standard singleline, vertical shift timing. timing this region area same timing Region Region sensor gate line where pulses transfer image into vertical registers. This region might require second V-pattern group active line. Region also uses standard single-line, vertical shift timing, same timing Region Four regions required each three fields. timing Region Region essentially same, reducing complexity register programming. Other registers need used during actual readout operation. These include MODE registers, shutter control registers (PRIMARY_ACTION, SUBCK, MSHUT, VSUB control) gain register.
Important Note Regarding Signal Polarities
When programming AD9992 generate SUBCK signals, external V-driver circuit usually inverts these signals. Carefully check required timing signals needed input output V-driver circuit being used adjust polarities AD9992 outputs accordingly.
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AD9992
EXPOSURE (tEXP) FIRST FIELD READOUT THIRD FIELD READOUT SECOND FIELD READOUT
Figure Timing Example-Dividing Each Field into Regions
REGION REGION FIELD REGION
REGION
REGION REGION
REGION REGION FIELD
REGION REGION
REGION REGION FIELD
05891-055
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SUBCK
MSHUT OPEN
OPEN
CLOSED
VSUB
AD9992
SHUTTER TIMING CONTROL
AD9992 supports generation electronic shuttering (SUBCK) also features flexible general-purpose outputs (GPO) control mechanical shuttering, substrate bias switching, strobe circuitry. following documentation, terms sense gate (SG) vertical sense gate (VSG) used interchangeably.
SUBCK: Speed Operation
Normal high precision shutter operations used when exposure time less than field. exposure times greater than field, speed (LS) shutter features used. AD9992 includes field counter (primary field counter) regulate long exposure times. primary field counter must activated (Address 0x70) serve trigger operation. durations exposure read specified SGMASK_NUM SUBCKMASK_NUM register (Address 0x74), respectively. shown Figure this mode suppresses SUBCK outputs 8192 fields periods). activate shutter operation, trigger start exposure writing PRIMARY_ACTION register bits according desired effect. When primary counter activated, next period becomes first active period exposure which SUBCK masks applied. Optionally, SUBCKMASK_SKIP1 register enabled, AD9992 ignores first SUBCK masks subsequent fields. This generally desired that exposure time begins field after exposure operation initiated. Figure shows operation with SUBCKMASK_SKIP1 PRIMARY_ACTION register used while SUBCKMASK_NUM SGMASK_NUM registers behavior SUBCK signals different from normal shutter high precision shutter operations. Therefore, primary field counter used other tasks (described General-Purpose Outputs (GPOS) section) without disrupting normal activity. addition, there exists secondary field counter that effect SUBCK signals. These counters described detail Field Counters section.
SUBSTRATE CLOCK OPERATION (SUBCK)
image exposure time controlled substrate clock signal (SUBCK), which pulses substrate clear accumulated charge. AD9992 supports three types electronic shuttering: normal, high precision, speed. Along with SUBCK pulse placement, AD9992 accommodate different readout configurations further suppress SUBCK pulses during multiple field readouts. SUBCK signal programmable string pulses, each occupying line following primary sense gate active line, SGACTLINE1 (registers shown Table 20). SUBCK signal programmable pulse width, line placement, number pulses accurately control exposure time.
SUBCK: Normal Operation
default, AD9992 operates normal SUBCK configuration, which SUBCK signal pulsing every field (see Figure 55). SUBCK pulse occurs once line, total number repetitions within field determines length exposure time. SUBCK pulse polarity toggle positions within line programmable using SUBCK_POL SUBCK_TOG1 registers (see Table 20). number SUBCK pulses field programmed SUBCKNUM register (Address 0x75). shown Figure SUBCK pulses always begin line following SG-active line, which specified SGACTLINE registers each field. SUBCK_POL, SUBCK_TOG1, SUBCK_TOG2, SUBCKNUM, SUBCKSTARTLINE registers updated start line after sensor gate line, described Updating Register Values section.
SUBCK Start Line
default, SUBCK pulses begin line following SGACTLINE1. applications where SUBCK pulse should suppressed more lines following line, SUBCKSTARTLINE register programmed. This register setting delays start SUBCK pulses until specified number lines following SGACTLINE1.
SUBCK: High Precision Operation
High precision shuttering used same manner normal shuttering uses additional register control last SUBCK pulse. this mode, SUBCK still pulses once line, last SUBCK field additional SUBCK pulse, whose location determined SUBCKHP_TOG registers, shown Figure Finer resolution exposure time possible using this mode. Leaving SUBCKHP_TOG registers maximum value (0xFFFFFF) disables last SUBCK pulse (default setting).
Caution
value should used SUBCKSTARTLINE register. value used specify SUBCK pulses begin next line after line. value used specify SUBCK pulses begin lines after line,
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AD9992
Read After Exposure
read data after exposure, should resume normal activity while SUBCK remains null. default, AD9992 generates pulses every field. When only single exposure single frame read desired, such case preview mode, SUBCK pulses operate every field. Other applications require that greater number frames read, which case SUBCK must masked until readout finished. SUBCKMASK_NUM register specifies total number fields (exposure read) mask SUBCK. 2-field frame read mode typically requires additional fields SUBCK masking (SUBCKMASK_NUM 3-field, 6-phase requires three additional fields SUBCK masking after read begins (SUBCKMASK_NUM Note that SUBCKMASK_SKIP1 register setting allows SUBCK pulses beginning field exposure.
Table SUBCK Exposure/Read Register Parameters
Register SGMASK_NUM SUBCKMASK_NUM SUBCKMASK_SKIP1 SUBCKSTARTLINE SUBCKNUM1 SG_SUPPRESS1 SUBCK_TOG1 SUBCK_TOG2 SUBCK_POL SUBCKHP_TOG1 SUBCKHP_TOG2
Length
Range 8191 fields 8191 fields On/off 8191 line location 8191 pulses On/off 8191 pixel locations 8191 pixel locations Low/high 8191 pixel locations 8191 pixel locations
Description Exposure duration (number fields suppress VSG) operation. Exposure plus readout duration (number fields suppress SUBCK) Suppress SG/SUBCK masks field (default Typically Line location start SUBCK pulses, relative SGLINE location. value invalid. SUBCK Start Line section. Total number SUBCKs field, pulse line. Must <VDLEN. Suppress allow SUBCK finish SUBCKNUM. SUBCK Toggle Position SUBCK Toggle Position SUBCK start polarity. Hi-precision SUBCK Toggle Position Selectable updated. Hi-precision SUBCK Toggle Position Selectable updated.
Register updated updated start line after sensor gate line.
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AD9992
tEXP
SUBCK
tEXP
Figure Normal SUBCK Operation
tEXP
tEXP
SUBCK
05891-057 05891-058
NOTES SECOND SUBCK PULSE ADDED LAST SUBCK LINE. LOCATION SECOND PULSE FULLY PROGRAMMABLE USING SUBCKHP TOGGLE POSITION REGISTERS.
Figure High Precision SUBCK Operation
TRIGGER EXPOSURE (0x70)
tEXP
SUBCK
NOTES SUBCK SUPPRESSED MULTIPLE FIELDS PROGRAMMING EXPOSURE REGISTER GREATER THAN ABOVE EXAMPLE USES EXPOSURE TRIGGER REGISTER MUST ALSO USED START SPEED EXPOSURE. VD/HD OUTPUTS ALSO SUPPRESSED USING VDHDOFF REGISTER
Figure Speed SUBCK Operation
Rev. Page
05891-056
SUBCK PROGRAMMABLE SETTINGS: PULSE POLARITY USING SUBCK_POL REGISTER. NUMBER PULSES WITHIN FIELD USING SUBCKNUM REGISTER (SUBCKNUM ABOVE EXAMPLE). PIXEL LOCATION PULSE WITHIN LINE PULSE WIDTH PROGRAMMED USING SUBCK1 TOGGLE POSITION REGISTERS.
AD9992
FIELD COUNTERS
AD9992 contains three field counters (primary, secondary, mode). When these counters active, they increment with each cycle. mode counter field counter used with mode register control vertical timing signals, which discussed MODE Registers section. primary secondary counters more flexible generally used shuttering signal applications. Both primary secondary counters have several modes operation that dictated Address 0x70, including
ShotDelay with RapidShot Manual exposure Manual readout Force idle
Normal (single count) RapidShot (repeating count) ShotDelay (delayed count)
primary counter regulates expose read actions regulating SUBCK signals. addition, RapidShot feature used with primary counter, SUBCK masking automatically repeats necessary multiple expose/read cycles. secondary counter effect SUBCK signal. Both counters used regulate general-purpose signals described General-Purpose Outputs (GPOS) section.
Table Primary/Secondary Field Counter Registers (Address 0x70, Address 0x71, Address 0x72)
Register PRIMARY_ACTION SECOND_ACTION Length Description idle, counter action. signals still controlled using polarity GP_PROTOCOL activate counter. Single cycle counter from counter maximum value, then returns idle state. RapidShot. After reaching maximum counter value, counter wraps repeats until reset. ShotTimer. Active single cycle counter after added delay fields (use corresponding DELAY register). ShotTimer with RapidShot. Same with added delay fields between each repetition. manual exposure. Primary counter stays exposure until manual readout reset idle. This mode keeps SUBCK pulses masked indefinitely. manual readout. Primary counter switches readout (VSG pulses becomes active). force idle. Primary counter maximum value. Secondary counter maximum value. Mask VD/HD during counter operation. ShotTimer. Number fields delay before next primary count (exposure) starts. using ShotTimer with RapidShot, delay value used between each repeat. When using ShotTimer with RapidShot, primary delay value only before first count (exposure). ShotTimer. Number fields delay before next secondary count starts. using ShotTimer with RapidShot, delay value used between each repeat. When using ShotTimer with RapidShot, secondary delay value only before first count.
PRIMARY_MAX SECOND_MAX VDHD_MASK PRIMARY_DELAY PRIMARY_SKIP SECOND_DELAY SECOND_SKIP
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AD9992
GENERAL-PURPOSE OUTPUTS (GPOS)
AD9992 provides programmable outputs control mechanical shutter, strobe/flash, bias select signal, other external component with general-purpose (GP) signals. Eight signals, with four toggles each, available that programmed assigned special pins. These pins bidirectional allow visibility output) external control input) HBLK, PBLK, CLPOB, OUTCONTROL. registers introduced this section described Table Protocol counter association), skip Steps With these four steps, signals programmed accomplish many common tasks. Careful protocol selection application field counters yields efficient results allow signals smooth integration with concurrent operations. Note that SUBCK masks linked primary counter; however, their parameters primary counter without expose/read activity. secondary counter independent used simultaneously with primary counter. Some applications require both primary secondary field counters with different protocols, start times, durations. Such operations easily handled AD9992. Several simple examples applications using only field counter follow. These examples used building blocks more complex activity. addition, specific signals passed through 4-input realize combinational logic between them. example, sent through look-up table, result delivered GP1, GP2, both. Also, either deliver their original toggles.
Toggles
When configured output, each GPO1 GPO8 output deliver signal that result programmable toggle positions. signals independent linked either specific period over range periods primary secondary field counters through protocol register (Address 0x73). result their associations with field counters, toggles inherit characteristics field counters, such RapidShot ShotDelay. toggles Program toggle positions (Address 0x7A Address 0xA9). Program protocol (Address 0x73). Program counter parameters (Address 0x71 Address 0x72). Activate counter (Address 0x70).
Table Registers
Register GP1_PROTOCOL GP2_PROTOCOL GP3_PROTOCOL GP4_PROTOCOL GP5_PROTOCOL GP6_PROTOCOL GP7_PROTOCOL GP8_PROTOCOL MANUAL_TRIG GP<1:8>_POL SEL_GP<1:8> Length Range Off/on Low/high Off/on Description idle. counter association, MANUAL_TRIG bits enable each signal. link primary counter. link secondary counter. link mode counter (from vertical timing generation). primary repeat (allows signals repeat with RapidShot). secondary repeat (allows signals repeat with RapidShot). keep Manual trigger each signal, with Protocol Starting polarity signals, only updated during PROTOCOL select toggles visible GPO1 GPO8 when output enabled (default); select vertical signals visible GPO4 GPO8 when output enabled. GPO4: SUBCK. GPO5: XV21. GPO6: XV22. GPO7: XV23. GPO8: XV24. enable GPO1 GPO8 outputs (one output); disable GPO1 GPO8 outputs, pins will high-Z state (default). Send signals through programmable look-up table (LUT). Desired logic realized combined with GP2. Desired logic realized combined with GP4.
GPO_OUTPUT_EN GP*_USE_LUT LUT_FOR_GP12 LUT_FOR_GP34
Off/on Off/on Logic setting Logic setting
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AD9992
Register LUT_FOR_GP56 LUT_FOR_GP78 Length Range Logic setting Logic setting Description Desired logic realized combined with GP6. Desired logic realized combined with GP8. Example logic settings LUT_FOR_GPxy: (see Figure 63). NAND GPx. GPx. GPx. Field activity, relative primary secondary counter corresponding toggle. Line activity corresponding toggle. Pixel activity corresponding toggle. When internal signals viewable GPO5 GPO8. GPO5: OUTCONTROL. GPO6: HBLK. GPO7: CLPOB. GPO8: PBLK.
GP*_TOG*_FD GP*_TOG*_LN GP*_TOG*_PX GPO_INT_EN
8191 field 8191 line 8191 pixel Off/on
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AD9992
Single-Field Toggles
Single-field toggles occur next field only. There four toggles field. mode with GP_PROTOCOL equal then toggles triggered next field writing MANUAL_TRIG register (0x70 [13:6]). this mode, field toggle settings must value consecutive fields have activity. toggles required repeat next field, MANUAL_TRIG register written consecutive fields.
Scheduled Toggles
Scheduled toggles programmed occur during upcoming field. example, there toggle Field toggles Field last toggle Field mode with GP_PROTOCOL GP_PROTOCOL Mode tells obey primary field counter, Mode tells obey secondary field counter.
Preparation
toggle positions programmed time prior use. example, 0x7A 0x7B 0x7C 0x00C4002 0x0004000 0x00000B3
Preparation
toggle positions programmed time prior use. example, 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x000A001 0x0002000 0x000000F 0x00C4002 0x0004000 0x00000B3
Details
Field 0x70 0x73 0x0000008 0x0000003
Details
Field Field 0x70 0x73 0x73 0x0000040 0x0000001 0x0000000
REGISTER WRITE
GP1_PROTOCOL
SECONDARY (IDLE) COUNT
GPO1
REGISTER WRITE
05891-060
GP1_PROTOCOL
CAUTION! PRIMARY COUNTER REGULATES SUBCK ACTIVITY. LINK PRIMARY COUNTER ONLY HAPPEN DURING EXPOSURE/READ.
Figure Scheduled Toggles Using GP_PROTOCOL
GPO1 NOTES FIELD TOGGLE POSITION MUST WHEN PROTOCOL CAUTION! GP_PROTOCOL MUST RESET BEFORE USING AGAIN.
Figure Single-Field Toggles Using GP_PROTOCOL
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05891-059
AD9992
RapidShot Sequences
RapidShot technology provides continuous repetition scheduled toggles.
ShotDelay Sequences
ShotDelay technology provides internal delay scheduled toggles. delay terms fields.
Preparation
toggle positions programmed time prior use. example, 0x71 0x7A 0x7B 0x7C 0x7D 0x7E 0x7F 0x73 0x0004000 0x000A001 0x0002000 0x000000F 0x00C4002 0x0004000 0x00000B3 0x0000006
Preparation
toggle positions programmed time prior use. example, 0x71 0x72 0x7A 0x7B 0x7C 0x73 0x0004000 0x000C000 0x000A001 0x0002000 0x000000F 0x0000003
Details
Field 0x70 0x0000018
Details
Field Field 0x70 0x70 0x0000010
0x0000007
REGISTER WRITE
GP1_PROTOCOL
REGISTER WRITE
SECONDARY (IDLE) COUNT
05891-063
GP1_PROTOCOL
GPO1
SECONDARY (IDLE) COUNT
Figure ShotDelay Toggle Operation Using GP_PROTOCOL
GPO1
Figure RapidShot Toggle Operation Using GP_PROTOCOL
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05891-062
TERMINATED EDGE NOTES PROTOCOLS SAME SCHEDULED TOGGLES, EXCEPT TOGGLES EXCLUDED FROM REPETITION CHOOSING PROTOCOL CAUTION! FIELD COUNTER MUST FORCED INTO IDLE STATE TERMINATE REPETITIONS.
AD9992
LOOK-UP TABLES (LUT)
AD9992 equipped with look-up table each pair consecutive signals when configured outputs. always combined with GP2, always combined with GP4, always combined with GP6, always combined with GP8. external outputs from each pair output result original internal signal.
GP1_USE_LUT
05891-064
Table Results Based GP1, Values
LUT: LUT: NAND LUT: LUT:
LUT_FOR_GP12[11:8] 0x06 GP2_USE_LUT GP1_USE_LUT
GPO1
GPO2
GPO1 NOTES LOGIC COMBINATION (XOR) PROGRAMMED TOGGLES GP2.
05891-065
GPO2
Figure Example
GP2_USE_LUT
Field Counter Limitations
following summary known limitations field counters signals that dictate usability.
Figure Internal Signals
Address 0x79 dictates behavior which signals receive result. Each 4-bit LUT_FOR_GPxy register realize logic combination GPy. example, Table shows register values LUT_FOR_GP12 [11:8] determined. XOR, NAND, AND, results shown, 4-bit combination possible. simple example gating shown Figure
field counter trigger (PRIMARY_ACTION SECONDARY_ACTION registers, Address 0x70) self-reset start every period. Therefore, there must period between sequential programming that address. GP*_PROTOCOL must manually reset GP*_PROTOCOL period before used again. manual toggles desired sequential fields, MANUAL_TRIG register should used conjunction with GP*_PROTOCOL
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AD9992
COMPLETE EXPOSURE/READOUT OPERATION USING PRIMARY COUNTER SIGNALS
Figure demonstrates typical expose/read cycle while exercising signals. Using 3-field with exposure time that greater than field less than fields duration, requires total five fields entire exposure/readout operation. Other exposure times other field configurations require modification these example settings. Note that MODE registers changed updated, shown MODE Registers section Figure MODE update will delayed additional field. This should accounted selecting number fields cycle which location write MODE registers. primary counter used control masking SUBCK during exposure/readout. PRIMARY_MAX register should equal total number fields used exposure readout. this example, PRIMARY_MAX SUBCK masking should occur immediately next edge (Step because this would define exposure time that begins previous field. Write PRIMARY_DELAY register delay masking SUBCK pulses first exposure field. this example, MASKDELAY Write SUBCKMASK_NUM register (Address 0x74) specify number fields mask SUBCK while data read. this example, SUBCKMASK_NUM Write SGMASK_NUM register (Address 0x74) specify number fields mask outputs during exposure. this example, SGMASK_NUM Write PRIMARY_ACTION register (Address 0x70) trigger (STROBE), (MSHUT), (VSUB) signals start expose/read operation. Write MODE registers configure next five fields. first fields during exposure same current draft mode fields, following three fields still-frame readout fields. register settings draft mode field three readout fields previously programmed. Note that MODE registers changed updated, only field exposure should included (the second one) because MODE settings will delayed extra field. VD/HD falling edge updates serial writes from (VSUB) output turns field/line/pixel specified. VSUB Example Example GP3TOG1_FD (STROBE) output turns location specified. (MSHUT) output turns location specified. next falling edge automatically starts first read field. next falling edge automatically starts second read field. next falling edge automatically starts third read field. Write MODE register reconfigure single draft mode field timing. Note that MODE registers changed updated, this write should occur field earlier.
VD/HD falling edge updates serial writes from outputs return draft mode timing. SUBCK output resumes operation. (MSHUT) output returns position (active open). (VSUB) output returns position (inactive).
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SERIAL WRITES (IDLE)
PRIMARY COUNT
STILL IMAGE READOUT
tEXP
SUBCK
STROBE (GPO1)
Figure Complete Exposure/Readout Operation Using Primary Counter Signals
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OPEN CLOSED EXAMPLE EXAMPLE DRAFT IMAGE DRAFT IMAGE STILL IMAGE FIRST FIELD STILL IMAGE SECOND FIELD
MSHUT (GPO2)
MECHANICAL SHUTTER
OPEN STILL IMAGE THIRD FIELD
VSUB (GPO3)
DRAFT IMAGE
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AD9992
AD9992
MANUAL SHUTTER OPERATION USING ENHANCED SYNC MODES
AD9992 also supports external signal control exposure, using SYNC input. Generally, SYNC input used asynchronous reset signal during master mode operation. When enhanced SYNC mode enabled, SYNC input provides additional control exposure operation.
Shutter Operation Mode
Referring Figure turn VSUB, write appropriate registers trigger VSUB start manual exposure [PRIMARY_ACTION This change takes effect after next SUBCK suppressed during exposure readout phases. turn MSHUT during interval between next SYNC, write appropriate register. When MSHUT position, line pixel control. This change takes effect SYNC falling edge since there internal MODE register programmed cycle through multiple fields this example), internal field designator increments. MODE register required increment, MODE register such that outputs only field. This prevents MODE counter from incrementing during SYNC interval. Write manual readout trigger begin manual readout [PRIMARY_ACTION Write appropriate registers trigger MSHUT toggle exposure. This change takes effect SYNC rising edge during readout. Since register update disabled, trigger takes effect SYNC rising edge. MSHUT falling edge aligned SYNC rising edge. Because MSHUT falling edge aligned with necessary insert dummy delay readout.
Normal SYNC Mode (Mode
default, SYNC input used master mode synchronizing internal counters AD9992 with external timing. SYNC During Master Mode Operation section describes horizontal, vertical, field designator signals reset rising edge SYNC pulse. Figure also shows this mode operates, highlighting behavior mode field designator.
Enhanced SYNC Modes (Modes
enhanced SYNC modes used accommodate unique synchronization requirements during exposure operations. SYNC Mode outputs suspended output masked. V-outputs held value established Sequence start polarities. There operation, H-counter still enabled. Finally, sampling clocks, H/RG, CLPOB, HBLK, operational Sequence behavior. Figure more details. enable enhanced SYNC modes, register ENH_SYNC_EN (Address 0x13 [3]) Mode uses these features, V-outputs continuous through SYNC pulse interval. control pulses masked during SYNC interval, pulse also masked, required. Figure important note that both these enhanced modes, SYNC pulse resets counters both falling edge rising edge SYNC pulse.
Note that since internal exposure counter (PRIMARY counter) used during manual SYNC mode operation register update disabled, control lost fine placement signals VSUB, MSHUT, STROBE edges while SYNC low.
Serial Registers
SYNC Modes controlled using registers listed Table Table Registers Enhanced SYNC Modes
Register ENH_SYNC_EN SYNC_MASK_V SYNC_MASK_VD SYNC_MASK_HD Length Description active enable (default active enable masking (default active enable masking (default active enable masking (default
Register Update Field Designator
When using special SYNC Mode VD-updated registers, such PRIMARY_ACTION, updated during SYNC interval, SCP0 function ignored held (see Figure 68). When using either SYNC Mode both rising falling edges increment internal field designator; therefore, register data takes effect information updated SEQ0 data. However, this does occur MODE register create output field. that case, region, sequence, group information does change (see Figure 69).
Note that registers enhanced SYNC modes located Address 0x13 Bits [6:3].
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AD9992
SYNC
FIELD DESIGNATOR
SUSPEND
XV24 VSG, SUBCK NOTES SYNC RISING EDGE RESETS VD/HD COUNTERS SYNC POLARITY PROGRAMMABLE USING SYNCPOL REGISTER (ADDR 0x13). DURING SYNC LOW, INTERNAL COUNTERS RESET VD/HD SUSPENDED USING SYNCSUSPEND REGISTER (ADDR 0x13). SYNC RISING EDGE CAUSES INTERNAL FIELD DESIGNATOR INCREMENT. SYSCSUSPEND VERTICAL CLOCKS, HELD SAME POLARITY SPECIFIED OUTCONTROL LOW. SYNCSUSPEND CLOCK OUTPUTS CONTINUE OPERATE NORMALLY UNTIL SYNC RESET EDGE.
Figure Default Mode
SYNC
VDLEN
Figure Enhanced SYNC Mode with Vertical Signals Held Start Value
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05891-084
1FALLING EDGE RESYNCS CIRCUIT LINE/PIXEL NUMBER INTERNALLY RESYNC. 2RISING EDGE RESETS COUNTERS. DISABLED DURING SYNC. REGISTER PROGRAMMABLE. 4SCP, HBLK, CLPOB HELD SEQ0 VALUE. SIGNALS HELD V-OUTPUT START POLARITY.
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AD9992
SYNC
VDLEN
Figure Enhanced SYNC Mode
SYNC
REGISTERS UPDATED HERE.
05891-086
NOTES VD-UPDATED REGISTERS (FOR EXAMPLE, PRIMARY_ACTION) DISABLED DURING SYNC INTERVAL.
Figure Register Update Behavior
SYNC
FIELD DESIGNATOR
1FIELD
DESIGNATOR INCREMENTED BOTH SYNC EDGES.
Figure Special SYNC Mode Effect Field Designator
Rev. Page
05891-087
05891-085
1SYNC_MASK_VD REGISTER. WILL MASK DEFAULT 2SYNC_MASK_HD REGISTER. WILL MASK DEFAULT 3V-OUTPUT PULSES CONTINUE SEQUENCE.
AD9992
SYNC
FIELD DESIGNATOR
V-OUTPUTS
MSHUT
VSUB
DRAFT
EXPOSURE
DUMMY FIELD
READOUT
READOUT EVEN
DRAFT
1SEE SHUTTER OPERATION MODE SECTION. 2SEE SHUTTER OPERATION MODE SECTION. 3SEE SHUTTER OPERATION MODE SECTION. 4SEE SHUTTER OPERATION MODE SECTION. 5SUBCK OUTPUT SUPPRESSED DURING EXPOSURE
READOUT WHEN EXPOSURE TRIGGER USED.
Figure Enhanced SYNC Mode-Manual Shutter Operation, Mode
Rev. Page
05891-088
AD9992
ANALOG FRONT-END DESCRIPTION OPERATION
0.1µF 0.1µF REFB REFT RESTORE 1.2V PBLK (WHEN DCBYP 0.1µF CCDIN -3dB, 0dB, +3dB, +6dB 12-BIT OUTPUT DATA LATCH 0.4V 1.4V INTERNAL VREF DOUTPHASE FIXED DELAY DCLK MODE
AD9992
DCLK
42dB
FULL SCALE
DCLKINV
DOUT
PBLK GAIN REGISTER GAIN REGISTER
OPTICAL BLACK CLAMP CLPOB PBLK DIGITAL FILTER BLANK ZERO CLAMP LEVEL CLAMP LEVEL REGISTER
DOUTPHASE
CLPOB
PBLK
PRECISION TIMING GENERATION
TIMING GENERATION
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NORMALLY CLOSED; NORMALLY OPEN.
Figure Analog Front-End Functional Block Diagram
AD9992 signal processing chain shown Figure Each processing step essential achieving high quality image from pixel data.
Note that because input shorted during PBLK, CLPOB pulse should used during same active time PBLK pulse.
Restore
reduce large offset output signal, restore circuit used with external series coupling capacitor. This restores level signal approximately making compatible with core supply voltage AD9992. restore switch active during sample pulse time. restore circuit disabled when optional PBLK signal used isolate large-signal swings from input (see Analog Preblanking). Register Address 0x00 controls whether restore active during PBLK interval.
Correlated Double Sampler (CDS)
circuit samples each pixel twice extract video information reject frequency noise. timing shown Figure illustrates internally generated clocks, SHD, used sample reference level data level signal, respectively. placement sampling edges determined setting SHPLOC SHDLOC registers located Address 0x37. Placement these clock signals critical achieving best performance from CCD. gain variable three steps using Address 0x04: (default), Improved noise performance results from using setting, input range will reduced (see Analog Specifications).
Analog Preblanking
During certain blanking substrate clocking intervals, input signal AD9992 increase amplitude beyond recommended input range. PBLK signal used isolate input from large-signal swings. While PBLK active (low), input internally shorted ground.
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AD9992
Variable Gain Amplifier
stage provides gain range approximately programmable with 10-bit resolution through serial digital interface. gain needed match input signal with full-scale range When compared full-scale systems, equivalent gain range gain curve follows linear-in-dB characteristic. exact gain calculated gain register value
black clamping disabled using Register Address 0x00. When loop disabled, clamp level register still used provide fixed offset adjustment. Note that CLPOB loop disabled, higher gain settings reduce dynamic range because uncorrected offset signal path gained CLPOB pulse should aligned with CCD's optical black pixels. recommended that CLPOB pulse duration least pixels wide. Shorter pulse widths used, ability loop track frequency variations black level will reduced. Horizontal Clamping Blanking section timing examples.
Gain (dB) (0.0358 Code) 5.75 where Code range 1023.
Digital Data Outputs
AD9992 digital output data latched using rising edge DOUTPHASE register value, shown Figure Output data timing shown Figure Figure also possible leave output latches transparent, that data outputs valid immediately from ADC. Programming Register Address 0x01, sets output latches transparent. data outputs also disabled (three-stated) setting Register Address 0x01,
GAIN REGISTER CODE 1023
GAIN (dB)
Figure Gain Curve
AD9992 uses high performance architecture optimized high speed power. Differential nonlinearity (DNL) performance typically better than LSB. uses input range. Figure Figure typical linearity noise performance plots AD9992.
05891-068
DCLK output used external latching data outputs. default, DCLK output tracks values DOUTPHASE registers. changing DCLKMODE register, DCLK output held fixed phase, DOUTPHASE register values ignored. DCLK output also inverted with respect DOUT, using DCLKINV register bit. switching data outputs couple noise back into analog signal path. minimize switching noise, recommended that DOUTPHASE registers same edge sampling location, edges after sampling location. Other settings produce good results, experimentation necessary. recommended that DOUTPHASE location occur between sampling location edges after location. example, SHDLOC DOUTPHASE should edge location greater. adjustable phase required data outputs, output latch left transparent using Address 0x01, data output coding normally straight binary, coding changed gray coding setting Register Address 0x01,
Optical Black Clamp
optical black clamp loop used remove residual offsets signal chain track frequency variations CCD's black level. During optical black (shielded) pixel interval each line, output compared with fixed black level reference, selected user clamp level register. value programmed between 1023 steps. resulting error signal filtered reduce noise, correction value applied input through DAC. Normally, optical black clamp loop turned once horizontal line, this loop updated more slowly suit particular application. external digital clamping used during postprocessing, AD9992 optical
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AD9992
POWER-UP SEQUENCE MASTER MODE
When AD9992 powered following sequence recommended (refer Figure each step). Note that SYNC signal required master mode operation. external SYNC pulse available, possible generate internal SYNC event writing SWSYNC register. Turn power supplies AD9992 start master clock, CLI. Reset internal AD9992 registers writing SW_RST register (Address 0x10). default, Vertical Outputs low. necessary, write Standby3 output polarity (Address 0x26) different polarities vertical outputs order avoid damage V-driver CCD. Write Address 0x1C configure each V-output vertical transfer clock (XV) sensor pulse (VSG). Power-up V-driver supplies, anytime after Step complete proper polarities. Load required registers configure necessary vertical timing, horizontal timing, high speed timing, shutter timing. recommended start-up Address 0xD8 0x888. place part into normal power operation, write 0x04 register 0x00. This sets STANDBY register (AFE Register Address 0x00, Bits [1:0]) normal operation enables clamp (AFE Register Address 0x00, [2]). output being used drive crystal, also power oscillator writing Address 0x15. default, internal timing core held reset state, with TGCORE_RSTB register Write TGCORE_RSTB register (Address 0x14) start internal timing core operation. Note clock used input, CLIDIVIDE register (0x0D) should before resetting timing core. Configure AD9992 master mode timing writing MASTER register (Address 0x20). Write OUTCONTROL register (Address 0x11). This allows outputs become active after next SYNC rising edge. Normally OUTCONTROL takes effect after next edge; however, because part just being powered there edge until rising edge SYNC signal. Generate SYNC event. SYNC high power-up, bring SYNC input minimum then bring SYNC high again. This causes internal counters reset starts VD/HD operation. first VD/HD edge allows VD-updated register updates occur, including OUTCONTROL enable outputs. hardware SYNC available, SWSYNC register (Address 0x13, [14]) used initiate SYNC event.
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AD9992
SUPPLY V-DRIVER
POWER SUPPLIES
SUPPLY V-DRIVER
(INPUT) SERIAL WRITES SYNC (INPUT)
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