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analog supply operation output supply 71.8 (72.8 dBFS) input SFDR inpu


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14-Bit, MSPS, Analog-to-Digital Converter AD9254
analog supply operation output supply 71.8 (72.8 dBFS) input SFDR input power: MSPS Differential input with bandwidth On-chip voltage reference sample-and-hold amplifier ±0.4 Flexible analog input: range Offset binary, Gray code, twos complement data format Clock duty cycle stabilizer Data output clock Serial port control Built-in selectable digital test pattern generation Programmable clock data alignment
AVDD DRVDD
AD9254
VIN+ VIN- MDAC1 REFT REFB CORRECTION LOGIC OUTPUT BUFFERS VREF SENSE SELECT (MSB) (LSB) 0.5V CLOCK DUTY CYCLE STABILIZER MODE SELECT SCLK/DFS SDIO/DCS
06216-001
8-STAGE 1/2-BIT PIPELINE
APPLICATIONS
Ultrasound equipment sampling communications receivers CDMA2000, WCDMA, TD-SCDMA, WiMax Battery-powered instruments Hand-held scopemeters cost digital oscilloscopes Macro, micro, pico cell infrastructure
AGND
CLK+
CLK-
PDWN
DRGND
Figure
GENERAL DESCRIPTION
AD9254 monolithic, single supply, 14-bit, MSPS analog-to-digital converter (ADC), featuring high performance sample-and-hold amplifier (SHA) on-chip voltage reference. product uses multistage differential pipeline architecture with output error correction logic provide 14-bit accuracy MSPS data rates guarantees missing codes over full operating temperature range. wide bandwidth, truly differential allows variety user-selectable input ranges offsets, including single-ended applications. suitable multiplexed systems that switch full-scale voltage levels successive channels sampling single-channel inputs frequencies well beyond Nyquist rate. Combined with power cost savings over previously available ADCs, AD9254 suitable applications communications, imaging, medical ultrasound. differential clock input controls internal conversion cycles. duty cycle stabilizer (DCS) compensates wide variations clock duty cycle while maintaining excellent overall performance.
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
digital output data presented offset binary, Gray code, twos complement formats. data output clock (DCO) provided ensure proper latch timing with receiving logic. AD9254 available 48-lead LFCSP_VQ specified over industrial temperature range (-40°C +85°C).
PRODUCT HIGHLIGHTS
AD9254 operates from single power supply features separate digital output driver supply accommodate logic families. patented input maintains excellent performance input frequencies MHz. clock maintains overall performance over wide range clock pulse widths. standard serial port interface supports various product features functions, such data formatting (offset binary, twos complement, Gray coding), enabling clock DCS, power-down, voltage reference mode. AD9254 pin-compatible with AD9233, allowing simple migration from bits bits.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. rights reserved.
AD9254 TABLE CONTENTS
Features Applications. General Description Functional Block Diagram Product Highlights Revision History Specifications. Specifications Specifications. Digital Specifications Switching Specifications Timing Diagram Absolute Maximum Ratings. Thermal Resistance Caution. Configuration Function Descriptions. Equivalent Circuits Typical Performance Characteristics Theory Operation Analog Input Considerations. Differential Input Configurations Voltage Reference Clock Input Considerations Jitter Considerations Power Dissipation Standby Mode. Digital Outputs Timing Serial Port Interface (SPI). Configuration Using SPI. Hardware Interface. Configuration Without Memory Reading Memory Register Table. Memory Register Table. Layout Considerations. Power Ground Recommendations RBIAS. Reference Decoupling. Evaluation Board Power Supplies Input Signals. Output Signals Default Operation Jumper Selection Settings. Alternative Clock Configurations. Alternative Analog Input Drive Configuration. Schematics. Evaluation Board Layout. Bill Materials. Outline Dimensions Ordering Guide
REVISION HISTORY
10/06-Revision Initial Version
Rev. Page
AD9254 SPECIFICATIONS
SPECIFICATIONS
AVDD DRVDD maximum sample rate, differential input, internal reference; -1.0 dBFS, enabled, unless otherwise noted. Table
Parameter RESOLUTION ACCURACY Missing Codes Offset Error Gain Error Differential Nonlinearity (DNL) Integral Nonlinearity (INL)1 TEMPERATURE DRIFT Offset Error Gain Error INTERNAL VOLTAGE REFERENCE Output Voltage Error Mode) Load Regulation INPUT REFERRED NOISE VREF ANALOG INPUT Input Span, VREF Input Capacitance REFERENCE INPUT RESISTANCE POWER SUPPLIES Supply Voltage AVDD DRVDD Supply Current IAVDD1 IDRVDD1(DRVDD IDRVDD1 (DRVDD POWER CONSUMPTION Input Sine Wave Input1 (DRVDD Sine Wave Input1 (DRVDD Standby Power Power-Down Power
Temperature Full Full Full Full 25°C Full 25°C Full Full Full Full Full 25°C Full Full Full
AD9254BCPZ-150
Unit Bits
Guaranteed ±0.3 ±0.8 ±0.6 ±4.5 ±0.4 ±1.0 ±1.5 ±5.0
ppm/°C ppm/°C
Full Full Full Full Full Full Full Full Full Full
Measured with input frequency, full-scale sine wave, with approximately loading each output bit. Input capacitance refers effective capacitance between differential input AGND. Refer Figure equivalent analog input structure. Standby power measured with input, inactive (set AVDD AGND).
Rev. Page
AD9254
SPECIFICATIONS
AVDD DRVDD maximum sample rate, differential input, internal reference; -1.0 dBFS, enabled, unless otherwise noted. Table
Parameter SIGNAL-TO-NOISE-RATIO (SNR) SIGNAL-TO-NOISE DISTORTION (SINAD) EFFECTIVE NUMBER BITS (ENOB) WORST SECOND THIRD HARMONIC SPURIOUS-FREE DYNAMIC RANGE (SFDR) WORST OTHER (HARMONIC SPUR) TWO-TONE SFDR dBFS dBFS dBFS dBFS ANALOG INPUT BANDWIDTH
Temperature 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C Full 25°C 25°C 25°C 25°C 25°C
AD9254BCPZ-150 72.0 71.8
Unit Bits Bits Bits Bits dBFS dBFS
70.0 71.6 70.8 71.7 71.0 69.0 70.6 69.8 11.7 11.7 11.6 11.5
Application Note AN-835, Understanding High Speed Testing Evaluation, complete definitions.
Rev. Page
AD9254
DIGITAL SPECIFICATIONS
AVDD DRVDD maximum sample rate, differential input, internal reference; -1.0 dBFS, enabled, unless otherwise noted. Table
Parameter DIFFERENTIAL CLOCK INPUTS (CLK+, CLK-) Logic Compliance Internal Common-Mode Bias Differential Input Voltage Input Voltage Range Input Common-Mode Range High Level Input Voltage (VIH) Level Input Voltage (VIL) High Level Input Current (IIH) Level Input Current (IIL) Input Resistance Input Capacitance LOGIC INPUTS (SCLK/DFS, OEB, PWDN) High Level Input Voltage (VIH) Level Input Voltage (VIL) High Level Input Current (IIH) Level Input Current (IIL) Input Resistance Input Capacitance LOGIC INPUTS (CSB) High Level Input Voltage (VIH) Level Input Voltage (VIL) High Level Input Current (IIH) Level Input Current (IIL) Input Resistance Input Capacitance LOGIC INPUTS (SDIO/DCS) High Level Input Voltage (VIH) Level Input Voltage (VIL) High Level Input Current (IIH) Level Input Current (IIL) Input Resistance Input Capacitance DIGITAL OUTPUTS DRVDD High Level Output Voltage (VOH, High Level Output Voltage (VOH, Level Output Voltage (VOL, Level Output Voltage (VOL, DRVDD High Level Output Voltage (VOH, High Level Output Voltage (VOH, Level Output Voltage (VOL, Level Output Voltage (VOL, Temperature AD9254BCPZ-150 CMOS/LVDS/LVPECL AVDD AVDD AVDD Unit
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
+135
DRVDD +130
Full Full Full Full Full Full Full Full
3.29 3.25 0.05 1.79 1.75 0.05
Rev. Page
AD9254
SWITCHING SPECIFICATIONS
AVDD DRVDD unless otherwise noted. Table
Parameter CLOCK INPUT PARAMETERS Conversion Rate, Enabled Conversion Rate, Disabled Period Pulse Width High, Enabled Pulse Width High, Disabled DATA OUTPUT PARAMETERS Data Propagation Delay (tPD) Propagation Delay (tDCO) Setup Time (tS) Hold Time (tH) Pipeline Delay (Latency) Aperture Delay (tA) Aperture Uncertainty (Jitter, Wake-Up Time OUT-OF-RANGE RECOVERY TIME SERIAL PORT INTERFACE SCLK Period (tCLK) SCLK Pulse Width High Time (tHI) SCLK Pulse Width Time (tLO) SDIO SCLK Setup Time (tDS) SDIO SCLK Hold Time (tDH) SCLK Setup Time (tS) SCLK Hold Time (tH)
Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
AD9254BCPZ-150
Unit MSPS MSPS Cycles Cycles
Application Note AN-835, Understanding High Speed Testing Evaluation, complete definitions. Output propagation delay measured from transition DATA transition, with load. Wake-up time dependent value decoupling capacitors, values shown with capacitor across REFT REFB. Figure Serial Port Interface (SPI) section.
TIMING DIAGRAM
tCLK
CLK+ CLK-
DATA
Figure Timing Diagram
Rev. Page
06216-002
tDCO
tCLK
AD9254 ABSOLUTE MAXIMUM RATINGS
Table
Parameter ELECTRICAL AVDD AGND DRVDD DGND AGND DGND AVDD DRVDD through DGND DGND DGND CLK+ AGND CLK- AGND VIN+ AGND VIN- AGND VREF AGND SENSE AGND REFT AGND REFB AGND SDIO/DCS DGND PDWN AGND AGND SCLK/DFS AGND AGND ENVIRONMENTAL Storage Temperature Range Operating Temperature Range Lead Temperature (Soldering Sec) Junction Temperature Rating -0.3 +2.0 -0.3 +3.9 -0.3 +0.3 -3.9 +2.0 -0.3 DRVDD -0.3 DRVDD -0.3 DRVDD -0.3 +3.9 -0.3 +3.9 -0.3 AVDD -0.3 AVDD -0.3 AVDD -0.3 AVDD -0.3 AVDD -0.3 AVDD -0.3 DRVDD -0.3 +3.9 -0.3 +3.9 -0.3 +3.9 -0.3 +3.9 -65°C +125°C -40°C +85°C 300°C 150°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
THERMAL RESISTANCE
exposed paddle must soldered ground plane LFCSP_VQ package. Soldering exposed paddle customer board increases reliability solder joints, maximizing thermal capability package. Table Thermal Resistance
Package Type 48-lead LFCSP_VQ (CP-48-3) 26.4 Unit °C/W
Typical specified 4-layer board still air. Airflow increases heat dissipation, effectively reducing addition, metal direct contact with package leads from metal traces through holes, ground, power planes, reduces
CAUTION
Rev. Page
AD9254 CONFIGURATION FUNCTION DESCRIPTIONS
DRVDD DRGND (LSB) AVDD AGND AVDD CLK- CLK+ AGND
INDICATOR
DRGND DRVDD
AD9254
VIEW (Not Scale)
PDWN RBIAS AVDD AGND VIN- VIN+ AGND REFT REFB VREF SENSE
(MSB) DRGND DRVDD SDIO/DCS SCLK/DFS AGND AVDD AGND AVDD
Figure Configuration
Table Function Description
Mnemonic AGND (LSB) (MSB) DRGND DRVDD SDIO/DCS SCLK/DFS AVDD SENSE VREF REFB REFT VIN+ VIN- RBIAS PDWN CLK+ CLK- Description Analog Ground. (Pin exposed thermal bottom package.) Data Output Bits. Digital Output Ground. Digital Output Driver Supply (1.8 Out-of-Range Indicator. Serial Port Interface (SPI) Data Input/Output (Serial Port Mode); Duty Cycle Stabilizer Select (External Mode). Table Serial Port Interface Clock (Serial Port Mode); Data Format Select (External Mode). Serial Port Interface Chip Select (Active Low). Table Analog Power Supply. Reference Mode Selection. Table Voltage Reference Input/Output. Differential Reference (-). Differential Reference (+). Analog Input (+). Analog Input (-). Common-Mode Level Bias Output. External Bias Resistor Connection. resistor must connected between this analog ground (AGND). Power-Down Function Select. Clock Input (+). Clock Input (-). Output Enable (Active Low). Data Clock Output.
Rev. Page
06216-003
AD9254 EQUIVALENT CIRCUITS
SCLK/DFS PDWN
06216-004
Figure Equivalent Analog Input Circuit
AVDD
Figure Equivalent SCLK/DFS, OEB, PDWN Input Circuit
AVDD
1.2V CLK+ CLK-
06216-005
Figure Equivalent Clock Input Circuit
DRVDD
Figure Equivalent Input Circuit
SENSE
SDIO/DCS
06216-006
Figure Equivalent SDIO/DCS Input Circuit
DRVDD
Figure Equivalent Sense Circuit
AVDD
VREF
06216-011
DRGND
06216-007
Figure Equivalent Digital Output Circuit
Figure Equivalent VREF Circuit
Rev. Page
06216-010
06216-009
06216-008
AD9254 TYPICAL PERFORMANCE CHARACTERISTICS
AVDD DRVDD maximum sample rate, enabled, internal reference; differential input; -1.0 dBFS; sample; 25°C, unless otherwise noted.
150MSPS 2.3MHz -1dBFS 72.0dBc (73.0dBFS) ENOB 11.7 BITS SFDR 90.0dBc
AMPLITUDE (dBFS)
150MSPS 100.3MHz -1dBFS 71.6dBc (72.6dBFS) ENOB 11.6 BITS SFDR 83dBc
AMPLITUDE (dBFS)
-100
-100
06216-012
18.75
37.50 FREQUENCY (MHz)
56.25
75.00
18.75
37.50 FREQUENCY (MHz)
56.25
75.00
Figure AD9254 Single-Tone with
Figure AD9254 Single-Tone with 100.3
150MSPS 30.3MHz -1dBFS 71.9dBc (72.9dBFS) ENOB 11.7 BITS SFDR 88dBc
AMPLITUDE (dBFS)
150MSPS 140.3MHz -1dBFS 71.5dBc (72.5dBFS) ENOB 11.5 BITS SFDR 81dBc
AMPLITUDE (dBFS)
-100
-100
06216-013
18.75
37.50 FREQUENCY (MHz)
56.25
75.00
18.75
37.50 FREQUENCY (MHz)
56.25
75.00
Figure AD9254 Single-Tone with 30.3
Figure AD9254 Single-Tone with 140.3
150MSPS 70.3MHz -1dBFS 71.8dBc (72.8dBFS) ENOB 11.7 BITS SFDR 84dBc
AMPLITUDE (dBFS)
150MSPS 170.3MHz -1dBFS 70.8dBc (71.8dBFS) ENOB 11.5 BITS SFDR 80dBc
AMPLITUDE (dBFS)
-100
-100
06216-014
18.75
37.50 FREQUENCY (MHz)
56.25
75.00
18.75
37.50 FREQUENCY (MHz)
56.25
75.00
Figure AD9254 Single-Tone with 70.3
Figure AD9254 Single-Tone with 170.3
Rev. Page
06216-017
-120
-120
06216-016
-120
-120
06216-015
-120
-120
AD9254
150MSPS 250.3MHz -1dBFS 69.3dBc (70.3dBFS) ENOB 11.3 BITS SFDR 79dBc SFDR (dBFS)
SNR/SFDR (dBc dBFS)
AMPLITUDE (dBFS)
(dBFS)
SFDR (dBc)
-100
(dBc)
06216-018
85dBc REFERENCE LINE
18.75
37.50 FREQUENCY (MHz)
56.25
75.00
INPUT AMPLITUDE (dBFS)
Figure AD9254 Single-Tone with 250.3
Figure AD9254 Single-Tone SNR/SFDR Input Amplitude (AIN) with
SFDR/WORST IMD3 (dBc dBFS)
150MSPS fIN1 29.1MHz -7dBFS fIN2 32.1MHz -7dBFS SFDR 83.2dBc (90.2dBFS) WoIMD3 -83.9dBc (-90.9dBFS)
SFDR (-dBc) WORST IMD3 (dBc)
AMPLITUDE (dBFS)
SFDR (-dBFS) -100 WORST IMD3 (dBFS) INPUT AMPLITUDE (dBFS)
06216-022 06216-023
-100
18.75
37.50 FREQUENCY (MHz)
56.25
75.00
06216-019
-120
-120
Figure AD9254 Two-Tone with fIN1 29.1 MHz, fIN2 32.1
SFDR -40°C SFDR +25°C
SNR/SFDR (dBc)
Figure AD9254 Two-Tone SFDR/IMD3 Input Amplitude (AIN) with fIN1 29.1 MHz, fIN2 32.1
SFDR +25°C SFDR -40°C
SNR/SFDR (dBc)
SFDR +85°C
-40°C SFDR +85°C
+25°C
-40°C
+25°C
+85°C
06216-020
+85°C INPUT FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure AD9254 Single-Tone SNR/SFDR Input Frequency (fIN) Temperature with Full Scale
Figure AD9254 Single-Tone SNR/SFDR Input Frequency (fIN) Temperature with Full Scale
Rev. Page
06216-021
-120
AD9254
150MSPS fIN1 169.1MHz -7dBFS fIN2 172.1MHz -7dBFS SFDR 83dBc (90dBFS) WoIMD3 -83dBc (90dBFS)
AMPLITUDE (dBFS)
ERROR (LSB)
-0.5 -1.0
-100
-1.5 -2.0
06216-024
18.75
37.50 FREQUENCY (MHz)
56.25
75.00
2048
4096
6144
8192
10240
12288
14336
16384
OUTPUT CODE
Figure AD9254 Two-Tone with fIN1 169.1 MHz, fIN2 172.1
12000
Figure AD9254 with 10.3
32768 SAMPLES 1.25
SFDR
10000
NUMBER HITS
SNR/SFDR (dBc)
8000
6000
4000
2000
06216-025
N-5N-4N-3N-2N-1
CODE
N+1N+2N+3N+4N+5
CLOCK FREQUENCY (MSPS)
Figure AD9254 Single-Tone SNR/SFDR Clock Frequency (fCLK) with
Figure AD9254 Grounded Input Histogram
SFDR/WORST IMD3 (dBc dBFS)
SFDR (-dBc)
OFFSET ERROR -0.5
ERROR (%FS)
WORST IMD3 (dBc)
-1.0
-1.5 GAIN ERROR
SFDR (-dBFS) -100 WORST IMD3 (dBFS)
06216-027
-2.0
INPUT AMPLITUDE (dBFS)
TEMPERATURE (°C)
Figure AD9254 Two-Tone SFDR/IMD3 Input Amplitude (AIN) with fIN1 169.1 MHz, fIN2 172.11
Figure AD9254 Gain Offset Temperature
Rev. Page
06216-033
-120
-2.5
06216-032
06216-031
-120
AD9254
ERROR (LSB)
-0.1 -0.2 -0.3 -0.4 2048 4096 6144 8192 10240 12288 14336 16384
06216-034
-0.5
OTUPUT CODE
Figure AD9254 with 10.3
Rev. Page
AD9254 THEORY OPERATION
AD9254 architecture consists front-end sample-andhold amplifier (SHA) followed pipelined switched capacitor ADC. quantized outputs from each stage combined into final 14-bit result digital correction logic. pipeline architecture permits first stage operate input sample, while remaining stages operate preceding samples. Sampling occurs rising edge clock. Each stage pipeline, excluding last, consists resolution flash connected switched capacitor interstage residue amplifier (MDAC). residue amplifier magnifies difference between reconstructed output flash input next stage pipeline. redundancy used each stage facilitate digital correction flash errors. last stage consists only flash ADC. input stage contains differential that dc-coupled differential single-ended modes. output staging block aligns data, carries error correction, passes data output buffers. output buffers powered from separate supply, allowing adjustment output voltage swing. During power-down, output buffers into high impedance state.
VIN+ CPIN, VIN- CPIN,
Figure Switched-Capacitor Input
best dynamic performance, source impedances driving VIN+ VIN- should match such that common-mode settling errors symmetrical. These errors reduced common-mode rejection ADC. internal differential reference buffer creates reference voltages used define input span core. span core buffer VREF. reference voltages available user. bypass points, REFT REFB, brought decoupling reduce noise contributed internal reference buffer. recommended that REFT decoupled REFB capacitor, described Layout Considerations section.
ANALOG INPUT CONSIDERATIONS
analog input AD9254 differential switched capacitor that been designed optimum performance while processing differential input signal. clock signal alternately switches between sample mode hold mode (see Figure 31). When switched into sample mode, signal source must capable charging sample capacitors settling within one-half clock cycle. small resistor series with each input help reduce peak transient current required from output stage driving source. shunt capacitor placed across inputs provide dynamic charging currents. This passive network creates lowpass filter input; therefore, precise values dependent upon application. undersampling applications, shunt capacitors should reduced. combination with driving source impedance, these capacitors would limit input bandwidth. more information, Application Note AN-742, Frequency Domain Response Switched-Capacitor ADCs; Application Note AN-827, Resonant Approach Interfacing Amplifiers SwitchedCapacitor ADCs; Analog Dialogue article, "TransformerCoupled Front-End Wideband Converters."
Input Common Mode
analog inputs AD9254 internally dc-biased. ac-coupled applications, user must provide this bias externally. Setting device such that 0.55 AVDD recommended optimum performance; however, device functions over wider range with reasonable performance (see Figure 30). on-board common-mode voltage reference included design available from pin. Optimum performance achieved when common-mode voltage analog input voltage (typically 0.55 AVDD). must decoupled ground capacitor, described Layout Considerations section.
Rev. Page
06216-035
AD9254
DIFFERENTIAL INPUT CONFIGURATIONS
Optimum performance achieved driving AD9254 differential input configuration. baseband applications, AD8138 differential driver provides excellent performance flexible interface ADC. output common-mode voltage AD8138 easily with AD9254 (see Figure 32), driver configured Sallen-Key filter topology provide band limiting input signal.
49.9 VIN+ AVDD
alternative using transformer-coupled input frequencies second Nyquist zone, AD8352 differential driver used (see Figure 36). configuration, value shunt capacitor, dependent input frequency source impedance need reduced removed. Table displays recommended values network. However, these values dependent input signal should only used starting guide. Table Network Recommended Values
Frequency Range (MHz) >300 Series Differential (pF) Open
AD8138
0.1µF
AD9254
06216-036
VIN-
Figure Differential Input Configuration Using AD8138
Single-Ended Input Configuration
Although recommended, possible operate AD9254 single-ended input configuration, long input voltage swing within AVDD supply. Single-ended operation provide adequate performance cost-sensitive applications. this configuration, SFDR distortion performance degrade large input common-mode swing. source impedances each input matched, there should little effect performance. Figure details typical single-ended input configuration.
10µF AVDD 49.9 0.1µF VIN+
baseband applications where parameter, differential transformer coupling recommended input configuration (see Figure 33). voltage connected center secondary winding transformer bias analog input. signal characteristics must considered when selecting transformer. Most transformers saturate frequencies below megahertz, excessive signal power cause core saturation, which leads distortion.
VIN+
49.9
AD9254
VIN-
AVDD 10µF 0.1µF
AD9254
VIN-
06216-038
0.1µF
Figure Differential Transformer-Coupled Configuration
06216-037
input frequencies second Nyquist zone above, noise performance most amplifiers adequate achieve true performance AD9254. applications where parameter, transformer coupling recommended input. applications where SFDR parameter, differential double balun coupling recommended input configuration (see Figure 35).
Figure Single-Ended Input Configuration
Rev. Page
AD9254
0.1µF 0.1µF 0.1µF 0.1µF VIN+
AD9254
VIN-
06216-039
Figure Differential Double Balun Input Configuration
0.1µF 0.1µF 0.1µF 0.1µF
06216-040
0.1µF
VIN+
AD8352
0.1µF
AD9254
VIN-
0.1µF
Figure Differential Input Configuration Using AD8352
Table Reference Configuration Summary
Selected Mode External Reference Internal Fixed Reference Programmable Reference Internal Fixed Reference SENSE Voltage AVDD VREF VREF AGND Resulting VREF Resulting Differential Span p-p) external reference VREF
(see Figure
VOLTAGE REFERENCE
stable accurate voltage reference built into AD9254. input range adjustable varying reference voltage applied AD9254, using either internal reference externally applied reference voltage. input span tracks reference voltage changes linearly. various reference modes summarized following sections. Reference Decoupling section describes best practices requirements layout reference.
Connecting SENSE VREF switches reference amplifier input SENSE pin, completing loop providing reference output. resistor divider connected external chip, shown Figure switch sets SENSE pin. This puts reference amplifier noninverting mode with VREF output defined
VREF
Internal Reference Connection
comparator within AD9254 detects potential SENSE configures reference into four possible states, summarized Table SENSE grounded, reference amplifier switch connected internal resistor divider (see Figure 37), setting VREF
SENSE connected AVDD, reference amplifier disabled, external reference voltage applied VREF (see External Reference Operation section). input range always equals twice voltage reference either internal external reference.
Rev. Page
AD9254
VIN+ VIN-
CORE
External Reference Operation
REFT
0.1µF
external reference necessary enhance gain accuracy improve thermal drift characteristics. Figure shows typical drift characteristics internal reference both modes.
REFB VREF SELECT LOGIC SENSE 0.5V
06216-041
REFERENCE VOLTAGE ERROR (mV)
0.1µF
0.1µF
VREF
VREF 0.5V
AD9254
Figure Internal Reference Configuration
VIN+ VIN-
REFT
TEMPERATURE (°C)
0.1µF
Figure Typical VREF Drift
REFB VREF 0.1µF 0.1µF SENSE SELECT LOGIC
0.5V
06216-042
When SENSE tied AVDD, internal reference disabled, allowing external reference. internal resistor divider loads external reference with equivalent load (see Figure 11). addition, internal buffer generates positive negative full-scale references core. Therefore, external reference must limited maximum
AD9254
Figure Programmable Reference Configuration
CLOCK INPUT CONSIDERATIONS
optimum performance, AD9254 sample clock inputs (CLK+ CLK-) should clocked with differential signal. signal typically ac-coupled into CLK+ CLK- transformer capacitors. These pins biased internally (see Figure require external bias.
internal reference AD9254 used drive multiple converters improve gain matching, loading reference other converters must considered. Figure depicts internal reference voltage affected loading.
VREF 0.5V
Clock Input Options
AD9254 very flexible clock input structure. clock input CMOS, LVDS, LVPECL, sine wave signal. Regardless type signal used, jitter clock source most concern, described Jitter Considerations section. Figure shows preferred method clocking AD9254. jitter clock source converted from singleended differential signal using transformer. back-to-back Schottky diodes across transformer secondary limit clock excursions into AD9254 approximately differential. This helps prevent large voltage swings clock from feeding through other portions AD9254, while preserving fast rise fall times signal, which critical jitter performance.
REFERENCE VOLTAGE ERROR
-0.25 VREF -0.50
-0.75
-1.00
LOAD CURRENT (mA)
Figure VREF Accuracy Load
06216-043
-1.25
Rev. Page
06216-044
CORE
AD9254
0.1µF CLOCK INPUT MINI-CIRCUITS ADT1-1WT, 1:1Z 0.1µF XFMR 0.1µF 0.1µF SCHOTTKY DIODES: HMS2812
0.1µF CLOCK INPUT AD951x CMOS DRIVER OPTIONAL 0.1µF CLK+
CLK+
AD9254
06216-045
AD9254
CLK- 0.1µF
06216-048
CLK-
Figure Transformer Coupled Differential Clock
RESISTOR OPTIONAL.
Figure Single-Ended CMOS Sample Clock
jitter clock source available, another option ac-couple differential PECL signal sample clock input pins shown Figure AD9510/AD9511/AD9512/ AD9513/AD9514/AD9515 family clock drivers offers excellent jitter performance.
CLOCK INPUT 0.1µF 0.1µF AD951x CMOS DRIVER OPTIONAL 0.1µF CLK+
AD9254
06216-049
CLK-
0.1µF AD951x 0.1µF PECL DRIVER
CLOCK INPUT
0.1µF CLK+ 0.1µF
06216-046
RESISTOR OPTIONAL.
AD9254
CLK-
Figure Single-Ended CMOS Sample Clock
Clock Duty Cycle
Typical high speed ADCs both clock edges generate variety internal timing signals. result, these ADCs sensitive clock duty cycle. Commonly, tolerance required clock duty cycle maintain dynamic performance characteristics. AD9254 contains duty cycle stabilizer (DCS) that retimes nonsampling, falling edge, providing internal clock signal with nominal duty cycle. This allows wide range clock input duty cycles without affecting performance AD9254. Noise distortion performance nearly flat wide range duty cycles when shown Figure Jitter rising edge input still paramount concern reduced internal stabilization circuit. duty cycle control loop does function clock rates less than nominally. loop time constant associated with that needs considered applications where clock rate change dynamically. This requires wait time after dynamic clock frequency increase decrease) before loop relocked input signal. During time period loop locked, loop bypassed, internal device timing dependent duty cycle input clock signal. such application, appropriate disable duty cycle stabilizer. other applications, enabling circuit recommended maximize performance.
CLOCK INPUT
RESISTORS OPTIONAL.
Figure Differential PECL Sample Clock
third option ac-couple differential LVDS signal sample clock input pins, shown Figure AD9510/ family clock drivers offers excellent jitter performance.
0.1µF CLOCK INPUT AD951x 0.1µF LVDS DRIVER
0.1µF CLK+ 0.1µF
AD9254
CLK-
06216-047
CLOCK INPUT
RESISTORS OPTIONAL.
Figure Differential LVDS Sample Clock
some applications, acceptable drive sample clock inputs with single-ended CMOS signal. such applications, directly drive CLK+ from CMOS gate, while bypassing CLK- ground using capacitor parallel with resistor (see Figure 44). CLK+ directly driven from CMOS gate. This input designed withstand input voltages making selection drive logic voltage very flexible. When driving CLK+ with CMOS signal, biasing CLK- with capacitor parallel with resistor (see Figure required. resistor required when driving CLK+ with CMOS signal (see Figure 45).
Rev. Page
AD9254
enabled disabled setting SDIO/DCS when operating external mode (see Table 10), SPI, described Table Table Mode Selection (External Mode)
Voltage AGND AVDD SCLK/DFS Binary (default) Twos complement SDIO/DCS disabled enabled (default)
POWER DISSIPATION STANDBY MODE
power dissipated AD9254 proportional sample rate (see Figure 47). digital power dissipation determined primarily strength digital drivers load each output bit. Maximum DRVDD current (IDRVDD) calculated
DRVDD VDRVDD CLOAD
fCLK
JITTER CONSIDERATIONS
High speed, high resolution ADCs sensitive quality clock input. degradation given input frequency (fIN) jitter (tJ) calculated follows: equation, aperture jitter represents root mean square jitter sources, which include clock input, analog input signal, aperture jitter specification. undersampling applications particularly sensitive jitter, shown Figure
where number output bits, AD9254. This maximum current occurs when every output switches every clock cycle, that full-scale square wave Nyquist frequency, fCLK/2. practice, DRVDD current established average number output bits switching, which determined sample rate characteristics analog input signal. Reducing capacitive load presented output drivers minimize digital power consumption. data Figure taken under same operating conditions data Typical Performance Characteristics section, with load each output driver.
0.05ps
MEASURED PERFORMANCE
(AVDD)
POWER (mW)
0.20ps
POWER (DRVDD)
0.5ps 1.0ps 1.50ps 2.00ps 2.50ps 3.00ps 1000
06216-050
CLOCK FREQUENCY (MHz)
INPUT FREQUENCY (MHz)
Figure Input Frequency Jitter
Figure AD9254 Power Current Clock Frequency
Power-Down Mode
Treat clock input analog signal cases where aperture jitter affect dynamic range AD9254. Power supplies clock drivers should separated from output driver supplies avoid modulating clock signal with digital noise. power supplies should also shared with analog input circuits, such buffers, avoid clock modulating onto input signal vice versa. jitter, crystal-controlled oscillators make best clock sources. clock generated from another type source gating, dividing, other methods), should retimed original clock last step. Refer Application Notes AN-501, Aperture Uncertainty System Performance; AN-756, Sampled Systems Effects Clock Phase Noise Jitter, more in-depth information about jitter performance relates ADCs.
asserting PDWN high, AD9254 placed powerdown mode. this state, typically dissipates During power-down, output drivers placed high impedance state. Reasserting PDWN returns AD9254 normal operational mode. This both tolerant. power dissipation power-down mode achieved shutting down reference, reference buffer, biasing networks, clock. decoupling capacitors REFT REFB discharged when entering power-down mode then must recharged when returning normal operation. result, wake-up time related time spent power-down mode; shorter power-down cycles result proportionally shorter wake-up times. With recommended decoupling capacitors REFT REFB, takes approximately 0.25 fully discharge reference buffer decoupling capacitors 0.35 restore full operation.
Rev. Page
06216-051
CURRENT (mA)
(dBc)
AD9254
Standby Mode
When using port interface, user place power-down standby modes. Standby mode allows user keep internal reference circuitry powered when faster wake-up times required (see Memory section). logically AND'ing with complement, overrange high underrange conditions detected. Table truth table overrange/underrange circuit Figure which uses NAND gates.
UNDER
06216-053
OVER
DIGITAL OUTPUTS
AD9254 output drivers configured interface with logic families matching DRVDD digital supply interfaced logic. output drivers sized provide sufficient output current drive wide variety logic families. However, large drive currents tend cause current glitches supplies that affect converter performance. Applications requiring drive large capacitive loads large fan-outs require external buffers latches. output data format selected either offset binary twos complement setting SCLK/DFS when operating external mode (see Table 10). detailed Interfacing High Speed ADCs user manual, data format selected either offset binary, twos complement, Gray code when using control.
Figure Overrange/Underrange Logic
Table Overrange/Underrange Truth Table
Analog Input Within range Within range Underrange Overrange
Digital Output Enable Function (OEB)
AD9254 three-state ability. low, output data drivers enabled. high, output data drivers placed high impedance state. This intended rapid access data bus. Note that referenced digital supplies (DRVDD) should exceed that supply voltage.
Out-of-Range (OR) Condition
out-of-range condition exists when analog input voltage beyond input range ADC. digital output that updated along with data output corresponding particular sampled input voltage. Thus, same pipeline latency digital data.
DATA OUTPUTS 1111 1111 1111 1111 1111 1111 1111 1111 1110
TIMING
lowest typical conversion rate AD9254 MSPS. clock rates below MSPS, dynamic performance degrade. AD9254 provides latched data outputs with pipeline delay twelve clock cycles. Data outputs available propagation delay (tPD) after rising edge clock signal. length output data lines loads placed them should minimized reduce transients within AD9254. These transients degrade dynamic performance converter.
0000 0000 0001 0000 0000 0000 0000 0000 0000
06216-052
Data Clock Output (DCO)
AD9254 also provides data clock output (DCO) intended capturing data external register. data outputs valid rising edge DCO, unless clock polarity been changed SPI. Figure graphical timing description.
Figure Relation Input Voltage Output Data
when analog input voltage within analog input range high when analog input voltage exceeds input range, shown Figure remains high until analog input returns within input range another conversion completed. Table Output Data Format
Input VIN+ VIN- VIN+ VIN- VIN+ VIN- VIN+ VIN- VIN+ VIN- Condition -VREF -VREF +VREF +VREF Binary Output Mode 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111
Twos Complement Mode 0000 0000 0000 0000 0000 0000 0000 0000 0000 1111 1111 1111 1111 1111 1111
Gray Code Mode (SPI Accessible) 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000 0000
Rev. Page
AD9254 SERIAL PORT INTERFACE (SPI)
AD9254 serial port interface (SPI) allows user configure converter specific functions operations through structured register space provided inside ADC. This provides user added flexibility customization depending application. Addresses accessed serial port written read from port. Memory organized into bytes that further divided into fields, documented Memory section. detailed operational information, Interfacing High Speed ADCs user manual. addition word length, instruction phase determines serial frame read write operation, allowing serial port used both program chip well read contents on-chip memory. instruction readback operation, performing readback causes serial data input/output (SDIO) change direction from input output appropriate point serial frame. Data sent MSB- LSB-first mode. first default power-up changed configuration register. more information, Interfacing High Speed ADCs user manual. Table Timing Diagram Specifications
Name tCLK Description Setup time between data rising edge SCLK Hold time between data rising edge SCLK Period clock Setup time between SCLK Hold time between SCLK Minimum period that SCLK should logic high state Minimum period that SCLK should logic state
CONFIGURATION USING
summarized Table three pins define this ADC. SCLK/DFS synchronizes read write data presented ADC. SDIO/DCS dual-purpose allows data sent read from internal memory registers. active control that enables disables read write cycles. Table Serial Port Interface Pins
Name SCLK/DFS SDIO/DCS Function SCLK (serial clock) serial shift clock SCLK synchronizes serial interface reads writes. SDIO (serial data input/output) dual-purpose pin. typical role this input output, depending instruction being sent relative position timing frame. (chip select bar) active-low control that gates read write cycles.
HARDWARE INTERFACE
pins described Table comprise physical interface between user's programming device serial port AD9254. SCLK pins function inputs when using interface. SDIO bidirectional, functioning input during write phases output during readback. interface flexible enough controlled either PROM microcontrollers. This provides user with ability alternate method program ADC. method described detail Application Note AN-812, Microcontroller-Based Serial Port Interface Boot Circuit. When interface used, some pins serve dual function. When strapped AVDD ground during device power pins associated with specific function.
falling edge conjunction with rising edge SCLK determines start framing. Figure Table provide examples serial timing definitions. Other modes involving available. held indefinitely permanently enable device (this called streaming). stall high between bytes allow additional external timing. When tied high, functions placed high impedance mode. This mode turns secondary functions. During instruction phase, 16-bit instruction transmitted. Data follows instruction phase length determined bit. data composed 8-bit words. first each individual byte serial data indicates whether read write command issued. This allows serial data input/output (SDIO) change direction from input output.
CONFIGURATION WITHOUT
applications that interface control registers, SDIO/DCS SCLK/DFS pins serve stand-alone CMOS-compatible control pins. When device powered assumed that user intends pins static control lines output data format duty cycle stabilizer (see Table 10). this mode, chip select should connected AVDD, which disables serial port interface. more information, Interfacing High Speed ADCs user manual.
Rev. Page
AD9254 MEMORY
READING MEMORY REGISTER TABLE
Each memory register table eight address locations. memory roughly divided into three sections: chip configuration registers (Address 0x00 Address 0x02), device index transfer registers (Address 0xFF), functions (Address 0x08 Address 0x18). Table displays register address number hexadecimal first column. last column displays default value each hexadecimal address. (MSB) column start default hexadecimal value given. example, Hexadecimal Address 0x14, output_phase, hexadecimal default value 0x00. This means 0011 binary. This setting default output clock phase adjust option. default value adjusts phase relative nominal edge 180° relative data edge. more information this function, consult Interfacing High Speed ADCs user manual.
Default Values
Coming reset, critical registers loaded with default values. default values registers shown Table
Logic Levels
explanation registers follows: "Bit set" synonymous with "Bit Logic "Writing Logic bit." "Clear bit" synonymous with "Bit Logic "Writing Logic bit."
SPI-Accessible Features
list features accessible brief description what user with these features follows. These features described detail Interfacing High Speed ADCs user manual. Modes: either power-down standby mode. Clock: Access SPI. Offset: Digitally adjust converter offset. Test I/O: test modes have known data output bits. Output Mode: Setup outputs, vary strength output drivers. Output Phase: output clock polarity. VREF: reference voltage.
Open Locations
Locations marked open currently supported this device. When required, these locations should written with Writing these locations required only when part address location open (for example, Address 0x14). entire address location open (Address 0x13), then address location does need written.
tCLK
SCLK DON'T CARE
DON'T CARE
SDIO DON'T CARE
DON'T CARE
Figure Serial Port Interface Timing Diagram
Rev. Page
06216-054
AD9254
MEMORY REGISTER TABLE
Table Memory Register
Addr. (Hex) Parameter Name (MSB) Chip Configuration Registers chip_port_config first (Default) Soft reset (Default) Soft reset (Default) first (Default) (LSB) Default Value (Hex) 0x18 Default Notes/ Comments nibbles should mirrored. Interfacing High Speed ADCs user manual. Default unique chip different each device. Child used differentiate speed grades. Synchronously transfers data from master shift register slave. Determines various generic modes chip operation. Power
chip_id
8-bit Chip Bits (AD9254 0x00), (default) Open Open Open Open Child MSPS Open Open Open Open
Read only Read only
chip_grade
Device Index Transfer Registers device_update Open
Open
Open
Open
Open
Open
transfer
0x00
Global Functions modes
Open
Open
PDWN 0-Full Standby
Open
Open
Internal power-down mode 000-normal (power-up) 001-full power-down 010-standby 011-normal (power-up) Note: External PDWN overrides this setting.
0x00
Dissipation Standby Mode SPIAccessible Features
sections. 0x01 Clock
clock
Open
Open
Open
Open
Open
Open
Open
Duty cycle stabilizer disabled enabled
Duty Cycle
section
SPI-Accessible Features section.
Rev. Page
AD9254
Addr. (Hex) Parameter Name (MSB) Flexible Functions offset (LSB) Default Value (Hex) 0x00 Default Notes/ Comments Adjustable offset inherent converter.
test_io
Digital Offset Adjust<5:0> 011111 011110 011101 000010 000001 000000 111111 111110 111101 100001 100000 PN23 normal normal (Default) (Default) reset reset
Offset LSBs (Default) Global Output Test Options 000-off 001-midscale short 010-+FS short 011-FS short 100-checker board output 101-PN sequence 110-PN 111-one/zero word toggle Data Format Select Output 00-offset binary Data (default) Invert 01-twos complement invert 10-Gray Code Open Open Open
SPIAccessible Features
section.
0x00
Interfacing High Speed ADCs user manual.
output_mode
Output Driver Configuration DRVDD DRVDD Open Output Clock Polarity inverted normal (Default) Internal Reference Resistor Divider 00-VREF 1.25 01-VREF 10-VREF 1.75 11-VREF 2.00 (Default)
Open
output_phase
Open
Output Disable disabled enabled Open
Open
0x00
Configures outputs format data.
Open
0x00
SPIAccessible Features section. SPIAccessible Features section.
VREF
Open
Open
Open
Open
Open
Open
0xC0
External output enable (OEB) must high.
Rev. Page
AD9254 LAYOUT CONSIDERATIONS
POWER GROUND RECOMMENDATIONS
When connecting power AD9254, recommended that separate supplies used: analog (AVDD, nominal) digital (DRVDD, nominal). only single supply available, routed AVDD first, then tapped isolated with ferrite bead filter choke with decoupling capacitors proceeding connection DRVDD. user employ several different decoupling capacitors cover both high frequencies. These should located close point entry board level close parts with minimal trace length. single board ground plane sufficient when using AD9254. With proper decoupling smart partitioning analog, digital, clock sections board, optimum performance easily achieved.
SILKSCREEN PARTITION INDICATOR
Figure Typical Layout
should decoupled ground with capacitor, shown Figure
RBIAS
AD9254 requires user place resistor between RBIAS ground. This resister sets master current reference core should have least tolerance.
Exposed Paddle Thermal Heat Slug Recommendations
required that exposed paddle underside connected analog ground (AGND) achieve best electrical thermal performance AD9254. exposed, continuous copper plane should mate AD9254 exposed paddle, copper plane should have several vias achieve lowest possible resistive thermal path heat dissipation flow through bottom PCB. These vias should solder-filled plugged. maximize coverage adhesion between PCB, partition continuous plane overlaying silkscreen into several uniform sections. This provides several points between during reflow process. Using continuous plane with partitions guarantees only point between PCB. Figure layout example. detailed information packaging layout chip scale packages, Application Note AN-772, Design Manufacturing Guide Lead Frame Chip Scale Package.
REFERENCE DECOUPLING
VREF should externally decoupled ground with capacitor parallel with ceramic capacitor. reference configurations, REFT REFB bypass points provided reducing noise contributed internal reference buffer. recommended that external ceramic capacitor placed across REFT/REFB. While placement this capacitor required, performance degrades approximately without reference decoupling capacitors should placed close possible with minimal trace lengths.
Rev. Page
06216-055
AD9254 EVALUATION BOARD
AD9254 evaluation board provides support circuitry required operate various modes configurations. converter driven differentially through double balun configuration (default) through AD8352 differential driver. also driven single-ended fashion. Separate power pins provided isolate from AD8352 drive circuitry. Each input configuration selected proper connection various components (see Figure Figure 63). Figure shows typical bench characterization setup used evaluate performance AD9254. critical that signal sources used analog input clock have very phase noise jitter) realize optimum performance converter. Proper filtering analog input signal remove harmonics lower integrated broadband noise input also necessary achieve specified noise performance. Figure Figure complete schematics layout diagrams that demonstrate routing grounding techniques that should applied system level. When operating evaluation board nondefault condition, L501, L503, L504, L508, L509 removed disconnect switching power supply. This enables user individually bias each section board. P501 connect different supply each section. least supply needed with current capability AVDD_DUT DRVDD_DUT; however, recommended that separate supplies used analog digital. operate evaluation board using AD8352 option, separate supply (AMP_VDD) with current capability needed. operate evaluation board using alternate options, separate analog supply needed, addition other supplies. supply (AVDD_3.3V) should have current capability well. Solder Jumpers J501, J502, J505 allow user combine these supplies (see Figure more details).
INPUT SIGNALS
When connecting clock analog source, clean signal generators with phase noise, such Rohde Schwarz SMHU Agilent HP8644 signal generators equivalent. meter long, shielded, RG-58, coaxial cable making connections evaluation board. Enter desired frequency amplitude ADC. Typically, most evaluation boards from Analog Devices, Inc. accept ~2.8 sine wave input clock. When connecting analog input source, recommended multipole, narrowband, band-pass filter with terminations. Analog Devices uses TTE®, Allen Avionics, K&L® types band-pass filters. Connect filter directly evaluation board, possible.
POWER SUPPLIES
This evaluation board comes with wall-mountable switching power supply that provides maximum output. Connect supply rated wall outlet other inner diameter jack that connects P500. Once board, supply fused conditioned before connecting five dropout linear regulators that supply proper bias each various sections board.
OUTPUT SIGNALS
parallel CMOS outputs interface directly with Analog Devices standard single-channel FIFO data capture board (HSC-ADC-EVALB-SC). more information FIFO boards their optional settings, visit www.analog.com/FIFO.
WALL OUTLET 100V 240V 47Hz 63Hz SWITCHING POWER SUPPLY
5.0V
1.8V
2.5V
3.3V
3.3V
3.3V
AMP_VDD
DRVDD_DUT
AVDD_3.3V
AVDD_DUT
ROHDE SCHWARZ, SMHU, SIGNAL SYNTHESIZER ROHDE SCHWARZ, SMHU, SIGNAL SYNTHESIZER
BAND-PASS FILTER
AD9254
EVALUATION BOARD
14-BIT PARALLEL CMOS
Figure Evaluation Board Connection
Rev. Page
06216-056
HSC-ADC-EVALB-SC FIFO DATA CAPTURE BOARD CONNECTION
RUNNING ANALYZER USER SOFTWARE
AD9254
DEFAULT OPERATION JUMPER SELECTION SETTINGS
following list default optional settings modes allowed AD9254 Rev. evaluation board.
SCLK/DFS
port external mode, SCLK/DFS sets data format outputs. left floating, internally pulled down, setting default condition binary. Connecting sets format twos complement. port serial mode, connecting connects SCLK on-board circuitry (see Serial Port Interface (SPI) section).
POWER
Connect switching power supply that supplied evaluation between rated wall outlet P500.
SDIO/DCS
port external mode, SDIO/DCS acts duty cycle stabilizer. left floating, internally pulled setting default condition enabled. disable DCS, connect port serial mode, connecting connects SDIO on-board circuitry (see Serial Port Interface (SPI) section).
evaluation board double balun configuration analog input with optimum impedance matching MHz. more bandwidth response, differential capacitor across analog inputs changed removed (see Table common mode analog inputs developed from center transformer (see Analog Input Considerations section). VREF VREF tying SENSE ground JP507 (Pin This causes operate full-scale range. separate external reference option also included evaluation board. Connect JP507 between connect JP501, provide external reference E500. Proper VREF options detailed Voltage Reference section. RBIAS RBIAS requires resistor (R503) ground used core bias current.
ALTERNATIVE CLOCK CONFIGURATIONS
differential LVPECL clock also used clock input using AD9515 (U500). When using this drive option, components listed Table need populated. Consult AD9515 data sheet further information. configure analog input drive AD9515 instead default transformer option, following components need added, removed, and/or changed. Remove R507, R508, C532, C533 default clock path. Populate R505 with resistor C531 default clock path. Populate R511, R512, R513, R515 R524, U500, R580, R582, R583, R584, C536, C537, R586.
CLOCK
default clock input circuitry derived from simple transformer-coupled circuit using high bandwidth impedance ratio transformer (T503) that adds very amount jitter clock path. clock input terminated ac-coupled handle single-ended sine wave inputs. transformer converts single-ended input differential signal that clipped before entering clock inputs.
using oscillator, oscillator footprint options also available (OSC500) check performance ADC. JP508 provides user flexibility using enable pin, which common most oscillators. Populate OSC500, R575, R587, R588 this option.
PDWN
enable power-down feature, connect JP506, shorting PDWN AVDD.
ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION
This section provides brief description alternative analog input drive configuration using AD8352. When using this particular drive option, some components need populated, listed Table more details AD8352 differential driver, including works optional settings, consult AD8352 data sheet.
internally pulled-up, setting chip into external mode, ignore SDIO SCLK information. connect control circuitry evaluation board, connect chip into serial mode, enable information SDIO SCLK pins, (connect always enabled mode.
Rev. Page
AD9254
configure analog input drive AD8352 instead default transformer option, following components need added, removed, and/or changed: Remove default analog input path. Populate with resistors analog input path. Populate optional amplifier input path with components except R594, R595, C502. Note that terminate input path, only following components should populated: R592, combination R590 R591). Populate C529 with capacitor analog input path.
Currently, R561 R562 populated with resistors allow signal connection. This area allows user design filter additional requirements necessary.
Rev. Page
SCHEMATICS
DOUBLE BALUN XFMR INPUT
.1UF C528 0.1UF
RC040
AMPOUT+
R561
RC0402 RC0402
R566
S500
RC0402 RC0402
VIN+
RC0402
SMAEDGE
R560
T500 T501
CC0402
RC040
ETC1-1-13
.1UF
RC0402
R571
RC0402
R562 C510 .1UF
RC0603
R565 R574
GND;3,4,5
RC0402
R563
CC0402
C529 20PF R567
RC0402
R502
ETC1-1-13
S503
RC0402
SMAEDGE
CC0402
RC0402
RC060
VIN-
T502
RC0402
AMPOUT-
C509 .1UF
VIN+
VIND501
Ain/
RC0603
When using remove R4,R6. Replace with 0.1UF Replace with resistors.
GND;3,4,5
HSMS281
D500
When using T502, remove T500, T501. Repalce with resistors. Remove Place R502,.
R594 AMPVDD J500 R593 C500 .1UF
OPTIONAL INPUT
DUTAVDD
HSMS281
DUTAVDD
RC060
disable
GND;3,4,5
CC0402
Ampin/
RC0603
CC0402
Figure Evaluation Board Schematic, Analog Inputs
AMPVDD enable
Rev. Page
RC0603
S504
SMA200UP
R595
C502 .1UF
Ampin
R591 R592 C501 0.3PF R597 4.3K
U511 R596 AD8352 SIGNAL=GND;17 R598
R535
RC0402
AMPOUT+
C504 .1UF
R590
RC060
R536
RC0402
AMPOUTC505 .1UF
S505
SMA200UP
GND;3,4,5
C503 .1UF
AMPVDD
RC060
06216-057
amplifier (AD8352): Install optional input components. R590/R591,R9,R592 Only should installed time. Remove R3=R4=200 OHM.
AD9254
AD9254
CSB_DUT SCLK_DTP SDIO_ODM DUTAVDD DUTAVDD
SENSE
VREF
TP503 TP501 DUTDRVDD
CC0402
C554 0.1UF
VIN+
VIN-
C556 0.1UF
R503
chip corners
RP502 RP502 RP502 RP502 RP502 RP502 RP501 RP501 RP501 RP501 RP501 RP501 RP500 RP500 RP500 RP502 RP502
SENSE VREF REFB REFT AGND VIN+ VINAGND AVDD RBIAS PDWN
AVDD AGND AVDD AGND SCLK/DFS SDIO/DCS DRVDD DRGND (MSB)
CC0603
JP506
DUTAVDD
RC060
GND7 VCC4 GND8 GND6 VCC3 VCC2 GND3 GND2 VCC1 GND1 GND5
FIFOCLK FD10 FD12 FD11
74VCX16224 GND4
TP502 RP501 RP501
FIFOCLK FDOR FD13 FD13 FD12 FD11 FD10 FDOR
SDI_CHA
JP502
U509
TP504
CSB1_CHA
TP500
SDO_CHA
DUTDRVDD
AGND CLK+ EPAD CLKD8 AVDD AGND DRVDD AVDD DRGND (LSB) U510 DRGND DRVDD AD9246LFCSP
Figure Evaluation Board Schematic, DUT, VREF, Digital Output Interface
JP500 R500
R0402
Rev. Page
JP507
SCLK_CHA
E500
DUTAVDD
JP501
J503
J503
J503
VREF RP500 R501
CC0805
R0402
OUTPUT CONNECTOR
CC0402
C555 0.1UF
C553 1.0UF
OUTPUT BUFFER
06216-058
AVDD_3P3V R587
DISABLE RC0402
ENABLE RC0402
JP508
XFMR/AD9515 Clock Circuitry
OSC500
AD9515 LOGIC SETUP
R588 AVDD_3P3V R514
RC0603
R575
RC0402 CB3LV-3C
R513
RC0603
R525 R506
CC0402
RC0603
R515
RC0603
C530 0.1UF R508 C533 0.1UF
RC0603
SMAEDGE S501
OPT_CLK
T503
RC0603
CC0402
GND;3,4,5
D502 HSMS2812 R509
CC0402
RC0603
C532 0.1UF
R527
R517
RC0603
RC0603
SMAEDGE S502
C531 0.1UF R507
OPT_CLK
RC0603
CLK/
R512
RC060
CC0402
R526
R516
RC0603
R531 R521
RC0603
RC0603
GND;3,4,5 C511 .1UF
R505 49.9
R504 49.9
R530 R520
RC0603
RC0603
RC0402
RC0402
RC0402
CC0402
RC0402
CC0402
RC0402
R511
SYNCB
RC0603
NC=27,28
OUT1 OUT1B RC0402 RC0402 VREF
RC0402
RC0402
R585
C534 0.1UF
CC0402
C535 0.1UF
06216-059
CC0402
Figure Evaluation Board Schematic, Clock Input
Rev. Page
AVDD_3P3V R576 R581 R580 R586 4.12K
RC0402
R510
RC0603
RC0402
RC060
RC060
AD9515 (OPT _CLK), remove R507, R508, C533, C532. Place C531,R505=0.
R528 R518
RC0603
RC0603
RC0603
C536 0.1UF
R529
R519
RC0603
RC0603
R534 R582 C537 0.1UF R524
RC0603
OPT_CLK
U500
OUT0 OUT0B RSET CLKB GND_PAD
RC0603
R577 AD9515
R533
R523
RC0603
RC0603
OPT_CLK
R579 R578 E501
R584
R583
R532 R522
RC0603
E502
RC0603
E503
AD9254
AD9254
SDO_CHA
CSB1_CHA
SDI_CH
SCLK_CHA
REMOVE WHEN USING PROGRAMMING (U506)
RC0603 RC0603 RC0603 RC0603
CIRCUITRY
R555 R554 R557 R556
+5V=PROGRAMMING ONLY=AMPVDD +3.3V=NORMAL OPERATION=AVDD_3P3V
JP509
U506
SOIC8
RC0603
R546 4.7K
RC0603
R545 4.7K R547 4.7K
RC0603
MCLR PIC12F629
RC0603
R558 4.7K
DUTAVDD AVDD_3P3V
RC0603 RC0603
RC060
C557 CC0603 0.1UF
R559 D505 Optional
R551
R553
U508
E504
RC0603
MCLR-GP3 PICVCC
R550
PICVCC
R549
RC0603
RC0603
Figure Evaluation Board Schematic, Circuitry
PIC-HEADER
Rev. Page
HEADER MALE
J504
AVDD_3P3V
NC7WZ07
R552
RC0603
When using PICSPI controlled port, populate R545, R546, R547. When using PICSPI controlled port, remove R555, R556, R557. FIFO controlled port, populate R555, R556, R557.
MCLR-GP3
SDIO_ODM
U507
SCLK_DTP
R548
CSB_DUT
NC7WZ16
06216-060
TP506 U502 ADP3339AKC-1.8 L504 10UH
LC1210 DUTAVDDIN
Power Supply Input
FER500 CHOKE_COIL
F500 PWR_IN PWR_IN OUTPUT4
D503 SHOT_RECT DO-214AB
DUTAVDD=1.8V DUTDRVDD=2.5V VDL=3.3V AMPVDD=5V AVDD_3.3V=3.3V
TP507 U501 ADP3339AKC-5 PWR_IN
P500
SMDC110F
C527 10UF
CR500
C519
C518
L501 10UH OUTPUT4
LC1210 AMPVDDIN
D504 S2A_RECT DO-214AA
U503 ADP3339AKC-2.5 L503 10UH
LC1210 DUTDRVDDIN
PWR_IN
OUTPUT4
R589 TP505
7.5V POWER CON005 2.5MM JACK
C523
C522
TP513 C520
PWR_IN
C521
U505 ADP3339AKC-3.3 OUTPUT4
L509 10UH
LC1210 AVDD_3P3V
OPTIONAL POWER CONNECTION
TP508 U504 ADP3339AKC-3.3 L508 10UH
LC1210 VDLIN PWR_IN
L505 10UH OUTPUT4
P501 AMPVDD
AMPVDDIN
LC1210
C549 1OUF 6.3V C514 0.1UF
ACASE
J505
DUTDRVDDIN
L507 10UH
LC1210
ACASE
VDLIN C550 1OUF 6.3V C515 0.1UF AMPVDD AVDD_3P3V
AVDD_3P3VIN
TP510
TP512
LC1210 CC0603
AVDD_3P3V C569 0.1UF
CC0603
TP511
TP509
Figure Evaluation Board Schematic, Power Supply Inputs
C513 DUTAVDD
CC0603 CC0603
Rev. Page
C567 0.1UF C568 0.1UF
CC0402 ACASE
DUTAVDDIN
L502 10UH
LC1210
C524 C526
C545 0.1UF
CC0402
C544 0.1UF
CC0402
C525
C546 0.1UF
CC0402
C543 0.1UF
J502 0.1UF DUTDRVDD
CC0603 CC0603 CC0603 CC0603
C551 1OUF 6.3V C516 0.1UF
AVDD_3P3V
L506 10UH 0.1UF C559 C564 0.1UF C558 C565 0.1UF
LC1210
CC0402
C540 0.1UF
CC0402
C539 0.1UF
CC0402
C542 0.1UF
CC0402
C538 0.1UF
GROUND TEST POINTS
J501
ACASE
C552 1OUF 6.3V C517 0.1UF DUTAVDD
L500 10UH C575 0.1UF
H501
H502
CC0603
C566 0.1UF
CC0603
C570 0.1UF
CC0603
C574 0.1UF
H500
H503
ACASE
C548 1OUF 6.3V C512 0.1UF
Mounting Holes Connected Ground
DUTDRVDD
CC0603
C573 0.1UF
CC0603
C572 0.1UF
CC0603
C599 0.1UF
optional power connection
Remove L501,L503,L504,L508,L509.
06216-061
AD9254
AD9254
EVALUATION BOARD LAYOUT
Figure Evaluation Board Layout, Primary Side
Figure Evaluation Board Layout, Secondary Side (Mirrored Image)
Rev. Page
06216-063
06216-062
AD9254
Figure Evaluation Board Layout, Ground Plane
Figure Evaluation Board Layout, Power Plane
Rev. Page
06216-065
06216-064
AD9254
Figure Evaluation Board Layout, Silkscreen Primary Side
Figure Evaluation Board Layout, Silkscreen Secondary Side (Mirrored Image)
Rev. Page
06216-067
06216-066
AD9254
BILL MATERIALS
Table Evaluation Board Bill Materials (BOM)
Item Qty. Omit (DNP) Reference Designator AD9246CE_REVA C509, C510, C511, C512, C514, C515, C516, C517, C528, C530, C532, C533, C538, C539, C540, C542, C543, C544, C545, C546, C554, C555 C500, C502, C503, C504, C505, C531, C534, C535, C536, C537, C557 C501 C513, C518, C519, C520, C521, C522, C523, C524, C525, C526 C527 C529 C548, C549, C550, C551, C552 C553 C556, C558, C559, C564, C565, C566, C567, C568, C569, C570, C572, C573, C574, C575, C599 CR500 D502 D500, D501 D503 Device Capacitor Package 0402 Description Supplier/Part Number
Capacitor Resistor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor
0402 0402 0402 1206 0402 ACASE 0805 0603
Diode Diode
0603 SOT-23 DO-214AB
green dual Schottky
Panasonic LNJ314G8TRA HSMS2812 Micro Commercial Components SK33TPMSCT-ND Micro Commercial Components S2ATPMSTR-ND Amber Tyco, Raychem NANOSMDC110F-2 Murata DLW5BSN191SQ2
D504
Diode
DO-214AA
D505 F500
Fuse
LN1461C 1210
trip current resettable fuse
FER500 J500 J501, J502, J505 J503 J504 JP1, JP2, JP500, JP501, JP502, JP506 JP507 JP508, JP509 L500, L501, L502, L503, L504, L505, L506, L507, L508, L509 OSC500 P500
Choke Jumper Jumper Connector Connector Jumper Jumper Jumper Ferrite Bead
2020 Solder jumper Solder jumper Male header Male, Male, straight Male, straight Male, straight
3-pin jumper PJ-102A
Samtec TSW-140-08-G-T-RA
Samtec Samtec TSW-103-07-G-S Samtec TSW-102-07-G-S Samtec TSW-103-07-G-S Digikey P9811CT-ND
Oscillator Connector
Rev. Page
power jack
Reeves CB3LV-3C Digikey CP-102A-ND
AD9254
Item Qty. Omit (DNP) Reference Designator P501 R563, R565, R574, R577 R561, R562, R571 R10, R11, R12, R535, R536, R575 R502, R510, R511 R500, R501, R576, R578, R579, R581 R503, R548, R549, R550 R504 R505 R506, R508, R509, R512, R554, R555, R556, R557, R560 R507, R513, R514, R515, R516, R517, R518, R519, R520, R521, R522, R523, R524, R525, R526, R527, R528, R529, R530, R531, R532, R533, R534, R545, R546, R547, R558 R551, R552, R553 R559 R566, R567 R582, R585, R598 R583, R584 R586 R580, R587, R588 R589 R590, R591 R592 R593, R596 R594, R595 R597 RP500 RP501, RP502 Device Connector Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Package 0402 0402 0402 0603 0402 0603 0603 0603 Description Male, straight 49.9 Supplier/Part Number PTMICRO10
Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Resistor Switch
0603 0603 0603 0402 0402 0402 0402 0402 0603 0402 0402 0402 0402 0402 RCA74204 RCA74208
S500, S501 S502, S503 S504, S505 T500, T501 T503 T502 U500 U501
Connector Connector Transformer Transformer
SMAEDGE SMA200UP SM-22 CD542 32-pin LFCSP SOT-223
4.12 Momentary (normally open) edge right angle 5-pin upright
Panasonic EVQ-PLDA15
M/A-Com ETC1-1-13 Mini-Circuits ADT1-1WT Clock distribution Voltage regulator AD9515BCPZ ADP3339AKCZ-5
Rev. Page
AD9254
Item Total Qty. Omit (DNP) Reference Designator U502 U503 U504, U505 U506 U507 U508 U509 U510 U511 Z500) Device (AD9254) Package SOT-223 SOT-223 SOT-223 8-pin SOIC SC70 SC70 48-pin TSSOP 48-pin LFCSP_VQ 16-pin LFCSP_VQ Description Voltage regulator Voltage regulator Voltage regulator 8-bit microcontroller Dual buffer Dual buffer Buffer/line driver Differential amplifier Supplier/Part Number ADP3339AKCZ-1.8 ADP3339AKCZ-2.5 ADP3339AKCZ-3.3 Microchip PIC12F629 Fairchild NC7WZ16 Fairchild NC7WZ07 Fairchild 74VCX162244 AD9254BCPZ AD8352ACPZ
Rev. Page
AD9254 OUTLINE DIMENSIONS
7.00 0.60 0.60
0.30 0.23 0.18
INDICATOR
INDICATOR
VIEW
6.75
EXPOSED
(BOTTOM VIEW)
4.25 4.10 3.95
0.50 0.40 0.30
0.25 5.50
1.00 0.85 0.80
0.80 0.65 0.05 0.02 0.50
SEATING PLANE
0.20
COPLANARITY 0.08
COMPLIANT JEDEC STANDARDS MO-220-VKKD-2
Figure 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Body, Very Thin Quad (CP-48-3) Dimensions shown millimeters
ORDERING GUIDE
Model AD9254BCPZ-150 AD9254BCPZRL7-1501, AD9254-150EBZ1
Temperature Range -40°C +85°C -40°C +85°C
Package Description 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) 48-Lead Lead Frame Chip Scale Package (LFCSP_VQ) Evaluation Board
Package Option CP-48-3 CP-48-3
Pb-free part. required that exposed paddle soldered AGND plane achieve best electrical thermal performance.
©2006 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D06216-0-10/06(0)
Rev. Page

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