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Quad, 12-bit, 40/65 MSPS Serial LVDS Converter AD9228
Four ADCs integrated into package power channel MSPS Nyquist) Excellent linearity ±0.3 (typical) ±0.4 (typical) Serial LVDS (ANSI-644, default) power reduced signal option, IEEE 1596.3 similar Data frame clock outputs full power analog bandwidth input voltage range supply operation Serial port control Full-chip individual-channel power-down modes Flexible orientation Built-in custom digital test pattern generation Programmable clock data alignment Programmable output resolution Standby mode
AVDD PDWN DRVDD DRGND
AD9228
VIN+A VIN-A VIN+B VIN-B VIN+C VIN-C VIN+D VIN-D VREF SENSE REFT REFB SELECT PIPELINE
SERIAL LVDS PIPELINE PIPELINE PIPELINE SERIAL LVDS SERIAL LVDS SERIAL LVDS
FCO+ 0.5V SERIAL PORT INTERFACE DATA RATE MULTIPLIER FCO- DCO+ DCO-
Figure
APPLICATIONS
Medical imaging nondestructive ultrasound Portable ultrasound digital beam forming systems Quadrature radio receivers Diversity radio receivers Tape drives Optical networking Test equipment
capturing data output frame clock (FCO) signaling output byte provided. Individual channel power-down supported typically consumes less than when channels disabled. contains several features designed maximize flexibility minimize system cost, such programmable clock data alignment programmable digital test pattern generation. available digital test patterns include built-in deterministic pseudorandom patterns, along with custom userdefined test patterns entered serial port interface (SPI®). AD9228 available Pb-free, 48-lead LFCSP package. specified over industrial temperature range -40°C +85°C.
GENERAL DESCRIPTION
AD9228 quad, 12-bit, 40/65 MSPS analog-to-digital converter (ADC) with on-chip sample-and-hold circuit that designed cost, power, small size, ease use. product operates conversion rate MSPS optimized outstanding dynamic performance power applications where small package size critical. requires single power supply LVPECL-/ CMOS-/LVDS-compatible sample rate clock full performance operation. external reference driver components required many applications. automatically multiplies sample rate clock appropriate LVDS serial data rate. data clock (DCO)
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
PRODUCT HIGHLIGHTS
Small Footprint. Four ADCs contained small, spacesaving package; power mW/channel MSPS. Ease Use. data clock output (DCO) provided that operates supports double data rate operation (DDR). User Flexibility. Serial port interface (SPI) control offers wide range flexible features meet specific system requirements. Pin-Compatible Family. This includes AD9287 (8-bit), AD9219 (10-bit), AD9259 (14-bit).
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.461.3113 ©2006 Analog Devices, Inc. rights reserved.
05727-001
RBIAS AGND SDIO/ODM SCLK/DTP CLK+ CLK-
AD9228 TABLE CONTENTS
Features Applications. General Description Functional Block Diagram Product Highlights Revision History Specifications. Specifications. Digital Specifications Switching Specifications Timing Diagrams. Absolute Maximum Ratings. Thermal Impedance Caution. Configuration Function Descriptions. Equivalent Circuits Typical Performance Characteristics Theory Operation Analog Input Considerations Clock Input Considerations. Serial Port Interface (SPI). Hardware Interface. Memory Reading Memory Table. Reserved Locations Default Values Logic Levels. Evaluation Board Power Supplies Input Signals. Output Signals Default Operation Jumper Selection Settings. Alternative Analog Input Drive Configuration. Outline Dimensions Ordering Guide
REVISION HISTORY
4/06-Revision Initial Version
Rev. Page
AD9228 SPECIFICATIONS
AVDD DRVDD differential input, internal reference, -0.5 dBFS, unless otherwise noted. Table
Parameter RESOLUTION ACCURACY Missing Codes Offset Error Offset Matching Gain Error Gain Matching Differential Nonlinearity (DNL) Integral Nonlinearity (INL) TEMPERATURE DRIFT Offset Error Gain Error Reference Voltage Mode) REFERENCE Output Voltage Error (VREF Load Regulation (VREF Input Resistance ANALOG INPUTS Differential Input Voltage Range (VREF Common-Mode Voltage Differential Input Capacitance Analog Bandwidth, Full Power POWER SUPPLY AVDD DRVDD IAVDD IDRVDD Total Power Dissipation (Including Output Drivers) Power-Down Dissipation Standby Dissipation CROSSTALK CROSSTALK (Overrange Condition)
Temperature
AD9228-40
AD9228-65
Unit Bits
Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full
Guaranteed ±0.4 ±0.3 ±0.25 ±0.4 AVDD/2 -100 -100
±1.2 ±0.7 ±0.5
Guaranteed ±0.3 ±0.3 ±0.4
±3.5 ±0.7 ±0.65
ppm/°C ppm/°C ppm/°C
AVDD/2
-100 -100
AN-835 Application Note, "Understanding High Speed Testing Evaluation," complete definitions these tests were completed. controlled SPI. Overrange condition specific with full-scale input range.
Rev. Page
AD9228
SPECIFICATIONS
AVDD DRVDD differential input, internal reference, -0.5 dBFS, unless otherwise noted. Table
Parameter SIGNAL-TO-NOISE RATIO (SNR) Temperature Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full Full 25°C 25°C AD9228-40 70.5 68.5 70.2 70.2 70.0 70.3 68.0 69.8 69.7 69.5 11.4 11.1 11.37 11.37 11.33 80.8 75.0 AD9228-65 70.2 70.0 68.5 70.0 69.5 70.0 70.0 68.0 69.8 69.0 11.37 11.33 11.1 11.33 11.25 77.8 77.0 Unit Bits Bits Bits Bits
SIGNAL-TO-NOISE DISTORTION RATIO (SINAD)
EFFECTIVE NUMBER BITS (ENOB)
SPURIOUS-FREE DYNAMIC RANGE (SFDR)
WORST HARMONIC (Second Third)
WORST OTHER (Excluding Second Third)
TWO-TONE INTERMODULATION DISTORTION (IMD)- AIN1 AIN2 -7.0 dBFS
19.7 19.7 19.7 19.7 19.7 19.7 fIN1 MHz, fIN2 fIN1 MHz, fIN2
AN-835 Application Note, "Understanding High Speed Testing Evaluation," complete definitions these tests were completed.
Rev. Page
AD9228
DIGITAL SPECIFICATIONS
AVDD DRVDD differential input, internal reference, -0.5 dBFS, unless otherwise noted. Table
Parameter CLOCK INPUTS (CLK+, CLK-) Logic Compliance Differential Input Voltage Input Common-Mode Voltage Input Resistance (Differential) Input Capacitance LOGIC INPUTS (PDWN, SCLK/DTP) Logic Voltage Logic Voltage Input Resistance Input Capacitance LOGIC INPUT (CSB) Logic Voltage Logic Voltage Input Resistance Input Capacitance LOGIC INPUT (SDIO/ODM) Logic Voltage Logic Voltage Input Resistance Input Capacitance LOGIC OUTPUT (SDIO/ODM) Logic Voltage (IOH Logic Voltage (IOL DIGITAL OUTPUTS (D+, D-), (ANSI-644)1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default) DIGITAL OUTPUTS (D+, D-), (Low Power, Reduced Signal Option)1 Logic Compliance Differential Output Voltage (VOD) Output Offset Voltage (VOS) Output Coding (Default)
Temperature
AD9228-40 CMOS/LVDS/LVPECL
AD9228-65 CMOS/LVDS/LVPECL
Unit
Full Full 25°C 25°C Full Full 25°C 25°C Full Full 25°C 25°C Full Full 25°C 25°C Full Full
1.79 0.05 LVDS DRVDD
1.79 0.05 LVDS 1.125 1.375 Offset binary DRVDD
Full Full
1.125
1.375 Offset binary
LVDS Full Full 1.10 1.30 Offset binary 1.10
LVDS 1.30 Offset binary
AN-835 Application Note, "Understanding High Speed Testing Evaluation," complete definitions these tests were completed. This specified LVDS LVPECL only.
Rev. Page
AD9228
SWITCHING SPECIFICATIONS
AVDD DRVDD differential input, internal reference, -0.5 dBFS, unless otherwise noted. Table
AD9228-40 Parameter CLOCK Maximum Clock Rate Minimum Clock Rate Clock Pulse Width High (tEH) Clock Pulse Width (tEL) OUTPUT PARAMETERS2 Propagation Delay (tPD) Rise Time (tR) (20% 80%) Fall Time (tF) (20% 80%) Propagation Delay (tFCO) Propagation Delay (tCPD) Data Delay (tDATA)3 Delay (tFRAME) Data Data Skew (tDATA-MAX tDATA-MIN) Wake-Up Time (Standby) Wake-Up Time (Power Down) Pipeline Latency APERTURE Aperture Delay (tA) Aperture Uncertainty (Jitter) Out-of-Range Recovery Time
AD9228-65 tFCO (tSAMPLE/24) (tSAMPLE/24) (tSAMPLE/24) Unit MSPS MSPS cycles cycles
Temp Full Full Full Full Full Full Full Full Full Full Full Full 25°C 25°C Full
12.5 12.5 tFCO (tSAMPLE/24) (tSAMPLE/24) (tSAMPLE/24)
(tSAMPLE/24) (tSAMPLE/24)
(tSAMPLE/24) (tSAMPLE/24) ±150
(tSAMPLE/24) (tSAMPLE/24)
(tSAMPLE/24) (tSAMPLE/24) ±150
25°C 25°C 25°C
AN-835 Application Note, "Understanding High Speed Testing Evaluation," complete definitions these tests were completed. adjusted interface. tSAMPLE/24 based number bits divided because delays based half duty cycles.
Rev. Page
AD9228 TIMING DIAGRAMS
CLK-
CLK+
tCPD
DCO-
DCO+
tFCO
FCO-
tFRAME
FCO+
tDATA
05727-039
05727-040
Figure 12-Bit Data Serial Stream (Default)
CLK-
CLK+
tCPD
DCO-
DCO+
tFCO
FCO-
tFRAME
FCO+
N-10 N-10 N-10 N-10 N-10
tDATA
N-10 N-10 N-10 N-10 N-10
Figure 10-Bit Data Serial Stream
Rev. Page
AD9228
CLK-
CLK+
tCPD
DCO-
DCO+
tFCO
FCO-
tFRAME
FCO+
tDATA
05727-041
Figure 12-Bit Data Serial Stream, First
Rev. Page
AD9228 ABSOLUTE MAXIMUM RATINGS
Table
Parameter ELECTRICAL AVDD DRVDD AGND AVDD Digital Outputs (D+, DCO+, DCO-, FCO+, FCO-) CLK+, CLK- VIN+, VIN- SDIO/ODM PDWN, SCLK/DTP, REFT, REFB, RBIAS VREF, SENSE ENVIRONMENTAL Operating Temperature Range (Ambient) Maximum Junction Temperature Lead Temperature (Soldering, sec) Storage Temperature Range (Ambient) With Respect AGND DRGND DRGND DRVDD DRGND Rating -0.3 +2.0 -0.3 +2.0 -0.3 +0.3 -2.0 +2.0 -0.3 +2.0
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
THERMAL IMPEDANCE
Table
Flow Velocity (m/s)
AGND AGND AGND AGND AGND AGND
-0.3 +3.9 -0.3 +2.0 -0.3 +2.0 -0.3 +3.9 -0.3 +2.0 -0.3 +2.0 -40°C +85°C 150°C 300°C -65°C +150°C
24°C/W 21°C/W 19°C/W
12.6°C/W
1.2°C/W
4-layer with solid ground plane (simulated). Exposed soldered PCB.
CAUTION
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this product features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Rev. Page
AD9228 CONFIGURATION FUNCTION DESCRIPTIONS
AVDD AVDD AVDD AVDD CLK- CLK+ AVDD AVDD DRGND DRVDD
INDICATOR
SENSE
RBIAS
AVDD
AVDD
AVDD
REFB
VREF
REFT
AVDD AVDD AVDD PDWN SDIO/ODM SCLK/DTP AVDD DRGND DRVDD
EXPOSED PADDLE, (BOTTOM PACKAGE)
AD9228
VIEW
FCO+
DCO+
FCO-
Figure 48-Lead LFCSP View
Table Function Descriptions
Name AGND AVDD DRGND DRVDD CLK- CLK+ FCO- FCO+ DCO- DCO+ SCLK/DTP SDIO/ODM PDWN Description Analog Ground (Exposed Paddle) Analog Supply Digital Output Driver Ground Digital Output Driver Supply Analog Input-Complement Analog Input-True Input Clock-Complement Input Clock-True Complement Digital Output True Digital Output Complement Digital Output True Digital Output Complement Digital Output True Digital Output Complement Digital Output True Digital Output Frame Clock Output-Complement Frame Clock Output-True Data Clock Output-Complement Data Clock Output-True Serial Clock/Digital Test Pattern Serial Data Input-Output/Output Driver Mode Power-Down Analog Input-True Analog Input-Complement
Rev. Page
DCO-
05727-003
AD9228
Name RBIAS SENSE VREF REFB REFT Description Analog Input-Complement Analog Input-True External Resistor Sets Internal Core Bias Current Reference Mode Selection Voltage Reference Input/Output Differential Reference (Negative) Differential Reference (Positive) Analog Input-True Analog Input-Complement
Rev. Page
AD9228 EQUIVALENT CIRCUITS
DRVDD
05727-030
DRGND
Figure Equivalent Analog Input Circuit
Figure Equivalent Digital Output Circuit
1.25V
SCLK/PDWN
05727-032
05727-005
Figure Equivalent Clock Input Circuit
Figure Equivalent SCLK/PDWN Input Circuit
RBIAS
SDIO/ODM
05727-035
Figure Equivalent SDIO/ODM Input Circuit
Figure Equivalent RBIAS Circuit
Rev. Page
05727-031
05727-033
AD9228
AVDD
05727-034
Figure Equivalent Input Circuit
Figure Equivalent VREF Circuit
SENSE
Figure Equivalent SENSE Circuit
05727-036
Rev. Page
05727-037
VREF
AD9228 TYPICAL PERFORMANCE CHARACTERISTICS
-0.5dBFS 70.51dB ENOB 11.38 BITS SFDR 86.00dBc
-0.5dBFS 69.62dB ENOB 10.96 BITS SFDR 72.48dBc
AMPLITUDE (dBFS)
AMPLITUDE (dBFS)
-100
05727-052
-100
05727-054
-120
-120
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Single-Tone with MHz, fSAMPLE MSPS
Figure Single-Tone with MHz, fSAMPLE MSPS
-0.5dBFS 70.38dB ENOB 11.40 BITS SFDR 81.13dBc
AMPLITUDE (dBFS)
-0.5dBFS 68.74dB ENOB 10.88 BITS SFDR 72.99dBc
AMPLITUDE (dBFS)
-100
05727-085
-100
05727-055
-120
-120
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Single-Tone with MHz, fSAMPLE MSPS
Figure Single-Tone with MHz, fSAMPLE MSPS
-0.5dBFS 70.53dB ENOB 11.38 BITS SFDR 86.04dBc
AMPLITUDE (dBFS)
-0.5dBFS 67.68dB ENOB 10.95 BITS SFDR 62.23dBc
AMPLITUDE (dBFS)
-100
05727-053
-100
05727-056
-120
-120
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure Single-Tone with MHz, fSAMPLE MSPS
Rev. Page
Figure Single-Tone with MHz, fSAMPLE MSPS
AD9228
-0.5dBFS 67.58dB ENOB 10.93 BITS SFDR 68.39dBc
p-p, SFDR
AMPLITUDE (dBFS)
SNR/SFDR (dB)
-100
05727-057
p-p, ENCODE (MSPS)
-120
FREQUENCY (MHz)
Figure Single-Tone with MHz, fSAMPLE MSPS
Figure SNR/SFDR fSAMPLE, MHz, fSAMPLE MSPS
-0.5dBFS 65.56dB ENOB 10.6 BITS SFDR 62.72dBc
p-p, SFDR
AMPLITUDE (dBFS)
SNR/SFDR (dB)
-100
05727-058
p-p,
05727-062
-120
FREQUENCY (MHz)
ENCODE (MSPS)
Figure Single-Tone with MHz, fSAMPLE MSPS
Figure SNR/SFDR fSAMPLE, 10.3 MHz, fSAMPLE MSPS
p-p, SFDR
p-p, SFDR
SNR/SFDR (dB)
SNR/SFDR (dB)
p-p,
05727-059
p-p,
ENCODE (MSPS)
ENCODE (MSPS)
Figure SNR/SFDR fSAMPLE, 10.3 MHz, fSAMPLE MSPS
Figure SNR/SFDR fSAMPLE, MHz, fSAMPLE MSPS
Rev. Page
05727-064
05727-061
AD9228
p-p, SFDR
SNR/SFDR (dB)
10.3MHz SAMPLE 40MSPS
05727-065
35MHz FSAMPLE 65MSPS
p-p, SFDR
SNR/SFDR (dB)
80dB REFERENCE
p-p, 80dB REFERENCE
p-p,
ANALOG INPUT LEVEL (dBFS)
ANALOG INPUT LEVEL (dBFS)
Figure SNR/SFDR Analog Input Level, 10.3 MHz, fSAMPLE MSPS
Figure SNR/SFDR Analog Input Level, MHz, fSAMPLE MSPS
35MHz SAMPLE 40MSPS p-p, SFDR
AIN1 AIN2 -7dBFS SFDR 80.75dBc IMD2 85.53dBc IMD3 80.83dBc
AMPLITUDE (dBFS)
SNR/SFDR (dB)
05727-066
80dB REFERENCE
p-p,
-100
05727-049
-120
ANALOG INPUT LEVEL (dBFS)
FREQUENCY (MHz)
Figure SNR/SFDR Analog Input Level, MHz, fSAMPLE MSPS
Figure Two-Tone with fIN1 fIN2 MHz, fSAMPLE MSPS
AMPLITUDE (dBFS)
10.3MHz SAMPLE 65MSPS p-p, SFDR
AIN1 AIN2 -7dBFS SFDR 74.76dBc IMD2 81.03dBc IMD3 75.00dBc
SNR/SFDR (dB)
05727-068
80dB REFERENCE
p-p,
-100
05727-050
-120
ANALOG INPUT LEVEL (dBFS)
FREQUENCY (MHz)
Figure SNR/SFDR Analog Input Level, 10.3 MHz, fSAMPLE MSPS
Figure Two-Tone with fIN1 fIN2 MHz, fSAMPLE MSPS
Rev. Page
05727-070
AD9228
AIN1 AIN2 -7dBFS SFDR 78.15dBc IMD2 77.84dBc IMD3 88.94dBc
p-p, SFDR
AMPLITUDE (dBFS)
SNR/SFDR (dB)
p-p, SINAD
-100
05727-048
05727-072
-120
FREQUENCY (MHz)
TEMPERATURE (°C)
Figure Two-Tone with fIN1 fIN2 MHz, fSAMPLE MSPS
Figure SINAD/SFDR Temperature, 10.3 MHz, fSAMPLE MSPS
AIN1 AIN2 -7dBFS SFDR 76.75dBc IMD2 77.56dBc IMD3 77.01dBc
(LSB)
05727-051
AMPLITUDE (dBFS)
-0.1 -0.2 -0.3 -0.4 -0.5 1000 1500 2000 CODE 2500 3000 3500 4000
05727-073
-100
-120
FREQUENCY (MHz)
Figure Two-Tone with fIN1 fIN2 MHz, fSAMPLE MSPS
Figure INL, MHz, fSAMPLE MSPS
2Vp-p, SFDR
SNR/SFDR (dB)
2Vp-p,
(LSB)
05727-071
-0.1 -0.2 -0.3 -0.4 -0.5 1000 1500 2000 CODE 2500 3000 3500 4000
05727-074
1000
ANALOG INPUT LEVEL (dBFS)
Figure SNR/SFDR fIN, fSAMPLE MSPS
Figure DNL, MHz, fSAMPLE MSPS
Rev. Page
AD9228
AMPLITUDE (dBFS)
60.83dB NOTCH 18.0MHz NOTCH WIDTH 3.0MHz
CMRR (dB)
05727-075
-120
FREQUENCY (MHz)
FREQUENCY (MHz)
Figure CMRR Frequency, fSAMPLE MSPS
Figure Noise Power Ratio (NPR), fSAMPLE MSPS
0.26
NUMBER HITS (Millions) FUNDAMENTAL LEVEL (dB)
05727-086
-3dB CUTOFF 315MHz
CODE
FREQUENCY (MHz)
Figure Input Referred Noise Histogram, fSAMPLE MSPS
Figure Full Power Bandwidth Frequency, fSAMPLE MSPS
Rev. Page
05727-077
05727-076
-100
AD9228 THEORY OPERATION
AD9228 architecture consists pipelined that divided into three sections: 4-bit first stage followed eight 1.5-bit stages final 3-bit flash. Each stage provides sufficient overlap correct flash errors preceding stages. quantized outputs from each stage combined into final 12-bit result digital correction logic. pipelined architecture permits first stage operate input sample while remaining stages operate preceding samples. Sampling occurs rising edge clock. Each stage pipeline, excluding last, consists resolution flash connected switched-capacitor interstage residue amplifier (MDAC). residue amplifier magnifies difference between reconstructed output flash input next stage pipeline. redundancy used each stage facilitate digital correction flash errors. last stage simply consists flash ADC. output staging block aligns data, carries error correction, passes data output buffers. data then serialized aligned frame output clock. realizing maximum bandwidth ADC. Such low-Q inductors ferrite beads required when driving converter front high frequencies. Either shunt capacitor single-ended capacitors placed inputs provide matching passive network. This ultimately creates low-pass filter input limit unwanted broadband noise. AN-742 Application Note, AN-827 Application Note, Analog Dialogue article "Transformer-Coupled Front-End Wideband Converters" more information this subject. general, precise values depend application. analog inputs AD9228 internally dc-biased. ac-coupled applications, user must provide this bias externally. Setting device that AVDD/2 recommended optimum performance, device function over wider range with reasonable performance, shown Figure Figure
SFDR (dBc)
ANALOG INPUT CONSIDERATIONS
SNR/SFDR (dB)
analog input AD9228 differential switched-capacitor circuit designed processing differential input signals. input support wide common-mode range maintain excellent performance. input common-mode voltage midsupply minimizes signal-dependent errors provides optimum performance.
(dB)
05727-078
ANALOG INPUT COMMON MODE VOLTAGE
CPAR
VIN+
Figure SNR/SFDR Common-Mode Voltage, MHz, fSAMPLE MSPS
SFDR (dBc)
CSAMPLE
CSAMPLE
VIN-
CPAR
SNR/SFDR (dB)
(dB)
05727-079
Figure Switched-Capacitor Input Circuit
clock signal alternately switches input circuit between sample mode hold mode (see Figure 43). When input circuit switched into sample mode, signal source must capable charging sample capacitors settling within one-half clock cycle. small resistor series with each input help reduce peak transient current injected from output stage driving source. addition, low-Q inductors ferrite beads placed each input reduce high differential capacitance seen analog inputs, thus
Rev. Page
05727-006
ANALOG INPUT COMMON MODE VOLTAGE
Figure SNR/SFDR Common-Mode Voltage, MHz, fSAMPLE MSPS
AD9228
best dynamic performance, source impedances driving VIN+ VIN- should matched such that common-mode settling errors symmetrical. These errors reduced common-mode rejection ADC. internal reference buffer creates positive negative reference voltages, REFT REFB, respectively, that define span core. output common-mode reference buffer midsupply, REFT REFB voltages span defined REFT (AVDD VREF) REFB (AVDD VREF) Span (REFT REFB) VREF seen from these equations that REFT REFB voltages symmetrical about midsupply voltage and, definition, input span twice value VREF voltage. Maximum performance always achieved setting largest span differential configuration. case AD9228, largest input span available p-p.
ADT1-1WT RATIO VIN+
49.9 AVDD 0.1F
*CDIFF
AD9228
VIN- AGND
*CDIFF OPTIONAL
05727-008
Figure Differential Transformer Coupled Configuration Baseband Applications
16nH ADT1-1WT 0.1F RATIO 16nH 16nH AVDD 0.1F
05727-047
2.2pF
VIN+
AD9228
VIN-
Figure Differential Transformer Coupled Configuration Applications
Differential Input Configurations
There several ways which drive AD9228 either actively passively. either case, optimum performance achieved driving analog input differentially. example using AD8332 differential driver. provides excellent performance flexible interface (see Figure baseband applications. This configuration common medical ultrasound systems. However, noise performance most amplifiers adequate achieve true performance AD9228. applications where parameter, differential transformer coupling recommended input configuration. examples shown Figure Figure configuration, value shunt capacitor, dependent input frequency need reduced removed.
Single-Ended Input Configuration
single-ended input provide adequate performance cost-sensitive applications. this configuration, SFDR distortion performance degrade large input commonmode swing. application requires single-ended input configuration, ensure that source impedances each input well matched order achieve best possible performance. full-scale input still applied ADC's VIN+ while VIN- terminated. Figure details typical single-ended input configuration.
AVDD 49.9 0.1µF AVDD 0.1µF *CDIFF *CDIFF OPTIONAL
05727-009
05727-007
VIN+
AD9228
VIN-
Figure Single-Ended Input Configuration
0.1F
0.1F 120nH 22pF
0.1F 1.0k 1.0k
AD8332
VIN+
AD9228
VIN- VREF
0.1F
0.1F 0.1F
18nF
0.1F
Figure Differential Input Configuration Using AD8332
Rev. Page
AD9228
CLOCK INPUT CONSIDERATIONS
optimum performance, AD9228 sample clock inputs (CLK+ CLK-) should clocked with differential signal. This signal typically ac-coupled into CLK+ CLK- pins transformer capacitors. These pins biased internally require additional bias. Figure shows preferred method clocking AD9228. jitter clock source converted from single-ended differential using transformer. back-to-back Schottky diodes across secondary transformer limit clock excursions into AD9228 approximately differential. This helps prevent large voltage swings clock from feeding through other portions AD9228 preserves fast rise fall times signal, which critical jitter performance.
MIN-CIRCUITS ADT1-1WT, 1:1Z 0.1µF XFMR 0.1µF 0.1µF SCHOTTKY DIODES: HSM2812
some applications, acceptable drive sample clock inputs with single-ended CMOS signal. such applications, CLK+ should directly driven from CMOS gate, CLK- should bypassed ground with capacitor parallel with resistor (see Figure 53). Although CLK+ input circuit supply AVDD (1.8 this input designed withstand input voltages making selection drive logic voltage very flexible.
0.1µF CLOCK INPUT
AD9510/1/2/3/4/5 CMOS DRIVER
OPTIONAL 0.1µF
CLK+
0.1µF
AD9228
CLK-
05727-027
0.1µF
RESISTOR OPTIONAL
Figure Single-Ended CMOS Sample Clock
0.1µF CLOCK INPUT
CLOCK INPUT 0.1µF
CLK+
CLK-
05727-024
AD9228
AD9510/1/2/3/4/5 CMOS DRIVER
OPTIONAL 0.1µF
CLK+
0.1µF
0.1µF
AD9228
CLK-
05727-028
Figure Transformer Coupled Differential Clock
RESISTOR OPTIONAL
jitter clock available, another option ac-couple differential PECL signal sample clock input pins shown Figure AD9515 family clock drivers offers excellent jitter performance.
Figure Single-Ended CMOS Sample Clock
Clock Duty Cycle Considerations
Typical high speed ADCs both clock edges generate variety internal timing signals. result, these ADCs sensitive clock duty cycle. Commonly, tolerance required clock duty cycle maintain dynamic performance characteristics. AD9228 contains duty cycle stabilizer (DCS) that retimes nonsampling edge, providing internal clock signal with nominal duty cycle. This allows wide range clock input duty cycles without affecting performance AD9228. When noise distortion performance nearly flat wide range duty cycles. function cannot turned off. duty cycle stabilizer uses delay-locked loop (DLL) create nonsampling edge. result, changes sampling frequency require approximately clock cycles allow acquire lock rate.
CLOCK INPUT
0.1µF AD9510/1/2/3/4/5 0.1µF PECL DRIVER
0.1µF CLK+ 0.1µF
AD9228
CLK-
05727-025
CLOCK INPUT
RESISTORS OPTIONAL
Figure Differential PECL Sample Clock
CLOCK INPUT
0.1µF AD9510/1/2/3/4/5 0.1µF LVDS DRIVER
0.1µF CLK+ 0.1µF
AD9228
CLK-
05727-026
CLOCK INPUT
RESISTORS OPTIONAL
Figure Differential LVDS Sample Clock
Rev. Page
AD9228
Clock Jitter Considerations
High speed, high resolution ADCs sensitive quality clock input. degradation given input frequency (fA) only aperture jitter (tJ) calculated degradation [1/2 this equation, aperture jitter represents root mean square jitter sources, including clock input, analog input signal, aperture jitter specifications. undersampling applications particularly sensitive jitter (see Figure 55). clock input should treated analog signal cases where aperture jitter affect dynamic range AD9228. Power supplies clock drivers should separated from output driver supplies avoid modulating clock signal with digital noise. jitter, crystal-controlled oscillators make best clock sources. clock generated from another type source gating, dividing, other methods), should retimed original clock last step. Refer AN-501 Application Note AN-756 Application Note more in-depth information about jitter performance relates ADCs (visit www.analog.com).
CURRENT (mA)
Power Dissipation Power-Down Mode
shown Figure Figure power dissipated AD9228 proportional sample rate. digital power dissipation does vary much because determined primarily DRVDD supply bias current LVDS output drivers.
CURRENT (mA)
AVDD CURRENT TOTAL POWER DRVDD CURRENT ENCODE (MSPS)
05727-089 05727-081
Figure Supply Current fSAMPLE 10.3 MHz, fSAMPLE MSPS
AVDD CURRENT TOTAL POWER DRVDD CURRENT
POWER (mW)
CLOCK JITTER REQUIREMENT
(dB)
BITS BITS BITS BITS 0.125 0.25 ANALOG INPUT FREQUENCY (MHz)
05727-038
ENCODE (MSPS)
1000
Figure Supply Current fSAMPLE 10.3 MHz, fSAMPLE MSPS
Figure Ideal Input Frequency Jitter
Rev. Page
POWER (mW)
AD9228
asserting PDWN high, AD9228 placed power-down mode. this state, typically dissipates During power-down, LVDS output drivers placed high impedance state. AD9228 returns normal operating mode when PDWN pulled low. This both tolerant. power-down mode, power dissipation achieved shutting down reference, reference buffer, PLL, biasing networks. decoupling capacitors REFT REFB discharged when entering power-down mode must recharged when returning normal operation. result, wake-up time related time spent power-down mode; shorter cycles result proportionally shorter wake-up times. With recommended decoupling capacitors REFT REFB, takes approximately fully discharge reference buffer decoupling capacitors restore full operation. There number other power-down options available when using port interface. user individually power down each channel entire device into standby mode. This allows user keep internal powered when fast wake-up times (~600 required. Memory section more details using these features. termination resistor placed close receiver possible. far-end receiver termination poor differential trace routing result timing errors. recommended that trace length longer than inches that differential output traces kept close together equal lengths. example data stream with proper trace length position found Figure
200mV/DIV 200mV/DIV DATA 500mV/DIV
2.5ns/DIV
Figure LVDS Output Timing Example ANSI Mode (Default)
Digital Outputs Timing
AD9228 differential outputs conform ANSI-644 LVDS standard default power-up. This changed power, reduced signal option similar IEEE 1596.3 standard using SDIO/ODM SPI. This LVDS standard further reduce overall power dissipation device roughly SDIO/ODM section Table Memory section more information. LVDS driver current derived on-chip sets output current each output equal nominal differential termination resistor placed LVDS receiver inputs results nominal swing receiver. AD9228 LVDS outputs facilitate interfacing with LVDS receivers custom ASICs FPGAs that have LVDS capability superior switching performance noisy environments. Single point-to-point topologies recommended with
example LVDS output using ANSI standard (default) data time interval error (TIE) jitter histogram with trace lengths less than inches regular FR-4 material shown Figure Figure shows example when trace lengths exceed inches regular FR-4 material. Notice that jitter histogram reflects decrease data opening edge deviates from ideal position. user determine waveforms meet timing budget design when trace lengths exceed inches. Additional options allow user further increase internal termination (increasing current) four outputs order drive longer trace lengths (see Figure 61). Even though this produces sharper rise fall times data edges less prone errors, power dissipation DRVDD supply increases when this option used. Also notice Figure that histogram improved. Memory section more details.
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05727-045
AD9228
DIAGRAM VOLTAGE
EYE: BITS
ULS: 10000/15600
DIAGRAM VOLTAGE
EYE: BITS
ULS: 9599/15599
-200 -400
-500 -1ns -0.5ns 0.5ns
-1ns
-0.5ns
0.5ns
JITTER HISTOGRAM (Hits)
JITTER HISTOGRAM (Hits)
05727-043
-100ps
-0ps
100ps
-150ps
-100ps
-50ps
-0ps
50ps
100ps
150ps
Figure Data LVDS Outputs ANSI Mode with Trace Lengths Less than Inches Standard FR-4
DIAGRAM VOLTAGE
Figure Data LVDS Outputs ANSI Mode with Termination Trace Lengths Greater than Inches Standard FR-4
EYE: BITS
ULS: 9600/15600
format output data offset binary default. example output coding format found Table desired change output data format twos complement, Memory section. Table Digital Output Coding
Code 4095 2048 2047 (VIN+) (VIN-), Input Span +1.00 0.00 -0.000488 -1.00 Digital Output Offset Binary (D11 1111 1111 1111 1000 0000 0000 0111 1111 1111 0000 0000 0000
-200 -1ns -0.5ns 0.5ns
JITTER HISTOGRAM (Hits)
Data from each serialized provided separate channel. data rate each serial stream equal bits times sample clock rate, with maximum Mbps bits MSPS Mbps). lowest typical conversion rate MSPS. However, lower sample rates required specific application, encode rates lower than MSPS SPI. This allows encode rates MSPS. Memory section enable this feature.
-150ps
-100ps
-50ps
-0ps
50ps
100ps
150ps
Figure Data LVDS Outputs ANSI Mode with Trace Lengths Greater than Inches Standard FR-4
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05727-044
05727-042
AD9228
output clocks provided assist capturing data from AD9228. used clock output data equal times sampling clock (CLK) rate. Data clocked AD9228 must captured rising falling edges that supports double data rate Table Flex Output Test Modes
Output Test Mode Sequence 0000 0001 Subject Data Format Select
(DDR) capturing. frame clock (FCO) used signal start output byte equal sampling clock rate. timing diagram shown Figure more information.
Pattern Name (default) Midscale Short
0010
+Full-Scale Short
0011
-Full-Scale Short
0100
Checker Board
0101 0110 0111
Sequence Long Sequence Short1 One/Zero Word Toggle
1000 1001
User Input One/Zero Toggle
1010
Sync
1011
High
1100
Mixed Frequency
Digital Output Word 1000 0000 (8-bit) 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 0000 0000 0000 (14-bit) 1111 1111 (8-bit) 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 1111 1111 1111 (14-bit) 0000 0000 (8-bit) 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 0000 0000 0000 (14-bit) 1010 1010 (8-bit) 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 1010 1010 1010 (14-bit) 1111 1111 (8-bit) 1111 1111 (10-bit) 1111 1111 1111 (12-bit) 1111 1111 1111 (14-bit) Register 0x19 Register 0x1A 1010 1010 (8-bit) 1010 1010 (10-bit) 1010 1010 1010 (12-bit) 1010 1010 1010 (14-bit) 0000 1111 (8-bit) 0001 1111 (10-bit) 0000 0011 1111 (12-bit) 0000 0111 1111 (14-bit) 1000 0000 (8-bit) 0000 0000 (10-bit) 1000 0000 0000 (12-bit) 0000 0000 0000 (14-bit) 1010 0011 (8-bit) 0110 0011 (10-bit) 1010 0011 0011 (12-bit) 1000 0110 0111 (14-bit)
Digital Output Word Same
Same
Same
0101 0101 (8-bit) 0101 0101 (10-bit) 0101 0101 0101 (12-bit) 0101 0101 0101 (14-bit) 0000 0000 (8-bit) 0000 0000 (10-bit) 0000 0000 0000 (12-bit) 0000 0000 0000 (14-bit) Register 0x1B Register 0x1C
pseudorandom number, sequence determined number bits shift register. long sequence bits short sequence bits. sequence generated utilized described O.150 standard. general, polynomial, (long) (short), defines pseudorandom sequence.
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AD9228
When using serial port interface (SPI), phase adjusted increments relative data edge. This enables user refine system timing margins required. default timing, shown Figure relative output data edge. 10-, 14-bit serial stream also initiated from SPI. This allows user implement test compatibility lower higher resolution systems. When changing resolution 10-bit serial stream, data stream shortened. Figure 10-bit example. However, when using 14-bit option, data stream stuffs normal 14-bit serial data. When using SPI, data outputs also inverted from their nominal state. This confused with inverting serial stream LSB-first mode. default mode, shown Figure represented first data output serial stream. However, this inverted that represented first data output serial stream (see Figure There digital output test pattern options available that initiated through SPI. This useful feature when validating receiver capture timing. Refer Table output sequencing options available. Some test patterns have serial sequential words alternated various ways, depending test pattern chosen. should noted that some patterns adhere data format select option. addition, customer user patterns assigned 0x19, 0x1A, 0x1B, 0x1C register addresses. test mode options support 14-bit word lengths order verify data capture receiver. Please consult Memory section information change these additional digital output timing features through serial port interface SPI. Table Output Driver Mode Settings
Selected Normal operation Voltage AGND AVDD Resulting Output Standard ANSI-644 (default) Resulting ANSI-644 (default)
power, reduced signal option
power, reduced signal option
SCLK/DTP
This applications that require mode operation. serial clock/digital test pattern (SCLK/DTP) enable single digital test pattern this held high during device power-up. When tied AVDD, channel outputs shift following pattern: 1000 0000 0000. outputs still work usual while channels shift repeatable test pattern. This pattern allows user perform timing alignment adjustments among FCO, DCO, output data. normal operation, this should tied AGND through resistor. This both tolerant. Table Digital Test Pattern Settings
Selected Normal operation Voltage AGND AVDD Resulting Normal operation 1000 0000 0000 Resulting Normal operation Normal operation
Additional custom test patterns also observed when commanded from port. Consult Memory section choose from different options available.
chip select (CSB) should tied AVDD applications that require mode operation. tying high, SCLK SDIO information ignored. This both tolerant.
SDIO/ODM
This applications that require mode operation. SDIO/ODM enable power, reduced signal option similar IEEE 1596.3 reduced range link output standard this tied AVDD during device powerup. This option should only used when digital output trace lengths less than inches length LVDS receiver. FCO, DCO, outputs still work usual, LVDS signal swing channels reduced from p-p. This output mode allows user further lower power DRVDD supply. applications where this used, should tied low. this case, device left open, internal pull-down resistor pulls this low. This only tolerant. applications require this driven from logic level, insert resistor series with this limit current.
RBIAS
internal core bias current ADC, place resistor (nominally equal 10.0 ground RBIAS pin. resistor current derived on-chip sets ADC's AVDD current nominal MSPS. Therefore, imperative that least tolerance this resistor used achieve consistent performance. SFDR performance critical power, simply adjust core current achieve lower power. Figure Figure show relationship between dynamic range power RBIAS resistance changed. Nominally, 10.0 value, indicated dashed line.
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AD9228
Internal Reference Operation
comparator within AD9228 detects potential SENSE configures reference. SENSE grounded, reference amplifier switch connected internal resistor divider (see Figure 64), setting VREF REFT REFB pins establish their input span core from reference configuration. analog input fullscale range equals twice voltage reference either internal external reference configuration. reference AD9228 used drive multiple converters improve gain matching, loading reference other converters must considered. Figure depicts internal reference voltage affected loading.
VIN+ VIN- REFT CORE 0.1µF 0.1µF REFB
SFDR (dBc)
SFDR
05727-063
RESISTANCE
Figure SFDR RBIAS
(dBc)
IAVDD (mA)
2.2µF
VREF 0.1µF SELECT LOGIC SENSE
05727-082
0.1µF 0.5V
RESISTANCE
05727-010
Figure IAVDD RBIAS Figure Internal Reference Configuration
Voltage Reference
stable accurate voltage reference built into AD9228. This gained factor internally, setting VREF which results full-scale differential input span p-p. VREF internally default; however, VREF driven externally with reference achieve more accuracy. When applying decoupling capacitors VREF, REFT, REFB pins, ceramic capacitors. These capacitors should close pins same layer AD9228. recommended capacitor values configurations AD9228 reference found Figure Table Reference Settings
Selected Mode External Reference Internal, SENSE Voltage AVDD AGND Resulting VREF Resulting Differential Span p-p) external reference
VIN+ VIN- REFT CORE 0.1µF 0.1µF REFB VREF 0.1µF AVDD SENSE SELECT LOGIC 0.5V 0.1µF
2.2µF
Figure External Reference Operation
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05727-046
AD9228
External Reference Operation
external reference necessary enhance gain accuracy improve thermal drift characteristics. Figure shows typical drift characteristics internal reference mode. When SENSE tied AVDD, internal reference disabled, allowing external reference. external reference loaded with equivalent load. internal reference buffer generates positive negative full-scale references, REFT REFB, core. Therefore, external reference must limited nominal
0.20 0.15 0.10
VREF ERROR
0.05 -0.05 -0.10
05727-084
-0.15 -0.20
TEMPERATURE (°C)
Figure Typical VREF Drift
VREF ERROR
CURRENT LOAD (mA)
Figure VREF Accuracy Load
05727-083
Rev. Page
AD9228 SERIAL PORT INTERFACE (SPI)
AD9228 serial port interface allows user configure converter specific functions operations through structured register space provided inside ADC. This gives user added flexibility customization depending application. Addresses accessed serial port written read from port. Memory organized into bytes that further divided down into fields, documented Memory section. Detailed operational information found Analog Devices user manual Interfacing High Speed ADCs SPI. There three pins that define serial port interface this particular ADC. They SCLK, SDIO, pins. SCLK (serial clock) used synchronize read write data presented ADC. SDIO (serial data input/output) dual-purpose that allows data sent read from internal memory registers. (chip select bar) active control that enables disables read write cycles (see Table 13). Table Serial Port Pins
SCLK SDIO Function Serial Clock. serial shift clock SCLK used synchronize serial interface reads writes. Serial Data Input/Output. dual-purpose pin. typical role this input output, depending instruction sent relative position timing frame. Chip Select (Active Low). This control gates read write cycles.
middle byte transfer, state machine reset device waits instruction. addition operation modes, port configured operate different manners. applications that require control port, line tied held high. This places remainder pins their secondary mode defined Serial Port Interface (SPI) section. also tied enable 2-wire mode. When tied low, SCLK SDIO only pins required communication. Although device synchronized during power-up, caution must exercised when using this mode ensure that serial port remains synchronized with line. When operating 2-wire mode, recommended 3-byte transfer exclusively. Without active line, streaming mode entered exited. addition word length, instruction phase determines serial frame read write operation, allowing serial port used both program chip read contents on-chip memory. instruction readback operation, performing readback causes serial data input/output (SDIO) change direction from input output appropriate point serial frame. Data sent MSB- LSB-first mode. MSB-first mode default power-up changed adjusting configuration register. more information about this other features, user manual Interfacing High Speed ADCs SPI.
falling edge conjunction with rising edge SCLK determines start framing sequence. During instruction phase, 16-bit instruction transmitted followed more data bytes, which determined Fields example serial timing definitions found Figure Table normal operation, used signal device that commands received processed. When brought low, device processes SCLK SDIO process instructions. Normally, remains until communication cycle complete. However, connected slow device, brought high between bytes, allowing microcontrollers enough time transfer data into shift registers. stalled when transferring one, two, three bytes data. When device enters streaming mode continues process data, either reading writing, until taken high communication cycle. This allows complete memory transfers without having provide additional instructions. Regardless mode, taken high
HARDWARE INTERFACE
pins described Table compose physical interface between user's programming device serial port AD9228. SCLK pins function inputs when using interface. SDIO bidirectional, functioning input during write phases output during readback. This interface flexible enough controlled either serial PROMS mirocontrollers. This provides user alternative method, other than full controller, program (see AN-812 Application Note). user chooses interface, these pins serve dual function associated with secondary functions when strapped AVDD during device power-up. Theory Operation section details which pinstrappable functions supported pins.
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AD9228
tCLK
SCLK DON'T CARE
DON'T CARE
SDIO DON'T CARE
DON'T CARE
Figure Serial Timing Details
Table Serial Timing Definitions
Parameter tCLK Timing (minimum, Description Set-up time between data rising edge SCLK Hold time between data rising edge SCLK Period clock Set-up time between SCLK Hold time between SCLK Minimum period that SCLK should logic high state Minimum period that SCLK should logic state
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05727-012
AD9228 MEMORY
READING MEMORY TABLE
Each memory table eight address locations. memory roughly divided into three sections: chip configuration register (Address 0x00 Address 0x02), device index transfer register (Address 0x05 Address 0xFF), program register (Address 0x08 Address 0x25). left-hand column memory indicates register address number hexadecimal. default value this address shown hexadecimal right-hand column. (MSB) column start default hexadecimal value given. example, Hexadecimal Address 0x09, Clock, hexadecimal default value 0x01. This means 0000 0001 binary. This setting default duty cycle stabilizer condition. writing this address, duty cycle stabilizer turns off. more information this other functions, consult user manual Interfacing High Speed ADCs SPI.
RESERVED LOCATIONS
Undefined memory locations should written except when writing default values suggested this data sheet. Addresses that have values marked should considered reserved have written into their registers during power-up.
DEFAULT VALUES
Coming reset, critical registers preloaded with default values. These values indicated Table where refers undefined feature.
LOGIC LEVELS
explanation various registers follows: "Bit set" synonymous with "bit Logic "writing Logic bit." Similarly, "clear bit" synonymous with "bit Logic "writing Logic bit."
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AD9228
Table Memory Register
Addr. (Hex) Parameter Name (MSB) Chip Configuration Registers chip_port_config first (default) Soft reset (default) Soft reset (default) first (default) (LSB) Default Value (Hex) 0x18 Default Notes/ Comments nibbles should mirrored that LSB- MSB-first mode registers correctly regardless shift mode. Default unique chip different each device. This readonly register. Child used differentiate graded devices.
chip_id
8-bit Chip Bits (AD9228 0x02), (default)
0x02
chip_grade
Child (identify device variants Chip MSPS, MSPS Clock Channel (default) Clock Channel (default)
Read only
Device Index Transfer Registers device_index_A
device_update
Data Channel (default)
Data Channel (default)
Data Channel (default)
Data Channel (default) transfer (default)
0x0F
Bits determine which on-chip device receives next write command. Synchronously transfers data from master shift register slave. Determines various generic modes chip operation. Turns internal duty cycle stabilizer off.
0x00
Functions modes
clock
Internal power-down mode chip (default) full power-down standby reset Duty cycle stabilizer (default)
0x00
0x01
test_io
User test mode (default) single alternate single once alternate once
Reset long (default)
Reset short (default)
Output test mode-see Table Digital Outputs Timing section 0000 (default) 0001 midscale short 0010 short 0011 short 0100 checker board output 0101 sequence 0110 0111 one/zero word toggle 1000 user input 1001 one/zero toggle 1010 sync 1011 high 1100 mixed frequency (format determined output_mode)
0x00
When set, test data placed output pins place normal data.
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AD9228
Addr. (Hex) Parameter Name output_mode (MSB) LVDS ANSI (default) LVDS power, (IEEE 1596.3 similar) Output invert (default) (LSB) offset binary (default) twos complement Default Value (Hex) 0x00 Default Notes/ Comments Configures outputs format data.
output_adjust
Output driver termination none (default)
0x00
output_phase
user_patt1_lsb user_patt1_msb user_patt2_lsb user_patt2_msb serial_control
first (default)
0011 output clock phase adjust (0000 through 1010) (Default: 180° relative DATA edge) 0000 relative DATA edge 0001 relative DATA edge 0010 120° relative DATA edge 0011 180° relative DATA edge 0100 240° relative DATA edge 0101 300° relative DATA edge 0110 360° relative DATA edge 0111 420° relative DATA edge 1000 480° relative DATA edge 1001 540° relative DATA edge 1010 600° relative DATA edge 1011 1111 660° relative DATA edge MSPS, encode rate mode (default)
0x03
Determines LVDS other output properties. Primarily functions LVDS span common-mode levels place external resistor. devices that utilize global clock divide, determines which phase divider output used supply output clock. Internal latching unaffected.
0x00 0x00 0x00 0x00 0x00
bits (default, normal stream) bits bits bits bits
User-defined pattern, LSB. User-defined pattern, MSB. User-defined pattern, LSB. User-defined pattern, MSB. Serial stream control. Default causes first native stream (global).
serial_ch_stat
Channel output reset (default)
Channel powerdown (default)
0x00
Used power down individual sections converter (local).
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AD9228
Power Ground Recommendations
When connecting power AD9228, recommended that separate supplies used: analog (AVDD) digital (DRVDD). only supply available, should routed AVDD first then tapped isolated with ferrite bead filter choke preceded decoupling capacitors DRVDD. user employ several different decoupling capacitors cover both high frequencies. These should located close point entry board level close parts with minimal trace length. single board ground plane should sufficient when using AD9228. With proper decoupling smart partitioning board's analog, digital, clock sections, optimum performance easily achieved.
Exposed Paddle Thermal Heat Slug Recommendations
required that exposed paddle underside connected analog ground (AGND) achieve best electrical thermal performance AD9228. exposed continuous copper plane should mate AD9228 exposed paddle, copper plane should have several vias achieve lowest possible resistive thermal path heat dissipation flow through bottom PCB. These vias should solder filled plugged. maximize coverage adhesion between PCB, partition continuous copper plane overlaying silkscreen into several uniform sections. This provides several points between during reflow process. Using continuous plane with partitions only guarantees point between PCB. Figure layout example. detailed information packaging layout chip scale packages, AN-772 Application Note, Design Manufacturing Guide Lead Frame Chip Scale Package (LFCSP)," www.analog.com.
SILKSCREEN PARTITION INDICATOR
Figure Typical Layout
Rev. Page
05727-013
AD9228 EVALUATION BOARD
AD9228 evaluation board provides support circuitry required operate various modes configurations. converter driven differentially through transformer (default) through AD8332 driver. also driven single-ended fashion. Separate power pins provided isolate from AD8332 drive circuitry. Each input configuration selected proper connection various jumpers (see Figure Figure 76). Figure shows typical bench characterization setup used evaluate performance AD9228. critical that signal sources used analog input clock have very phase noise jitter) realize optimum performance converter. Proper filtering analog input signal remove harmonics lower integrated broadband noise input also necessary achieve specified noise performance. Figure Figure complete schematics layout diagrams that demonstrate routing grounding techniques that should applied system level. each section. least supply needed with current capability AVDD_DUT DRVDD_DUT; however, recommended that separate supplies used both analog digital. operate evaluation board using option, separate analog supply needed. supply, AVDD_5 should have current capability. operate evaluation board using alternate clock options, separate analog supply needed addition other supplies. supply, AVDD_3.3 should have current capability well.
INPUT SIGNALS
When connecting clock analog source, clean signal generators with phase noise, such Rohde Schwarz SMHU HP8644 signal generators equivalent. shielded, RG-58, coaxial cable making connections evaluation board. Enter desired frequency amplitude from specifications tables. Typically, most evaluation boards accept ~2.8 sine wave input clock. When connecting analog input source, recommended multipole, narrow-band, band-pass filter with terminations. uses TTE, Allen Avionics, types band-pass filters. filter should connected directly evaluation board possible.
POWER SUPPLIES
This evaluation board comes with wall-mountable switching power supply that provides maximum output. Simply connect supply rated wall outlet other inner diameter jack that connects P503. Once board, supply fused conditioned before connecting three dropout linear regulators that supply proper bias each various sections board. When operating evaluation board nondefault condition, L504 L507 removed disconnect switching power supply. This enables user bias each section board individually. P501 connect different supply
OUTPUT SIGNALS
default setup uses HSC-ADC-FPGA high speed deserialization board deserialize digital output data convert parallel CMOS. These channels interface directly with standard dual-channel FIFO data capture board (HSC-ADC-EVALA-DC). four channels then evaluated same time. more information channel settings these boards their optional settings, visit www.analog.com/FIFO.
WALL OUTLET 100V 240V 47Hz 63Hz SWITCHING POWER SUPPLY
5.0V
1.8V
1.8V
3.3V
3.3V
1.5V
3.3V
1.5V_FPGA
AVDD_5V
DRVDD_DUT
AVDD_3.3V
AVDD_DUT
3.3V_D
ROHDE SCHWARZ, SMHU, SIGNAL SYNTHESIZER ROHDE SCHWARZ, SMHU, SIGNAL SYNTHESIZER
BAND-PASS FILTER
XFMR INPUT
AD9228
EVALUATION BOARD
Figure Evaluation Board Connection
Rev. Page
05727-014
CHA-CHD 12-BIT SERIAL LVDS
HSC-ADC-FPGA HIGH SPEED DESERIALIZATION BOARD 12-BIT PARALLEL CMOS
HSC-ADC-EVALA-DC FIFO DATA CAPTURE BOARD CONNECTION
RUNNING ANALYZER USER SOFTWARE
AD9228
DEFAULT OPERATION JUMPER SELECTION SETTINGS
following list default optional settings modes allowed AD9228 Rev. evaluation board. POWER: Connect switching power supply that supplied evaluation between rated wall outlet P503. AIN: evaluation board transformercoupled analog input with optimum impedance matching (see Figure 71). more bandwidth response, differential capacitor across analog inputs changed removed. common mode analog inputs developed from center transformer AVDD_DUT/2.
terminated ac-coupled handle single-ended sine wave types inputs. transformer converts single-ended input differential signal that clipped before entering clock inputs. differential LVPECL clock also used clock input using AD9515 (U202). Simply populate R225 R227 with resistors remove R217 R218 disconnect default clock path inputs. addition, populate C207 C208 with capacitor remove C210 C211 disconnect default cloth path outputs. AD9515 many pin-strappable options that default working condition. Consult AD9515 data sheet more information about these other options. using oscillator, oscillator footprint options also available (OSC201) check performance. J205 gives user flexibility using enable pin, which common most oscillators. PDWN: enable power-down feature, simply short J201 position (AVDD) PDWN pin. SCLK/DTP: enable digital test patterns digital outputs ADC, J204. J204 tied AVDD during device power-up, Test Pattern 1000 0000 0000 will enabled. SCLK/DTP section details. SDIO/ODM: enable power, reduced signal option similar IEEE 1595.3 reduced range link LVDS output standard, J203. J203 tied AVDD during device power-up, enables LVDS outputs power, reduced signal option from default ANSI standard. This option changes signal swing from p-p, which reduces power DRVDD supply. SDIO/ODM section more details. CSB: enable information SDIO SCLK pins that processed, simply J202 always enable mode. ignore SDIO SCLK information, J202 AVDD. alternative data capture method setup described Figure used, optional receiver terminations, R206 R211, installed next high speed backplane connector.
-3dB CUTOFF 200MHz
AMPLITUDE (dBFS)
05727-088
FREQUENCY (MHz)
Figure Evaluation Board Full Power Bandwidth
VREF: VREF tying SENSE ground, R237. This causes operate full-scale range. separate external reference option using ADR510 ADR520 also included evaluation board. Simply populate R231 R235 remove C214. Proper VREF options noted Voltage Reference section. RBIAS: RBIAS default setting (R201) ground used core bias current. further lower core power (excluding LVDS driver supply), simply change resistor setting. However, performance will degrade depending resistor chosen. RBIAS section more information. CLOCK: default clock input circuitry derived from simple transformer-coupled circuit using high bandwidth impedance ratio transformer (T201) that adds very amount jitter clock path. clock input
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AD9228
ALTERNATIVE ANALOG INPUT DRIVE CONFIGURATION
following brief description alternative analog input drive configuration using AD8332 dual VGA. this particular drive option use, some components need populated, which case necessary components listed Table more details AD8332 dual VGA, including works optional settings, consult AD8332 data sheet. configure analog input drive instead default transformer option, following components need removed and/or changed. Remove R102, R115, R128, R141, T101, T102, T103, T104 default analog input path. Populate R101, R114, R127, R140 with resistors analog input path. Populate R106, R107, R119, R120, R132, R133, R144, R145 with resistors provide input commonmode level analog input. Populate R105, R113, R118, R124, R131, R137, R151, R160 with resistors analog input path.
Currently, L301 L308 L401 L408 populated with resistors allow signal connection. This area allows user design filter additional requirements necessary.
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AD9228
AVDD_DUT R105 FB102 R108 R106
CH_A P102 INPUT CONNECTION INH1 CHANNEL R101 P101 R103 R102 64.9 R104 C101 0.1µF
R152
T101
VIN_A R161 C103 C104 2.2pF R109 VIN_A FB103 R110 C105 R156
R107
R113 FB101 C102 0.1µF CH_A E101
AVDD_DUT
R111 R112
C107 0.1µF
C106
AVDD_DUT AVDD_DUT
INPUT CONNECTION INH2 CHANNEL R114 P103 R115 64.9 P104 R117
CH_B
R118 FB105 R121 R119
R153
T102
FB104 C108 0.1µF R116
VIN_B R162 C110 C111 2.2pF R123 VIN_B FB106 R122 C112 R157
R120
R124 C109 0.1µF CH_B E102
AVDD_DUT
R125 R126
C114 0.1µF
C113 AVDD_DUT R154
AVDD_DUT
CH_C P106 INPUT CONNECTION INH3 CHANNEL R127 P105 R129 R128 64.9 R130 C115 0.1µF
R131 FB108 R134 R132
T103
VIN_C R163 C117 C118 2.2pF R135 VIN_C R158
R133
R137 FB107 C116 0.1µF CH_C E103
FB109 R136 C120
C119
AVDD_DUT
R138 R139
C121 0.1µF
AVDD_DUT AVDD_DUT
INPUT CONNECTION INH4 CHANNEL R140 P107 R141 64.9 P108 R142
CH_D
R151 FB111 R146 R144
R155
T104
FB110 C122 0.1µF
VIN_D R164 C124 C125 2.2pF R148 VIN_D FB112 R147 C126 R159
R145
R160 R143 C123 0.1µF CH_D E104
AVDD_DUT
DNP: POPULATE
Figure Evaluation Board Schematic, Analog Inputs
Rev. Page
05727-015
R149 R150
C128 0.1µF
C127
AVDD_DUT
REFERENCE CIRCUIT OPTIONAL AVDD_DUT R229 4.99k R231 R234 VREF 0.5V VREF EXTERNAL
R202 100k J201
C204 0.1µF
REFERENCE DECOUPLING
U203 ADR510/20 VOUT TRIM/NC VREF_DUT VREF SELECT VSENSE_DUT
DIGITAL OUTPUTS
VREF 0.5V(1+R232/R233) VREF R232 R235 R236 R237
AVDD_DUT
C202 2.2µF
C203 0.1µF
R201 R228 470k C213 0.1µF R233 C214 C212 0.1µF
R230
R206 R207 R208 R209 R210 R211
AVDD_DUT AVDD_DUT
VIN_C VIN_C
VREF_DUT VSENSE_DUT AVDD_DUT VIN_B VIN_B
C201 0.1µF
U201
VIN-C VIN+C AVDD AVDD REFT REFB VREF SENSE RBIAS AVDD VIN+B VIN-B
AVDD_DUT REMOVE C214 WHEN USING EXTERNAL VREF
PWDN ENABLE ALWAYS ENABLE
AVDD_3.3V R246 R248 R250 R252 R254 AVDD_3.3V R249 R251 R253 R255 R247 AVDD_3.3V AVDD_3.3V R244 R245
AVDD_DUT AVDD_DUT VIN_A VIN_A AVDD_DUT
R266 100k
R267 100k
AD9228LFCSP
AVDD AVDD VIN-A VIN+A AVDD PDWN J202
P202 GNDCD10 GNDCD9 GNDCD8 GNDCD7 GNDCD6 GNDCD5 GNDCD4 GNDCD3 R256 R257
GNDCD2
J203
ENABLE
CSB_DUT
C2GNDCD1
FCO- FCO+ DCO- DCO+
R203 100k
R204 100k
R205
AVDD_DUT AVDD_DUT VIN_D VIN_D AVDD_DUT AVDD_DUT AVDD_DUT AVDD_DUT DRVDD_DUT
SDIO/ODM SCLK/DTP AVDD DRVDD DRGND
AVDD AVDD VIN-D VIN+D AVDD AVDD CLK- CLK+ AVDD AVDD DRVDD DRGND
AVDD_DUT DRVDD_DUT ENABLE
SDIO_ODM J204 SCLK_DTP
AVDD_3.3V AVDD_3.3V
R258 R260 AVDD_3.3V AVDD_3.3V R262 R264 AVDD_3.3V
R259 R261 R263 R265
GNDAB10 GNDAB9 SCLK_CHB SDI_CHB CSB3_CHB LVPECL OUTPUT
GNDAB8
AVDD_3.3V AVDD_3.3V
GNDAB7
RSET
CB3LV-3C OPT_CLK
ENCODE INPUT GND_PAD
OSC201 VCC' OUT' GND' R220 R221 U202
E201
R238
R239
VREF
T201
CR201 HSMS2812
R216
C216 0.1µF
R218 C206 0.1µF
05727-016
Figure Evaluation Board Schematic, DUT, VREF, Clock Inputs, Digital Output Interface
R214 ENABLE AVDD_3.3V J205 OPTIONAL CLOCK DRIVE CIRCUIT R222 4.02k AVDD_3.3V C207 0.1µF DISABLE R219 R215 OPT_CLK R242 C208 0.1µF CSB4_CHB R240 R241 R243 C210 0.1µF C209 0.1µF E202 LVDS OUTPUT E203 C215 0.1µF CLIP SINE (DEFAULT) C217 0.1µF C218 0.1µF C219 0.1µF C220 0.1µF C221 0.1µF AVDD_3.3V SDO_CHB
Rev. Page
R225 R226 49.9 R227 OUT0 CLKB OUT0B AD9515 SYNCB OUT1 SIGNAL=DNC;27,28 OUT1B R217 R223 R224 DNP: POPULATE
C211 0.1µF
GNDAB6
AVDD_3.3V
C224 0.1µF
GNDAB5
GNDAB4
OPTIONAL CLOCK OSCILLATOR
GNDAB3
AVDD_3.3V
GNDAB2
SCLK_CHA SDI_CHA
GNDAB1
CSB1_CHA CSB2_CHA SDO_CHA
R212
P201
OPT_CLK
CONNECT
HEADERM1469169_1
CLOCK CIRCUIT
R213 49.9k
C205 0.1µF
R205-R211 OPTIONAL OUTPUT TERMINATIONS
P203
OPT_CLK
C222 0.1µF
C223 0.1µF
AD9228
AD9228
POPULATE L301-L308 WITH RESISTORS DESIGN YOUR FILTER.
CH_D CH_D CH_C CH_C
R301 C301 L301 C303 L305 R303 C305 0.1µF R305 R307 U301 ENBV ENBL HILO VCM1 VIN1 VIP1 COM1 LOP1 R308
R302 C302 L302 L303 L304 C304 L308 R304 C308 0.1µF C309 1000pF R310
POWER DOWN ENABLE (0-1V DISABLE POWER)
L306 L307
EXTERNAL VARIABLE GAIN DRIVE VARIABLE GAIN CIRCUIT (0-1.0V AVDD_5V R320 R319
JP301
OPTIONAL DRIVE CIRCUIT CHANNELS
AVDD_5V
R306 R309
AVDD_5V
VOL1 VPSV
R313
HILO GAIN RANGE 2.25V-5.0V GAIN RANGE 0-1.0V
VOL2 VOH2 COMM
COMM VOH1
R312
AVDD_5V
C310 0.1µF
R311
AD8332
LMD1 LMD2
LON1 VPS1 INH1
C312 0.1µF
INH2 VPS2 LON2
C311 0.1µF
C313 0.1µF
C314 0.1µF
R315
C315 10µF
C316 0.1µF
R316 C317 0.018µF
C320 0.1µF
C321 0.1µF
R317 C322 0.018µF
C325 0.1µF
C326 10µF
R318
C318 22pF L309 120nH C319 0.1µF
C323 22pF L310 120nH C324 0.1µF INH3
DNP: POPULATE
INH4
Figure Evaluation Board Schematic, Optional Analog Input Drive
Rev. Page
05727-017
MODE POSITIVE GAIN SLOPE 0-1.0V NEGATIVE GAIN SLOPE 2.25V-5.0V
RCLMP GAIN MODE VCM2 VIN2 VIP2 COM2 LOP2
R314
AVDD_5V
AVDD_5V
RCLAMP HILO ±50mV HILO ±75mV
C306 C307 0.1µF 0.1µF
CH_B
CH_B
CH_A
R401 C401 L401 CIRCUITRY FROM FIFO PROGRAMMING AVDD_5V +3.3V NORMAL OPERATION AVDD_3.3V AVDD_3.3V AVDD_5V J402 C402 L402 L403 L404
R402
POWER DOWN ENABLE (0-1V DISABLE POWER)
POPULATE L401-L408 WITH RESISTORS DESIGN YOUR FILTER.
C403 L405 R403 L406 L407
C404 L408 R404
CH_A
CSB1_CHA
SCLK_CHA
SDI_CHA
C405 0.1µF
C406 C407 0.1µF 0.1µF
R426
R428
R420
AVDD_5V
R407 R410 U402 R422 0-DNP
R408
R409
C412 0.1µF R421 0-DNP
C427 0.1µF
R427
R405 C411 1000pF R413
R406
C408 0.1µF
SDO_CHA
REMOVE WHEN USING PROGRAMMING (U402)
AVDD_3.3V
AVDD_5V
AVDD_5V RCLAMP HILO ±50mV HILO ±75mV
R411
U401
R433
COMM VOH1
VOL1 VPSV
VOL2 VOH2 COMM
R412
RESET/REPROGRAM
R424
MCLR/ PIC12F629 R419 CR401
R418 4.75k
S401
R423 0-DNP
SDIO_ODM AVDD_DUT R431 R425 E401 U403 AVDD_DUT C429 0.1µF
OPTIONAL
LON1 VPS1 INH1
LMD1 LMD2
OPTIONAL DRIVE CIRCUIT CHANNELS
HILO GAIN RANGE 2.25V-5.0V GAIN RANGE 0-1.0V
C410 0.1µF
INH2 VPS2 LON2
AVDD_5V
AVDD_5V
MODE POSITIVE GAIN SLOPE 0-1.0V NEGATIVE GAIN SLOPE 2.25V-5.0V
R416 C420 0.018µF
Figure Evaluation Board Schematic, Optional Analog Input Drive Interface (Continued)
AD8332 C423 0.1µF
Rev. Page
RCLMP GAIN MODE VCM2 VIN2 VIP2 COM2 LOP2 C424 0.1µF
C409 0.1µF
ENBV ENBL HILO VCM1 VIN1 VIP1 COM1 LOP1
R432 NC7WZ07
MCLR/GP3
J401 PICVCC
R414 C426 R417 10µF
C413 10µF
C414 0.1µF
R415 C416 0.1µF C417 0.1µF C425 0.1µF
C415 0.018µF
NC7WZ16
R430 R429
SCLK_DTP AVDD_DUT CSB_DUT
PICVCC
MCLR/GP3
PROGRAMMING HEADER
C418 22pF L409 120nH L410 120nH C422 0.1µF C419 0.1µF
C421 22pF
U404
C428 0.1µF
05727-018
INH2
INH1
DNP: POPULATE
AD9228
AD9228
POWER SUPPLY INPUT MAXIMUM F501 FER501 CHOKE_COIL CR501 R501 PWR_IN SMDC110F C501 10µF D501 S2A_RECT DO-214AA P503
D502 SHOT_RECT DO-214AB
OPTIONAL POWER INPUT P501 5V_AVDD AVDD_5V +5.0V C518 0.1µF C519 0.1µF C502 10µF C503 0.1µF L502 10µH AVDD_DUT C504 10µF C505 0.1µF C526 0.1µF L508 10µH AVDD_3.3V C508 10µF C509 0.1µF +3.3V AVDD_3.3V C524 0.1µF C525 0.1µF +1.8V AVDD_DUT C527 0.1µF C528 0.1µF AVDD_5V C520 0.1µF DUT_AVDD 3.3V_AVDD DUT_DRVDD L503 10µH
DECOUPLING CAPACITORS
C521 0.1µF
C522 0.1µF
C523 0.1µF
C529 0.1µF
C530 0.1µF
C531 0.1µF
C514
U503 PWR_IN INPUT C512 DNP: POPULATE ADP33339AKC-1.8 OUTPUT1 OUTPUT4
U504 L504 10µH DUT_DRVDD C513 PWR_IN C534 ADP33339AKC-5 INPUT OUTPUT1 OUTPUT4
C515
C532
05727-019
Figure Evaluation Board Schematic, Power Supply Inputs
Rev. Page
L501 10µH DRVDD_DUT +1.8V DRVDD_DUT C506 10µF C507 0.1µF U501 PWR_IN INPUT OUTPUT4 OUTPUT1 ADP33339AKC-1.8 L505 10µH DUT_AVDD PWR_IN U502 INPUT
C516 0.1µF
C517 0.1µF
MOUNTING HOLES CONNECTED GROUND
ADP33339AKC-3.3 OUTPUT1
OUTPUT4
L506 10µH 3.3V_AVDD C533
L507 10µH 5V_AVDD C535
AD9228
Figure Evaluation Board Layout, Primary Side
Rev. Page
05727-020
AD9228
Figure Evaluation Board Layout, Ground Plane
Rev. Page
05727-021
AD9228
Figure Evaluation Board Layout, Power Plane
Rev. Page
05727-022
AD9228
Figure Evaluation Board Layout, Secondary Side (Mirrored Image)
Rev. Page
05727-023
AD9228
Table Evaluation Board Bill Materials (BOM)
Qnty. Board
Item
REFDES AD9228LFCSP_REVA C101, C102, C107, C108, C109, C114, C115, C116, C121, C122, C123, C128, C201, C203, C204, C205, C206, C210, C211, C212, C213, C216, C217, C218, C219, C220, C221, C222, C223, C224, C310, C311, C312, C313, C314, C316, C319, C320, C321, C324, C325, C409, C410, C412, C414, C416, C417, C419, C422, C423, C424, C425, C427, C428, C429, C503, C505, C507, C509, C516, C517, C518, C519, C520, C521, C522, C523, C524, C525, C526, C527, C528, C529, C530, C531 C104, C111, C118, C125 C315, C326, C413, C426 C202 C309, C411 C317, C322, C415, C420 C318, C323, C418, C421 C501 C214, C512, C513, C514, C515, C532, C533, C534, C535 C305, C306, C307, C308, C405, C406, C407, C408 C502, C504, C506, C508 CR201 CR401, CR501 D502 D501
Device Capacitor
Pkg.
Value ceramic, X5R,
Mfg. Panasonic
Mfg. Part Number ECJ-0EB1A104K
Capacitor
Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor Capacitor
1206
ceramic, COG, 0.25 tol, ±10% ceramic, ceramic, X5R, 1000 ceramic, X7R, 0.018 ceramic, X7R, ceramic, NPO, tol, tantalum, ceramic, X5R, ceramic, X7R, ceramic, X5R, dual Schottky Green, candela
Murata
GRM1555C1H2R2GZ01B
Panasonic Kemet Kemet Rohm Panasonic
08056D106KAT2A ECJ-1VB0J225K C0402C102K3RACTU 0402YC183KAT2A C0402C220J5GACTU TCA1C106M8R ECJ-1VB0J105K
Capacitor
08055C104KAT2A
Capacitor Diode Diode Diode
SOT-23 DO-214AB DO-214AA
Panasonic Agilent Technologies Panasonic Micro Commercial Micro Commercial
ECJ-1VB0J106M HSMS2812 LNJ306G8TRA SK33MSCT
Rev. Page
AD9228
Item Qnty. Board REFDES F501 Device Fuse Pkg. 1210 Value tripcurrent resettable fuse test freq MHz, tol, header jumper, 2-pin header jumper, 3-pin header male, triple straight header, male, double straight bead core SMD, test freq MHz, tol, Mfg. Tyco/Raychem Mfg. Part Number NANOSMDC110F-2
FER501 FB101, FB102, FB103, FB104, FB105, FB106, FB107, FB108, FB109, FB110, FB111, FB112 JP301 J205, J402 J201 J204
Choke Coil Ferrite bead
2020
Murata Murata
DLW5BSN191SQ2L BLM18BA100SN1
Connector Connector Connector
2-pin 3-pin 12-pin
Samtec Samtec Samtec
TSW-102-07-G-S TSW-103-07-G-S TSW-104-08-G-T
J401
Connector
10-pin
Samtec
TSW-105-08-G-D
L501, L502, L503, L504, L505, L506, L507, L508 L309, L310, L409, L410
Ferrite bead
1210
Panasonic-ECG
EXC-CL3225U1
Inductor
Murata
LQG15HNR12J02B
L301, L302, L303, L304, L305, L306, L307, L308, L401, L402, L403, L404, L405, L406, L407, L408 OSC201 P101, P103, P105, P107, P201 P202
Resistor
Panasonic
ERJ-6GEY0R00V
Oscillator Connector
Connector
HEADER
P503 R201, R205, R214, R215, R221, R239, R312, R315, R318, R411, R414, R417, R425, R429, R430 R103, R117, R129, R142, R216, R217, R218, R223, R224, R237, R420, R426, R427, R428 R102, R115, R128, R141 R104, R116, R130, R143
Connector Resistor
0.1", PCMT
Clock oscillator, 65.00 MHz, Side-mount 0.063" board thickness 1469169-1, right angle 2-pair, header assembly RAPC722, power supply connector 1/16
REEVES Johnson Components Tyco
CB3LV-3C-65M0000-T 142-0711-821
1469169-1
Switchcraft Panasonic
SC1153 ERJ-2GEJ103X
Resistor
1/16
Panasonic
ERJ-2GE0R00X
Resistor Resistor
64.9 1/16 1/10
Panasonic Panasonic
ERJ-2RKF64R9X ERJ-3GEY0R00V
Rev. Page
AD9228
Item Qnty. Board REFDES R109, R111, R112, R123, R125, R126, R135, R138, R139, R148, R149, R150, R431, R432, R433 R108, R110, R121, R122, R134, R136, R146, R147 R161, R162, R163, R164 R202, R203, R204 R222 R213 R229 R230, R319 Device Resistor Pkg. Value 1/16 Mfg. Panasonic Mfg. Part Number ERJ-2RKF1001X
Resistor
1/16 1/16 1/16 4.02 1/16 49.9 1/16 0.5% 4.99 1/16 Cermet trimmer potentiometer, turn adjust, 10%, 1/16 1/16 1/16 1/16 1/16 1/20
Panasonic
ERJ-2GEJ330X
Resistor Resistor Resistor Resistor Resistor Potentiometer
3-lead
Panasonic Panasonic Panasonic Susumu Panasonic Components
ERJ-2RKF4990X ERJ-2RKF1003X ERJ-2RKF4021X RR0510R-49R9-D ERJ-2RKF4991X CT-94W-103
R228 R320 R307, R308, R309, R310, R407, R408, R409, R410 R305, R306, R405, R406 R316, R317, R415, R416 R245, R247, R249, R251, R253, R255, R257, R259, R261, R263, R265 R418 R419 R501 R240, R241 R242, R243 S401 T101, T102, T103, T104, T201 U501, U503
Resistor Resistor Resistor
Yageo America Susumu Panasonic
9C04021A4703JLHF3 RR0510P-393-D ERJ-2RKF1870X
Resistor Resistor Resistor
Panasonic Panasonic Panasonic
ERJ-2RKF3740X ERJ-2RKF2740X ERJ-1GE0R00C
Resistor Resistor Resistor Resistor Resistor Switch Transformer
CD542
SOT-223
4.75 1/16 1/16 1/16 1/16 1/16 LIGHT TOUCH, 100GE, ADT1-1WT, impedance ratio transformer ADP33339AKC-1.8, regulator
Panasonic Panasonic Panasonic Panasonic Panasonic Panasonic Mini-Circuits
ERJ-2RKF4751X ERJ-2RKF2610X ERJ-3EKF2610V ERJ-2RKF2430X ERJ-2RKF1000X EVQ-PLDA15 ADT1-1WT
ADP33339AKC-1.8
Rev. Page
AD9228
Item Qnty. Board REFDES U301, U401 Device Pkg. LFCSP, CP-32 Value AD8332ACP, ultralow noise precision dual ADP33339AKC-5 ADP33339AKC-3.3 AD9228-65, quad, 12-bit, MSPS serial LVDS ADR510AR, precision noise shunt voltage reference AD9515 NC7WZ07 NC7WZ16 Flash prog 1kx14, size speed, PIC12F controller series Mfg. Mfg. Part Number AD8332ACP
U504 U502 U201
SOT-223 SOT-223 LFCSP, CP-48-1
ADP33339AKC-5 ADP33339AKC-3.3 AD9228BCPZ-65
U203
SOT-23
ADR510AR
U202 U403 U404 U402
LFCSP CP-32-2 SC70, MAA06A SC70, MAA06A 8-SOIC
Fairchild Fairchild Microchip
AD9515BCPZ NC7WZ07P6X NC7WZ16P6X PIC12F629-I/SN
Rev. Page
AD9228 OUTLINE DIMENSIONS
7.00 0.60 0.60
0.30 0.23 0.18
INDICATOR
INDICATOR
VIEW
6.75
EXPOSED
(BOTTOM VIEW)
5.25 5.10 4.95
0.50 0.40 0.30
0.25 5.50
1.00 0.85 0.80
0.80 0.65 0.05 0.02 0.50
SEATING PLANE
0.20
COPLANARITY 0.08
COMPLIANT JEDEC STANDARDS MO-220-VKKD-2
Figure 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Body, Very Thin Quad (CP-48-1) Dimensions shown millimeters
ORDERING GUIDE
Model AD9228BCPZ-40 AD9228BCPZRL-401 AD9228BCPZ-651 AD9228BCPZRL-651 AD9228-65EB
Temperature Range -40°C +85°C -40°C +85°C -40°C +85°C -40°C +85°C
Package Description 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape Reel 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] 48-Lead Lead Frame Chip Scale Package [LFCSP_VQ] Tape Reel Evaluation Board
Package Option CP-48-1 CP-48-1 CP-48-1 CP-48-1
Pb-free part.
Rev. Page
AD9228 NOTES
©2006 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D05727-0-4/06(0)
Rev. Page

Four ADCs integrated into package power channel MSPS Nyquist) Excellen

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