High voltage drive within supply rails Output short-circuit protection

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High voltage drive within supply rails Output short-circuit protection

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10-Bit, 12-Channel Decimating DECDRIVER® with Level Shifters AD8385
High voltage drive within supply rails Output short-circuit protection High update rates Fast, Ms/s 10-bit input data update rate Static power dissipation: 1.84 Voltage controlled video reference (brightness), offset, full-scale (contrast) output levels reverses polarity video signal logic, analog supplies Level shifters panel timing signals High accuracy voltage outputs Laser trimming eliminates need adjustments calibration Flexible logic STSQ/XFR allow parallel AD8385 operation Fast settling into capacitive loads settling time 0.25% into load Slew rate V/µs Available 100-lead TQFP E-pad
DB(0:9) STSQ TSSDI SVRH SVRL SVRL DYIN DXIN DIRYIN DIRXIN NRGIN ENBX1I ENBX2I ENBX3I ENBX4I 12-BIT SHIFT REGISTER DUAL VAO1 VAO2
FUNCTIONAL BLOCK DIAGRAM
BIAS
SCALING CONTROL 2-STAGE LATCH SEQUENCE CONTROL CONTROL DACs
VID0 VID1 VID2 VID3 VID4 VID5 VID6 VID7 VID8 VID9 VID10 VID11
GENERAL DESCRIPTION
AD8385 provides fast, 10-bit, latched decimating digital input that drives high voltage outputs. 10-bit input words loaded into separate high speed, bipolar DACs sequentially. Flexible digital input format allows several AD8385s used parallel high resolution displays. output signal adjusted reference, signal inversion, contrast maximum flexibility. Integrated level shifters convert timing signals from timing controller high voltage panel timing inputs. Two, serial, 8-bit DACs integrated provide reference signals. 3-wire serial interface controls overload protection, output mode, serial DACs. AD8385 fabricated ADI's fast bipolar, XFHV process, which provides fast input logic, bipolar DACs with trimmed accuracy fast settling, high voltage, precision drive amplifiers same chip. AD8385 dissipates 1.84 nominal static power. AD8385 offered 100-lead, TQFP E-pad package operates over commercial temperature range 85°C.
DIRY DIRX ENBX1 ENBX2 ENBX3 ENBX4 CLXN CLYN
CLXIN CLYIN
MONITI MONITO
04514-0-001
AD8385
Figure
Rev.
Information furnished Analog Devices believed accurate reliable. However, responsibility assumed Analog Devices use, infringements patents other rights third parties that result from use. Specifications subject change without notice. license granted implication otherwise under patent patent rights Analog Devices. Trademarks registered trademarks property their respective owners.
Technology Way, P.O. 9106, Norwood, 02062-9106, U.S.A. Tel: 781.329.4700 www.analog.com Fax: 781.326.8703 2005 Analog Devices, Inc. rights reserved.
AD8385 TABLE CONTENTS
Specifications. DECDRIVER Section Level Shifters Level Shifting Edge Detector Serial Interface Power Supplies Operating Temperature Absolute Maximum Ratings. Caution. Overload Protection. Exposed Paddle. Maximum Power Dissipation Operating Temperature Range Configuration Function Descriptions. Block Diagrams Timing Diagrams DECDRIVER Section Level Shifters Level Shifting Edge Detector Serial Interface Functional Description Reference Control Input Output Operating Mode. Overload Protection. Serial DACs Theory Operation Transfer Function Analog Output Voltage Accuracy Applications. Optimized Reliability with Thermal Switch. Operation High Ambient Temperature Power Supply Sequencing VBIAS Generation-V1, Input Functionality Applications Circuit Design Optimized Thermal Performance Thermal Design Thermal Structure Design. AD8385 Design Recommendations Outline Dimensions Ordering Guide
REVISION HISTORY
1/05-Revision Initial Version
Rev. Page
AD8385 SPECIFICATIONS
DECDRIVER SECTION
25°C, AVCC 15.5 DVCC 0°C, 85°C, unless otherwise noted. Table
Parameter VIDEO PERFORMANCE1 VCME VIDEO OUTPUT DYNAMIC PERFORMANCE Data Switching Slew Rate Invert Switching Slew Rate Data Switching Settling Time Data Switching Settling Time 0.25% Invert Switching Settling Time Invert Switching Settling Time 0.25% Invert Switching Overshoot Data Feedthrough2 All-Hostile Crosstalk3 Amplitude Glitch Duration Transition Glitch Energy VIDEO OUTPUT CHARACTERISTICS Output Voltage Swing Output Voltage-Grounded Mode Data Switching Delay: Switching Delay: t105 Setup Time: Output Current Output Resistance REFERENCE INPUTS Range Range Input Current Input Current Range Range Range Input Resistance Bias Current Input Current RESOLUTION Coding Conditions TMIN TMAX Code Code TMIN TMAX step, -7.5 -3.5 0.25 0.25 0.25 (VRH VRL) -0.2 AVCC AVCC 2.75 AVCC AVCC fCLK +7.5 +3.5 Unit V/µs V/µs nV-s Bits
Code AVCC VOH, AGND VIDx VIDx fCLK
Binary
Rev. Page
AD8385
Parameter DIGITAL INPUT CHARACTERISTICS Max. Input Data Update Rate Data Setup Time: STSQ Setup Time: Setup Time: Data Hold Time: STSQ Hold Time: Hold Time: High Time: Time: Conditions Input 0.05 -0.6 1.65 Unit Ms/s
differential error voltage; VCME common-mode error voltage; full-scale output voltage (VRH VRL). Accuracy section. Measured outputs differentially DB(0:9) driven held low. Measured outputs differentially other four transitioning Measured both states INV. Measured from rising edge output change. Measurement made both states INV. Measured from rising edge that follows valid output change. Refer Figure definition.
LEVEL SHIFTERS
25°C, AVCC 15.5 DVCC 0°C, 85°C, unless otherwise noted. Table
Parameter LEVEL SHIFTER LOGIC INPUTS LEVEL SHIFTER OUTPUTS LEVEL SHIFTER DYNAMIC PERFORMANCE Output Rise, Fall Times-tr, CLX, CLXN, ENBX[1-4] CLY, CLYN DIRX, DIRY Propagation Delay Times-t11, t12, t13, CLX, CLXN, ENBX[1-4] CLY, CLYN DIRX, DIRY Output Skew ENBX[1-4]-t15, ENBX[1-4]-t16 CLX-t15, t16, t17, CLY, CLYN-t15, t16, t17, Conditions Unit
DGND
0.05 -0.6 1.65
DVCC AVCC 0.25 0.25
Rev. Page
18.5
AD8385
LEVEL SHIFTING EDGE DETECTOR
25°C, AVCC 15.5 DVCC 0°C, 85°C, unless otherwise noted. Table
Parameter Conditions Input Voltage Input High Voltage Input Rising Edge Threshold Voltage Input Falling Edge Threshold Voltage Output High Voltage Output Voltage Input Current High State Input Current State Input Rising Edge Propagation Delay Time Variation with Temperature Input Falling Edge Propagation Delay Time Variation with Temperature Output Rise Time Output Fall Time AGND AVCC AGND 0.75 AVCC Unit
-2.5
AGND AVCC DVCC 0.25 0.25 -1.2
SERIAL INTERFACE
AVCC 15.5 DVCC 0°C, 85°C, SVFS SVRL SVRH unless otherwise noted. Table
Parameter SERIAL REFERENCE INPUTS SVRH Range SVRL Range SVFS Range SVRH Input Current SVRL Input Current SVRH Input Resistance SERIAL ACCURACY Output Offset Error Scale Factor Error SERIAL LOGIC INPUTS Level Input Current HIGH High Level Input Current Input Threshold Voltage Input High Voltage Input Voltage SERIAL OUTPUTS Maximum Output Voltage Minimum Output Voltage VAO1-Grounded Mode IOUT CLOAD Range1 CLOAD High Range1 Conditions SVFS (SVRH SVRL) SVRL SVRH SVRL SVRH SVFS SVFS SVRL AGND -2.8 -2.5 AVCC SVRH Unit
SVFS SVFS
-1.0 -1.5 -2.0
+1.0 +1.5 +2.0 -0.6 0.05 1.65
Input
DGND SVRH SVRL
DVCC
0.002 0.047
Rev. Page
AD8385
Parameter SERIAL INTERFACE DYNAMIC PERFORMANCE Setup Time, SCL, High Level Pulse Width, SCL, Level Pulse Width, Setup Time, Hold Time, Hold Time, VAO1, VAO2 Settling Time, VAO1, VAO2 Settling Time, Conditions SVFS 0.5%, SVFS 0.5%, Unit
Outputs VAO1 VAO2 designed drive very high capacitive loads. proper operation these outputs, load capacitance must 0.002 0.047 Load capacitance range 0.002 0.047 causes output overshoot exceed
POWER SUPPLIES
25°C, AVCC 15.5 DVCC 0°C, 85°C, SVFS SVRL SVRH unless otherwise noted. Table
AD8385 Power Supplies DVCC, Operating Range DVCC, Quiescent Current AVCC Operating Range Total AVCC Quiescent Current Unit
OPERATING TEMPERATURE
25°C, AVCC 15.5 DVCC 0°C, 85°C, SVFS SVRL SVRH unless otherwise noted. Table
Parameter Ambient Temperature Range, Ambient Temperature Range, Unit
Operation high ambient temperature requires thermally-optimized layout (see Applications section), input data update rate exceeding MHz, blackto-white transition systems with limited airflow, maximum ambient operating temperature limited 75°C with overload protection enabled. operation above 75°C, Endnote addition requirements stated Endnote operation 85°C ambient temperature requires airflow overload protection disabled.
Rev. Page
AD8385 ABSOLUTE MAXIMUM RATINGS
Table
Parameter Supply Voltage AVCCx AGNDx DVCC DGND Input Voltage Maximum Digital Input Voltage Minimum Digital Input Voltage Maximum Analog Input Voltage Minimum Analog Input Voltage Internal Power Dissipation1 TQFP E-Pad Package 25°C Operating Temperature Range Storage Temperature Range Lead Temperature Range (Soldering, sec) Rating DVCC DGND AVCC AGND 5.00 85°C -65°C 125°C 300°C
Stresses above those listed under Absolute Maximum Ratings cause permanent damage device. This stress rating only; functional operation device these other conditions above those indicated operational section this specification implied. Exposure absolute maximum ratings extended periods reduce device reliability.
100-lead TQFP E-pad package: 20°C/W (still air), JEDEC STD, 4-layer still air.
CAUTION
(electrostatic discharge) sensitive device. Electrostatic charges high 4000 readily accumulate human body test equipment discharge without detection. Although this product features proprietary protection circuitry, permanent damage occur devices subjected high energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
Rev. Page
AD8385
OVERLOAD PROTECTION
AD8385 employs 2-stage overload protection circuit with enable/disable function that programmable through 3-wire serial interface. consists output current limiter thermal shut down. When enabled, maximum current output AD8385 average, internally limited event momentary short circuit between video output power supply rail (VCC AGND), output current limit sufficiently provide temporary protection. thermal shutdown debiases output amplifier when junction temperature reaches internally trip point. event extended short circuit between video output power supply rail, output amplifier current continues switch between typ, with period determined thermal time constant hysteresis thermal trip point. Thermal shutdown provides long-term protection limiting average junction temperature safe level. When disabled, overload protection present.
OPERATING TEMPERATURE RANGE
maximum operating junction temperature 150°C. junction temperature trip point overload protection 165°C. Production test guarantees minimum junction temperature trip point 125°C. Consequently, maximum guaranteed operating junction temperature 125°C with overload protection enabled, 150°C with overload protection disabled. ensure operation within specified operating temperature range, maximum power dissipation must limited:
PDMAX
JMAX
Airflow
MAXIMUM POWER DISSIPATION
STILL 100MHz 60Hz QUIESCENT
EXPOSED PADDLE
ensure optimal thermal performance, exposed paddle must electrically connected external plane such AVCC GND, described Applications Circuit section.
MAXIMUM POWER DISSIPATION
junction temperature limits maximum power that safely dissipated AD8385. maximum safe junction temperature plastic encapsulated devices, determined glass transition temperature plastic, approximately 150°C. Exceeding this limit cause temporary shift parametric performance change stresses exerted package. Exceeding junction temperature 175°C extended period result device failure.
*OVERLOAD PROTECTION ENABLED **OVERLOAD PROTECTION DISABLED
04514-0-002
**90
AMBIENT TEMPERATURE (°C)
AD8385 4-layer JEDEC with thermally optimized landing pattern, described Applications Circuit section.
Figure Maximum Power Dissipation Temperature
Note that quiescent power dissipation AD8385 1.84 when operating under conditions specified this data sheet. When driving 12-channel panel with input capacitance AD8385 dissipates total when displaying pixel wide alternating white black vertical lines generated standard input video. When frequency pixel clock raised MHz, total power dissipation increases 2.54 These specific power dissipations shown Figure reference.
Rev. Page
AD8385 CONFIGURATION FUNCTION DESCRIPTIONS
AGNDD AVCCD STSQ
DVCC DGND AGNDS AGNDS SVRL SVRL SVRH VAO1 VAO2 AVCCS DIRX DIRY CLYN DIRXIN DIRYIN DYIN CLYIN
AGND0 VID0 AVCC0,2 VID2 AGND2,4 VID4 AVCC4,6 VID6 AGND6,8 VID8 AVCC8,10 VID10 AGND10,1 VID1 AVCC1,3 VID3 AGND3,5 VID5 AVCC5,7 VID7 AGND7,9 VID9 AVCC9,11 VID11 AGND11
IDENTIFIER
AD8385
VIEW (Not Scale) 100L 14mm 14mm TQFP E-PAD
ENBX2I ENBX3I
ENBX1I
ENBX4I
ENBX1 ENBX2
ENBX3
AVCCL NRGIN
MONITO DXIN
ENBX4
CLXIN
CLXN
TSTA
DGND
AGNDL
MONITI
DGND
DVCC
CONNECT
Figure 100-Lead TQFP Package
Table Function Descriptions
Name DB(0:9) STSQ VID0-VID11 VRH, DVCC DGND AVCCx AGNDx SVRH, SVRL Function Data Input Clock Start Sequence Right/Left Select Data Transfer Analog Outputs Reference Voltages Full-Scale References Invert Digital Power Supply Digital Ground Analog Power Supplies Analog Ground Bypass Serial Reference Voltages Description 10-Bit Data Input. DB9. Clock Input. Data acquired both edges CLK. data loading sequence begins rising edge when this input high preceding rising edge CLK. data loading sequence begins left, with Channel when this input low; data loading sequence begins right, with Channel when this input high. Data transferred video outputs next rising edge when this input high rising edge CLK. These pins directly connected analog inputs panel. voltage applied between AGND sets white video level during low. voltage applied between AGND sets white video level during high. voltage applied between these pins sets full-scale video output voltage. When this input high, analog output voltages above When low, analog outputs voltages below Digital Power Supply. This normally connected digital ground plane. Analog Power Supplies. Analog Supply Returns. capacitor connected between this AGND ensures optimum settling time. Reference Voltages Output Amplifiers Serial DACs.
Rev. Page
04514-0-003
AD8385
Name Function Serial Interface Data Clock Serial Interface Data Input Serial Interface Enable Serial Voltage Output Test Mode Description Clock Serial Interface. While input low, 12-bit serial word loaded into serial interface rising edges SCL. first four bits select function; following eight bits data used serial DACs. falling edge this input initiates loading cycle. While this input held low, serial interface enabled data loaded every rising edge SCL. selected functions updated rising edge this input. While this input held high, serial interface disabled. These output voltages updated rising edge input. When this input low, overload protection output mode determined function programmed into serial interface. While this input held high, overload protection forced enabled output mode forced normal, regardless function programmed into serial interface. Connect this DGND. Logic Input Level Shifting Inverting Edge Detector. Output Level Shifting Inverting Edge Detector. Logic Input Inverting Level Shifters.
VAO1, VAO2 TS
TSTA MONITI MONITO DYIN, DIRYIN, DIRXIN, DXIN, NRGIN, ENBX(1-4)IN DIRX, DIRY, NRG, ENBX(1-4) CLXIN, CLYIN CLX, CLXN, CLY, CLYN,
Test Monitor Input Monitor Output Inverting Level Shifter Inputs
Inverting Level Shifter Outputs Complementary Level Shifter Inputs Complementary Level Shifter Outputs
While corresponding input voltage these level shifters below threshold voltage, output voltage these pins VOH. While corresponding input voltage these level shifters above threshold voltage, output voltage these pins VOL. Logic Input Complementary Level Shifters. While corresponding input voltage these level shifters below threshold voltage, voltage noninverting output pins voltage inverting outputs VOL. While corresponding input voltage these level shifters above threshold voltage, voltage noninverting output pins voltage inverting outputs VOH.
Rev. Page
AD8385 BLOCK DIAGRAMS TIMING DIAGRAMS
DECDRIVER SECTION
DB(0:9)
2-STAGE LATCH 2-STAGE LATCH 2-STAGE LATCH
VID0
AD8385
VID2
VID4
BIAS 2-STAGE LATCH VID6
STSQ
SEQUENCE CONTROL
2-STAGE LATCH 2-STAGE LATCH 2-STAGE LATCH 2-STAGE LATCH 2-STAGE LATCH 2-STAGE LATCH 2-STAGE LATCH 2-STAGE LATCH
VID8
VID10
VID1
VID3
VID5
VID7
VID9
VID11
CONTROL
04514-0-004
SCALING CONTROL
Figure Block Diagram
Rev. Page
AD8385
DB(0:9)
STSQ
Figure Input Timing
DB(0:9) STSQ V2+VFS VID(0:11)
PIXELS -12, -11, -10, PIXELS
V1-VFS
Figure Output Timing (R/L Low)
Table
Parameter Data Setup Time Data Hold Time STSQ Setup Time STSQ Hold Time Setup Time Hold Time High Time Time Data Switching Delay Invert Switching Delay Setup Time Conditions Input 0.5/fCLK Unit
5.5/fCLK
Rev. Page
04514-0-006
04514-0-005
AD8385
LEVEL SHIFTERS
DYIN DXIN DIRYIN DIRXIN NRGIN ENBX1I ENBX2I ENBX3I ENBX4I DIRY DIRX ENBX1 ENBX2 ENBX3 ENBX4
CLXN CLYN
04514-0-007
Figure Level Shifter-Complementary
Figure Level Shifter-Inverting
INPUTS
INVERTING OUTPUTS
NONINVERTING OUTPUTS
Figure Inverting Complementary Level Shifter Timing
Table Level Shifter Timing
Parameter Output Rise, Fall Times, CLX, CLXN, ENBX[1-4] CLY, CLYN DIRX, DIRY Propagation Delay Times-t11, t12, t13, CLX, CLXN, ENBX[1-4] CLY, CLYN DIRX, DIRY Propagation Delay Skew-t15, t16, t17, ENBX[1-4]-t15, ENBX[1-4]-t16 CLX-t15, t16, t17, CLY, CLYN-t15, t16, t17, Conditions 18.5 Unit
MAX,
04514-0-009
Rev. Page
04514-0-008
CLXIN CLYIN
AD8385
LEVEL SHIFTING EDGE DETECTOR
MONITI MONITO
04514-0-010
Figure Level Shifting Edge Detector Block Diagram
AVCC MONITI AGND
04514-0-011
MONITO
Figure Level Shifting Edge Detector Timing
Table Level Shifting Edge Detector, AVCC 15.5 DVCC 25°C, 85°C
Parameter Input Voltage Input High Voltage Input Rising Edge Threshold Voltage Input Falling Edge Threshold Voltage Output High Voltage Output Voltage Input Current High State Input Current State Input Rising Edge Propagation Delay Time Variation with Temperature Input Falling Edge Propagation Delay Time Variation with Temperature Output Rise Time Output Fall Time AGND AVCC AGND 0.75 AVCC Unit
-2.5
AGND AVCC DVCC 0.25 0.25 -1.2
Rev. Page
AD8385
SERIAL INTERFACE
SVRH SVRL SD(0:7) SD10 SD11
12-BIT SHIFT REGISTER
VAO1, VAO2 SVRL SDICODE (SVRH-SVRL)/256 DUAL SDAC
SELECT LOAD
CONTROL
ENABLE THERMAL SWITCH
VIDEO DACs
VID(0:11)
Figure Serial Interface Block Diagram
04514-0-013
VAO1, VAO2
VAO1, VAO2
Figure Serial Interface Timing
Table Serial Timing
Parameter Setup Time, SCL, High Level Pulse Width, SCL, Level Pulse Width, Setup Time, Hold Time, Hold Time, VAO1, VAO2 Settling Time, Conditions Unit
0.5%, 0.5%,
Rev. Page
04514-0-014
Figure Serial Interface Timing
04514-0-012
TS
AD8385 FUNCTIONAL DESCRIPTION
AD8385 system building block designed directly drive columns microdisplays type popularized projection systems. comprises channels precision, 10-bit digital-to-analog converters loaded from single, high speed, 10-bit wide input. Precision current feedback amplifiers, providing well-damped pulse response fast voltage settling into large capacitive loads, buffer outputs. Laser trimming wafer level ensures absolute output errors tight channel-to-channel matching. Tight part-topart matching high resolution systems guaranteed external voltage references. Three groups level shifters convert digital inputs high voltage outputs direct connection control inputs panels. edge detector conditions high voltage reference timing input from converts digital levels synchronizing timing controllers, such AD8389.
Control-Analog Output Inversion
analog voltage equivalent input code subtracted from VFS) while held high added VFS) while held low. Video inversion delayed cycles from input.
TSControl-Test Mode
this input allows serial interface control output operating mode thermal switch. high this input turns thermal switch releases video outputs VAO1 from grounded mode.
3-Wire Serial Interface-SDAC, Output, Thermal Switch Control
serial interface controls 8-bit serial DACs, thermal switch overload protection circuit, video output operating mode 12-bit-wide serial word from microprocessor. Four bits select function; remaining bits data serial DACs. Table Definitions
Name SD(0:7) SD10 SD11 Functionality 8-bit SDAC data. used Thermal switch control Output operating mode, SDAC selection, thermal switch control Output operating mode SDAC selection control
REFERENCE CONTROL INPUT
Start Sequence Control-Input Data Loading
valid STSQ control input initiates 6-clock loading cycle during which input data-words loaded sequentially into internal channels. Data loaded both rising falling edges CLK. loading sequence begins current rising edge only when STSQ held high preceding rising edge.
Right/Left Control-Input Data Loading
facilitate image mirroring, direction loading sequence control. loading sequence begins Channel proceeds Channel when control held low. begins Channel proceeds Channel when control held high.
Table Truth Table
Action Load VAO2. change VAO1. Load VAO1. Release video outputs from grounded mode. change VAO2. Release video outputs VAO1 from grounded mode. Disable thermal switch. change VAO1 VAO2. Release video outputs VAO1 from grounded mode. Enable thermal switch. change VAO1 VAO2. Video outputs VAO1 grounded output mode. Disable thermal switch. change VAO1, VAO2. Video outputs VAO1 grounded output mode. Enable thermal switch. change VAO1, VAO2. Start serial interface loading cycle. change outputs.
Control-Data Transfer Outputs
Data transfer outputs initiated control. Data transferred outputs simultaneously rising edge only when high during preceding rising edge.
Inputs-Voltage Reference Inputs
external analog voltage references levels outputs. sets output voltage Code 1023 while input low, sets output voltage Code 1023 while input held high.
VRH, Inputs-Full-Scale Video Reference Inputs
Twice difference between these analog input voltages sets full-scale output voltage (VRH-VRL).
Rev. Page
AD8385
Table Truth Table High. Thermal Switch Enabled. Grounded Output Disabled.
Don't Care.
Action Load VAO2. change VAO1. Load VAO1. change VAO2. change VAO1 VAO2 data. Start serial interface loading cycle. change outputs.
systems that operate high internal ambient temperatures require large capacitive loads driven AD8385 high frequencies, junction temperatures above 125°C required. such systems, thermal switch should either disabled minimum airflow maintained.
SERIAL DACS
Both serial DACs loaded serial interface. output voltage determined following equation: VAO1, VAO2 SVRL SD(0:7) (SVRH SVRL)/256 Output VAO1 designed drive very large capacitive loads, above 0.047 Lower capacitive loads result excessive overshoot VAO1.
OUTPUT OPERATING MODE
normal operating mode, voltage video outputs VAO1 determined inputs. grounded output mode, video outputs VAO1 forced (AGND typ.
Level Shifters
characteristics level shifters optimized based their intended use. Seven level shifters-DX, CLX, CLXN, ENBX[1:4]-are optimized direction three-DY, CLYN- optimized direction control signals. level shifter-NRG-is designed drive large capacitive load optimized direction control signal. level shifters-DIRX DIRY-are optimized very frequency control signals. level shifting edge detector-MONITI, MONITO-is optimized condition synchronizing feedback reference signal from LCD.
OVERLOAD PROTECTION
overload protection employs current limiters thermal switch protect video output pins against accidental shorts between video output AVCC AGND. junction temperature trip point thermal switch 165°C. Production test guarantees minimum junction temperature trip point 125°C. Consequently, operating junction temperature should allowed rise above 125°C with thermal switch enabled.
Rev. Page
AD8385 THEORY OPERATION
TRANSFER FUNCTION ANALOG OUTPUT VOLTAGE
DECDRIVER regions operation where video output voltages either above reference voltage below reference voltage transfer function defines video output voltage function digital input code: VIDx(n) n/1023), high VIDx(n) n/1023), where: input code (VRH VRL) number internal limits define usable range video output voltages, VIDx. Figure
ACCURACY
best correlate transfer function errors image artifacts, overall accuracy DECDRIVER defined parameters, VCME. VDE, differential error voltage, measures difference between value output value ideal. defining expression [VOUTN(n) [VOUTP(n) VDE(n) 1023 VCME, common-mode error voltage, measures bias output. defining expression
VCME(n) (VOUTN(n) +VOUTP(n))
AVCC 1.3V
HIGH VOUTN(n) (AVCC VOUTP(n) 5.5V (AVCC 1.3V AGND INPUT CODE 1023
INTERNAL LIMITS USABLE VOLTAGE RANGES
5.5V
AVCC
04514-0-015
VIDx
Figure Transfer Function Usable Voltage Ranges
Rev. Page
AD8385 APPLICATIONS
AD8385
DB(0:9) VID(0:11) 12-CHANNEL CHANNEL
STSQ, XFR, CLK, R/L,
IMAGE PROCESSOR
DIRXIN, DIRYIN, DYIN, CLYIN, NRGIN
DIRX, DIRY, CLY, CLYN,
TIMING CONTROLS
AD8389
DXI, CLXI, ENBX(1-4)I DXxO, CLXxO, ENBX(1-4)xO MONITxI DXIN, CLXIN, ENBXIN (1-4) MONITO CLX, CLXN, ENBX (1-4) MONITI VAO1 VAO2 TIMING CONTROLS
MONITOR VCOM
VRH, VRL, SVRH, SVRL
REFERENCE VOLTAGES
Figure Typical Applications Circuit
OPTIMIZED RELIABILITY WITH THERMAL SWITCH
While internal current limiters provide short-term protection against temporary shorts outputs, thermal switch must enabled protect against persistent shorts lasting several seconds.
OPTION OPTION
DVCC
DVCC
AD8385
SERVICE JUMPER TSPIN7
04514-0-016
Initial Power-Up After Assembly Repair Using Service Jumper
optimize reliability with thermal switch, following sequence operations recommended: Ensure that TSpin high initial power-up inserting service jumper. Figure Execute initial power-up. Identify shorts outputs. Power down, repair shorts, repeat initial power-up sequence until proper system functionality verified. Remove service jumper. Resume normal operation.
SERVICE JUMPER
AD8385
TSPIN7
DGND
Figure Service Jumper Location
Initial Power-Up after Assembly Repair Using Serial Interface
Immediately after power-up, send Code 011XXXXXXXXX through serial interface enable thermal switch disable grounded output mode. Identify shorts outputs. Power down, repair shorts, repeat initial power-up sequence until proper system functionality verified. Resume normal operation.
Rev. Page
04514-0-017
AD8385
Power-Up During Normal Operation
serial interface power-on reset. Code 010XXXXXXXXX, sent immediately following power-up places, outputs into normal operating mode disables thermal switch.
Internal Bias Voltage Generation
Standard systems that internally generate bias voltage reserve uppermost code range bias voltage, remaining code range encode video gamma correction. high degree symmetry guaranteed AD8385 these systems. inputs these systems tied together normally connected VCOM, shown Figure
OPERATION HIGH AMBIENT TEMPERATURE
extend maximum operating junction temperature AD8385 150°C, keep thermal switch disabled during normal operation. Code format X10XXXXXXXXX ensures disabled thermal switch.
POWER SUPPLY SEQUENCING
indicated Absolute Maximum Ratings, voltage input cannot exceed supply voltage more than ensure compliance with Absolute Maximum Ratings, following power-up power-down sequencing recommended. During power-up, initial application nonzero voltages input pins must delayed until supply voltage ramps highest operational input voltage. During power-down, voltage input must reach zero during period exceeding hold-up time power supply. Failure comply with Absolute Maximum Ratings, result functional failure damage internal diodes. Damaged diodes cause temporary parametric failures, which result image artifacts. Damaged diodes cannot provide full protection, reducing reliability. Table
Power-On Apply power supplies. Apply power other I/Os. Power-Off Remove power from I/Os. Remove power from supplies.
AD8385
VCOM VCOM
VBIAS VBIAS 1023
Figure Connection Transfer Function Typical Standard System
External Bias Voltage Generation
systems that require improved brightness resolution higher accuracy, inputs, connected external voltage references, provide necessary bias voltage (VBIAS) while allowing full code range used gamma correction. ensure symmetrical voltage AD8385's outputs, VBIAS must remain constant both states INV. Therefore, defined VCOM VBIAS VCOM VBIAS
VBIAS GENERATION-V1, INPUT FUNCTIONALITY
avoid image flicker, symmetrical voltage required bias voltage approximately minimum must maintained across pixels HTPS LCDs. AD8385 provides internal external method maintaining this bias voltage.
Rev. Page
04514-0-018
RESERVED CODE RANGE
AD8385
APPLICATIONS CIRCUIT
following circuit ensures VBIAS symmetry within with minimum component count. Bypass capacitors shown clarity.
AVCC 15.5V
DESIGN OPTIMIZED THERMAL PERFORMANCE
total maximum power dissipation AD8385 partly load-dependent. 12-channel system running pixel rate, total maximum power dissipation channel input capacitance pixel rate, total maximum power dissipation exceed limit operating junction temperature below guaranteed maximum, package, conjunction with PCB, must effectively conduct heat away from junction. AD8385 package designed provide enhanced thermal characteristics through exposed paddle bottom surface package. take full advantage this feature, exposed paddle must direct thermal contact with PCB, which then serves heat sink. thermally effective must incorporate thermal pads thermal structure. thermal layer provides solderable contact surface surface PCB. thermal bottom layer provides surface direct contact with ambient. thermal structure provides thermal path inner bottom layers remove heat.
5.1V
VCOM
AD8385
AD8132
04514-0-019
DVCC 3.3V
Figure External VBIAS Generator with AD8132
VCOM
04514-0-020
VBIAS VBIAS 1023
THERMAL DESIGN
minimize thermal performance degradation production PCBs, contact area between thermal should maximized. Therefore, size thermal layer should match exposed paddle size. second thermal least same size should placed bottom side PCB. least thermal should direct thermal contact with plane such AVCC GND.
Figure AD8385 Transfer Function Typical High Accuracy System
8.75 7.50 6.25 5.00
THERMAL STRUCTURE DESIGN
85°C 25°C
V1)/2 VCOM (mV)
3.75 2.50 1.25 0.00 -1.25 -2.50 -3.75 -5.00 -6.25 -7.50 10.2 10.7
04514-0-021
Effective heat transfer from inner bottom layers requires thermal vias incorporated into thermal design. Thermal performance increases logarithmically with number vias. Near optimal thermal performance production PCBs attained only when tightly spaced thermal vias placed full extent thermal pad.
-8.75 (V+) (V-)
Figure Typical Asymmetry Outputs AD8132 Power Supply Application Circuit
Figure shows that AD8132 (Figure typically produces symmetrical output 85°C when supply, (V+) (V-),
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AD8385
AD8385 DESIGN RECOMMENDATIONS
Layer
size: 0.25 0.25
pitch:
Thermal size: Thermal structure: 0.25 diameter vias grid
Bottom Layer
recommended that bottom thermal thermally connected plane. connection should direct such that thermal becomes part plane.
Figure Land Pattern-Top Layer
04514-0-022
thermal spokes recommended when connecting thermal pads structure AVCC plane.
Solder Masking
minimize formation solder voids solder flowing into holes (solder wicking), diameter should small. Optional solder masking holes layer plugs holes, inhibiting solder flow into holes. optimize thermal coverage, solder mask diameter should more than larger than hole diameter.
Solder Mask-Top Layer
04514-0-023
Pads: customer's design rules Thermal vias: 0.25 diameter circular mask, centered vias.
Figure Land Pattern-Bottom Layer
Solder Mask-Bottom Layer
customer's design rules.
Figure Solder Mask-Top Layer
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04514-0-024
AD8385 OUTLINE DIMENSIONS
Figure 100-Lead, Thermally Enhanced Thin Quad Flat Package (with Exposed Heat Sink) [TQFP_EP] (SV-100-3) Dimensions shown millimeters
ORDERING GUIDE
Model AD8385ASVZ1 Temperature Range 85°C Package Description 100-Lead TQFP_EP Package Option SV-100-3
Pb-free part.
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AD8385 NOTES
2005 Analog Devices, Inc. rights reserved. Trademarks registered trademarks property their respective owners. D04514-0-1/05(0)
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High voltage drive within supply rails Output short-circuit protection

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