8-bit 120MSPS Flash Converter Description CXA3256R 8-bit high-spe

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8-bit 120MSPS Flash Converter Description CXA3256R 8-bit high-spe

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CXA3256R
8-bit 120MSPS Flash Converter
Description CXA3256R 8-bit high-speed flash converter capable digitizing analog signals maximum rate 120MSPS. ECL, PECL selected digital input level accordance with application. digital output level allows demultiplexed output. CXA3256R easier used adding functions CXA3246Q adopting ultra-small package. Features Differential linearity error: ±0.5LSB less Integral linearity error: ±0.5LSB less High-speed operation with maximum conversion rate 120MSPS input capacitance: 10pF Wide analog input bandwidth: 200MHz power consumption: 450mW Power saving function Output voltage control function demultiplexed output frequency-divided clock output (with reset function) Compatible with ECL, PECL digital input levels Single power supply operation available Ultra-small surface mounting package (48-pin LQFP)
DGND3 AGND VRM3 AVCC VRM2
LQFP (Plastic)
LEAD TREATMENT: PALLADIUM PLATING
Structure Bipolar silicon monolithic Applications Magnetic recording (PRML) Communications (QPSK, QAM) LCDs Digital oscilloscopes
AVCC
VRM1
CLK/E CLKN/E CLK/T SELECT2 VOCLP DVCC2 DGND2 PAD0 PAD1 PAD2 PAD3
Configuration (Top View)
DVEE3
RESETN/E RESET/E RESETN/T SELECT1 CLKOUT DVCC2 DGND2 PBD7 PBD6 PBD5 PBD4
DGND2
PBD1
AGND
PAD7
PAD5
DVCC1
PBD0
PAD4
PAD6
DGND1
Sony reserves right change products specifications without prior notice. This information does convey license implication otherwise under patents other right. Application circuits shown, any, typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits.
DVCC2
PBD2
PBD3
PE98305-PS
CXA3256R
Absolute Maximum Ratings 25°C) Unit AVCC, DVCC1, DVCC2 -0.5 +7.0 DGND3 -0.5 +7.0 DVEE3 -7.0 +0.5 DGND3 DVEE3 -0.5 +7.0 AVCC Analog input voltage Reference input voltage AVCC AVCC |VRT VRB| Digital input voltage ECL/PECL input DVEE3 DGND3 input DGND1 DVCC1 SELECT2 DGND1 DVCC1 VOCLP DGND1 DVCC1 VID1 (|/E N/E|) Storage temperature Tstg +150 Allowable power dissipation (when mounted two-layer glass fabric base epoxy board with dimentions 50mm 50mm, 1.6mm thick) Supply voltage Recommended Operating Conditions With single power supply With dual power supply Unit Min. Typ. Max. Min. Typ. Max. Supply voltage DVCC1, DVCC2, AVCC +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 DGND1, DGND2, AGND -0.05 +0.05 -0.05 +0.05 DGND3 +4.75 +5.0 +5.25 -0.05 +0.05 -0.05 +0.05 -5.5 -5.0 -4.75 DVEE3 Analog input voltage Reference input voltage +2.9 +4.1 +2.9 +4.1 +1.4 +2.6 +1.4 +2.6 |VRT VRB| Digital input voltage ECL/PECL input DVEE3 DGND3 DVEE3 DGND3 DVEE3 DVEE3 input SELECT2 DVCC1 DVCC1 DGND1 DGND1 VOCLP DGND1 DVCC1 DGND1 DVCC1 VID1 (|/E N/E|) Maximum conversion rate (Straight mode) MSPS (DMUX mode) MSPS Ambient temperature
VID: Input Voltage Differential PECL switching level
DGND3 (max.) (DGND3 1.3V) (min.)
CXA3256R
Description [Symbol] DVEE3 AGND VRM1 AVCC VRM2 AVCC VRM3 AGND DGND3 CLK/E CLKN/E CLK/T SELECT2 VOCLP DVCC2 DGND2 PAD0 PAD7 DGND1 DVCC1 DVCC2 DGND2 PBD0 PBD7 DGND2 DVCC2 CLKOUT SELECT1 RESETN/T RESET/E RESETN/E [Pin No.] [Description] Digital power supply Bottom reference voltage Analog ground Reference voltage point Analog power supply Typical voltage level with single power supply Typical voltage level with dual power supply
-5.0V 2.6V 2.6V Analog signal input Reference voltage point Analog power supply Reference voltage point Analog ground Reference voltage (typ.) 4.1V 4.1V Digital power supply ECL/PECL clock input PECL ECL/PECL clock input PECL clock input Data output switching DGND1 Open DVcc1 DGND1 Open DVcc1 high level clamp Clamp voltage Clamp voltage Power saving Digital power supply Digital ground side data output Digital ground Digital power supply Digital power supply Digital ground side data output Digital ground Digital power supply Clock output Data output polarity inversion Output mode selection reset input ECL/PECL reset input PECL ECL/PECL reset input PECL
CXA3256R
Block Diagram
AVCC
DVCC1
DVCC2
DGND3
(MSB) PBD7 PBD6
VRM3
6bit
PBD5
LATCH
TTLOUT
8bit
PBD4 PBD3 PBD2
6bit
PBD1
6bit LATCH ENCODER
VRM2
ENCODER
PBD0 (LSB)
(MSB) PAD7 PAD6 PAD5
VRM1
6bit
LATCH
LATCH
TTLOUT
PAD4 PAD3 PAD2 PAD1
8bit 6bit
CLK/T CLK/E CLKN/E
PAD0 (LSB) SELECT2 VOCLP Select CLKOUT
RESETN/T RESETN/E RESET/E AGND
SELECT1
DGND1
DGND2
DVEE3
CXA3256R
Description Equivalent Circuit Symbol AGND Standard voltage level (typ.) (typ.) (typ.) (With single power supply) (With dual power supply) (With single power supply) (typ.) (With dual power supply)
DVCC1
Equivalent circuit
Description Analog ground. Separated from digital ground. Analog power supply. Separated from digital power supply. Digital ground. Digital power supply.
AVCC
DGND1 DGND2 DVCC1 DVCC2
DGND3
Digital power supply. Ground input. PECL inputs.
DVEE3
Digital power supply. input. Ground PECL inputs.
SELECT2
DVCC1 Open DGND1
DGND1
Data output switching. Data output from both side side setting this open. When DVcc1 level, only side output port outputs data, makes side high impedance. When DGND1 level, only side output port outputs data, makes side high impedance.
DVCC2
VOCLP
Clamp voltage
output high level clamp. high level voltage clamped approximately same value voltage applied this pin.
DGND2
CXA3256R
Symbol
Standard voltage level
Equivalent circuit
DVCC1
Description
Power saving. Power saving activated when level. Pull high level normal operation because this becomes open.
DGND1
CLK/E
Clock input. CLK/E complementary input. When left open, this goes threshold voltage. Only CLK/E used operation, complementary inputs recommended attain fast stable operation. Reset signal input. When level, built-in frequency divider circuit reset. RESETN/E complementary input. When left open, this goes threshold voltage. Only RESETN/E used operation. Clock input. Reset signal input. When left open, this goes high level. When level, built-in frequency divider circuit reset. Data output polarity inversion input. When left open, this input goes high level. (See Table Correspondence Table.) Data output mode selection. (See Table Operation Mode Table.)
CLKN/E
DGND3
ECL/ PECL RESETN/E
DVEE3
RESET/E
CLK/T
DVCC1
RESETN/T
DGND1 DVEE3
1.5V
SELECT1
CXA3256R
Symbol
Standard voltage level 4.0V (typ.)
Equivalent circuit
Description reference voltage. By-pass AGND with tantal capacitor 0.1µF chip capacitor. Reference voltage point. By-pass AGND with 0.1µF chip capacitor. Reference voltage point. By-pass AGND with 0.1µF chip capacitor. Reference voltage point. By-pass AGND with 0.1µF chip capacitor. Bottom reference voltage. By-pass AGND with tantal capacitor 0.1µF chip capacitor.
VRM3
(VRT VRB)
Comparator
Comparator Comparator
VRM2
(VRT VRB)
Comparator Comparator
VRM1
(VRT VRB)
Comparator Comparator
Comparator
2.0V (typ.)
AVCC
Comparator AVCC
Analog input.
Vref
DVEE3
AGND
PAD0 PAD7 PBD0 PBD7
DVCC1 DVCC2
Port side data output.
100k
DGND2 DVEE3
Port side data output.
DGND1
CLKOUT
Clock output. (See Table Operation Mode Table.)
CXA3256R
Electrical Characteristics (DVCC1, AVCC, DGND3 +5V, DGND1, AGND, DVEE3 25°C) Item Resolution characteristics Integral linearity error Differential linearity error Analog input Analog input capacitance Analog input resistance Analog input current Reference input Reference resistance Reference current Offset voltage side side Digital input (ECL, PECL) Digital input voltage: High Threshold voltage Digital input current High Digital input capacitance Digital input (TTL) Digital input voltage: High Threshold voltage Digital input current High Digital input capacitance Digital output (TTL) Digital output voltage High Switching characteristics Maximum conversion rate Aperture jitter Sampling delay Clock high pulse width Clock pulse width Reset signal setup time Reset signal hold time Clock output delay Data output delay Output rise time Output fall time Rref3 Iref4 Symbol Conditions Min. Typ. ±0.5 ±0.5 DVEE3 DVEE3 DGND DGND3 0.8V DGND3 1.6V DGND3 Max. Unit bits MSPS
2Vp-p, 5MSPS
+3.0V 0.07Vrms
3.5V 0.2V
Tpw1 Tpw0 T_rs T_rh Td_clk Tdo1 Tdo2
-2mA DMUX mode
RESETN RESETN DMUX mode 2.0V 2.0V 5pF) 5pF) 5pF) 5pF) 5pF)
These characteristics PECL input unless otherwise specified.
CXA3256R
Item Dynamic characteristics Input bandwidth ratio
Symbol
Conditions 2Vp-p, -3dB 120MSPS, 1kHz DMUX mode 120MSPS, 29.999MHz DMUX mode 120MSPS, 1kHz DMUX mode Error 16LSB 120MSPS, 29.999MHz DMUX mode Error 16LSB 100MSPS, 24.999MHz Straight mode Error 16LSB
Min.
Typ.
Max.
Unit
TPS6
Error rate
10-12
10-9
10-9
Power supply Supply current Supply current Supply current Power consumption Power consumption
Power saving Power saving
0.07 0.35
Rref: Resistance value between Iref Rref TPS: Times Sample (ICC IEE) (VRT VRB) Rref
Step
VRM2
Table Correspondence Table
CXA3256R
Electrical Characteristics Measurement Circuit Current Consumption Measurement Circuit
AVCC DVCC1 DVCC2 DGND3
Sampling Delay Measurement Circuit Aperture Jitter Measurement Circuit
100MHz OSC1 Variable CXA3256R Logic Analizer 1024 samples Buffer
1.95V
CLK/E
5MHz PECL OSC2
DGND2 DGND1 AGND
DVEE3
100MHz
Integral Linearity Error Measurement Circuit Differential Linearity Error Measurement Circuit
Aperture Jitter Measurement Method
VRM2 when when
Comparator CXA3256R Controller Buffer
(LSB)
Sampling timing fluctuation aperture jitter)
Where (LSB) deviation output codes when largest slew rate point sampled clock which exactly same frequency analog input signal, aperture jitter Comparator Pulse Counter
Error Rate Measurement Circuit
Signal Source CXA3256R Latch
-1kHz 2Vp-p Sine Wave
Latch
16LSB Signal Source
CXA3256R
Description Operation Modes CXA3256R types operation modes which selected with (SELECT). Operation mode DMUX mode Straight mode SELECT1 Maximum conversion rate 120MSPS 100MSPS Data output Demultiplexed output 60Mbps Straight output 100Mbps Clock output input clock frequency divided output. 60MHz input clock inverted output. 100MHz
Table Operation Mode Table
DMUX mode (See Application Circuit 1-(1), (3).) SELECT1 this mode. this mode, clock frequency divided data output after being demultiplexed this frequency-divided clock. frequency-divided clock, which adequate setup time hold time output data, output from clock output pin. When using multiple CXA3256R DMUX mode, start timing frequency-divided clocks becomes phase, producing operation such that shown example next page. countermeasure, CXA3256R function that resets frequency-divided clocks. When resetting this frequency-divided clock, level reset signal should input RESETN (Pin 48). reset signal requires setup time (T_rs 2.5ns) hold time (T_rh 1.0ns) clock rising edge because synchronized with taken clock. Therefore, reset signal T_rs (min.) T_rh (min.) 3.5ns longer clock rising edge. reset period extended making level period reset signal longer because clock output fixed (reset) during level period clock rising edge. reset start timing regarded important, timing where reset signal from high consequence. However, when reset released timing where reset signal from high must become significant because timing used commence frequency-divided clock. this case, setup time (T_rs) also necessary. timing chart detail. (This chart shows example reset 2T.) converter operate (min.) 120MSPS this mode.
CXA3256R
When reset signal used
CXA3256R
CLKOUT 8bit DATA
RESETN
CXA3256R
CLKOUT 8bit DATA
RESETN
When reset signal used
Reset signal CXA3256R
RESETN
CLKOUT 8bit DATA
(Reset period)
CXA3256R
CLKOUT 8bit DATA
(Reset period)
Reset signal
RESETN
Straight mode (See Application Circuits 1-(4), (6).) SELECT1 this mode. this mode, data output obtained accordance with clock frequency applied converter applications which clock applied converter system clock. converter operate (min.) 100MSPS this mode. Digital input level supply voltage settings logic input level CXA3256R supports ECL, PECL levels. power supplies (DVEE3, DGND3) logic input block must match logic input (CLK reset signals) level. Digital input level PECL DVEE3 DGND3 Supply voltage Application circuits
Table Logic Input Level Power Supply Settings Description SELECT2 CXA3256R systems data output. SELECT2 used select port where data output. SELECT2 Open Vcc1 GND1 Data output Output possible both Output possible output high impedance. Output possible output high impedance.
CXA3256R
Application Circuit DMUX input
RESET signal
+5V(D)
+5V(A) -5V(D)
PAD0 PAD7 Digital Data Latch PBD0 PBD7 Digital Data Latch
Digital Data
+5V(D)
+5V(A)
Digital Data
ECL-CLK +5V(D)
DMUX PECL input
PECL RESET signal
+5V(D)
+5V(A)
PBD0 PBD7 Digital Data Latch
Digital Data
+5V(D)
+5V(D)
+5V(A)
Digital Data PAD0 PAD7 Digital Data Latch
PECL-CLK +5V(D)
DMUX input
+5V(D) RESET signal
PBD0 PBD7 Digital Data Latch
Digital Data
+5V(A)
+5V(D)
+5V(D) +5V(A)
Digital Data PAD0 PAD7 Digital Data Latch
TTL-CLK +5V(D)
CXA3256R
Straight input
+5V(D)
-5V(D)
PBD0 PBD7 Digital Data Latch
Digital Data
+5V(A)
+5V(D)
+5V(A)
ECL-CLK +5V(D)
Straight PECL input
+5V(D)
+5V(A)
PBD0 PBD7 Digital Data Latch
Digital Data
+5V(D)
+5V(D)
+5V(A)
PECL-CLK PECL +5V(D)
Straight input
+5V(D)
+5V(A)
PBD0 PBD7 Digital Data
Digital Data Latch
+5V(D)
+5V(D)
+5V(A)
TTL-CLK
+5V(D)
CXA3256R
Application Circuit
Straight Mode (When single power supply used)
Analog input
short short 10µF
10µF
DGND3
AGND
CLK/E
RESETN/E RESET/E RESETN/T SELECT1 CLKOUT DVCC2 DGND2 PBD7 PBD6 PBD5
CLKN/E CLK/T SELECT2 VOCLP Clamp voltage DVCC2 DGND2 PAD0 PAD1 PAD2
DGND1
DGND2
DVCC1
DVCC2
PAD3
DVEE3
PBD4
AGND
VRM3
AVCC
VRM2
AVCC
VRM1
PBD0
PBD1
PAD4
PAD5
PAD6
PAD7
PAD5
PBD2
PBD3
PAD2 PAD3
PBD1
PBD2
(MSB) PAD7
PAD6
PBD3
PBD4 PBD5
Short analog system digital system point immediately under converter. Notes Operation. chip capacitor 0.1µF.
Application circuits shown typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits infringement third party patent other right same.
PBD6 (MSB) PBD7
(LSB) PAD0 PAD1
(LSB) PBD0
PAD4
CXA3256R
DMUX Mode Timing Chart (Select VCC)
Tpw1 Tpw0 Tdo2; 5.0ns (typ.) 1.5ns (typ.)
PAD0
2.0V 0.8V
PBD0 Td_clk; 4.5ns (typ.)
Tdo1 1.0ns (typ.)
2.0V 0.8V
(Reset period)
2.0V 0.8V
2.0V 0.8V
2.0V 0.8V
T_rh
T_rs
T_rh
T_rs
RESETN
CXA3256R
Straight Mode Timing Chart (Select GND)
1.5ns (typ.)
Tpw1 Tpw0
Tdo2; 5.0ns (typ.)
PAD0
2.0V 0.8V
PBD0
2.0V 0.8V
Td_clk; 4.5ns (typ.)
(CLK inverted output.)
2.0V 0.8V
RESETN
CXA3256R
Timing Converter Peripheral Circuit maximum clock rate DEMUX mode, timing channels converter same phase described detail below. example, from converter used data latch clock. current clock delay data output delay follows. Td_clk (min.) (max.) Tdo2 (min.) (max.) These values considered temperature change supply voltage variation. maximum clock rate 120MSPS, setup time (ts) seemed very small from above specifications. when channels converter used same circuit board, DATA delay delay changed same trend same condition temperature change supply voltage variation. 0.5ns delay faster when high temperature increased supply voltage used. Also, 0.5ns delay later when temperature decreased supply voltage used. These delay omitted this case. When 25°C, +5V, clock delay data output delay follows. Td_clk (min.) (max.) Tdo2 (min.) (max.) timing DATA with above delay variation shown below. Consequently, setup time data latching obtained (min.) output delay change DATA temperature change supply voltage variation same trend delay change, that (min.) guaranteed temperature change supply voltage variation.
Analog input CXA3256R PAD/out PBD/out RESET CXA3256R PAD/out PBD/out RESET CXA3256R PAD/out PBD/out RESET 1/120MSPS) 8bit 8bit Gate Array Latch
Analog input
8bit 8bit
Analog input RESET
8bit 8bit
th-reset RESET signal
Td_clk (min.) Td_clk (max.) Tdo2 (min.) Tdo2 (min.) (min.) (min.)
PAD/out PBD/out
Note: timing chart, values brackets includes temperature change power supply variation.
CXA3256R
Notes Operation CXA3256R PECL input pins clock reset input pins. When clock input PECL level, inputting reset signal PECL level recommended. Also, when clock input level, inputting reset signal recommended. impedance input signal should properly matched ensure CXA3256R's stable operation high speed. CXA3256R, input pins excluding become high level when left open. becomes level when left open. high level activate power supply grounding have profound influence converter performance. power supply grounding method particularly important during high-speed operation. General points caution follows. ground pattern should large possible. recommended make power supply ground patterns wider inner layer using multi-layer board. prevent interference between AGND DGND between AVcc DVcc, make sure respective patterns separated. prevent offset power supply pattern, connect AVcc DVcc lines point each ferrite-bead filter, etc. Shorting AGND DGND patterns place immediately under converter improves converter performance. Ground power supply pins (AVcc, DVcc1, DVcc2, DVEE3) close each possible with 0.1µF larger ceramic chip capacitor. (Connect AVcc AGND pattern DVcc1, DVcc2 DVEE3 pins DGND pattern.) digital output wiring should short possible. digital output wiring long, wiring capacitance will increase, deteriorating output slew rate resulting reflection output waveform since original output slew rate quite fast. analog input input capacitance approximately 10pF. drive converter with proper frequency response, necessary prevent performance deterioration parasitic capacitance parasitic inductance using large capacity drive circuit, keeping wiring short possible, using chip parts resistors capacitors, etc. pins must have adequate by-pass protect them from high-frequency noise. By-pass them AGND with approximately tantal capacitor 0.1µF chip capacitor short possible. CLKN/E used, by-pass this DGND with approximately 0.1µF capacitor. this time, approximately DGND3 1.3V voltage generated. However, this recommended threshold voltage because weak. When digital input level PECL level, pins should used pins left open. When digital input level TTL, pins should used pins left open. CXA3026Q output pins However, CXA3256R, these symbols changed follows: (Only symbols changed) pipeline delay CXA3256R smaller clock, compared that CXA3026Q.
CXA3256R
Example Representative Characteristics
Current consumption Ambient temperature characteristics
Current consumption Conversion rate characteristics
Current consumption [mA]
Current consumption [mA]
fCLK 1kHz
DMUX mode
Ambient temperature [°C]
Conversion rate [MSPS]
Analog input current Analog input voltage characteristics
Reference current Ambient temperature characteristics
Analog input current [µA]
Reference current [mA]
Ambient temperature [°C] Analog input voltage
CXA3256R
Input frequency response
Error rate Conversion rate characteristics
10-6 fCLK 1kHz
10-7
Error Rate [TPS]
Error 16LSB 10-8
[dB]
120MSPS
10-9
10-10 Conversion rate [MSPS]
Input frequency [MHz]
Maximum conversion rate Ambient temperature characteristics
Maximum conversion rate [MSPS]
fCLK 1kHz Error 16LSB Error rate: 10-9
Ambient temperature [°C]
CXA3256R
Package Outline
Unit:
48PIN LQFP (PLASTIC)
(8.0)
0.08 0.18 0.03
(0.22)
0.05 0.127 0.02 0.13
NOTE: Dimension does include mold protrusion.
DETAIL
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g
NOTE PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).

8-bit 120MSPS Flash Converter Description CXA3256R 8-bit high-spe

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