8-bit 120MSPS Flash Converter Description CXA3246Q 8-bit high-spe
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CXA3246Q
8-bit 120MSPS Flash Converter
Description CXA3246Q 8-bit high-speed flash converter capable digitizing analog signals maximum rate 120MSPS. ECL, PECL selected digital input level accordance with application. digital output level allows demultiplexed output. This pin-compatible with CXA3026Q, replace conventional models easily.
(Plastic)
LEAD TREATMENT: PALLADIUM PLATING
DGND3
Structure Features Bipolar silicon monolithic Differential linearity error: ±0.5LSB less Integral linearity error: ±0.5LSB less Applications High-speed operation with maximum conversion Magnetic recording (PRML) rate 120MSPS Communications (QPSK, QAM) input capacitance: 10pF LCDs Wide analog input bandwidth: 200MHz Digital oscilloscopes power consumption: 340mW error rate Excellent temperature characteristics demultiplexed output frequency divided clock output (with reset function) Compatible with ECL, PECL digital input levels Single power supply operation available Surface mounting package
AVCC
Configuration (Top View)
CLK/E CLKN/E CLK/T N.C. N.C. N.C. DVCC2 DGND2 P2D0 P2D1 P2D2 P2D3
DVEE3
RESETN/E RESET/E RESETN/T SELECT CLKOUT DVCC2 DGND2 P1D7 P1D6 P1D5 P1D4
AGND
P2D4
DGND2
P1D1
AGND
AVCC
VRM3
VRM2
VRM1
P2D7
DVCC1
P1D0
P2D6
DGND1
P2D5
Sony reserves right change products specifications without prior notice. This information does convey license implication otherwise under patents other right. Application circuits shown, any, typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits.
DVCC2
P1D2
P1D3
PE97902-PS
CXA3246Q
Absolute Maximum Ratings 25°C) Unit Supply voltage AVCC, DVCC1, DVCC2 -0.5 +7.0 DGND3 -0.5 +7.0 DVEE3 -7.0 +0.5 DGND3 DVEE3 -0.5 +7.0 AVCC Analog input voltage Reference input voltage AVCC AVCC |VRT VRB| Digital input voltage (/E1) DVEE3 +0.5 PECL (/E) -0.5 DGND3 (/T, INV) -0.5 DVCC1 other (SELECT) -0.5 DVCC1 (|/E N/E|) Storage temperature Tstg +150 Allowable power dissipation (when mounted double glass fabric base epoxy board with 50mm 50mm, 1.6mm thick)
Recommended Operating Conditions With single power supply With dual power supplies Unit Min. Typ. Max. Min. Typ. Max. Supply voltage DVCC1, DVCC2, AVCC +4.75 +5.0 +5.25 +4.75 +5.0 +5.25 DGND1, DGND2, AGND -0.05 +0.05 -0.05 +0.05 DGND3 +4.75 +5.0 +5.25 -0.05 +0.05 -0.05 +0.05 -5.5 -5.0 -4.75 DVEE3 Analog input voltage Reference input voltage +2.9 +4.1 +2.9 +4.1 +1.4 +2.6 +1.4 +2.6 |VRT VRB| Digital input voltage (/E) DGND3 1.05 DGND3 DGND3 DGND3 PECL (/E) DGND3 1.05 DGND3 DGND3 DGND3 (/T, INV) other (SELECT) DVCC1 DVCC1 DGND1 DGND1 VID2 (|/E N/E|) Maximum conversion rate (Straight mode) MSPS (DMUX mode) MSPS Ambient temperature
indicate CLK/E CLK/T, etc. name. VID: Input Voltage Differential PECL switching level
DGND3 (max.) (DGND3 1.3V) (min.)
CXA3246Q
Block Diagram
AVCC
DVCC1
DVCC2
DGND3
(MSB) P1D7 P1D6
VRM3
6bit
P1D5
LATCH
TTLOUT
8bit
P1D4 P1D3 P1D2
6bit
P1D1
6bit LATCH ENCODER
VRM2
ENCODER
P1D0 (LSB)
(MSB) P2D7 P2D6 P2D5
VRM1
6bit
LATCH
LATCH
TTLOUT
P2D4 P2D3 P2D2 P2D1
8bit 6bit
CLK/T CLK/E CLKN/E
P2D0 (LSB) Select CLKOUT
RESETN/T RESETN/E RESET/E AGND
DGND2
DVEE3
SELECT DGND1
CXA3246Q
Description Equivalent Circuit Symbol AGND Standard voltage level (typ.) (typ.) (Typ.) (With single power supply) (With dual power supplies) (With single power supply) (Typ.) (With dual power supplies) N.C. CLK/E
DGND3
Equivalent circuit
Description Analog ground. Separated from digital ground. Analog power supply. Separated from digital power supply. Digital ground. Digital power supply.
AVCC
DGND1 DGND2 DVCC1 DVCC2
DGND3
Digital power supply. Ground input. PECL input.
DVEE3
Digital power supply. input. Ground PECL input.
connected pin. connected with internal circuits. Clock input. CLK/E complementary input. When left open, this goes threshold potential. Only CLK/E used operation, complementary input recommended attain fast stable operation. Reset input. When input level, built-in frequency divider circuit reset.
CLKN/E
ECL/ PECL RESETN/E
1.2V
DVEE3
RESET/E
RESETN/E complementary input. When left open, this goes threshold voltage. Only RESETN/E used operation.
CXA3246Q
Symbol
Standard voltage level
DVCC1
Equivalent circuit
Description
CLK/T
Clock input.
1.5V
RESETN/T
DGND1 DVEE3
DVCC1
Reset input. When left open, this input goes high level. When input level, built-in frequency divider circuit reset.
Data output polarity inversion input. When left open, this input goes high level. (See Table Correspondence Table.)
DGND1 DVEE3
DVCC1
SELECT
1.5V
Data output mode selection. (See Table Operating Mode Table.)
DGND1
4.0V (typ.)
reference voltage. By-pass AGND with tantal capacitor 0.1µF chip capacitor. Reference voltage point. By-pass AGND with 0.1µF chip capacitor. Reference voltage point. By-pass AGND with 0.1µF chip capacitor. Reference voltage point. By-pass AGND with 0.1µF chip capacitor. Bottom reference voltage. By-pass AGND with tantal capacitor 0.1µF chip capacitor.
VRM3
(VRT VRB)
Comparator
Comparator Comparator
VRM2
(VRT VRB)
Comparator Comparator
VRM1
(VRT VRB)
Comparator Comparator
Comparator
2.0V (typ.)
CXA3246Q
Symbol
Standard voltage level
AVCC
Equivalent circuit
Comparator AVCC
Description
Analog input.
Vref
DVEE3
AGND
P1D0 P1D7 P2D0 P2D7
DVCC1 DVCC2
Port side data output.
100K
DGND2 DVEE3
Port side data output.
DGND1
CLKOUT
Clock output. (See Table Operating Mode Table.)
CXA3246Q
Electrical Characteristics (DVCC1, AVCC, DGND3 +5V, DGND1, AGND, DVEE3 25°C) Item Resolution characteristics Integral linearity error Differential linearity error Analog input Analog input capacitance Analog input resistance Analog input current Reference input Reference resistance Reference current Offset voltage side side Digital input (ECL, PECL) Digital input voltage: High Threshold voltage Digital input current High Digital input capacitance Digital input (TTL) Digital input voltage: High Threshold voltage Digital input current High Digital input capacitance Digital output (TTL) Digital output voltage High Switching characteristics Maximum conversion rate Aperture jitter Sampling delay Clock high pulse width Clock pulse width RESETN_CLK setup RESETN_CLK hold time CLKOUT output delay Data output delay Output rise time Output fall time Rref3 Iref4 Symbol Conditions Min. Typ. ±0.5 ±0.5
DGND3 1.05 DGND3 DGND3
Max.
Unit bits MSPS
2Vp-p, 5MSPS
+3.0V 0.07Vrms
DGND3 DGND3
DGND3 0.8V DGND3 1.6V
3.5V 0.2V -500
Tpw1 Tpw0 T_rs T_rh Td_clk Tdo1 Tdo2
-2mA DMUX mode
RESETN RESETN DMUX mode 2.0V 2.0V 5pF) 5pF) 5pF) 5pF) 5pF)
These characteristics PECL input,unless otherwise specified.
CXA3246Q
Item Dynamic characteristics Input bandwidth ratio
Symbol
Conditions 2Vp-p, -3dB 120MSPS, 1kHz DMUX mode 120MSPS, 29.999MHz DMUX mode 120MSPS, 1kHz DMUX mode Error 16LSB 120MSPS, 29.999MHz DMUX mode Error 16LSB 100MSPS, 24.999MHz Straight mode Error 16LSB
Min.
Typ.
Max.
Unit
TPS6
Error rate
10-12
10-9
10-9
Power supply Supply current Supply current Power consumption
Rref: Resistance value between Iref Rref TPS: Times Sample (ICC IEE) (VRT VRB) Rref
Step
VRM2
Table Correspondence Table
CXA3246Q
Electrical Characteristics Measurement Circuit Current Consumption Measurement Circuit
Sampling Delay Measurement Circuit Aperture Jitter Measurement Circuit
100MHz
AVCC DVCC1 DVCC2
DGND3 OSC1 Variable
CXA3246Q
Logic Analizer 1024 samples
1.95V
CLK/E
5MHz PECL OSC2
DGND2 DGND1 AGND
Buffer DVEE3 100MHz
Integral Linearity Error Measurement Circuit Differential Linearity Error Measurement Circuit
Aperture Jitter Measurement Method
VRM2 when when
Comparator CXA3246Q Controller Buffer
(LSB)
Sampling timing fluctuation aperture jitter)
Where (LSB) deviation output codes when largest slew rate point sampled clock which exactly same frequency analog input signal, aperture jitter
Error Rate Measurement Circuit
CXA3246Q Latch
Signal Source
Latch Comparator Pulse Counter
-1kHz 2Vp-p Wave
16LSB Signal Source
CXA3246Q
Description Operating Modes CXA3246Q types operating modes which selected with (SELECT). Operating mode DMUX mode Straight mode SELECT Maximum conversion rate 120MSPS 100MSPS Data output Demultiplexed output 60Mbps Straight output 100Mbps Clock output input clock frequency divided output. 60MHz input clock inverted output. 100MHz
Table Operating Mode Table
DMUX mode (See Application Circuit 1-(1), (3).) SELECT this mode. this mode, clock frequency divided data output after being demultiplexed this frequency divided clock. frequency divided clock, which adequate setup time hold time output data, output from CLKOUT pin. When resetting this frequency divided clock, level RESET signal should input RESETN (Pin 46or 48). RESET signal requires setup time (T_rs hold time (T_rh clock rising edge because synchronized with taken clock. Therefore, RESET signal T_rs (min.) T_rh (min.) longer clock rising edge. reset period extended making level period RESET signal longer because clock output fixed (reset) during level period clock rising edge. reset start timing regarded important, timing where RESET signal from high consequence. However, when reset released this timing must become significant because timing used commence frequency divided clock. this case, setup time (T_rs) also necessary. timing chart detail. (This chart shows example reset 2T.) converter operate (min.) 120MSPS this mode.
CXA3246Q
When RESET signal used.
CXA3246Q
CLKOUT 8bits DATA
RESETN
CXA3246Q
CLKOUT 8bits DATA
RESETN
When RESET signal used.
RESET signal CXA3246Q
RESETN
CLKOUT 8bits DATA
(Reset period)
CXA3246Q
CLKOUT 8bits DATA
(Reset period)
RESET signal
RESETN
Straight mode (See Application Circuits 1-(4), (6).) SELECT this mode. this mode, data output obtained accordance with clock frequency applied converter applications which clock applied converter system clock. converter operate (min.) 100MSPS this mode.
Digital input level supply voltage settings logic input level CXA3246Q supports ECL, PECL levels. power supplies (DVEE3, DGND3) logic input block must match logic input (CLK RESET signals) level. Digital input level PECL DVEE3 DGND3 Supply voltage Application circuits
Table Logic Input Level Power Supply Settings
CXA3246Q
Application Circuit DMUX input
+5V(D) RESET signal
+5V(A) -5V(D)
P2D0 P2D7 8-bit Digital Data Latch P1D0 P1D7 8-bit Digital Data Latch
8-bit Digital Data
+5V(D)
+5V(A)
8-bit Digital Data
ECL-CLK +5V(D)
DMUX PECL input
+5V(D) PECL RESET signal
+5V(A)
P1D0 P1D7 8-bit Digital Data Latch
8-bit Digital Data
+5V(D)
+5V(D)
+5V(A)
8-bit Digital Data P2D0 P2D7 8-bit Digital Data Latch
PECL-CLK +5V(D)
DMUX input
+5V(D) RESET signal
P1D0 P1D7 8-bit Digital Data Latch
8-bit Digital Data
+5V(A)
+5V(D)
+5V(D) +5V(A)
8-bit Digital Data P2D0 P2D7 8-bit Digital Data Latch
TTL-CLK +5V(D)
CXA3246Q
Straight input
+5V(D)
-5V(D)
P1D0 P1D7 8-bit Digital Data Latch
8-bit Digital Data
+5V(A)
+5V(D)
+5V(A)
ECL-CLK +5V(D)
Straight PECL input
+5V(D)
+5V(A)
P1D0 P1D7 8-bit Digital Data Latch
8-bit Digital Data
+5V(D)
+5V(D)
+5V(A)
PECL-CLK PECL +5V(D)
Straight input
+5V(D)
+5V(A)
P1D0 P1D7 8-bit Digital Data Latch
8-bit Digital Data
+5V(D)
+5V(D)
+5V(A)
TTL-CLK
+5V(D)
CXA3246Q
Application Circuit
Straight Mode (When single power supply used)
Analog input
10µF short short 10µF
DGND3
AGND
CLK/E
RESETN/E RESET/E RESETN/T SELECT CLKOUT DVCC2 DGND2 P1D7 P1D6 P1D5
CLKN/E CLK/T N.C. N.C. N.C. DVCC2 DGND2 P2D0 P2D1 P2D2
DGND1
DGND2
DVCC1
DVCC2
P2D3
DVEE3
P1D4
AGND
VRM3
AVCC
VRM2
AVCC
VRM1
P1D0
P1D1
P2D4
P2D5
P2D6
P2D7
P2D5
P1D2
P1D3
P2D2 P2D3
P1D1
P1D2
(MSB) P2D7
P2D6
P1D3
P1D4 P1D5
Short analog system digital system point immediately under converter. Notes Operation. chip capacitor 0.1µF.
Application circuits shown typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits infringement third party patent other right same.
P1D6 (MSB) P1D7
(LSB) P2D0 P2D1
(LSB) P1D0
P2D4
CXA3246Q
DMUX Mode Timing Chart (Select VCC)
Tpw1 Tpw0 Tdo2; (typ.) (min.) (max.) 2.0V 0.8V (typ.)
P1D0
P2D0
Tdo1 (typ.)
2.0V 0.8V
Td_clk; (typ.) (max.) (min.) 2.0V (Reset period) 0.8V (min.) (max.) T_rh T_rs T_rh T_rs Td_clk 2.0V 0.8V
2.0V 0.8V
RESET
CXA3246Q
Straight Mode Timing Chart (Select GND)
(typ.)
Tpw1 Tpw0
Tdo2; (typ.) (min.) (max.) 2.0V 0.8V
P1D0
P2D0
2.0V 0.8V
Td_clk; (typ.) (min.) (max.)
(CLK inverted output.)
2.0V 0.8V
RESET
CXA3246Q
Timing Converter Peripheral Circuit maximum clock rate DEMUX Mode, timing channels same phase described detail below. example, from used data latch clock. clock delay data delay showed following specification, i.e. Td_clk (min.) (max.) Tdo2 (min.) (max.) These values considered temperature change power supply variation. When maximum clock rate 120MSPS used, set-up time (ts) seemed very small from above specifications. channels same circuit board, that DATA delay delay will changed same trend same condition temperature change power supply variation. result, 0.5ns delay will faster, when highest temperature highest power supply used. Also, 0.5ns delay will later, when lowest temperature lowest power supply used. These delay omitted this case. When 25°C, +5V, clock delay data delay Td_clk (min.) (max.) Tdo2 (min.) (max.) timing DATA with above delay variation showed below. Consequently, set-up time data latching obtained (min.) output delay change DATA temperature change power supply variation should have same trend delay change, minimum guaranteed temperature change power supply variation.
Analog input CXA3246Q P1D/out P2D/out RESET CXA3246Q P1D/out P2D/out RESET CXA3246Q P1D/out P2D/out RESET 1/120MSPS) 8bit 8bit Gate Array Latch
Analog input
8bit 8bit
Analog input RESET
8bit 8bit
th-reset RESET
Td_clk (min.) Td_clk (max.) Tdo2 (min.) Tdo2 (min.) (min.) (min.)
P1D/out P2D/out
16ns
Note: timing chart, values brackets included temperature change power supply variation.
CXA3246Q
Notes Operation CXA3246Q high-speed converter which capable TTL, PECL level clock input. Characteristic impedance should properly matched ensure optimum performance during high-speed operation. power supply grounding have profound influence converter performance. power supply grounding method particularly important during high-speed operation. General points caution follows. ground pattern should large possible. recommended make power supply ground patterns wider inner layer using multi-layer board. prevent interference between AGND DGND between AVcc DVcc, make sure respective patterns separated. prevent offset power supply pattern, connect AVcc DVcc lines point each ferrite-bead filter Shorting AGND DGND patterns place immediately under converter improves converter performance. Ground power supply pins (AVcc, DVcc1, DVcc2, DVEE3) close each possible with 0.1µF larger ceramic chip capacitor. (Connect AVcc AGND pattern DVcc1, DVcc2 DVEE3 pins DGND pattern.) digital output wiring should short possible. digital output wiring long, wiring capacitance will increase, deteriorating output slew rate resulting reflection output waveform since original output slew rate quite fast. analog input input capacitance approximately 10pF. drive converter with proper frequency response, necessary prevent performance deterioration parasitic capacitance parasitic inductance using large capacity drive circuit. keeping wiring short possible, using chip parts resistors capacitors, etc. pins must have adequate by-pass protect them from high-frequency noise. By-pass them AGND with approximately tantal capacitor and, 0.1µF chip capacitor short possible. CLK/E used, by-pass this DGND with approximately 0.1µF capacitor. this time, approximately DGND3 1.3V voltage generated. However, this recommended threshold voltage weak. When digital input level PECL level, pins should used pins left open. When digital input level TTL, pins should used pins left open.
CXA3246Q
Example Representative Characteristics
Current consumption Ambient temperature characteristics
Current consumption Conversion rate characteristics response
Current consumption [mA]
Current consumption [mA]
fCLK 1kHz
DMUX mode
Ambient temperature [°C]
Conversion rate [MSPS]
Analog input current Analog input voltage characteristics
Reference current Ambient temperature characteristics
Analog input current [µA]
Reference current [mA]
Ambient temperature [°C] Analog input voltage
CXA3246Q
Input frequency response
Error rate Conversion rate characteristics
10-6 fCLK 1kHz
10-7
Error Rate [TPS]
Error 16LSB 10-8
[dB]
120MSPS
10-9
10-10 Conversion rate [MSPS]
Input frequency [MHz]
Maximum conversion rate Ambient temperature characteristics
Maximum conversion rate [MSPS]
fCLK 1kHz Error 16LSB Error rate: 10-9
Ambient temperature [°C]
CXA3246Q
Package Outline
Unit:
48PIN (PLASTIC)
15.3 12.0 0.15 0.05
0.15
0.15
0.12
0.35 0.15
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE QFP-48P-L04 QFP048-P-1212-B LEAD TREATMENT LEAD MATERIAL PACKAGE WEIGHT EPOXY RESIN SOLDER PALLADIUM PLATING COPPER ALLOY 0.7g
NOTE PALLADIUM PLATING This product uses S-PdPPF (Sony Spec.-Palladium Pre-Plated Lead Frame).
13.5
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