10-bit 125MSPS Converter Description CXA3197R high-speed converte

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10-bit 125MSPS Converter Description CXA3197R high-speed converte

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CXA3197R
10-bit 125MSPS Converter
Description CXA3197R high-speed converter which perform multiplexed input system 10-bit data. maximum conversion rate achieves 125MSPS. multiplexed operation possible frequency-divided clock halving frequency clock with clock frequency divider circuit having reset data input TTL; clock input reset input select either PECL according application. Features Maximum conversion rate: 125MSPS Resolution: bits glitch energy: 1.5pVs power consumption: 400mW (typ.) Differential linearity error: ±0.5LSB less Integral linearity error: ±1.0LSB less Data input level: Clock, reset input level: PECL compatible multiplexed input function frequency-divided clock output possible built-in clock frequency divider circuit Voltage output load drive possible) Single power supply ±dual power supplies Polarity switching function reset signal
AGND2 AOUTP AOUTN AVCC2
Preliminary
LQFP (Plastic)
Structure Bipolar silicon monolithic Applications HDTV Communications (QPSK, QAM) Measuring device
AGND2 VOCLP POLARITY DVCC1 N.C. DGND1 (MSB) RESETN/E RESETP/E RESET/T CLKN/E CLKP/E CLK/T DIV2OUT
DGND2
DIV2IN (LSB)
AVCCO
VSET
DVCC2
Configuration
VREF
(MSB)
(LSB)
Sony reserves right change products specifications without prior notice. This information does convey license implication otherwise under patents other right. Application circuits shown, any, typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits.
PE97639-PS
CXA3197R
Absolute Maximum Ratings 25°C) Supply voltage AVCCO, AVCC2, DVCC2 AGND2, DGND2 DVCC1 AVCC2 AGND2 AVCCO AGND2 DVCC2 DGND2 -0.5 +7.0 -7.0 +0.5 -0.5 +7.0 -0.5 +7.0 -0.5 +7.0 -0.5 +7.0
VSET AGND2 AVCC2 DGND1 DVCC1 PECL DGND1 DVCC1 DGND1 DVCC1 (Others) VOCLP DGND1 DVCC1 Storage temperature Tstg +150 Allowable power dissipation (when mounted glass fabric base epoxy board with 76mm 114mm, 1.6mm thick)
Input voltage (Analog) (Digital)
Recommended Operating Conditions [Single power supply] Supply voltage Min. Typ. Max. AVCCO +4.75 +5.0 +5.25 AVCC2 AGND2 DVCC1 DGND1 DVCC2 DGND2 Input voltage (Analog) (Digital) +4.75 -0.05 +4.75 -0.05 +4.75 -0.05 +5.0 +5.0 +5.0 +5.25 +0.05 +5.25 +0.05 +5.25 +0.05
[Dual power supplies] Min. Typ. Max. -0.05 -0.05 -5.50 +4.75 -0.05 -0.05 -5.50 Typ. -5.0 +5.0 -5.0 +0.05 +0.05 -4.75 +5.25 +0.05 +0.05 -4.75
Unit Unit MSPS
VSET PECL
Min. AGND2 DGND1 DGND1 DGND1 DGND1 0.75
Max. AGND2 1.03 DGND1 DVCC1 DGND1 DVCC1
DVCC1 DVCC1
(Others) pulse width
VOCLP tpw1 tpw0 Maximum conversion rate Load resistance Analog output full-scale voltage Operating temperature
CXA3197R
Description [Level single power supply] Side data input. Side data input. frequency-divided clock input. frequency-divided clock output. clock input. PECL clock input. PECL PECL clock input. PECL reset input. PECL reset input. PECL PECL reset input. PECL Digital ground. Function setting. Function setting. Function setting. Digital power supply. Analog output power supply. (typ.) negative output. AVCCO positive output. AVCCO Analog ground. Analog reference voltage. AGND2 1.2V Full-scale adjustment. Analog power supply. Analog ground. High level clamp. Clamp voltage Reset signal polarity switching. Analog output inversion. Power saving. Digital power supply. connected. Digital ground. [Description] [Level dual power supplies] PECL PECL PECL PECL (typ.) AVCCO AVCCO AGND2 1.2V Clamp voltage
[Symbol] DIV2IN DIV2OUT CLK/T CLKP/E CLKN/E RESET/T RESETP/E RESETN/E DGND2 DVCC2 AVCCO AOUTN AOUTP AGND2 VREF VSET AVCC2 AGND2 VOCLP POLARITY DVCC1 N.C. DGND1
[Pin No.]
CXA3197R
Block Diagram
VREF
VSET
AVCC2 Current Cont.
AGND2 DVCC1 DVCC2
10bit
Input Latch
10bit 10bit Latch 10bit
AVCCO AOUTP
AOUTN 10bit Input Latch 10bit AGND2 AGND2
DIV2IN
DIV2OUT
CLK/T CLKP/E CLKN/E RESET/T RESETP/E RESETN/E POLARITY
DGND1
DGND2
VOCLP
CXA3197R
Description Equivalent Circuit Symbol Typical voltage level Equivalent circuit Description
DVCC1
Side data input.
Vref
DGND1
Side data input.
DVCC1
DIV2IN
Vref
DGND1
frequency-divided clock input. this MUX.1A MUX.2 mode. Leave open other modes.
DVCC1
DIV2OUT
100K
DGND1
frequency-divided clock output. signal with frequency-divided clock (DIV2OUT) output MUX.1A mode. Leave open other modes.
DVCC1
CLK/T
Vref
Clock input. this when clock input level. this time, leave Pins open.
DGND1
CXA3197R
Symbol
Typical voltage level
Equivalent circuit
Description Clock input. this when clock input PECL level. this time, leave open. CLKP/E complimentary input. When left open, this goes threshold potential(DVCC1 1.3V). Operation possible only with CLKP/E, complimentary input recommended attain fast stable operation. Reset signal input. When multiple CXA3197R operated time MUX.1A MUX.1B mode, start timing internal frequency divider circuits should matched. this time, reset signal used; when reset signal level, used Pins left open. When reset signal PECL level, Pins used left open. PECL level, operation possible only with RESETP/E with case clock. reset signal polarity POLARITY). Leave reset open when other modes used.
CLKP/E
PECL
DVCC1
DGND1
CLKN/E
PECL
DVCC1
RESET/T
Vref
DGND1
RESETP/E
PECL
DVCC1
DGND1
RESETN/E
PECL
DGND2
Single power supply: Dual power supplies:
Digital power supply.
CXA3197R
Symbol
Typical voltage level
DVCC1
Equivalent circuit
Description
Function setting.
Vref
Function setting.
DGND1
Single power supply: Dual power supplies:
Function setting.
DVCC2
Digital power supply.
AVCCO
AVCC0
Analog output power supply. negative output. inversion positive output output. Terminate inversion output with when inversion output used positive output terminated with positive output.
AOUTN
AVCCO
AGND2
AOUTP
AVCCO Single power supply: Dual power supplies:
AVCC2
AGND2
Analog ground.
VREF
AGND 1.2V
Analog reference voltage. Output.
AGND2
CXA3197R
Symbol
Typical voltage level
AVCC2
Equivalent circuit
Description
VSET
AGND2+0.7V AGND2+1.03V
Full-scale adjustment.
AGND2
AVCC2
Single power supply: Dual power supplies: Single power supply: Dual power supplies:
Analog power supply.
AGND2
Analog power supply.
DVCC1
VOCLP
Clamp voltage
DGND1
output High level clamp. level signal output from DIV2OUT MUX.1A mode. High level voltage clamped value approximately equivalent voltage supplied this pin. Leave VOCLP open other modes.
DVCC1
POLARITY
Vref
Reset signal polarity switching. High level, reset polarity active High; level, active Low.
DGND1
DVCC1
Vref
Analog output polarity inversion. analog output inverted level.
DGND1
CXA3197R
Symbol
Typical voltage level
DVCC1
Equivalent circuit
Description
Power saving. Power saving level. Normally pull High level this open Low.
DGND1
DVCC1 DGND1
Digital power supply. connected.
Digital ground.
CXA3197R
Electrical Characteristics Item Resolution Differential linearity error Integral linearity error Digital input current (TTL pin) Digital input current (PECL pin) Digital input current (PS) Clamp input current (VOCLP) Digital input capacitance Digital output voltage (DIV2OUT) VREF voltage Analog output voltage Compliance voltage Output zero offset voltage Output resistance Output capacitance Absolute amplitude error Absolute amplitude error temperature characteristics Current consumption Maximum conversion rate Analog output Rise time Fall time Settling time Glitch energy Symbol VREF 1000mV -2mA Iref AGND2 +1.16 0.75 AGND2 +1.20 AGND2 +1.24 1000mV 2.0V 0.8V DVCC1 DVCC1 2.0V more 0.8V less DVCC1 2.7V Conditions Min. Typ. Max. ±0.5 ±1.0
25°C) Unit F.S. F.S./°C MSPS
tSET
CXA3197R
Input Coding Table Data input
AOUT AVCCO AVCCO AVCCO
AOUT AVCCO AVCCO AVCCO AVCCO
AVCCO
Description Operating Modes Mode MUX.1A MUX.1B MUX.2 SELE.A SELE.B 62.5 (MSPS) Data (Mbps) AOUT (Mbps)
DIV2OUT Enable
Description
operation internal CLK/2 operation High impedance internal CLK/2 operation High impedance external DIV2IN High impedance Side data select High impedance Side data select
CXA3197R
Description Operation Block Diagram Timing Chart (MUX.1A Mode)
RESET DIV2OUT DIV2IN Input Data Input Latch Latch Input Data Input Latch Latch Latch Analog CLK/2 (Internal)
th-reset (Active High) (Active Low) D-FF
RESET CLK/2 (Internal) DIV2OUT DIV2IN Input Data Input Data
MUX.1A mode, Data Data internally multiplexed then resulting signal analog output. frequency clock halved built-in clock divider circuit CLK/2 output level (DIV2OUT). CLK/2 reset reset signal.
CXA3197R
Block Diagram Timing Chart (MUX.1B Mode)
RESET CLK/2 (Internal)
Input Data
Input Latch Latch Analog
Input Data
Input Latch
RESET (Active High) CLK/2 (Internal) Input Data Input Data th-reset (Active High) (Active Low) D-FF
MUX.1B mode, Data Data internally multiplexed then resulting signal analog output. frequency internal clock halved built-in clock divider circuit. CLK/2 reset reset signal.
CXA3197R
Block Diagram Timing Chart (MUX.2 Mode)
DIV2IN CLK/2 (Internal)
Input Data
Input Latch
Latch Latch Analog
Input Data
Input Latch
Latch
Data Data CLK/2 (Internal)
Latch-td
MUX.2 mode, frequency-halved CLK/2 Data Data which synchronized with CLK/2, provided simultaneously. They internally multiplexed resulting signal analog output.
CXA3197R
Block Diagram Timing Chart (SELE.A SELE.B Mode)
Latch
Input Data
Input Latch Select Latch Analog
Input Data
Input Latch
Input Data
Input Data
Latch
SELE.
SELE.
SELE.A SELE.B modes, input Data Data selected selected data analog output. state C1=1, C3=0,Data selected C2=0 Data selected C2=1.
CXA3197R
Application Circuit circuit shown below basic circuit when analog output terminated with external resistance dual power supplies MUX.2 mode. analog output full-scale voltage obtained with following equation. VSET RO//RL Output impedance External termination resistance
Here, VSET
VREF (VREF 1.2V) 1.2k)
+5V(D)
0V(D)
-5V(A)
0V(A)
(MSB)
DVCC1
DGND1
POLARITY
AGND2
VOCLP
Latch
AVCC2 VSET VREF AGND2 AOUTP AOUTN AVCCO DVCC2
0V(A) -5V(A) -5V(A) 0V(A) 0V(A) 0V(A) 0V(D) 0V(A)
(LSB)
(MSB)
(LSB)
RESETP/E
RESETN/E
DIV2OUT
+5V(D)
CLKP/E
CLKN/E
0V(D)
CLK/2 PECL
Application circuits shown typical examples illustrating operation devices. Sony cannot assume responsibility problems arising these circuits infringement third party patent other right same.
RESET/T
DGND2
-5V(D)
DIV2IN
CLK/T
CXA3197R
Package Outline
Unit:
48PIN LQFP (PLASTIC)
(8.0)
0.08 0.08 0.18 0.03
(0.22)
0.05 0.127 0.02
NOTE: Dimension does include mold protrusion. DETAIL
PACKAGE STRUCTURE
PACKAGE MATERIAL SONY CODE EIAJ CODE JEDEC CODE LQFP-48P-L01 LQFP048-P-0707 LEAD TREATMENT LEAD MATERIAL PACKAGE MASS EPOXY RESIN SOLDER/PALLADIUM PLATING 42/COPPER ALLOY 0.2g

10-bit 125MSPS Converter Description CXA3197R high-speed converte

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