ACS8530 SETS ADVANCED COMMUNICATIONS COMMUNICATION Description
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Synchronous Equipment Timing Source Stratum 2/3E Systems
ACS8530 SETS
ADVANCED COMMUNICATIONS COMMUNICATION Description
ACS8530 highly integrated, single-chip solution Synchronous Equipment Timing Source (SETS) function SONET Network Element. device generates SONET Equipment Clocks (SEC) Frame Synchronization clocks. ACS8530 fully compliant with required international specifications standards. device supports Free-run, Locked Holdover modes. also supports three types reference clock source: recovered line clock, network, node synchronization. ACS8530 generates independent BITS clocks, Frame Synchronization clock Multi-Frame Synchronization clock. ACS8530 devices used together Master/ Slave configuration mode allowing system protection against single ACS8530 failure. microprocessor port incorporated, providing access configuration status registers device setup monitoring. ACS8530 supports IEEE 1149.1[5] JTAG boundary scan.
Features
Suitable Stratum SONET Minimum Clock (SMC) SONET/SDH Equipment Clock (SEC) applications Meets Telcordia 1244-CORE[19] Stratum GR-253[17], ITU-T G.812[10] Type G.813[11] specifications Accepts individual input reference clocks, with robust input clock source quality monitoring Simultaneously generates nine output clocks, plus sync pulse outputs Absolute Holdover accuracy better than 10-4 (manual), 10-8 (instantaneous); Holdover stability defined choice external Programmable wander jitter tracking/attenuation steps Automatic hit-less source switchover loss input Phase Transient Protection Phase Build-out locked reference reference switching Microprocessor interface Intel, Motorola, Serial, Multiplexed, boot from EPROM Output phase adjustment steps ±200 IEEE 1149.1 JTAG[5] Boundary Scan Single operation. tolerant
Block Diagram
Figure Block Diagram ACS8530 SETS
DPLL/Freq. Synthesis
PECL/LVDS Programmable; 64/8 (AMI) 1.544/2.048 6.48 19.44 25.92 38.88 51.84 77.76 155.52
Selector Input Port Monitors Selection Control
F8530P_001BlockDia_07.EPS
Optional Divider,
Digital Loop Filter
APLL Frequency Dividers
Output Ports
Outputs T01-TO7: E1/DS1 (2.048/ 1.544 MHz) frequency multiples: E3/DS3 OC-N* rates T08: TO9: E1/DS1 TO10: (FrSync) TO11: (MFrSync)
DPLL/Freq. Synthesis APLL (output) Frequency Dividers APLL (feedback) TO10 TO11
Selector Optional Digital Loop Filter
TRST
IEEE 1149.1 JTAG
Chip Clock Generator
Priority Register Table
Microprocessor Port
OCXO
OC-N* rates OC-1 51.84 OC-3 155.52 derivatives: 6.48 9.44 25.92 38.88 51.84 77.76 155.52 311.04
F8530P_001BLOCKDIA_07
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Table Contents ADVANCED COMMUNICATION Table Contents
Section
ACS8530 SETS
Page
Description Block Diagram. Features Table Contents Navigation Features On-screen Users this Datasheet Hyperlinks Bookmarks. Searches Diagram Description. Introduction. General Description. Overview Input Reference Clock Ports Locking Frequency Modes PECL/LVDS/AMI Port Selection. Clock Quality Monitoring. Activity Monitoring Frequency Monitoring Selection Input Reference Clock Source. Forced Control Selection. Automatic Control Selection Ultra Fast Switching External Protection Switching. Modes Operation Free-run Mode Pre-locked Mode Locked Mode Lost-phase Mode. Holdover Mode Pre-locked2 Mode DPLL Architecture Configuration Phase Detectors Phase Lock Detection Damping Factor Local Oscillator Clock Output Wander Jitter Wander Transfer Phase Build-out Input Output Phase Adjustment. Input Wander Jitter Tolerance. Using DPLLs Accurate Frequency Phase Reporting Configuration Redundancy Protection Alignment Priority Tables Master Slave ACS8530 Generation Master Slave ACS8530 Alignment Output Clock Phases Master Slave ACS8530. MFrSync FrSync Alignment-SYNC2K. Output Clock Ports Output Frequency Selection Configuration Microprocessor Interface Introduction Microprocessor Modes Motorola Mode Intel Mode. Multiplexed Mode. Serial Mode. EPROM Mode. Power Reset.
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ACS8530 SETS
ADVANCED COMMUNICATION Section Page Register Map. Register Organisation Configuration Registers Status Registers Register Access Interrupt Enable Clear Defaults. Register Map. Register Descriptions Electrical Specifications JTAG Over-voltage Protection Maximum Ratings Operating Conditions Characteristics: Input/Output Port Input/Output Timing Package Information Thermal Conditions. Application Information References Abbreviations Trademark Acknowlegements Revision Status/History Ordering Information Disclaimers. Contacts.
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ACS8530 SETS
ADVANCED COMMUNICATION Diagram
Figure
ACS8530 Diagram Synchronous Equipment Timing Source Stratum 2/3E Systems
AGND TRST AGND1 VA1+ INTREQ REFCLK DGND1 VD1+ VD3+ DGND3 DGND2 VD2+ SRCSW VA2+ AGND2
SONSDHB MSTSLVB AGND3 VA3+ DGNDb VDDb VDDc DGNDc
F8520D_002PINDIAG_04 SCALE
ACS8530 SONET/SDH SETS
PORB DGNDd VDDd UPSEL0 UPSEL1 UPSEL2
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VAMI+ TO8NEG TO8POS GND_AMI FrSync MFrSync GND_DIFFa VDD_DIFFa TO6POS TO6NEG TO7POS TO7NEG GND_DIFFb VDD_DIFFb I5POS I5NEG I6POS I6NEG VDD5 SYNC2K DGNDa VDDa
F8530D_002PINDIAG_04
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ACS8530 SETS
ADVANCED COMMUNICATION Description
Table Power Pins
Number Symbol VD1+, VD3+, VD2+ VAMI+ VDD_DIFFa, VDD_DIFFb VDD5 Type Description Supply voltage: Digital supply gates analog section, +3.3 Volts 10%. Supply voltage: Digital supply output, +3.3 Volts 10%. Supply voltage: Digital supply differential ports, +3.3 Volts 10%. VDD5: Digital supply Volts tolerance input pins. Connect Volts 10%) clamping Volts. Connect clamping +3.3 Volts. Leave floating clamping, input pins tolerant +5.5 Volts. Supply voltage: Digital supply logic, +3.3 Volts 10%. Supply voltage: Analog supply clock multiplying PLL, +3.3 Volts 10%. Supply voltage: Analog supply output PLLs, +3.3 Volts 10%. Supply Ground: Digital ground components PLLs. Supply Ground: Digital ground logic. Supply Ground: Digital ground output. Supply Ground: Digital ground differential ports. Supply Ground: Analog grounds.
VDDa, VDDd, VDDc, VDDb VA1+ VA2+, VA3+ DGND1, DGND3, DGND2, DGNDa,DGNDd, DGNDc,DGNDb GND_AMI GND_DIFFa, GND_DIFFb AGND, AGND1, AGND2, AGND3
Notes: above number power pins provisional. (ii) Input, Output, Power, TTLU input with pull-up resistor, TTLD input with pull-down resistor.
Table Internally Connected
Number Symbol IC1, IC2, IC3, IC4, IC5, IC6, Type Description Internally Connected: Leave Float.
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Table Other Pins
Number Symbol TRST Type TTLD Description JTAG Control Reset Input: TRST enable JTAG Boundary Scan mode. TRST normal device operation (JTAG logic transparent). used connect leave floating. JTAG Test Mode Select: Boundary Scan enable. Sampled rising edge TCK. used connect leave floating. Interrupt Request: Active high/low software Interrupt output. JTAG Clock: Boundary Scan clock input. used connect leave floating. Reference Clock: 12.8 (refer section headed Local Oscillator Clock). Source Switching: Force Fast Source Switching. "External Protection Switching" page JTAG Output: Serial test data output. Updated falling edge TCK. used leave floating. JTAG Input: Serial test data Input. Sampled rising edge TCK. used connect leave floating. Input reference Composite clock kHz. Input reference Composite clock kHz. Output reference Composite clock, negative pulse. Output reference Composite clock, positive pulse. Output reference Frame Sync output. Output reference Multi-Frame Sync output. Output reference Programmable, default 38.88 MHz, default type LVDS. Output reference Programmable, default 19.44 MHz, default type PECL. Input reference Programmable, default 19.44 MHz, default type LVDS. Input reference Programmable, default 19.44 MHz, default type PECL. External Sync input: kHz, frame alignment. Input reference Programmable, default kHz. Input reference Programmable, default kHz. Input reference Programmable, default 19.44 MHz. Input reference Programmable, default 19.44 MHz. Input reference Programmable, default 19.44 MHz. Input reference Programmable, default 19.44 MHz.
INTREQ REFCLK SRCSW TO8NEG TO8POS FrSync MFrSync TO6POS, TO6NEG TO7POS, TO7NEG I5POS, I5NEG I6POS, I6NEG SYNC2K
TTLU TTL/CMOS TTLD TTLD TTL/CMOS TTLU TTL/CMOS TTL/CMOS LVDS/PECL PECL/LVDS LVDS/PECL PECL/LVDS TTLD TTLD TTLD TTLD TTLD TTLD TTLD
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Table Other Pins (cont.)
Number UPSEL(2:0) A(6:0) Symbol Type TTLD TTLD TTLD TTLD TTLD TTLD Description Input reference Programmable, default (Master mode) 1.544/2.048 MHz, default (Slave mode) 6.48 MHz. Input reference Programmable, default 1.544/2.048 MHz. Input reference Programmable, default 1.544/2.048 MHz. Input reference Programmable, default 1.544/2.048 MHz. Microprocessor select: Configures interface particular microprocessor type reset. Microprocessor Interface Address: Address microprocessor interface registers. A(0) Serial mode output EPROM mode only. Chip Select (Active Low): This asserted microprocessor enable microprocessor interface output EPROM mode only. Write (Active Low): This asserted microprocessor initiate write cycle. Motorola mode, Read. Read (Active Low): This asserted microprocessor initiate read cycle. Address Latch Enable: This becomes address latch enable from microprocessor. When this transitions from High Low, address inputs latched into internal registers. SCLK Serial mode. Power Reset: Master reset. PORB forced Low, internal states reset back default values. Ready/Data acknowledge: This asserted High indicate device completed read write operation. Address/Data: Multiplexed data/address depending microprocessor mode selection. AD(0) Serial mode. Output reference Programmable, default 6.48 MHz. Output reference Programmable, default 38.88 MHz. Output reference Programmable, default 19.44 MHz. Output reference Programmable, default 38.88 MHz. Output reference Programmable, default 77.76 MHz. Output reference 1.544/2.048 MHz, G.783 BITS requirements. Master/Slave select: sets state Master/Slave selection register, Reg. SONET frequency select: sets initial power state state after PORB) SONET/SDH frequency selection registers, Reg. Reg. Reg. register states changed after power software.
TTLU TTLU TTLU TTLD
PORB AD(7:0) MSTSLVB SONSDHB
TTLU TTL/CMOS TTLD TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTLU TTLD
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ACS8530 SETS
ADVANCED COMMUNICATION Introduction
ACS8530 highly integrated, single-chip solution SETS function SONET/SDH Network Element, generation Frame/MultiFrame Synchronization pulses. Digital Phase Locked Loop (DPLL) direct digital synthesis methods used device that overall characteristics very stable consistent compared traditional analog PLLs. Free-run mode, ACS8530 generates stable, lownoise clock signal frequency same accuracy external oscillator, made more accurate software calibration 0.0196 ppm. Locked mode, ACS8530 selects most appropriate input reference source generates stable, low-noise clock signal locked selected reference. Holdover mode, ACS8530 generates stable, low-noise clock signal, adjusted match last known good frequency last selected reference source. high level phase frequency accuracy made possible internal resolution bits internal Holdover accuracy 0.0012 (1.2 10-12). modes, frequency accuracy, jitter drift performance clock meet requirements G.736[7], G.742[8], G783[9], G.812[10], G.813[11], G.823[13],G.824[14] Telcordia GR-253-CORE[17] GR-1244-CORE[19]. ACS8530 supports three types reference clock source: recovered line clock (TIN1), network synchronization timing (TIN2) node synchronization (TIN3). ACS8530 generates independent clocks, Frame Synchronization clock Multi-Frame Synchronization clock. architectural advantage that ACS8530 over traditional solutions DPLL technology precise repeatable performance over temperature voltage variations between parts. overall bandwidth, loop damping, pull-in range frequency accuracy determined digital parameters that provide consistent level performance. Analog (APLL) takes signal from DPLL output provides lower jitter output. APLL bandwidth four orders magnitude higher than DPLL bandwidth. This ensures that overall system performance still maintains advantage consistent behaviour provided digital approach. DPLLs clocked external Oscillator module (OCXO) that Free-run Holdover frequency
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stability only determined stability external oscillator module. This second advantage confines temperature critical components well defined pre-calibrated module, whose performance chosen match application; example OCXO Stratum applications. performance parameters DPLLs programmable without need understand detailed equations. Bandwidth, damping factor lock range directly, example. bandwidth over wide range, steps, cover SONET/SDH clock synchronisation applications. ACS8530 supports protection. ACS8530 devices configured provide protection against single ACS8530 failure. protection maintains alignment ACS8530 devices (Master Slave) ensures that both ACS8530 devices maintain same priority table, choose same reference input generate clock, Frame Synchronization clock Multi-Frame Synchronization clock with same phase. ACS8530 includes multistandard microprocessor port, providing access configuration status registers device setup monitoring.
General Description Overview
following description refers Block Diagram (Figure page ACS8530 SETS device input clocks, generates output clocks, total possible output frequencies. There main paths through device: Each path independent DPLL APLL pair. path high quality, highly configurable path designed provide features necessary node timing synchronization within SONET/SDH network. path simpler less configurable path designed give totally independent path internal equipment synchronization. device supports either both paths, either locked together independent. input references, composite clock, LVDS/PECL remaining TTL/CMOS compatible inputs. TTL/CMOS
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compatible (with clamping required connecting VDD5 pin). inputs typically A.C. coupled. Refer electrical characteristics section more information electrical compatibility details. Input frequencies supported range from 155.52 MHz. Common DS1, sub-divisions supported spot frequencies that DPLLs will directly lock input frequency, MHz, that multiple also locked inbuilt programmable divider. input reference monitor assigned each inputs. monitors operate continuously such that times status inputs device known. Each input monitored both frequency activity, activity alone, monitors disabled. frequency monitors have "hard" (rejection) alarm limit "soft" (flag only) alarm limit monitoring frequency, whilst reference still within allowed frequency band. Each input reference programmed with priority number allowing references chosen according highest priority valid input. paths have independent priorities allow completely independent operation paths. Both paths operate either automatic external source selection. automatic input reference selection, path more complex state machine than path. paths support following common features: Automatic source selection according input priorities quality level Different quality levels (activity alarm thresholds) each input Variable bandwidth, lock range damping factor. Direct locking common SONET/SDH input frequencies multiple Automatic mode switching between Free-run, Locked Holdover states Fast detection input failure entry into Holdover mode (holds last good frequency value) Frequency translation between input output rates direct digital synthesis High accuracy digital architecture stable dynamics combined with APLL jitter final output clocks.
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There number features supported path that supported path, although these also externally controlled software. additional features supported are: Non-revertive mode Phase Build-out source switch (hitless source switching) Phase Build-out following phase locked-to source phase offset control Greater programmable bandwidth from steps path programmable bandwidth steps, Noise rejection frequency input Manual Holdover frequency control Controllable automatic Holdover frequency filtering Frame Sync pulse alignment. Either software internal state machine controls operation DPLL path. state machine path very simple cannot manually/externally controlled, however overall operation controlled manual reference source selection. additional feature path ability measure phase difference between inputs. path DPLL always produces output 77.76 feed APLL, regardless frequency selected output pins. path operated number frequencies. This enable generation extra output frequencies, which cannot easily related 77.76 MHz. When path selected lock path, DPLL locks from DPLL. This because frequencies operation path divided this will ensure synchronization frequencies within paths. Both DPLL's outputs connected multiplying filtering APLLs. outputs these APLLs divided making number frequencies simultaneously available selection output clock ports. various combinations DPLL, APLL divider configurations allow generation comprehensive frequencies, listed Table synchronise lower output frequencies when locked high frequency reference input, additional input provided. SYNC2K (pin used reset dividers that generate 2kHz
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outputs such that output clocks lined with input kHz. This synchronisation method allows example, master slave device precise alignment. ACS8530 also supports Sync pulse references although these cases frequencies lower than Sync pulse reference necessarily phase.
divide input frequency before used phase comparisons DPLL.
Lock8k Mode
Input Reference Clock Ports
Table gives details input reference ports, showing input technologies range frequencies supported each port; default spot frequencies default priorities assigned each port power-up reset also shown. Note that SONET networks different default frequencies; network type pinselectable (using either SONSDHB software). Specific frequencies priorities configuration. Although each input ports shown belonging types, TIN1, TIN2 TIN3, they fully interchangeable long selected speed within maximum operating speed input port technology. SONET networks different default frequencies; network type selectable using config_input_mode Reg. ip_sonsdhb. SONET, ip_sonsdhb SDH, ip_sonsdhb power-up reset, default will state SONSDHB (pin 100). Specific frequencies priorities configuration. frequency selection programmed cnfg_ref_source_frequency register (Reg. Reg. 2D).
Lock8k mode automatically sets divider parameters divide input frequency down kHz. Lock8k only used supported spot frequencies (see Table Note(i)). Lock8k mode enabled setting lock8k (bit appropriate cnfg_ref_source_frequency register location. Using lower frequencies phase comparisons DPLL results greater tolerance input jitter. possible choose which edge input reference clock lock setting cnfg_control1 register.
DivN Mode
DivN mode, divider parameters manually configuration (bit cnfg_ref_source_frequency register), must that frequency after division kHz. DivN function defined DivN "Divide i.e. dividing factor used division input frequency, value (N+1) where integer from 12499 inclusive. Therefore, DivN mode input frequency divided integer value between 12500. Consequently, input frequency which multiple kHz, between MHz, supported using DivN mode.
Note.Any reference input DivN independently frequencies configurations other inputs. However only value allowed, inputs with DivN selected must running same frequency. DivN Examples
Locking Frequency Modes
There three locking frequency modes that configured: Direct Lock, Lock8k DivN.
Direct Lock Mode
lock 2.000 MHz: cnfg_ref_source_frequency register 10XX0000 (binary) enable DivN, frequency frequency required after division. "Leaky Bucket" this input).
Direct Lock Mode, internal DPLL lock selected input spot frequency input, example 19.44 performs DPLL phase comparisons 19.44 MHz. Lock8k DivN modes (and special case MHz), internal divider used prior DPLL
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(ii) achieve kHz, input must divided 250. DivN then must 249. This done writing (249 decimal) DivN register pair Reg. 46/47. lock 10.000 MHz:
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cnfg_ref_source_frequency register 10XX0000 (binary) DivN frequency kHz, post-division frequency. "Leaky Bucket" this input).
PECL/LVDS/AMI Port Selection
choice PECL LVDS compatibility programmed cnfg_differential_inputs register. Unused PECL differential inputs should fixed with input high (VDD) other input (GND), LVDS mode left floating, which case input internally pulled high other low. port supports composite clock, consisting clock with boundaries marked deliberate violations coding rules, specified recommendation G.703[6]. Departures from nominal pattern detected within ACS8530, cause reference-switching frequent. section Characteristics: Input/Output Port, more details. port unused, pins should tied GND.
(ii) achieve kHz, input must divided 1,250. DivN, (N+1) then must 1,249. This done writing (1,249 decimal) DivN register pair Reg. 46/47.
Direct Lock Mode MHz.
frequency allowed phase comparison 77.76 MHz, special case input Direct Lock Mode, there divide-by-two function automatically selected bring frequency down within limits operation.
Table Input Reference Source Selection Priority Table
Port Number Channel Number 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 Port Type (Note(iii)) TIN3 TIN3 TIN3 TIN3 TIN1 TIN1 TIN1 TIN1 TIN1 TIN1 TIN2 TIN2 Input Port Technology TTL/CMOS TTL/CMOS LVDS/PECL LVDS default PECL/LVDS PECL default TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS Frequencies Supported 64/8 (composite clock, kHz) Default (SONET): 64/8 Default (SDH): 64/8 64/8 (composite clock, kHz) Default (SONET): 64/8 Default (SDH): 64/8 (see Note (i)) Default (SONET): Default (SDH): (see Note (i)) Default (SONET): Default (SDH): 155.52 (see Note (i)) Default (SONET): 19.44 Default (SDH): 19.44 155.52 (see Note (i)) Default (SONET): 19.44 Default (SDH): 19.44 (see Note (i)) Default (SONET): 19.44 Default (SDH): 19.44 (see Note (i)) Default (SONET): 19.44 Default (SDH): 19.44 (see Note (i)) Default (SONET): 19.44 Default (SDH): 19.44 (see Note (i)) Default (SONET): 19.44 Default (SDH): 19.44 (see Note (i)) Default (Master) (SONET): 1.544 Default (Master) (SDH): 2.048 Default (Slave) 6.48 (see Note (i)) Default (SONET): 1.544 Default (SDH): 2.048 12/1 (Note (ii)) Default Priority
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Table Input Reference Source Selection Priority Table (cont.)
Port Number Channel Number 1101 1110 Port Type (Note(iii)) TIN2 TIN2 Input Port Technology TTL/CMOS TTL/CMOS Frequencies Supported (see Note (i)) Default (SONET): 1.544 Default (SDH): 2.048 (see Note (i)) Default (SONET): 1.544 Default (SDH): 2.048 Default Priority
Notes: ports (compatible also with CMOS signals) support clock speeds MHz, with highest spot frequency being 77.76 MHz. actual spot frequencies are: kHz, kHz, (and kHz), 1.544 (SONET)/2.048 (SDH), 6.48 MHz, 19.44 MHz, 25.92 MHz, 38.88 MHz, 51.84 MHz, 77.76 MHz. SONET input rate selected Reg. ip_sonsdhb). PECL LVDS ports support spot clock frequencies listed above plus 155.52 (and 311.04 only). (ii) Input port <I11> priority Master SETS priority Slave SETS default power PORB). default setup Master Slave <I11> priority determined MSTSLVB pin. (iii) ACS8530 supports three types reference clock source: recovered line clock (TIN1), network synchronization timing (TIN2) node synchronization (TIN3). input type.
Clock Quality Monitoring
Clock quality monitored used modify priority tables local remote ACS8530 devices. each input, following parameters monitored: Activity (toggling). Frequency (this monitoring only performed when there irregular operation clock loss clock condition). addition, input ports carry AMI-encoded composite clocks which monitored AMIdecoder blocks. Loss signal declared decoders when either signal amplitude falls below +0.3 there activity reference source that suffers loss-of-activity clock-out-of-band condition will declared unavailable. Clock quality monitoring continuous process which used identify clock problems. There difference dynamics between selected clock other reference clocks. Anomalies occurring non-selected reference sources affect only that source's suitability selection, whereas anomalies occurring selected clock could have detrimental impact accuracy output clock. Anomalies detected activity detector integrated Leaky Bucket Accumulator (one input channel). Occasional anomalies cause Accumulator cross alarm setting threshold, selected
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reference source retained. Persistent anomalies cause alarm setting threshold crossed result selected reference source being rejected. Anomalies currently locked-to input reference clock, whether affecting signal purity signal frequency, could induce jitter frequency offsets output clock, leading anomalous behaviour. Anomalies selected clock, therefore, have detected they occur phase locked loop must temporarily isolated until clock once again pure. clock monitoring process cannot used this because high degree accuracy required dictates that process slow. achieve immediacy required phase locked loop requires alternative mechanism. phase locked loop itself contains fast activity detector such that within approximately missing input clock cycles, no-activity flag raised DPLL frozen Holdover mode. This flag also read main_ref_failed (from Reg. indicate phase lost state enabling Reg. With DPLL Holdover mode isolated from further disturbances. input becomes available again before activity frequency monitor rejection alarms have been raised, then DPLL will continue lock input, with little disturbance. this scenario, with DPLL "locked" state, DPLL uses "nearest edge locking" mode 180° capture) avoiding cycle slips glitches caused trying lock edge 360° away, would happen with traditional PLLs.
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Activity Monitoring
ACS8530 combined inactivity irregularity monitor. ACS8530 uses Leaky Bucket Accumulator, which digital circuit which mimics operation analog integrator, which input pulses increase output amplitude away over time. Such integrators used when alarms have triggered either fairly regular defect events, which occur sufficiently close together, defect events which occur bursts. Events which sufficiently spread should trigger alarm. adjusting alarm setting threshold, point which alarm triggered controlled. point which alarm cleared depends upon decay rate alarm clearing threshold. alarm setting side, several events occur close together, each event adds amplitude alarm will triggered quickly; events occur little more spread out, still sufficiently close together overcome decay, alarm will triggered eventually. events occur rate which sufficient overcome decay, alarm will triggered. alarm clearing side, defect events occur sufficient time, amplitude will decay gradually alarm will cleared when amplitude falls below alarm clearing threshold. ability decay amplitude over time allows importance defect events reduced time passes This means that, case isolated events, alarm will set, whereas, once alarm becomes set, will held until normal operation persisted suitable time Figure Inactivity Irregularity Monitoring
Inactivities/Irregularities
(but operation still erratic, alarm will remain set). Figure There Leaky Bucket Accumulator input channel. Each Leaky Bucket select from four configurations (Leaky Bucket Configuration Each Leaky Bucket Configuration programmable size, alarm reset thresholds, decay rate. Each source monitored over period. within period, irregularity occurs that deemed allowable jitter/wander, then Accumulator incremented. Accumulator will continue increment point that reaches programmed Bucket size. "fill rate" Leaky Bucket therefore, units/second. "leak rate" Leaky Bucket programmable multiples fill rate 0.5, 0.25 0.125) give programmable leak rate from units/sec down unit/sec. conflict between trying "leak" same time "fill" avoided preventing leak when fill event occurs. Disqualification non-selected reference source based inactivity, out-of-band result from frequency monitors. currently selected reference source disqualified phase, frequency, inactivity source outside DPLL lock range. currently selected reference source disqualified, next highest priority, qualified reference source selected.
F8530_026Inact_Irreg_Mon_02
Reference Source bucket_size Leaky Bucket Response Programmable Fall Slopes upper_threshold lower_threshold (all programmable)
Alarm
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Leaky Bucket Timing
special circumstances, such chip board testing, selection forced configuration. Automatic operation selects reference source based pre-defined priority current availability. table maintained which lists reference sources order priority. This initially defined default configuration changed microprocessor interface Network Manager. this way, when defined sources active valid, source with highest programmed priority selected but, this source fails, next-highest source selected, Restoration repaired reference sources handled carefully avoid inadvertent disturbance output clock. this, ACS8530 modes operation; Revertive Non-revertive. Revertive mode, re-validated newly validated) source higher priority than reference source which currently selected, switch over will take place. Many applications prefer minimise clock switching events choose Non-revertive mode. Non-revertive mode, when re-validated newly validated) source higher priority then selected source will maintained. re-validation reference source will flagged sts_sources_valid register and, masked, will generate interrupt. Selection re-validated source take place under software control currently selected source fails. enable software control, software should briefly enable Revertive mode affect switch-over higher priority source. When there reference available with higher priority than selected reference, there will change reference source long Nonrevertive mode remains currently selected source valid. failure selected reference will always trigger switch-over regardless whether Revertive Non-revertive mode been chosen. Also, Master/Slave redundancy-protection scheme, Slave device(s) must follow Master device. alignment Master Slave devices part protection mechanism. availability each source determined combination local remote monitoring each source. Each input reference source supplied each ACS8530 device monitored locally results made available other devices.
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time taken seconds) raise inactivity alarm reference source that previously been fully active (Leaky Bucket empty) will (cnfg_activ_upper_thresholdn) where number Leaky Bucket Configuration. input intermittently inactive then this time longer. default setting cnfg_activ_upper_threshold therefore default time 0.75 time taken seconds) cancel activity alarm previously completely inactive reference source calculated, particular Leaky Bucket, where: cnfg_decay_raten cnfg_Bucket_sizen cnfg_activ_lower_thresholdn (where number relevant Leaky Bucket Configuration each case). default setting shown following: secs
Frequency Monitoring
ACS8530 performs frequency monitoring identify reference sources which have drifted outside acceptable frequency range measured with respect either output clock clock. sts_reference_sources out-of-band alarm particular reference source raised when reference source outside acceptable frequency range. With default register settings soft alarm raised drift outside 11.43 hard alarm raised drift outside 15.24 ppm. Both these limits programmable from ppm. ACS8530 DPLL programmable lock capture range frequency limit (default ppm).
Selection Input Reference Clock Source
Under normal operation, input reference sources selected automatically order priority. But,
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Forced Control Selection
configuration register, force_select_reference_source Reg. controls both choice automatic forced selection selection itself (when forced selection required). Automatic choice source selection, value zeros ones (default). force particular input (In), value (bin). Forced selection normal mode operation, force_select_reference_source variable defaulted all-one value reset, thereby adopting automatic selection reference source.
Ultra Fast Switching
reference source normally disqualified after Leaky Bucket monitor thresholds have been crossed. option faster disqualification been implemented, whereby Reg. (ultra_fast_switch) set, then loss activity just reference clock cycles will no_activity_alarm cause reference switch. This configured (see Reg. cause interrupt occur instead well causing reference switch. sts_interrupts register Reg. (main_ref_failed) used flag inactivity reference that device locked much faster than activity monitors support. Reg. cnfg_monitors register (los_flag_on_TDO) set, then state this driven onto device.
Note.The flagging loss main reference failure simply allowing status sts_interrupt reflected state output pin. will, therefore, remain High until interrupt cleared. This functionality enabled default usual JTAG functions used. When output from ACS8530 connected next device JTAG scan chain, implementation should such that logic change caused action interrupt input should effect operation when JTAG active.
Automatic Control Selection
When automatic selection required, force_select_reference_source register bits must zeros ones. configuration registers, cnfg_ref_selection_priority, held port block, consist seven, registers organised 4-bit register input reference port. Each register holds value which represents desired priority that particular port. Unused ports should given value, 0000, relevant register indicate they included priority table. power-up, following reset, whole configuration file will defaulted values defined Table selection priority values relative each other, with lowervalued numbers taking higher priorities. Each reference source should given unique number; valid values (dec). value disables reference source. However more inputs given same priority number those inputs will selected first first basis. first same priority number sources goes invalid second will switched first then becomes valid again, becomes second source first first basis, there will switch. third source with same priority number other becomes valid, joins priority list same first first basis. There implied priority based channel numbers. Revertive/Non-revertive mode effect sources with same priority value. input port <I11> also connection synchronous clock output Master device active-Slave device), used align output with Master active-Slave) device this device acting subordinate-Slave subordinateMaster role.
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External Protection Switching
Fast external switching mode, fast switching between inputs also triggered directly from dedicated (SRCSW), Figure This mode activated either holding SRCSW high during reset, writing Reg. Once external protection switching enabled, then value this directly selects either I3/I5 (SRCSW high) I4/I6 (SRCSW low). this mode activated reset pulling SRCSW high, then configures default frequency tolerance I3/I5 I4/I6 (Reg. Reg. 42). these registers subsequently external software, required. Selection either input determined Priority value programmed priority then selected. Similarly, selected programmed priority
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Figure I3/I5 I4/I6 Switching
Priority
accuracy software calibration routine using register cnfg_nominal_frequency (Reg. 3D). example offset crystal could made look like accurate 0.0196 ppm. transition from Free-run Pre-locked occurs when ACS8530 selects reference source.
DPLL
F8530D_006IPSWI3I4I5I6_01
SRCSW
reduced
Pre-locked Mode
ACS8530 will enter Locked state maximum seconds, defined GR-1244-CORE[19] specification, selected reference source good quality. device cannot achieve lock within seconds, reverts Free-run mode another reference source selected.
F8530D_006IPSWI3I4I5I6_01
Priority
When external protection switching enabled, device will operate simple switch. clock monitoring disabled DPLL will simply forced lock indicated reference source. Consequently device will always indicate "locked" state sts_operating register (Reg. bits 2:0).
Locked Mode
Locked mode used when input reference source been selected time lock. When Locked mode achieved, output signal phase locked selected input reference source. priority table determines selected input reference source. When ACS8530 Locked mode, output frequency phase follows that selected input reference source. Variations external crystal frequency have minimal effect output frequency. Only minimum maximum frequency range affected. Note that term phase" applied conventional sense when ACS8530 used frequency translator (e.g., when input frequency 2.048 output frequency 19.44 MHz) input output cycles will constantly moving past each other; however, they will align every period since output frequencies exact multiple kHz.
Modes Operation
ACS8530 three primary modes operation (Free-run, Locked Holdover) supported three secondary, temporary modes (Pre-Locked, Lost-Phase Pre-Locked2). These shown State Transition Diagram, Figure ACS8530 operate Forced Automatic control. reset, ACS8530 reverts Automatic Control, where transitions between states controlled completely automatically. Forced Control invoked configuration, allowing transitions performed under external control. This normal mode operation, provided special occasions such testing, where high degree hands-on control required.
Lost-phase Mode
Lost-phase mode used whenever selected reference source suffers most kinds anomalous behaviour. will stiil trying lock input clock reference, exists. Leaky Bucket Accumulator calculates that anomaly serious, device rejects reference source following transitions takes place: Pre-locked2; known good stand-by source available. Holdover; stand-by sources available.
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Free-run Mode
Free-run mode typically used following power-onreset device reset before network synchronization been achieved. Free-run mode, timing synchronization signals generated from ACS8530 based 12.8 clock frequency provided from external oscillator synchronized input reference source. default, frequency output clock fixed multiple frequency external oscillator, accuracy output clock equal accuracy oscillator. However external oscillator frequency calibrated improve
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Holdover Mode
Holdover mode operating condition device enters when currently selected input source becomes invalid, other valid replacement source available. this mode, device resorts using stored frequency data, acquired when input reference source still valid, control output frequency. Holdover mode, ACS8530 provides timing synchronisation signals maintain Network Element phase locked input reference source. output frequency determined averaged version DPLL frequency when last Locked Mode. Holdover configured operate either: Automatic Mode (Reg. cnfg_input_mode: man_holdover low), Manual Mode (Reg. cnfg_input_mode: man_holdover high).
Automatic Mode Instantaneous
Instantaneous mode, DPLL freezes frequency operating time entering Holdover mode. does this using only internal DPLL integral path value reported Reg. determine output frequency. DPLL proportional path used that recent phase disturbances have minimal effect Holdover frequency. integral value used viewed filtered version locked output frequency over short period time. period being inverse proportion DPLL bandwidth setting.
Manual Mode
Automatic mode, device configured operate using either: Averaged (Reg. cnfg_holdover_frequency, auto_averaging: high) Instantaneous (Reg. cnfg_holdover_frequency, auto_averaging: low).
Averaged
(Reg. cnfg_input_mode, man_holdover high.) Holdover frequency determined value register cnfg_holdover_frequency (Reg. Reg. Reg. 40). This 19-bit signed number, with resolution 0.0003 ppm, which gives adjustment range ppm. This value derived from reading register sts_current_DPLL_frequency (Reg. Reg. Reg. 07), which gives, same format, indication current output frequency deviation, which would read when device locked. required, this value could read external software averaged over time. averaged value could then cnfg_holdover_frequency register, ready setting averaged frequency value when device enters Holdover mode. sts_current_DPLL_frequency value internally derived from Digital Phase Locked Loop (DPLL) integral path, which represents short-term average measure current frequency, depending locked loop bandwidth (Reg. selected. also possible combine internal averaging filters with some additional software filtering. example internal fast filter could used anti-aliasing filter software could further filter this before determining actual Holdover frequency. support this feature, facility read internally averaged frequency been provided. setting Reg. cnfg_holdover_frequency, read_average, value read back from cnfg_holdover_frequency register will filtered value. filtered value available regardless what actual Holdover mode selected. Clearly this results register reading back data that written
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Averaged mode, frequency reported sts_current_DPLL_frequency, Reg. Reg. Reg. filtered internally using Infinite Impulse Response filter, which either: Fast (Reg. cnfg_holdover_frequency, fast_averaging: high), giving filter response point corresponding period approx eight minutes, Slow (Reg. cnfg_holdover_frequency, fast_averaging: low) giving filter response point corresponding period approx minutes.
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Figure Automatic Mode Control State Diagram
Reset
(state 001)
Free-run select
valid standby (main invalid lock 100s
refs evaluated least valid
Reference sources flagged valid when active, in-band have phase alarm set.
valid standby [main invalid (higher-priority valid revertive mode) lock 100s] Pre-locked wait 100s (state 110)
sources continuously checked activity frequency Only main source checked phase. phase lock alarm only raised reference when that reference lost phase whilst being used main reference. micro-processor reset phase lock alarm. source considered have phase locked when been continuously phase lock between seconds.
selected phase locked
Locked keep (state 100) (10) selected source phase locked phase regained valid standby within 100s [main invalid (higher priority valid revertive mode)] (12) valid standby (main invalid lock >100s) valid standby main invalid phase lost main
Pre-locked2 wait 100s (state 101)
(11) valid standby Lost-phase (main invalid wait 100s lock >100s) (state 111)
Holdover select (state 010)
(15) valid standby [main invalid (higher-priority valid revertive mode) lock >100s]
(13) valid standby (main invalid lock >100s)
(14) refs evaluated least valid
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Example: Software averaging eliminate temperature drift.
frequency accuracy Holdover mode meet ITU-T, ETSI Telcordia performance requirements. performance external oscillator clock critical this mode, although only frequency stability important stability output clock Holdover directly related stability external oscillator.
Select Manual Holdover mode setting Reg. cnfg_input_mode, man_holdover high. Select Fast Holdover Averaging mode setting Reg. cnfg_holdover_frequency, auto_averaging high Reg. high. Select able read back filtered output setting Reg. cnfg_holdover_frequency, read_average high. Software periodically reads averaged value from cnfg_holdover_frequency register temperature (not supplied from ACS8530). Software processed frequency temperature places data software look-up table other algorithm. Software writes back appropriate averaged value into cnfg_holdover_frequency register. Once Holdover mode entered, software periodically updates cnfg_holdover_frequency register using temperature information (not supplied from ACS8530).
Mini-holdover Mode
Pre-locked2 Mode
This state very similar Pre-Locked state. entered from Holdover state when reference source been selected applied phase locked loop. also entered device operating Revertive mode higher-priority reference source restored. Upon applying reference source phase locked loop, ACS8530 will enter Locked state maximum seconds, defined GR-1244CORE[19] specification, selected reference source good quality. device cannot achieve lock within seconds, reverts Holdover mode another reference source selected.
Holdover mode described refers state which internal state machine switches result activity frequency alarms, this state reported Reg. avoid DPLL's frequency being pulled result failed input, then DPLL fast mechanism freeze current frequency within cycles input clock source stopping. Under these circumstances DPLL enters Mini-holdover mode; Mini-holdover frequency used being determined Reg. Bits [4:3], cnfg_holdover_frequency, mini_holdover_mode. Mini-holdover mode only lasts until following happens: source been selected, state machine enters Holdover mode, original fault input recovers.
External Factors Affecting Holdover Mode
DPLL Architecture Configuration
Digital gives stable consistent level performance that easily programmed different dynamic behaviour operating range. affected operating conditions silicon process variations. Digital synthesis used generate required SONET/SDH output frequencies. digital logic operates 204.8 that multiplied from external 12.8 oscillator module. Hence best resolution output signals from DPLL 204.8 cycle Additional resolution lower final output jitter provided de-jittering Analog that reduces pk-pk jitter from digital down pk-pk typical final outputs measured broadband (from GHz). This arrangement combines advantages flexibility repeatability DPLL with jitter APLL. DPLLs ACS8530 uniquely very programmable parameters bandwidth (from Hz), damping factor (from 20), frequency acceptance output range (from ppm, typically ppm), input frequency common SONET/SDH spot frequencies) input-to-output phase offset steps ns). There
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external OCXO frequency varying temperature fluctuations room, then instantaneous value different from average value, then possible exceed 0.05 limit (depending extreme temperature fluctuations are). advantageous shield OCXO slow down frequency changes drift external temperature fluctuations.
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requirement understand loop filter equations detailed gain parameters since high level factors such overall bandwidth directly registers microprocessor interface. external critical components required either internal DPLLs APLLs, providing another advantage over traditional discrete designs. DPLL similar structure DPLL, since only providing clock synthesis input output frequency translation function, with defined requirement jitter attenuation input phase jump absorption, then bandwidth limited high does incorporate many Phase Buildout adjustment facilities DPLL.
DPLL Main Features
Programmable damping factor optional faster locking peaking control. Factors 1.2, 2.5, Multiple phase lock detectors. Multi-cycle phase detection locking programmable ±8192 improves jitter tolerance direct lock mode. DS3/E3 support (44.736 34.368 MHz) same time OC-N rates from jitter E1/DS1 options same time OC-N rates from Frequencies E1/DS1 including supported. jitter outputs TO7. DPLL Independent FrSync DPLL. phase detector DPLL measure input phase difference between inputs. structure PLLs shown later Figure section output clock ports. That section also details DPLLs particular output frequencies configured. following sections detail some component parts DPLL.
main features DPLL are: Programmable DPLL bandwidth steps from steps. Programmable damping factor optional faster locking peaking control. Factors 1.2, 2.5, Multiple phase lock detectors Input output phase offset adjustment (Master/Slave), resolution step size phase offset source switching disturbance down Detection phase jump current source: programmable limit from Optional automatic Phase Build-out event detected input phase jump Multi-cycle phase detection locking, programmable ±8192 improves jitter tolerance direct lock mode Holdover frequency averaging with choice Average times Order anti-aliasing filter Readout filtered value. Multiple outputs supported. jitter MFrSync kHz) FrSync kHz) outputs. with programmable pulse width polarity.
DPLL Main Features
Phase Detectors
Phase Frequency detector used compare input feedback clocks. This operates input frequencies 77.76 MHz. whole DPLL operate spot frequencies from 77.76 (155.52 internally divided down 77.76 MHz). common arrangement however Lock8k mode (See Reg. where input frequencies divided down internally. Marginally better MTIE figures possible direct lock mode more regular phase updates. This direct locking capability unique features ACS8530. multi-phase detector (patent pending) approach used order give infinitesimally small input phase resolution combined with large jitter tolerance. following phase detectors used: Phase frequency detector range). Early/ Late Phase detector fine resolution. multi-cycle phase detector large input jitter tolerance 8191 UI), which captures remembers phase differences many cycles between input feedback clocks.
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main features DPLL are: Programmable DPLL bandwidth steps from
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phase detectors configured immune occasional missing input clock pulses using nearest edge detection capture) normal phase capture range which gives frequency locking. device will automatically switch nearest edge locking when detected that phase lock been achieved. possible disable selection nearest edge locking Reg. this setting, frequency locking will always enabled. balance between first types phase detector employed adjusted registers default settings should sufficient modes. Adjustment these settings affects only small signal overshoot bandwidth. multi-cycle phase detector enabled Reg. range exponentially increasing steps from 8191 Reg. bits [3:0]. When this detector enabled keeps track correct phase position over many cycles phase difference give excellent jitter tolerance. This provides alternative switching Lock8k mode method achieving high jitter tolerance. additional control (Reg. enables multiphase detector value used final phase value part DPLL loop. When enabled setting high, multi cycle phase value will used loop gives faster pull (but more overshoot). characteristics loop will similar Lock8k mode where again large input phase differences contribute loop dynamics. Setting only uses figure degrees loop will give slower pullin gives less overshoot. final phase position that loop pull still tracked remembered multi-cycle phase detector either case.
4D). Phase lock lost used determine whether switch nearest edge locking whether acquisition normal bandwidth settings DPLL. Acquisition bandwidth used faster pull from unlocked state. coarse phase lock detector detects phase differences cycles between input feedback clocks, where Reg. bits 3:0; same register that used coarse phase detector range, since these functions hand hand. This detector used case where required that phase loss indication given reasonable amounts input jitter fine phase loss detector disabled coarse detector used instead.
Damping Factor
default damping factor ensures that jitter gain peaking jitter transfer characteristic always below higher damping factor give example <0.1 jitter gain peaking.
Local Oscillator Clock
Master system clock ACS8530 should provided external clock oscillator frequency 12.80 MHz. clock specification important meeting AT&T, ITU/ETSI Telcordia performance requirements Holdover mode. Telcordia specifications require non-temperature-related drift less than drift over temperature range
Telcordia GR-1244 Specification
Table Stratum Specification
Initial Offset Offset Over Temperature (Note Drift Rate Ageing 10-9 10-9 (Note 1.16 10-14/second (Note 10-9/day)
Phase Lock Detection
Phase lock detection handled several ways. Phase loss triggered from: fine phase lock detector, which measures phase between input feedback clock. coarse phase lock detector, which monitors whole cycle slips. Detection that DPLL frequency. Detection activity input. Each these sources phase loss indication individually enabled registers bits (see Reg.
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Notes: Figure quoted long-term drift over range short-term (<96 hours) range rate drift °C/hr. (ii) Determined external
Please contact Semtech information crystal oscillator suppliers.
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Crystal Frequency Calibration
There phase shift across ACS8530 between selected input reference source output clock over time, mainly caused frequency wander external oscillator module. Higher stability will give better performance MTIE. oscillator becomes more critical DPLL bandwidth near below since rate change DPLL slow compared rate change oscillator frequency. Shielding OCXO TCXO futher slow down rate change temperature hence frequency, thus improving output wander performance. phase shift vary over time will constrained within specified limits. phase shift characterised using parameters, MTIE (Maximum Time Interval Error) TDEV (Time Deviation) which, although being specified relevant specifications, differ acceptable limits each one. Typical measurements ACS8530 shown Figure Locked mode operation. Figure shows typical measurement Phase Error accumulation Holdover mode operation. required performance phase variation during Holdover specified several ways depends relevant specification (See ``References'' page 145) example: ETSI 462-5[4], Section 9.1, requires that short-term phase error during switchover (i.e. Locked Holdover Locked) limited accumulation rate greater than 0.05 during second interval. [3]ETSI 462-5[4], Section 9.2, requires that long-term phase error Holdover mode should exceed {(a1+a2)S+0.5bS2+c} where ns/s (allowance initial frequency offset) 2000 ns/s (allowance temperature variation) 1.16 10-4 ns/s2 (allowance ageing) (allowance entry into Holdover mode). Elapsed time after loss external ref. input. ANSI Tin1.101-1999[1], Section 8.2.2, requires that phase variation limited that more than slips each) occur during first Holdover. This requires freq. accuracy better than: ((24 60)+(255 125µs))/(24 0.37 ppm. Temperature variation restricted, except within normal bounds
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absolute crystal frequency accuracy less important than stability since frequency offset compensated adjustment register values This allows calibration compensation crystal frequency variation away from nominal value. adjustment would sufficient cope with most crystals, fact range order magnitude larger register locations. setting conf_nominal_frequency register allows this adjustment. increase register value increases output frequencies 0.0196 each step. default register value decimal) 39321 (9999 hex) offset. minimum maximum offset range register 65535 dec, giving adjustment range -786 +524 output frequencies, 0.0196 steps. Example: crystal oscillating 12.8 ppm, then calibration value register give adjustment output frequencies compensate crystal inaccuracy, would 39321 0.0196) 39066 (dec) 989A (hex).
Output Wander
Wander jitter present output clocks dependent magnitude wander jitter selected input reference clock Locked mode). internal wander jitter transfer characteristic Locked mode). jitter local oscillator clock. wander local oscillator clock Holdover mode). Wander jitter treated different ways reflect their differing impacts network design. Jitter always strongly attenuated, whilst wander attenuation varied suit application operating state. Wander jitter attenuation performed using digital phase locked loop (DPLL) with programmable bandwidth. This gives transfer characteristic pass filter, with programmable pole. sometimes necessary change filter dynamics suit particular circumstances example being when locking source, filter opened reduce locking time then tightened again remove wander. change between different bandwidths locking acquisition handled automatically within ACS8530.
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Figure Maximum Time Interval Error Time Deviation Output Port
MTIE G.813 option Constant temperature wander limit
TDEV G.813 option Constant temperature wander limit
F8530D_027MtieTdevCombF6_01
Figure
Phase Error Accumulation Output Port Holdover Mode
10000000
Scale
1000000 Phase Error (ns)
Permitted Phase Error Limit
100000
10000
Typical measurement, 25°C constant temperature
1000
1000
10000
100000 Observation interval
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[19]Telcordia Section 5.2, shows that initial frequency offset permitted entering Holdover, whilst drift over temperature allowed; allowance permitted other effects. G.822[12], Section 2.6, requires that slip rate during category operation (interpreted being applicable Holdover mode operation) limited less than slips each) hour. ((60 µs))/(60 60)) 1.042 GR.1244.CORE[19],
supply voltage both cause drifts operating frequency, does ageing. These effects must limited careful selection suitable component local oscillator, specified section Local Oscillator Clock.
Phase Build-out
Phase Transient Response Holdover
Jitter Wander Transfer
ACS8530 programmable jitter wander transfer characteristic. This DPLL bandwidth. jitter transfer attenuation point range from steps. wander jitter transfer characteristic shown Figure Wander local oscillator clock will have significant effect output clock whilst Locked mode, provided that DPLL bandwidth high enough that DPLL compensate quickly enough frequency changes crystal. Free-run Holdover mode wander crystal more significant. Variation crystal temperature Figure
Phase Build-out (PBO) function minimise phase transients output clock during input reference switching. currently selected input reference clock source lost (due short interruption, frequency detection, complete loss reference) second, next highest priority reference source will selected, event triggered. ITU-T G.813[11] states that maximum allowable shortterm phase transient response, resulting from switch from clock source another, with Holdover mode entered between, should maximum over second interval. maximum phase transient jump should less than rate change less than Holdover performance should better than 0.05 ppm. ACS8530 performance well within this requirement. typical phase disturbance clock reference source switching will less than ACS8530.
DPLL Wander Jitter Measured Transfer Characteristics (Jitter pk-pk)
F8530D_005WANJITTXFR_05.bmp
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requirement, specified Telcordia GR-1244CORE, Section 5.7, that phase transient greater than occurring less than seconds should absorbed Stratum level clocks. ACS8530 configured trigger event input phase transient between programmable, Reg. When Phase Build-out event triggered, device enters temporary Holdover state. When this temporary state, phase input reference measured, relative output. device then automatically accounts measured phase difference adds appropriate phase offset into DPLL compensate. Following event, whatever phase difference change input, output phase transient minimized greater than ACS8530, enabled, disabled frozen using microprocessor interface. default, enabled. When enabled, also frozen current offset setting). device will then ignore further events occurring subsequent reference switch, maintain current phase offset. disabled while device Locked mode, there phase shift output clocks DPLL locks back degrees phase error. rate phase shift will depend programmed bandwidth. Enabling whilst Locked stated will also trigger event.
Phase Offset
phase adjustment actually changes phase position feedback clock that DPLL adjusts output clock phases compensate. rate change phase therefore related DPLL bandwidth. DPLL track large instant changes phase, either Lock8k mode should coarse phase detector should enabled. Register cnfg_phase_offset Reg. controls output phase, which only used when Phase Build-out (Reg.
Input Wander Jitter Tolerance
ACS8530 compliant requirements relevant standards, principally Recommendation G.825[15], ANSI DS1.101-1999[1], Telcordia GR1244[19], GR253[17], G812[10], G813[11] 462-5 (1996)[4]. reference clock inputs have tight frequency tolerance generous jitter tolerance. Pull-in, hold-in pull-out ranges specified Table Minimum jitter tolerance masks specified Figures Tables respectively. ACS8530 will tolerate wander jitter components greater than those shown Figure Figure limit determined combination apparent long-term frequency offset caused wander eye-closure caused jitter (the input source will rejected offset pushes frequency outside hold-in range long enough detected, whilst signal will also rejected closes sufficiently affect signal purity). Either Lock8k mode, extended phase capture ranges should engaged high jitter tolerance according these masks. reference clock ports monitored quality, including frequency offset general activity. Single short-term interruptions selected reference clocks cause arrangements, whilst longer interruptions, multiple, short-term interruptions, will cause rearrangements, will frequency offsets which sufficiently large sufficiently long cause loss-of-lock phase-locked loop. failed reference source will removed from priority table declared unserviceable, until perceived quality been restored acceptable level.
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order minimise systematic (average) phase error PBO, Phase Offset programmed 0.101 steps cnfg_phase_offset_pbo register, Reg.72. range programmable phase offset restricted This used eliminate accumulation phase shifts direction.
Input Output Phase Adjustment
When Phase Build-out off, such that system tries align outputs inputs position, there mechanism provided ACS8530 precise fine tuning output phase position with respect input. This used compensate circuit board wiring delays. output phase adjusted steps positive negative direction.
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Table Input Reference Source Jitter Tolerance
Jitter Tolerance Frequency Monitor Acceptance Range Frequency Acceptance Range (Pull-in) Frequency Acceptance Range (Hold-in) Frequency Acceptance Range (Pull-out)
G.703[6] G.783[9] G.823[13] GR-1244CORE[19] Notes: frequency acceptance generation range will around required frequency when external crystal frequency accuracy within tolerance ppm. (ii) fundamental acceptance range generation range with exact external crystal frequency 12.8 MHz. This default DPLL range, range also programmable from 0.08 steps. 16.6 (see Note (i)) (see Note (ii)) (see Note (i)) (see Note (ii)) (see Note (i)) (see Note (ii))
Figure
Minimum Input Jitter Tolerance (OC-3/STM-1)
F8530D_003MINIPJITTOLOC3STM1_02 100%
Jitter Wander Frequency (log scale)
F8530_003MINIPJITTOLOC3STM1_02
Note.For inputs supporting G.783[9] compliant sources.)
Table Amplitude Frequency Values Jitter Tolerance (OC-3/STM-1)
Slevel Peak peak amplitude (unit Interval) STM-1 2800 Frequency (Hz) 19.3
0.15
15.6 0.125
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Figure Minimum Input Jitter Tolerance (DS1/E1)
Peak-to-peak Jitter Wander Amplitude (log scale)
F8530D_004MINIPJITTOLDS1E1_02
Jitter Wander Frequency (log scale)
F8530D_004MINIPJITTOLDS1E1_02
Table Amplitude Frequency Values Jitter Tolerance (DS1/E1)
Type Spec. Amplitude pk-pk) GR-1244-CORE[19] G.823[13] Frequency (Hz)
Using DPLLs Accurate Frequency Phase Reporting
frequency monitors ACS8530 perform frequency monitoring with programmable acceptable limit 60.96 ppm. resolution measurement measured frequency read back from Reg. with channel selection Reg. more accurate measurement both frequency phase, DPLLs their phase detectors, used monitor both input frequency phase. DPLL always monitoring currently locked source, path used then DPLL used roving phase frequency meter. software control could switched monitor each input turn both phase frequency reported with very fine resolution. registers sts_current_dpll_frequency (Reg. Reg. Reg. report frequency either DPLL with respect external crystal frequency (after calibration Reg. used). selection DPLL reporting made Reg. value 19-bit signed number with representing 0.0003 (range ppm). This value actually integral path value DPLL, such corresponds averaged measurement input
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frequency, with averaging time inversely proportional DPLL bandwidth setting. Reading this regularly show currently locked source varying value e.g. frequency wander input. input phase, seen DPLL phase detector, read back from register sts_current_phase, Reg. DPLL phase detector reporting again controlled Reg. corresponds approximately degrees phase difference. DPLL this will reporting phase difference between input internal feedback clock. phase result internally averaged filtered with attenuation point approximately DPLL bandwidths, example, this measured phase information from DPLL gives input phase wander frequency band from example This could used give crude input MTIE measurement observation period approximately 1000 seconds using external software. addition, DPLL phase detector used make phase measurement between inputs. Reg. used switch input phase detector over current input. other phase detector input remains connected selected input source, selected source forced Reg.
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bits 3:0, changed priority (Reg. when Reg. Consequently phase detector from DPLL could used measure phase difference between currently selected source stand-by source, could used measure phase wander standby sources with respect current source selecting each input sequence. MTIE TDEV calculation could made each input external processing.
expected that will output internal operations. phase outputs from path (TO8 TO9) will aligned, unless outputs locked outputs. many applications, clocks supplied into system required aligned only frequency, also phase between Master Slave devices. This ensures minimal disturbance when clock sink switches between Master Slave. order ensure that outputs ACS8530s always aligned frequency phase, procedures Table should followed. order maintain conditions outlined Table necessary software systems maintain monitoring control functions. These monitoring functions should either poll device respond interrupts order maintain correct settings within devices. Please refer descriptions registers mentioned Table also Regs more details these associated settings. also Application Note AN-SETS-7. Table MSTSLVB Operation
MSTSLVB Master Feature Priority input Setting programmed (program ensure gets disabled) programmed register. Reason Make sure that designated Master device cannot lock output Slave device. system requires PBO, then this being enabled Master will give overall system performance with PBO. slave only needs track Master PBO). Revertive behaviour Master Master/Slave system will define overall Revertive behaviour system. Device selects locked acquisition bandwidth.
Configuration Redundancy Protection
When ACS8530 devices used redundancy-protection scheme within Network Element (NE), will designated Master, Slave. Table Align Outputs ACS8530s
Action possible, device (the nominated Slave) should lock other device (the nominated Master). programmed priorities within devices should same, except fact that (1)the Master output designated highest priority input Slave.(2) Slave output designated zero priority (disabled) Master. (Reg. input detected invalid device should disabled within other device. (Reg. 0E/0F 30/31) Phase Build-out should disabled Slave whilst locked Master. This will ensure that phase Slave locked phase Master. also enables Phase offset control register compensate delays between Master Slave. This will ensure that Slave locks Master although have been locked another source previously. This ensures that transient occurring output Master followed closely possible Slave. Result With Slave locked Master, their output frequencies will guaranteed same. These actions ensure that Master device fails, Slave device will switch lock same source that Master locked before failed.
Phase Build-out
Revertive mode should enabled.
Revertive mode
programmed register.
bandwidth Slave should higher than that Master recommended configure slave with highest supported bandwidth).
DPLL bandwidth
programmed register (automatic manual).
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Table MSTSLVB Operation (cont.)
MSTSLVB Slave Feature Priority input Setting (highest priority). Reason When Slave, this input designated that connected output Master. This ensures that Slave locks Master with minimum phase offset possible. This ensures that Slave always locks Master when available. higher bandwidth Slave ensures closer phase tracking.
Reg. 0F), from device into cnfg_sts_remote_sources_valid register (Reg. other. This will ensure that device considered invalid device also considered invalid other. failure Master does occur, this will ensure that Slave will always select reference that Master locked
Phase Build-out
Disabled.
Generation Master Slave ACS8530
specified I.T.U., there need align phases outputs Master Slave devices. fully redundant system, there need, however, ensure that devices select same reference source. there need guarantee alignment phase outputs, Slave devices input does need lock Masters output, only needs ensure that locks same external reference source. actions aligning priority tables available reference sources performed outputs will equally valid outputs. only difference being that input connected Master's output disabled path (allowing only lock external references). This easily achieved paths have separate programmed priorities. There defined Holdover requirement path.
Revertive mode
Enabled
DPLL bandwidth
Forced acquisition bandwidth setting.
direct hardware control Master Slave operation Master/Slave control (MSTSLVB) used externally control some these functions according Table These functions also controlled software. Whilst Master Slave outputs could crossconnected connected input alternative device, input been chosen input controlled MSTSLVB pin.
Alignment Output Clock Phases Master Slave ACS8530
When ACS8530 locked reference source frequency output clocks frequency will inphase with reference source (with Phase Build-out disabled). output clocks from ACS8530 derived from same frequency, frequency greater than output will "falling edge aligned" with output frequency frequency less than will effectively division possible. Similarly output clocks will phase-related input. effect this relationship that Master Slave devices cross-connected with 19.44 clocks, their output clocks 19.44 MHz, 38.88 MHz, 77.76 MHz, 155.52 311.04 will aligned between devices. However, their outputs 6.48 MHZ, 1.544 MHz, 2.048 MHz, etc. would necessarily aligned. Whilst most applications would affected non-alignment most these clocks, non-alignment and/or cause framing errors.
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Alignment Priority Tables Master Slave ACS8530
redundant system where Slave normally locked Master device, Master device fails Slave device must revert locking same external reference that Master locked This will ensure that minimum disturbance, both frequency phase, created output Slave device failure Master device. stated previously (Table recommended that programmed priorities reference sources same both devices, apart from Master/Slave cross-connect inputs. Both devices also monitor their reference sources determine validity each source. recommended that availability valid sources also aligned between devices. This achieved writing value, reported sts_sources_valid
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There ways align and/or outputs: External syncing function, directly locking Slave from Master. directly locking Slave (MFrSync) output Master, frequencies output from Slave will phase alignment with same frequency generated from Master. Slave directly locked (FrSync) output from Master, then frequencies except MFrSync outputs will alignment. using external syncing function then signals need interconnected between Master Slave: clock and, Sync signal. This requires some configuration enhancements. Sync signal locked sampled using reference clock used realign generated outputs. generated outputs still always locked reference clock related each other. Details Master Slave interconnection wiring software configuration found refer application note AN-SETS-2. following section describes resynchronization operation MFrSync SYNC2K input.
Safe sampling SYNC2K input achieved using currently selected clock reference source input sampling. This based principle that FrSync alignment being used Slave device that locked clock reference Master device that also providing SYNC2K input. Phase Build-out mode should (Reg. MFrSync output from Master device falling edge aligned with falling edge other output clocks, hence SYNC2K input normally sampled rising edge current input reference clock, order provide most margin. Some modification expected timing SYNC2K with respect reference clock achieved Reg. bits 1:0. This allows SYNC2K input arrive either half reference clock cycle early half cycle late, hence allowing safe sampling margin maintained. different sampling resolution used depending input reference frequency setting Reg. cnfg_sync_phase. With this low, SYNC2K input sampling 6.48 resolution, this being preferred reference frequency lock from Master, conjunction with SYNC2K kHz, since gives most timing margin sampling aligns higher rate OC-3 derived clocks. When high SYNC2K have sampling resolution either 19.44 (when current locked reference 19.44 MHz) 38.88 (all other frequencies). This would allow instance 19.44 pair used Slave synchronization Line card synchronization. Reg. indep_Fr/MFrSync controls whether MFrSync FrSync outputs keep their precise alignment with other output clocks. When indep_Fr/MFrSync Reg. FrSyncs other higher rate clocks independent their alignment falling 8kHz edge maintained. This means that when Sync_OC-N_rates high, OC-N rate dividers clocks also synchronised SYNC2K input. change phase position SYNC2K, this could result shift phase 6.48 output clock when 19.44 precision used SYNC2K input. avoid disturbing output clocks only align MFrSync FrSync outputs, chosen level precision, then independent Frame Sync mode used (Reg. Edge alignment FrSync output with other clocks outputs then change depending SYNC2K sampling precision used. example with
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MFrSync FrSync Alignment-SYNC2K
SYNC2K input (pin monitored ACS8530 consistent phase correct frequency does pass these quality checks, alarm flag raised (Reg. bit7 Reg. check consistent phase involves checking that each input edge within expected timing window. window size Reg. bits 6:4. internal detector senses that correct SYNC2K signal present only then allows signal resynchronize internal dividers that generate FrSync MFrSync outputs. This sequence avoids spurious resynchronizations that otherwise occur with connections disconnections SYNC2K input. SYNC2K input will normally frequency, only falling edge used. however frequencies without change register setups. Only alignment will achieved this case.
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19.44 reference input clock bits both high (indendent mode Sync OC-N rates), then FrSync output will still align with 19.44 output with 6.48 output clock. FrSync MFrSync outputs always come from DPLL path. 2kHz 8kHz outputs also produced outputs. These come from either DPLL from DPLL, controlled Reg. required, this allows DPLL used separate FrSync MFrSync path with input Frame Sync outputs.
input reference either passed directly pre-divider (not shown) produce reference input. feedback 77.76 either divided synthesized generate locking frequency. Digital Frequency Synthesis (DFS) technique generating output frequency using higher frequency system clock (204.8 case 77.76 synthesis). However, edges output clock ideally placed time, since edges output clock will aligned active edge system clock. This will mean that generated clock will inherently have jitter equivalent period system clock. forward block uses clocked 204.8 system clock synthesize 77.76 and, therefore, inherent pk-pk jitter. There option APLL, feedback APLL, filter this jitter before 77.76 used generate feedback locking frequency feedback block. This analog feedback option allows lower jitter feedback signal give maximum performance. digital feedback option present that when output path switched digital feedback paths remain synchronized. forward block also block that handles Phase Build-out phase offset programmed into device. Hence, forward output blocks locked frequency offset phase. output block also uses 204.8 system clock always generates 77.76 output clocks (with inherent jitter). This another block output APLL. frequency output block used produce three frequencies; them, Digital1 Digital2, available selection produced outputs TO1TO7, third frequency produce multiple E1/DS1 rates filtering APLLs. input clock output block either 77.76 from output APLL (post jitter filtering) 77.76 direct from output DFS. Utilizing clock from output APLL will result lower jitter outputs from output block.
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Output Clock Ports
device supports main output clocks, pair secondary Sync outputs, FrSync MFrSync. main output clocks, independent each other individually selectable. secondary output clocks, FrSync MFrSync, derived from either frequencies main output clocks selectable from range predefined spot frequencies variety output technologies supported, defined Table
Output Frequency Selection Configuration
output frequency many outputs controlled number inter-dependent parameters. These parameters control selections within various blocks shown Figure ACS8530 contains main DPLL/APLL paths. Whilst they largely independent, there number ways which these structures interact. Figure shows expansion original Block Diagram (Figure paths.
DPLL APLLs
DPLL always produces 77.76 regardless either reference frequency (frequency input device) locking frequency (frequency input DPLL Phase Frequency Detector (PFD)).
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Figure Block Diagram
Lock_T4_to_T0 Sts_Current_Phase Control T4_DPLL_Frequency T4_APLL_for_T0
Reference Input
Loop Filter
T0_DPLL_Freq
Forward
T4_Dig_Feedback
Output APLL
Output Dividers
F8530D_017PLLBlockDia_03.eps
DPLL
Locking Frequency
Feedback
T4_Op_From_TO
/TO9
T0_DPLL_Frequency Control
Output
Phase Offset
Sts_Current_Phase Reference Input
Output
Output APLL
Output Dividers
TO10/TO11 Feedback APLL
Loop Filter
Forward
T0_DPLL_Frequency Control
Locking Frequency
Feedback
DPLL
Analog
F8530D_017BLOCKDIA_04
However, when input APLL taken from output block, input that block comes directly from output block that "loop" created. output APLL multiplying filtering. input output APLL either 77.76 from output block alternative frequency from output block (offering 77.76 MHz, 12E1, 16E1, 24DS1 16DS1). frequency from output APLL four times input frequency i.e. 311.04 when used with 77.76 input. output APLL subsequently divided these available TO1-TO7 outputs.
DPLL APLL
204.8 system clock will have inherent jitter feedback also facility able post APLL (jitter-filtered) clock generate feedback locking frequency. Again, this will give maximum performance using jitter feedback. output APLL block also multiplying filtering. input output APLL come either from forward block from path. input output APLL programmed following: Output from forward block (12E1, 24DS1, 16E1, 16DS1, DS3, OC-N), 12E1 from 16E1 from 24DS1 from 16DS1 from frequency generated from output APLL block four times input frequency i.e. 311.04 when used with 77.76 input. output APLL
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path much simpler than path. This path offers Phase Build-out phase offset. input used either lock reference clock input independent path, lock path. Unlike path, forward block does always generate 77.76 MHz. possible frequencies listed table. Similarly path, output forward block generated using clocked
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subsequently divided these available TO1-TO7 outputs. outputs driven from either path. TO10 TO11 outputs always generated from path. Reg. selects whether source outputs available from TO1-TO7 derived from either paths.
Output Frequency Configuration Steps
Refer Table Frequency Divider Look-up, choose output frequencies- each path, Only frequencies generated simultaneously from each path. Refer Table determine required APLL frequency support frequency set. Refer Table APLL Frequencies, Table APLL Frequencies, determine what mode paths need configured considering output jitter level. Refer Table output Frequency Selection, column headings Table Frequency Divider Look-up, select appropriate frequency from either APLLs each output required.
output frequency selection performed following steps: Does application require path independent path not. not, then path utilized produce extra frequencies locked path. Table Output Reference Source Selection Table
Port Name T010 T011 Output Port Technology TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS TTL/CMOS LVDS/PECL (LVDS default) PECL/LVDS (PECL default) TTL/CMOS TTL/CMOS TTL/CMOS
Frequencies Supported
Frequency selection Table Table
64/8 (composite clock, kHz), fixed frequency. Fixed frequency, either 1.544 2.048 MHz. FrSync, programmable pulse width polarity, Reg. MFrSync, programmable pulse width polarity, Reg.
Note.1.544 MHz/2.048 shown SONET/SDH respectively. SONSDHB controls default, when High SONET default
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Table Output Frequency Selection
Frequency (MHz, unless stated otherwise) DPLL Mode DPLL Mode APLLInput Jitter Level (typ) (ps) 1.536 1.536 1.544 1.544 1.544 1.544 2.048 2.048 2.048 2.048 2.048 2.048 2.048 2.059 2.059 2.059 2.316 2.316 2.731 2.731 2.731 2.796 3.088 3.088 3.088 3.088 3.088 (not TO6) (not TO6) (not TO4/TO5) (not TO6) (not TO4/TO5) (not TO4/TO5) (not TO4/TO5) (not TO4/TO5) (not TO6) (not TO4/TO5) (not TO4/TO5) (not TO4/TO5) (not TO4/TO5) 77.76 Analog Select DPLL Select DPLL 12E1 Select DPLL 1400 1400 Pk-Pk (ns) 0.75 0.75 0.75 0.75 0.75
digital feedback mode 77.76 Analog
digital feedback mode 12E1 mode 16DS1 mode
Select DPLL 16DS1 Select DPLL Select DPLL 12E1 Select DPLL Select DPLL 16E1 Select DPLL 3800 3800 3800 3800
Digital1 (not TO7) Digital2 (not TO6) 77.76 Analog
Digital1 (not TO7) Digital2 (not TO6) digital feedback mode 12E1 mode 12E1 mode 16E1 mode
Digital1 (not TO7) Digital2 (not TO6) 77.76 Analog
Digital1 (not TO7) Digital2 (not TO6) digital feedback mode 16DS1 mode 16E1 mode 24DS1 mode 16DS1 mode 24DS1 mode 16E1 mode mode 24DS1 mode
Select DPLL 16DS1 Select DPLL
Select DPLL 24DS1 Select DPLL Select DPLL 16E1 Select DPLL Select DPLL
Select DPLL 24DS1 3800 3800
Digital1 (not TO7) Digital2 (not TO6) 77.76 Analog
Digital1 (not TO7) Digital2 (not TO6) digital feedback mode
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Table Output Frequency Selection (cont.)
Frequency (MHz, unless stated otherwise) DPLL Mode DPLL Mode APLLInput Jitter Level (typ) (ps) 3.728 4.096 4.096 4.296 4.86 5.728 6.144 6.144 6.144 6.176 6.176 6.176 6.176 6.176 6.48 6.48 6.48 8.192 8.192 8.192 8.192 8.192 8.192 8.235 9.264 9.264 9.264 10.923 11.184 12.288 12.288 (not TO6) (not TO6) Digital1 (not TO7) Digital2 (not TO6) 77.76 Analog mode Select DPLL Select DPLL 3800 3800 Pk-Pk (ns) 0.75 0.75 0.75
Digital1 (not TO7) Digital2 (not TO6) digital feedback mode (not TO4/TO5) (not TO4/TO5) 12E1 mode 16DS1 mode Digital1 (not TO7) Digital2 (not TO6) 77.76 Analog mode
77.76 mode Select DPLL mode 12E1 mode 16DS1 mode Select DPLL Select DPLL Select DPLL 12E1 Select DPLL
Select DPLL 16DS1 3800 3800 3800 3800
Digital1 (not TO7) Digital2 (not TO6) digital feedback mode 77.76 analog 77.76 digital 12E1 mode 16E1 mode Digital1 (not TO7) Digital2 (not TO6) 77.76 Analog
77.76 mode Select DPLL 16E1 mode Select DPLL Select DPLL 16E1 Select DPLL
Digital1 (not TO7) Digital2 (not TO6) digital feedback mode 16DS1 mode 24DS1 mode 16E1 mode 12E1 mode 24DS1 mode mode 12E1 mode
Select DPLL 24DS1 Select DPLL Select DPLL
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Table Output Frequency Selection (cont.)
Frequency (MHz, unless stated otherwise) DPLL Mode DPLL Mode APLLInput Jitter Level (typ) (ps) 12.288 12.352 12.352 12.352 12.352 24DS1 mode 16DS1 mode 16DS1 mode Select DPLL 12E1 Select DPLL Pk-Pk (ns) 0.75 0.75 0.75 0.75 0.75
Select DPLL 16DS1 Select DPLL Select DPLL 16E1 Select DPLL Select DPLL 3800 3800 3800 3800
12.352 Digital1 (not TO7) Digital2 (not TO6) 77.76 Analog
12.352 Digital1 (not TO7) Digital2 (not TO6) digital feedback mode 16.384 16.384 16.384 16.384 12E1 mode 16E1 mode 16E1 mode
16.384 Digital1 (not TO7) Digital2 (not TO6) 77.76 Analog
16.384 Digital1 (not TO7) Digital2 (not TO6) digital feedback mode 16.469 17.184 18.528 18.528 18.528 19.44 19.44 19.44 21.845 22.368 24.576 24.576 24.576 24.704 24.704 24.704 24.704 25.92 16DS1 mode 24DS1 mode 77.76 analog 77.76 digital 16E1 mode 12E1 mode 24DS1 mode 16DS1 mode 77.76 analog mode 24DS1 mode 77.76MHz mode mode 12E1 mode 16DS1 mode
Select DPLL 24DS1 Select DPLL Select DPLL Select DPLL Select DPLL 12E1 Select DPLL
Select DPLL 16DS1
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Table Output Frequency Selection (cont.)
Frequency (MHz, unless stated otherwise) DPLL Mode DPLL Mode APLLInput Jitter Level (typ) (ps) 25.92 32.768 32.768 32.768 34.368 37.056 37.056 37.056 38.88 38.88 38.88 44.736 49.152 (TO4/TO5 only) 49.152 (TO4/TO5 only) 49.152 (TO6/TO7 only) 49.408 (TO4/TO5 only) 49.408 (TO4/TO5 only) 49.408 (TO6/TO7 only) 51.84 51.84 65.536 (TO4/TO5 only) 65.536 (TO4/TO5 only) 65.536 (TO6/TO7 only) 68.736 74.112 74.112 74.112 77.76 77.76 77.76 89.472 (TO4/TO5 only) (TO4/TO5 only) (TO4/TO5 only) (TO6/TO7 only) 77.76 digital 16E1 mode 24DS1 mode 77.76 analog 77.76 digital 12E1 mode 16DS1 mode 77.76 analog 77.76 digital 16E1 mode 24DS1 mode 77.76 analog 77.76 digital 16E1 mode mode 24DS1 mode Select DPLL Select DPLL 16E1 Select DPLL Select DPLL Pk-Pk (ns) 0.75 0.75 0.75 0.75 0.75 0.75
Select DPLL 24DS1
77.76 mode Select DPLL mode 12E1 mode 16DS1 mode 16E1 mode mode 24DS1 mode Select DPLL Select DPLL Select DPLL 12E1 Select DPLL
Select DPLL 16DS1 Select DPLL Select DPLL 16E1 Select DPLL Select DPLL
Select DPLL 24DS1
77.76 mode Select DPLL mode Select DPLL
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Table Output Frequency Selection (cont.)
Frequency (MHz, unless stated otherwise) DPLL Mode DPLL Mode APLLInput Jitter Level (typ) (ps) 98.304 (TO6 only) 98.816 131.07 137.47 (TO6 only) (TO6 only) (TO4/TO5 only) 12E1 mode 16DS1 mode 16E1 mode 24DS1 mode 77.76 analog 77.76 digital 77.76 analog 77.76 digital mode Select DPLL Pk-Pk (ns) 0.75
148.22 (TO6 only) 155.52 (TO4/TO5 only) 155.52 (TO6/TO7 only) 155.52 (TO6/TO7 only) 311.04 311.04 (TO6 only) (TO6 only)
77.76 mode Select DPLL
Table Frequency Divider Look-up
APLL Frequency 311.04 274.944 178.944 148.224 131.072 98.816 98.304 APLL/2 155.52 137.472 89.472 74.112 65.536 49.408 49.152 APLL/4 77.76 68.376 44.736 37.056 32.768 24.704 24.576 APLL/6 51.84 24,704 21.84533 16.46933 16.384 APLL/8 38.88 34.368 22.368 18.528 16.384 12.352 12.288 APLL/12 25.92 12.352 10.92267 8.234667 8.192 APLL/16 19.44 17.184 11.184 9.264 8.192 6.176 6.144 APLL/48 6.48 5.728 3.728 3.088 2.730667 2.058667 2.048 APLL/64 4.86 4.296 2.796 2.316 2.048 1.544 1.536
Note.All frequencies
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Table APLL Frequencies
APLL Frequency 311.04 311.04 98.304 131.072 148.224 98.816 Mode Normal (digital feedback) Normal (analog feedback) 12E1 (digital feedback) 16E1 (digital feedback) 24DS1 (digital feedback) 16DS1 (digital feedback) DPLL Frequency Control Register Bits Reg. Bits[2:0] <0.5 <0.5 Output Jitter Level (pk-pk)
Table APLL Frequencies
APLL Frequency 311.04 311.04 98.304 131.072 148.224 98.816 274.944 178.944 98.304 131.072 148.224 98.816 Mode Forward DPLL Freq Control Frequency Register Bits (MHz) Reg. Bits [2:0] 77.76 77.76 24.576 32.768 37.056 (2*18.528) 24.704 68.736 (2*34.368) 44.736 APLL Enable Register Reg. Freq APLL Register Bits Reg. Bits [5:4] Output Jitter Level (pk-pk) <0.5 <0.5 <0.5 <0.5 <0.5 <0.5 <0.5 <0.5
Squelched Normal 12E1 16E1 24DS1 16DS1 T0-12E1 T0-16E1 T0-24DS1 T0-16DS1
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Table Output Frequency Selection
Value register Reg. Bits [3:0] 0000 0001 0010 0011 0100 0101 0110 0111 1000 1001 1010 1011 1100 1101 1110 1111 Reg. Bits [3:0] Digital2 Digital1 APLL/48 APLL/16 APLL/12 APLL/8 APLL/6 APLL/4 APLL/64 APLL/48 APLL/16 APLL/8 APLL/4 Reg. Bits [7:4] Digital2 Digital1 APLL/48 APLL/16 APLL/12 APLL/8 APLL/6 APLL/4 APLL/64 APLL/48 APLL/16 APLL/8 APLL/4 Reg. Bits [3:0] Digital2 Digital1 APLL/48 APLL/16 APLL/12 APLL/8 APLL/6 APLL/4 APLL/64 APLL/48 APLL/16 APLL/8 APLL/4 Reg. Bits [7:4] Digital2 Digital1 APLL/48 APLL/16 APLL/12 APLL/8 APLL/6 APLL/4 APLL/2 APLL/48 APLL/16 APLL/8 APLL/4 Reg. Bits [3:0] Digital2 Digital1 APLL/48 APLL/16 APLL/12 APLL/8 APLL/6 APLL/4 APLL/2 APLL/48 APLL/16 APLL/8 APLL/4 Reg. Bits [7:4] APLL/2 Digital1 APLL/1 APLL/16 APLL/12 APLL/8 APLL/6 APLL/4 APLL/64 APLL/48 APLL/16 APLL/8 APLL/4 Reg. Bits [3:0] Digital2 APLL/2 APLL/48 APLL/16 APLL/12 APLL/8 APLL/6 APLL/4 APLL/64 APLL/48 APLL/16 APLL/8 APLL/4
Frequency Outputs
composite clock output. enabled, this always produces kHz/8 composite clock. enabled, always produces frequency output. Both generated within either path, controlled Reg. frequencies generated from independent Mode (frequency) either paths. amount jitter generated outputs will related clock period source block added jitter present that clock. This detailed following text. seen block diagram, blocks used generate these outputs feedback block case path output block path. feedback block clocked forward DFS, APLL. frequency forward block determined referring Table APLL frequencies). This region MHz-89 approximated have period between output forward
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block will have inherent pk-pk jitter approximately clock feedback block will have jitter when path analog feedback mode (Reg. However, will have when digital feedback mode. output, being kHz/8 kHz, directly divided from clock feedback block; therefore, will have similar amount jitter i.e. when using analog feedback, when using digital feedback. output will have more jitter because synthesized from clock feedback block. jitter, addition that present clock feedback block, will equivalent period that clock, i.e. between jitter present output will range from (when path mode combined with analog feedback) (when 16E1 mode combined with digital feedback).
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outputs enabled/disabled Reg. Bits [5:4].
"Digital" Frequencies
clock). maximum jitter generated when digital feedback mode, when total approximately
TO10, TO11, Clock Outputs
seen from Table (TO1-TO7 output frequency selection) that frequencies listed Digital1 Digital2 selected. Digital1 single frequency selected from range shown Table Digital2 another single frequency selected from same range. output block shown diagram clocked either output block output APLL, generates these frequencies. input clock frequency always 77.76 such period approximately jitter generated Digital outputs relatively high, fact that they pass through APLL jitter filtering. minimum level jitter when path analog feedback mode, when pk-pk jitter will approximately (equivalent period Figure Control Options.
output T010/8kHz output
seen from Table (TO1 Output Frequency Selection) that frequencies listed selected. Whilst TO10 TO11 outputs always supplied from path, options available from outputs supplied from either path (Reg. outputs either clocks (50:50 mark-space) pulses inverted. When pulses configured output, pulse width will cycle output (TO3 must configured generate least 1544 ensure that pulses generated correctly). Figure shows various options with controls Reg. There identical arrangement with Reg. Bits [1:0] kHz/TO11 outputs. Outputs TO10 TO11 disabled Reg. Bits [7:6].
output
T010/8kHz output
Clock inverted, Reg.7A[3:2]
Clock non-inverted, Reg.7A[3:2]
output T010/8kHz output Pulse non-inverted, Reg.7A[3:2]
output T010/8kHz output Pulse inverted, Reg.7A[3:2]
Table Digital Frequency Selections
Digital1 Control Reg.39 Bits [5:4] Digital1 Sonet/ Reg. Bit5 Digital1 Freq. (MHz) 2.048 4.096 8.192 16.384 1.544 3.088 6.176 12.352 Digital2 Control Reg. Bits[7:6] Digital2 Sonet/SDH Reg.38 Bit6 Digital2 Freq. (MHz) 2.048 4.096 8.192 16.384 1.544 3.088 6.176 12.352
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ACS8530 SETS
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ACS8530 incorporates microprocessor interface, which configured common microprocessor interface types, interface mode control pins UPSEL(2:0) defined Table These pins read power interface mode. optional EPROM mode allows internal registers loaded from EPROM when device comes "power-on reset" mode. microprocessor interface type altered after power register such that instance device could boot EPROM mode then switch Motorola mode, example, after EPROM data preconditioned device. Reading Data from EPROM boot time handled automatically ACS8530. chip select EPROM should driven from micro case mixed EPROM micro communication, order avoid conflict between EPROM ACS8530 access from microprocessor. following sections show interface timings each interface type. timings currently based those ACS8510. These preliminary currently pessimistically slow side, since ACS8530 offers substantial improvement access speed.
Table Microprocessor Interface Mode Selection
UPSEL(2:0) SERIAL MOTOROLA INTEL MULTIPLEXED EPROM Mode Interface disabled Interface disabled Serial interface Motorola interface Intel compatible interface Multiplexed interface EPROM read mode Interface disabled Description
Timing diagrams different microprocessor modes presented pages
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Motorola Mode
MOTOROLA mode, device configured interface with microprocessor using 680x0 type parallel data address. Figure Figure show timing diagrams write read accesses this mode. Figure Read Access Timing MOTOROLA Mode
tpw1 tsu2 copied from ACS8110 Handler vT001 F8110D_007Read Motor_01.eps tsu1 address (DTACK) tpw2 data
F8110D_007ReadAccMotor_01
Table Read Access Timing MOTOROLA Mode (for with Figure
Symbol tSU1 tSU2 tpw1 tpw2 Note: Parameter Setup valid CSBfalling edge Setup valid CSBfalling edge Delay CSBfalling edge valid Delay CSBfalling edge DTACKrising edge Delay CSBrising edge high-Z Delay CSBrising edge high-Z time high time Hold valid after CSBrising edge Hold valid after CSBrising edge Hold after RDYfalling edge Time between consecutive accesses (CSBrising edge CSBfalling edge) ns(i)
Timing with RDY. used, tpw1 becomes Page www.semtech.com
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Figure Write Access Timing MOTOROLA Mode
tpw1
tsu2 copied from 8110 Handler vT001 F8110D_008WriteAccMotor_01.eps tsu1 address tsu3 (DTACK) tpw2 data
F8110D_008WriteAccMotor_01
Table Write Access Timing MOTOROLA Mode (for with Figure
Symbol tSU1 tSU2 tsu3 tpw1 tpw2 Note: Parameter Setup valid CSBfalling edge Setup valid CSBfalling edge Setup valid before CSBrising edge Delay CSBfalling edge RDYrising edge Delay CSBrising edge high-Z time high time Hold valid after CSBrising edge Hold after CSBrising edge Hold after RDYfalling edge Hold valid after CSBrising edge Time between consecutive accesses (CSBrising edge CSBfalling edge) ns(i)
Timing with RDY. used, tpw1 becomes
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Intel Mode
Intel mode, device configured interface with microprocessor using 80x86 type parallel data address. Figure Figure show timing diagrams read write accesses this mode. Figure Read Access Timing INTEL Mode
copied from ACS8110 Handler vT001 F8110D_009ReadAccIntel_01.eps Reduced scale
tsu2 tpw1
tsu1 address tpw2 data
F8110D_009ReadAccIntel_01
Table Read Access Timing INTEL Mode (for with Figure
Symbol tSU1 tSU2 tpw1 tpw2 Parameter Setup valid CSBfalling edge Setup CSBfalling edge RDBfalling edge Delay RDBfalling edge valid Delay CSBfalling edge active Delay RDBfalling edge RDYfalling edge Delay RDBrising edge high-Z Delay CSBrising edge high-Z time time Hold valid after RDBrising edge Hold after RDBrising edge Hold after RDYrising edge Time between consecutive accesses (RDBrising edge RDBfalling edge, RDBrising edge WRBfalling edge) ns(i)
Note:
Timing with RDY. used, tpw1 becomes Page www.semtech.com
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Figure Write Access Timing INTEL Mode
tsu2 tpw1 copied from ACS8110 Handler vT001 F8110D_WriteAccIntel_01.eps reduced
tsu1 address tsu3 tpw2 data
F8110D_010WriteAccIntel_01
Table Write Access Timing INTEL Mode (for with Figure
Symbol tSU1 tSU2 tsu3 tpw1 tpw2 Parameter Setup valid CSBfalling edge Setup CSBfalling edge WRBfalling edge Setup valid before WRBrising edge Delay CSBfalling edge active Delay WRBfalling edge RDYfalling edge Delay CSBrising edge high-Z time time Hold valid after WRBrising edge Hold after WRBrising edge Hold after RDYrising edge Hold valid after WRBrising edge Time between consecutive accesses (WRBrising edge WRBfalling edge, WRBrising edge RDBfalling edge) ns(i) ns(ii)
Notes: Timing with RDY. used, tpw1 becomes (ii) Timing greater than otherwise after CSBrising edge.
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ACS8530 SETS
ADVANCED COMMUNICATION
Multiplexed Mode
Multiplexed Mode, device configured interface with microprocessors (e.g., Intel's 80x86 family) which share signals between address data. Figures show timing diagrams write read accesses. Figure Read Access Timing MULTIPLEXED Mode
tpw3 tsu1
copied from ACS8110 Handler vT001
Reduced
address
tpw1
data tpw2
F8110D_011ReadAccMultiplex_01
Table Read Access Timing MULTIPLEXED Mode (for with Figure
Symbol tSU1 tSU2 tpw1 tpw2 tpw3 Note: Parameter Setup address valid ALEfalling edge Setup CSBfalling edge RDBfalling edge Delay RDBfalling edge data valid Delay CSBfalling edge active Delay RDBfalling edge RDYfalling edge Delay RDBrising edge data high-Z Delay CSBrising edge high-Z time time high time Hold address valid after ALEfalling edge Hold after RDBrising edge Hold after RDYrising edge Time between ALEfalling edge RDBfalling edge Time between consecutive accesses (RDBrising edge ALErising edge) ns(i)
Timing with RDY. used, tpw1 becomes
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ACS8530 SETS
ADVANCED COMMUNICATION
Figure Write Access Timing MULTIPLEXED Mode
tpw3
Copied from ACS8110 Handler vT001
tsu1
tsu2 tpw1
reduced
tsu3 address data tpw2
F8110D_012WriteAccMultiplex_01
Table Write Access Timing MULTIPLEXED Mode (For with Figure
Symbol tSU1 tSU2 tSU3 tpw1 tpw2 tpw3 Note: Parameter address valid ALEfalling edge CSBfalling edge WRBfalling edge data valid WRBrising edge Delay CSBfalling edge active Delay WRBfalling edge RDYfalling edge Delay CSBrising edge high-Z time time high time Hold address valid after ALEfalling edge Hold after WRBrising edge Hold after RDYrising edge data hold valid after WRBrising edge Time between ALEfalling edge WRBfalling edge Time between consecutive accesses (WRBrising edge ALErising edge) ns(i)
Timing with RDY. used, tpw1 becomes Page www.semtech.com
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ACS8530 SETS
ADVANCED COMMUNICATION
Serial Mode
SERIAL Mode, device configured interface with serial microprocessor bus. Figure Figure show timing diagrams write read accesses this mode. During read access output data (AD(O)) clocked rising edge SCLK (ALE) when active edge selection control CLKE (A(1)) falling edge when CLKE Address, read/write control write data always clocked into interface rising edge SCLK. Both input data clock SCLK oversampled, filtered synchronised 204.8 internal clock. serial interface clock (SCLK) required between accesses (i.e., when
Figure Read Access Timing SERIAL Mode
CLKE data clocked rising edge SCLK tsu2 ALE=SCLK tsu1 tpw1 referenced F8110_013ReadAccSerial_03
tpw2
A(0)=SDI
AD(0)=SDO
Output driven, pulled internal resistor
CLKE data clocked falling edge SCLK ALE=SCLK
A(0)=SDI
AD(0)=SDO
Output driven, pulled internal resistor
F8110D_013ReadAccSerial_03
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ACS8530 SETS
ADVANCED COMMUNICATION
Table Read Access Timing SERIAL Mode (For with Figure
Symbol tSU1 tSU2 tpw1 tpw2 Parameter Setup valid SCLKrising edge Setup CSBfalling edge SCLKrising edge Delay SCLKrising edge (SCLKfalling edge CLKE valid Delay CSBrising edge high-Z SCLK time SCLK high time Hold valid after SCLKrising edge Hold after SCLKrising edge, CLKE Hold after SCLKfalling edge, CLKE Time between consecutive accesses (CSBrising edge CSBfalling edge)
Figure Write Access Timing SERIAL Mode
Copied from ACS8110 Handler vT001 F8110D_014WriteAccSerial_01.eps
changed F8110_014WriteAccSerial_02
ALE=SCLK
Reduced
tsu1
tpw1
A(0)=SDI
AD(0)=SDO
Output driven, pulled internal resistor
F8110D_014WriteAccSerial_02
Table Write Access Timing SERIAL Mode (For with Figure
Symbol tSU1 tSU2 tpw1 tpw2 Parameter Setup valid SCLKrising edge Setup CSBfalling edge SCLKrising edge SCLK time SCLK high time Hold valid after SCLKrising edge Hold after SCLKrising edge Time between consecutive accesses (CSBrising edge CSBfalling edge)
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ACS8530 SETS
ADVANCED COMMUNICATION
EPROM Mode
This mode suitable with EPROM, which configuration data stored (one-way communication status information will accessible). state machine internal ACS8530 device will perform numerous EPROM read operations read data EPROM. EPROM Mode, ACS8530 takes control Master reads device set-up from AM27C64 type EPROM lowest speed (250ns) after device set-up (system reset). EPROM access state machine interface sequences accesses. Figure shows access timing device EPROM mode. Further information found AM27C64 data sheet. Figure Access Timing EPROM mode
(=OEB) Copied from ACS8110 Handler vT001 F8110D_015ReadAccEEPROM_01.eps tacc data
F8110D_015ReadAccEEPROM_01
address
Table Access Timing EPROM mode (For with Figure
Symbol tacc Parameter Delay CSBfalling edge change valid
Power Reset
Power Reset (PORB) resets device forced Low. reset asynchronous, minimum pulse width Reset needed initialize register values their defaults. Reset must asserted power re-asserted time restore defaults. This implemented simply using external capacitor along with internal pull-up resistor. ACS8530 held reset state after PORB been pulled High. normal operation PORB should held High.
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ACS8530 SETS
ADVANCED COMMUNICATION Register
Each Register, register group, described following Register (Table subsequent Register Description Tabl
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