µPD98503 NETWORK CONTROLLER µPD98503 high performance contro

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µPD98503 NETWORK CONTROLLER µPD98503 high performance contro

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INTEGRATED CIRCUIT
µPD98503
NETWORK CONTROLLER
µPD98503 high performance controller which perform TCP/IP protocol stacks other application system related software. includes high performance MIPSbased 64-bit RISC processor VR4120ACPU core, Ethernetcontroller, controller block, general purpose input/output functions memory/systembus interface. Detailed function descriptions provided following user's manual. sure read manual before designing. µPD98503 User's Manual: S15906E
FEATURES
Includes high performance MIPS based 64-bit RISC processor VR4120A perform RTOS network middleware (M/W) chip Includes interface PROM flash used storing boot program Includes 10/100 Mbps Ethernet controllers compliant IEEE802.3, IEEE802.3u IEEE802.3x directly connect external Ethernet device through 3.3-V interface Includes full speed function controller compliant specification Supports operation conforming Communication Device Class Specification directly connect 64-Mbit 128-Mbit SDRAM external memory Includes boundary scan function (JTAG) compliant IEEE 1149.1 Includes UART Micro Wireinterface Includes 2-channel general purpose timers Includes general purpose input/output pins Using advanced CMOS technology Supply voltage (I/O) (Core) Package 256-pin Tape-BGA
ORDERING INFORMATION
Part Number Package 256-pin tape (heat spreader type)
µPD98503N7-B6
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Document S15894EJ2V0DS00 (2nd edition) Date Published November 2002 Printed Japan
mark
shows major revised points.
2002
µPD98503
BLOCK DIAGRAM
Full Speed Function Controller
MIPS Core with Instruction Data Cache
Control, Interrupt etc.
PROM FLASH 3.3V IBUS Ethernet System Controller with Memory Controller JTAG Controller Clock Control Unit speed section UART, Timer, GPIO SDRAM RS-232 GPIO
JTAG
Data Sheet S15894EJ2V0DS
µPD98503
CONFIGURATION (Bottom View)
256-pin tape (heat spread type)
PD98503N7-B6
Data Sheet S15894EJ2V0DS
µPD98503
Name
(1/2)
Address Name IC-PUpR IC-Open ENDCEN RMSL0 GPIO0 GPIO4 GPIO6 GPIO8 EXNMI_B GPIO13 GPIO14 MWDI MWDO URDCD_B URDTR_B SMA1 SMA3 SMA5 SMA8 SMA9 IC-PUpR IC-PUpR IC-PDnR IC-PDn RMSL1 GPIO3 GPIO5 GPIO7 GPIO11 GPIO12 GPIO15 MWCS URCTS_B URCLK URSDO SMA2 SMA7 SMA10 SMA11 IC-Open IC-PUpR IVDD Address Name GPIO2 IVDD GPIO10 IVDD EXINT_B URDSR_B IVDD URSDI SMA4 SMA6 IVDD SMA12 SMA14 IC-Open IC-Open EVDD GPIO1 EVDD GPIO9 EVDD MWSK URRTS_B SMA0 EVDD SMA13 SMA15 SMA16 IVDD IC-Open IC-Open EVDD SMA17 SMA18 IC-PDn IC-PDn Address Name IC-PDn IC-Open SMA19 SMA20 SRMOE_B SRMCS_B IC-PDn IC-PDn IVDD IVDD SEXCS0_B SEXCS1_B IVDD EVDD EVDD SEXCS2_B SDCS_B IC-PDn IC-PDn IC-Open IC-Open SDCKE1 SDRAS_B SDCKE0 SDCLK0 IC-PDn IC-PDn IVDD IVDD SDCLK1 IC-PUp IC-PDn IVDD SDWE_B IC-PDn EVDD Address Name SDCAS_B IC-PDn IC-PDn IVDD SMD2 SMD1 SMD0 MIMD MIRD0 EVDD EVDD SMD5 SMD4 SMD3 MIRD1 MIRD2 IVDD IVDD SMD7 SMD6 MIRD3 MIRER MIRDV MITD0 SMD11 SMD10 SMD9 SMD8 MITD1 MITD2 MICRS EVDD SMD14 SMD12 MITD3 MIRCLK IC-PDn
Data Sheet S15894EJ2V0DS
µPD98503
(2/2)
Address Name IC-PUp IC-Open PSDVD PUDGND EVDD SMD30 EVDD SMD17 SMD15 SMD13 MITCLK MICOL IVDD Address Name EVDD IC-PUp IVDD PSDGND PUDVD IC-PDn IVDD USBDM IVDD IVDD SMD31 SMD27 SMD24 IVDD SMD18 SMD16 MITER MITE Address Name RST_B CLKSL SCLK PSAGND PUAVD PUSTBY IC-PDn USBDP IC-Open IC-PDn IC-PDn SMD26 SMD23 SMD21 SMD19 MIMCLK Address Name IC-Open JRSTB_B IC-PUp IC-PDn PSTBY PSAVD PUAGND IC-Open USBCLK EVDD IC-Open IC-Open IC-PDn SMD29 SMD28 SMD25 SMD22 SMD20
Remarks1. Special name description: IC-PDn: IC-PUp: Pull Down Pull IC-PDnR: Pull Down with Resistor IC-PUpR: Pull with Resistor IC-Open: Test output shall left open this document, XXX_B stands active pin.
Data Sheet S15894EJ2V0DS
µPD98503
CONTENTS
FUNCTIONS
1.10 1.11 1.12 1.13 1.14 1.15 Power Supply. System Power Supply Power Supply System Control Interface Memory Interface. Ethernet Interface UART Micro Wire Interface. Interface Parallel Port Interface Boundary Scan Interface. I.C. Open. I.C. Pull Down I.C. Pull Down with Resistor I.C. Pull I.C. Pull with Resistor
ELECTRICAL SPECIFICATIONS PACKAGE DRAWING. RECOMMENDED SOLDERING CONDITIONS
Data Sheet S15894EJ2V0DS
µPD98503
FUNCTIONS
Symbol column indicates following status this section. Input Output Bidirection
I/OZ Bidirection (Include Hi-Z state) I/OD Bidirection (Open drain output) Output (Include Hi-Z state) Output (Open drain)
Power Supply
Name Address B17, C04, C08, C12, D01, D04, D07, D10, D14, D17, E01, E18, G04, G17, H01, H03, H18, K03, K17, K20, L04, M04, M17, N01, P04, P17, T04, T20, U04, U07, U11, U13, U14, U17, W03, C03, C07, C10, C14, C18, E02, G03, G18, H02, K04, K18, L03, M03, P03, P18, V03, V07, V11, V13, V14, D05, D08, D11, D16, E17, H04, H17, L19, N04, N17, T17, U12, U16, V05, 130, 204, 200, 196, 205, 254, 251, 247, 244, 188, 208, 241, 150, 185, 152, 238, 212, 213, 236, 215, 234, 217, 218, 221, 225, 227, 228, 231, 145, 201, 198, 194, 190, 149, 186, 211, 183, 153, 154, 156, 179, 160, 164, 168, 170, 171, 256, 253, 250, 245, 243, 209, 240, 119, 214, 235, 232, 226, 230, 162, Active Level Function
IVDD
Internal logic core power supply (+2.5
EVDD
External (I/O) power supply (+3.3
System Power Supply
Name PSAGND PSAVD PSDGND PSDVD Address Active Level Analog ground Analog power supply (+2.5 Digital ground Digital power supply (+2.5 Function
Remark power supply pins System shall blocked with capacitors separately closed device possible.
Data Sheet S15894EJ2V0DS
µPD98503
Power Supply
Name PUAGND PUAVD PUDGND PUDVD Address Active Level Analog ground Analog power supply (+2.5 Digital ground Digital power supply (+2.5 Function
Remark power supply pins shall blocked with capacitors separately closed device possible.
System Control Interface
Name SCLK CLKSL PSTBY PUSTBY ENDCEN EXINT_B EXNMI_B RST_B RMSL0, RMSL1 Address A04, Active Level System clock MHz) Clock select VR4120A SDRAM MHz/H: MHz) System standby mode control active, standby) standby mode control active, standby) VR4120A endian mode Endian conversion enable External interrupt External non-maskable interrupt System reset access width (RMSL1/0 L/L: bits, L/H: bits, H/L: bits) Function
Data Sheet S15894EJ2V0DS
µPD98503
Memory Interface
Name SDCLK0, SDCLK1 SDCKE0, SDCKE1 SDCS_B SDRAS_B SDCAS_B SDWE_B SRMCS_B SRMOE_B SEXCS0_B SEXCS2_B SMA0 SMA20 Address J20, J19, G19, G20, D15, A16, B16, A17, C16, A18, C17, B18, A19, A20, B19, B20, C19, D18, C20, D19, D20, E19, E20, F17, M20, M19, M18, N20, N19, N18, P20, P19, R20, R19, R18, R17, T19, U20, T18, U19, V20, U18, V19, W20, Y20, W19, Y19, W18, V17, Y18, W17, V16, Y17, Y16, U15, 121, 123, 246, 131, 192, 191, 129, 128, 127, 189, 126, 125, 242, 118, 181, 117, 180, 116, 115, 178, 233, 114, 177, 113, 176, 112, 111, 110, 174, 109, 173, 229, Active Level SDRAM Clock SDRAM Clock Enable SDRAM Chip select SDRAM address strobe SDRAM Column address strobe SDRAM/PROM/FLASH write enable PROM/FLASH chip select PROM/FLASH output enable Extended Chip Select System Address Function
SMD0 SMD31
System data
Data Sheet S15894EJ2V0DS
µPD98503
Ethernet Interface
Name MIRCLK MIMCLK MIMD MICOL MICRS MIRDV MIRER MIRD0 MIRD3 MITCLK MITE MITER MITD0 MITD3 Address N03, P01, P02, R04, T01, T02, 155, 216, Active Level Function Receive clock (2.5 MHz/25 MHz) management clock management Collision carrier Sense Receive data valid Receive error Receive data Transmit clock (2.5 MHz/25 MHz) Transmit enable Transmit error Transmit data
UART Micro Wire Interface
Name URCLK URSDO URSDI URDTR_B URRTS_B URCTS_B URDCD_B URDSR_B MWDI MWSK MWCS MWDO Address Active Level Function UART external Clock (18.432 MHz) UART serial data output UART serial data input UART data terminal ready UART data request send UART clear send UART data carrier detect UART data ready Micro Wire data Micro Wire sampling clock Micro Wire chip select Micro Wire data
Data Sheet S15894EJ2V0DS
µPD98503
Interface
Name USBCLK USBDM USBDP Address Active Level Function External clock MHz) data data
Parallel Port Interface
Name GPIO0 GPIO15 Address A05, D06, C06, B06, A06, B07, A07, B08, A08, D09, C09, B09, B10, A10, A11, 255, 202, 141, 140, 139, 252, 199, 138, 137, Active Level Function General Purpose Input/Output
1.10 Boundary Scan Interface
Name JRSTB_B Address Active Level B-SCAN clock B-SCAN input-data B-SCAN output-data B-SCAN mode select B-SCAN reset Function
Remark general above specified functional pins (and kind power supply pins) included boundary scan chain, with following exceptions: USBDM, USBDP, SDCLK0, SDCLK1 Beside above specified functional pins, scan chain includes some non-specified test-pins. boundary scan device part number 0503 (hex).
Data Sheet S15894EJ2V0DS
µPD98503
1.11 I.C. Open
Name IC-Open Address Active Level Function Test output pins which must left unconnected
146, 147, 206, A02, C01, D02, D03, E03, E04, F04, J03, J04, 207, 151, 210, 222, 105, U08, W13, Y02, Y10, Y13,
1.12 I.C. Pull Down
Name IC-PDn Address B04, F01, F02, F03, G01, G02, J01, J02, K01, K02, L02, L18, M01, M02, U03, V10, W11, W14, W15, Y06, 143, 148, 182, 159, 167, 103, 106, 107, Active Level Function Test input pins which shall connected
1.13 I.C. Pull Down with Resistor
Name IC-PDnR Address Active Level Function Test inputs which shall connected externally through resistor
1.14 I.C. Pull
Name IC-PUp Address L01, U06, V06, 220, 163, Active Level Function Test input pins shall connected EVDD
1.15 I.C. Pull with Resistor
Name IC-PUpR Address A01, B01, B02, Active Level Function Test inputs which shall connected externally EVDD through resistor
Data Sheet S15894EJ2V0DS
µPD98503
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Symbol IVDD EVDD Input/output voltage VI1/VO1 VI2/VO2 VI3/VO3 Output current Storage temperature Tstg Conditions Internal logic core buffer LVTTL-level LVTTL-level buffer LVTTL-level pin, LVTTL-level buffer, Ratings -0.5 +3.6 -0.5 +4.6 -0.5 +4.6 -0.5 +4.6 -0.5 +4.6 +150 Unit
Caution
Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded.
Recommended Operating Conditions
Parameter Supply voltage Symbol IVDD EVDD level input voltage VIL1 VIL2 VIL3 LVTTL-level LVTTL-level buffer, refer Interface Parameter (Single-end operation) LVTTL-level LVTTL-level buffer, refer Interface Parameter (Single-end operation) buffer, refer Interface Parameter (Differential operation) Conditions MIN. TYP. MAX. Unit
High level input voltage
VIH1 VIH2 VIH3
differential input voltage
VIDF
Operating ambient temperature
Data Sheet S15894EJ2V0DS
µPD98503
Characteristics (IVDD EVDD +70°C)
Parameter Supply current Supply current Input leakage current Symbol IIDD EIDD ILI1 ILI2 ILI3 state output current level output voltage VOL1 VOL2 VOL3 High level output voltage VOH1 VOH2 VOH3 EVDD EVDD (pin group (pin group EVDD LVTTL-level pin, LVTTL-level pin, buffer, refer Interface Parameter LVTTL-level pin, LVTTL-level pin, buffer, refer Interface Parameter EVDD Conditions MIN. TYP. MAX. ±1440 ±180 Unit
Capacitance 25°C,
Parameter Input Capacitance Output Capacitance Capacitance Symbol MHz, Unmeasured pins returned Conditions MIN. TYP. MAX. Unit
Data Sheet S15894EJ2V0DS
µPD98503
Classifications Caution pins listed twice input output section Input pins
Category LVTTL-level VI1, VIL1/VIH1 Application Pins SCLK, CLKSL, PSTBY, PUSTBY, BIG, ENDCEN, EXINT_B, EXNMI_B, RST_B, RMSL[1:0], SMD[31:0], USBCLK, URCLK, URSDI, MWDI, URCTS_B, URDCD_B, URDSR_B, GPIO[15:0], JCK, JDI, JMS, JRSTB_B MIRCLK, MIMD, MICOL, MICRS, MIRDV, MIRER, MIRD[3:0], MITCLK USBDP, USBDM Number Pins
LVTTL-level buffer
VI2, VIL2/VIH2 VI3, VIL3/VIH3, VIDF
group group
IC-PUp (Pin 163, 220) IC-PDn (Pin 159)
Output pins
Category LVTTL-level VO1, VOL1/VOH1 Application Pins SDCLK0, SDCLK1, SDCKE0, SDCKE1, SDCS_B, SDRAS_B, SDCAS_B, SDWE_B, SRMCS_B, SRMOE_B, SEXCS0_B, SEXCS1_B, SEXCS2_B, SMA[20:0], SMD[31:0], URSDO, URDTR_B, URRTS_B, MWSK, MWCS, MWDO, GPIO[15:0], MIMCLK, MIMD, MITE, MITER, MITD[3:0] USBDP, USBDM Number Pins
LVTTL-level buffer
VO2, VOL2/VOH2 VO3, VOL3/VOH3
Characteristics (IVDD EVDD Test Waveform
Input signal
0.5EVDD
Test points
0.5EVDD
Ouput signal
0.5EVDD
Test points
0.5EVDD
Data Sheet S15894EJ2V0DS
µPD98503
Clock Parameter
Clock Cycle Clock High Width Clock Width
(2)-1 Clock Input
Parameter SCLK Input Cycle SCLK Input High Width SCLK Input Width MITCLK Input Cycle MITCLK Input High Width MITCLK Input Width MIRCLK Input Cycle MIRCLK Input High Width MIRCLK Input Width USBCLK Input Cycle USBCLK Input High Width USBCLK Input Width URCLK Input Cycle URCLK Input High Width URCLK Input Width Input Cycle Input High Width Input Width Symbol tCYSCK tWHSCK tWLSCK tCYMTK tWHMTK tWLMTK tCYMRK tWHMRK tWLMRK tCYUBK tWHUBK tWLUBK tCYURK tWHURK tWLURK tCYJCK tWHJCK tWLJCK Conditions MIN. 30.00 tCYSCK tCYSCK 40.00 tCYMTK tCYMTK 40.00 tCYMRK tCYMRK 83.12 tCYUBK tCYUBK 54.25 tCYURK tCYURK 100.00 tCYJCK tCYJCK MAX. 33.00 tCYSCK tCYSCK 400.00 tCYMTK tCYMTK 400.00 tCYMRK tCYMRK 84.54 tCYUBK tCYUBK 55.55 tCYURK tCYURK 1000.00 tCYJCK tCYJCK Unit
Remarks SCLK, USBCLK, usage oscillator circuit recommended. MITCLK/MIRCLK required stability normally depends used Ethernet PHY. many cases oscillators recommended. clock input signals (USBCLK SCLK) shall derived from dedicated driving device ensure short rise fall times. Normally clock signals shall passed through resistor.
Data Sheet S15894EJ2V0DS
µPD98503
(2)-2 Clock Output
Parameter SDCLK0 Output Cycle SDCLK0 Output High Width SDCLK0 Output Width SDCLK1 Output Cycle SDCLK1 Output High Width SDCLK1 Output Width MIMCLK Output Cycle MIMCLK Output High Width MIMCLK Output Width Symbol tCYSK0 tWHSK0 tWLSK0 tCYSK1 tWHSK1 tWLSK1 tCYMCK tWHMCK tWLMCK Conditions Load Load Load Load Load Load Load Load Load MIN. 10.00 tCYSK0 tCYSK0 10.00 tCYSK1 tCYSK1 420.00 tCYMCK tCYMCK MAX. 15.00 tCYSK0 tCYSK0 15.00 tCYSK1 tCYSK1 Unit
Remark
value tCYSDCLK which referenced later this document refers cycle time signals SDCLK0/1 defined above table.
Reset, Parameter
IVDD, EVDD
PSTBY (System PLL), PUSTBY (USB PLL) SCLK (System Clock) External Unstable Period Internal
tWHPSY, tWHUSY
tWLPLK, tWLULK RST_B (System Reset)
Stable Period
tWLRSB
Parameter RST_B Input Level Width PSTBY Hold High Level Width PSTBY Lookup Time PUSTBY Hold High Level Width PUSTBY Lookup Time
Symbol tWLRSB tWHPSY tWLPLK tWHUSY tWLULK
Conditions
MIN. tCYSCK
MAX. 4000 Note
Unit
Load
1000
Load
1000
Note RST_B applied longer, operation PD98503 will start anyhow. Therefore shall made sure, that other logic also RESET state after even RST_B applied longer period.
Data Sheet S15894EJ2V0DS
µPD98503
Interrupt Interface Parameter
tWLEIN tWLENM EXINT_B, EXNMI_B (input)
Parameter EXINT_B Input Width EXNMI_B Input Width
Symbol tWLEIN tWLENM
Conditions
MIN. tCYSK0/1 tCYSK0/1
MAX.
Unit
Data Sheet S15894EJ2V0DS
µPD98503
System SDRAM interface parameter
SDCLK0 (output)
tDSE0SK0
SDCKE0 (output)
tDSE0SK0
tDSCSSK0
SDCS_B (output)
tDSCSSK0
tDSRASK0
SDRAS_B (output)
tDSRASK0
tDSCASK0
SDCAS_B (output)
tDSCASK0
tDSW ESK0
SDWE_B (output)
tDSW ESK0
tDSMASK0
SMA[20:0] (output)
tDSMASK0
tDSMDSK0
SMD[31:0] (output)
tDSMDSK0
tDSMDSK0
Hi-Z
tASMDSK0 tSSMDSK0 tHSMDSK0 tFSMDSK0
Hi-Z
SMD[31:0] (input)
Hi-Z
Hi-Z
Parameter SDCKE0 Output Delay from SDCLK0 SDCS_B Output Delay from SDCLK0 SDRAS_B Output Delay from SDCLK0 SDCAS_B Output Delay from SDCLK0 SDWE_B Output Delay from SDCLK0 SMA[20:0] Output Delay from SDCLK0 SMD[31:0] Output Floating Active Delay from SDCLK0 SMD[31:0] Output Delay from SDCLK0 SMD[31:0] Output Active Floating Delay from SDCLK0 SMD[31:0] Input Setup SDCLK0 SMD[31:0] Input Hold from SDCLK0
Symbol tDSE0SK0 tDSCSSK0 tDSRASK0 tDSCASK0 tDSWESK0 tDSMASK0 tASMDSK0 tDSMDSK0 tFSMDSK0 tSSMDSK0 tHSMDSK0
Conditions Load Load Load Load Load Load Load Load Load
MIN. 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00
MAX. 8.00 8.00 8.00 8.00 8.00 8.00
Unit
8.00 8.00
4.00 1.50
Data Sheet S15894EJ2V0DS
µPD98503
SDCLK1 (output)
tDSE1SK1
SDCKE1 (output)
tDSE0SK1
tDSCSSK1
SDCS_B (output)
tDSCSSK1
tDSRASK1
SDRAS_B (output)
tDSRASK1
tDSCASK1
SDCAS_B (output)
tDSCASK1
tDSWESK1
SDWE_B (output)
tDSWESK1
tDSMASK1
SMA[20:0] (output)
tDSMASK1
tDSMDSK1
SMD[31:0] (output)
tDSMDSK1
tDSMDSK1
Hi-Z
tASMDSK1 tSSMDSK1 tHSMDSK1 tFSMDSK1
Hi-Z
SMD[31:0] (input)
Hi-Z
Hi-Z
Parameter SDCKE1 Output Delay from SDCLK1 SDCS_B Output Delay from SDCLK1 SDRAS_B Output Delay from SDCLK1 SDCAS_B Output Delay from SDCLK1 SDWE_B Output Delay from SDCLK1 SMA[20:0] Output Delay from SDCLK1 SMD[31:0] Output Floating Active Delay from SDCLK1 SMD[31:0] Output Delay from SDCLK1 SMD[31:0] Output Active Floating Delay from SDCLK1 SMD[31:0] Input Setup SDCLK1 SMD[31:0] Input Hold from SDCLK1
Symbol tDSE1SK1 tDSCSSK1 tDSRASK1 tDSCASK1 tDSWESK1 tDSMASK1 tASMDSK1 tDSMDSK1 tFSMDSK1 tSSMDSK1 tHSMDSK1
Conditions Load Load Load Load Load Load Load Load Load
MIN. 1.00 1.00 1.00 1.00 1.00 1.00 1.00 1.00
MAX. 8.00 8.00 8.00 8.00 8.00 8.00
Unit
8.00 8.00
4.00 1.50
Data Sheet S15894EJ2V0DS
µPD98503
System Flash Interface Parameter <Read Cycle>
tSSMAROE
SMA[20:0] (output)
tHSMAROE
tSRCSROE
SRMCS_B (output)
tHRCSROE
tWHCSROE
tSSWEROE
SDWE_B (output)
tHSWEROE
tWLROE
SRMOE_B (output)
tWHROE
tSSMDROE
SMD[31:0] (input)
tHSMDROE
Hi-Z
Hi-Z
Parameter SMA[20:0] Setup SRMOE_B SMA[20:0] Hold from SRMOE_B SRMCS_B Setup SRMOE_B SRMCS_B Hold from SRMOE_B SRMCS_B High Pulse Width
Symbol tSSMAROE tHSMAROE tSRCSROE tHRCSROE tWHCSROE
Condition Load Load Load Load Load Note Note
MIN. (FAT+1) tCYSDCLK tCYSDCLK (FAT+1) tCYSDCLK tCYSDCLK tCYSDCLK tCYSDCLK tCYSDCLK (FAT+1) tCYSDCLK
MAX.
Unit
SDWE_B Setup Time SRMOE_B SDWE_B Hold Time from SRMOE_B SRMOE_B Pulse Width SRMOE_B High Pulse Width
tSSWEROE tHSWEROE tWLROE tWHROE
Load Load Load Load Note Note
tCYSDCLK tCYSDCLK
SMD[31:0] Setup SRMOE_B SMD[31:0] Hold from SRMOE_B
tSSMDROE tHSMDROE
Notes case burst transfers case subsequent non-burst single word transfers (only possible 32-bit width) Remarks timing parameter width selection equivalent Flash (SRMCS_B area) (SEXCS[2:0]_B area) access. programmed register RMATR according following table.
RMATR[2:0]
Data Sheet S15894EJ2V0DS
µPD98503
<Write Cycle>
tSSMASWE
SMA[20:0] (output)
tHSMASWE
tSRCSSWE
SRMCS_B (output)
tHRCSSWE
tWHSCS
tWLSWE
SDWE_B (output)
tWHSWE
tSROESWE
SRMOE_B (output)
tHROESWE
tSSMDSWE
SMD[31:0] (output)
tHSMDSWE
tASMDSWE
tFSMDSWE
Parameter SMA[20:0] Setup SDWE_B SMA[20:0] Hold from SDWE_B SRMCS_B Setup SDWE_B SRMCS_B Hold from SDWE_B SDMCS_B High Pulse Width SRMOE_B Setup Time SDWE_B SRMOE_B Hold Time from SDWE_B SDWE_B Pulse Width SDWE_B High Pulse Width
Symbol tSSMASWE tHSMASWE tSRCSSWE tHRCSSWE tWHSCS tSROESWE tHROESWE tWLSWE tWHSWE
Condition Load Load Load Load Load Load Load Load Load Note Note
MIN. tCYSDCLK tCYSDCLK tCYSDCLK tCYSDCLK tCYSDCLK Note tCYSDCLK tCYSDCLK (FAT-1) tCYSDCLK tCYSDCLK tCYSDCLK tCYSDCLK tCYSDCLK
MAX.
Unit
SMD[31:0] Setup SDWE_B SMD[31:0] Hold from SDWE_B
tSSMDSWE tHSMDSWE
Load Load Load Load
tCYSDCLK tCYSDCLK
SMD[31:0] Output Hi-Z Valid Delay tASMDSWE SMD[31:0] Output Valid Hi-Z Delay tFSMDSWE
Notes extend this short timing, recommended insert read access RMMDR register after write access, which directly followed read access cycle. case burst transfers case subsequent non-burst single word transfers (only possible 32-bit width) Remark programmed register RMATR according following table.
RMATR[2:0]
Data Sheet S15894EJ2V0DS
µPD98503
System Extended Chip Select Interface Parameter <Read Cycle>
tSSMAROE
SMA[20:0] (output)
tHSMAROE
tSRCSROE
SEXCS[2:0]_B (output)
tHRCSROE
tWHCSROE
tSSWEROE
SDWE_B (output)
tHSWEROE
tWLROE
SRMOE_B (output)
tWHROE
tSSMDROE
SMD[31:0] (input)
tHSMDROE
Hi-Z
Hi-Z
Parameter SMA[20:0] Setup SRMOE_B SMA[20:0] Hold from SRMOE_B SEXCS[2:0]_B Setup SRMOE_B SEXCS[2:0]_B Hold from SRMOE_B SEXCS[2:0]_B High Pulse Width
Symbol tSSMAROE tHSMAROE tSRCSROE tHRCSROE tWHCSROE
Condition Load Load Load Load Load Note Note
MIN. (FAT+1) tCYSDCLK tCYSDCLK (FAT+1) tCYSDCLK tCYSDCLK tCYSDCLK tCYSDCLK tCYSDCLK (FAT+1) tCYSDCLK
MAX.
Unit
SDWE_B Setup Time SRMOE_B SDWE_B Hold Time from SRMOE_B SRMOE_B Pulse Width SRMOE_B High Pulse Width
tSSWEROE tHSWEROE tWLROE tWHROE
Load Load Load Load Note Note
tCYSDCLK tCYSDCLK
SMD[31:0] Setup SRMOE_B SMD[31:0] Hold from SRMOE_B
tSSMDROE tHSMDROE
Notes case burst transfers case subsequent non-burst single word transfers (only possible 32-bit width) Remarks timing parameter width selection equivalent Flash (SRMCS_B area) (SEXCS[2:0]_B area) access. programmed register RMATR according following table.
RMATR[2:0]
Data Sheet S15894EJ2V0DS
µPD98503
<Write Cycle>
tSSMASWE
SMA[20:0] (output)
tHSMASWE
tSRCSSWE
SEXCS[2:0]_B (output)
tHRCSSWE
tWHSCS
tWLSWE
SDWE_B (output)
tWHSWE
tSROESWE
SRMOE_B (output)
tHROESWE
tSSMDSWE
SMD[31:0] (output)
tHSMDSWE
tASMDSWE
tFSMDSWE
Parameter SMA[20:0] Setup SDWE_B SMA[20:0] Hold from SDWE_B SEXCS[2:0]_B Setup SDWE_B SEXCS[2:0]_B Hold from SDWE_B SEXCS[2:0]_B High Pulse Width SRMOE_B Setup Time SDWE_B SRMOE_B Hold Time from SDWE_B SDWE_B Pulse Width SDWE_B High Pulse Width
Symbol tSSMASWE tHSMASWE tSRCSSWE tHRCSSWE tWHSCS tSROESWE tHROESWE tWLSWE tWHSWE
Condition Load Load Load Load Load Load Load Load Load Note Note
MIN. tCYSDCLK tCYSDCLK tCYSDCLK tCYSDCLK tCYSDCLK Note tCYSDCLK tCYSDCLK (FAT-1) tCYSDCLK tCYSDCLK tCYSDCLK tCYSDCLK tCYSDCLK
MAX.
Unit
SMD[31:0] Setup SDWE_B SMD[31:0] Hold from SDWE_B
tSSMDSWE tHSMDSWE
Load Load Load Load
SMD[31:0] Output Hi-Z Valid Delay tASMDSWE SMD[31:0] Output Valid Hi-Z Delay tFSMDSWE
tCYSDCLK tCYSDCLK
Notes extend this short timing, recommended insert read access RMMDR register after write access, which directly followed read access cycle. case burst transfers case subsequent non-burst single word transfers (only possible 32-bit width) Remark programmed register RMATR according following table.
RMATR[2:0]
Data Sheet S15894EJ2V0DS
µPD98503
Ethernet Interface Parameter <MII Data Transmission>
MITCLK (input)
tDMTEMTK
MITE (output)
tDMTEMTK
tDMTDMTK
MITD[3:0] (output)
tDMTDMTK
tDMTRMTK
MITER (output)
tDMTRMTK
Parameter MITE Output Delay MITD[3:0] Output Delay MITER Output Delay
Symbol tDMTEMTK tDMTDMTK tDMTRMTK
Conditions Load Load Load
MIN.
MAX. Note
Note
Unit
Note
Note Spec., Maximum output delay specified
Data Sheet S15894EJ2V0DS
µPD98503
<MII Data Reception>
MIRCLK (input)
tSMRVMRK
MIRDV (input)
tHMRVMRK
tSMRDMRK
MIRD[3:0] (input)
tHMRDMRK
tSMRRMRK
MIRER (input)
tHMRRMRK
Parameter MIRDV Setup Time MIRDV Hold Time MIRD[3:0] Setup Time MIRD[3:0] Hold Time MIRER Setup Time MIRER Hold Time
Symbol tSMRVMRK tHMRVMRK tSMRDMRK tHMRDMRK tSMRRMRK tHMRRMRK
Conditions
MIN.
MAX.
Unit
<MII Interface Signals>
tWHMCL MICOL (input) tWHMCS MICRS (input)
Parameter MICOL High Pulse Width MICRS High Pulse Width
Symbol tWHMCL tWHMCS
Conditions
MIN. tCYMTK tCYMTK
MAX.
Unit
Data Sheet S15894EJ2V0DS
µPD98503
<MII Management Interface>
MIMCLK (output)
tSMMDMCK tHMMDMCK
MIMD (input)
tAMMDMCK
MIMD (output)
tDMMDMCK
tFMMDMCK
Parameter MIMD Setup MIMCLK MIMD Hold from MIMCLK MIMD Active Delay from MIMCLK MIMD Output Delay from MIMCLK MIMD Floating Delay from MIMCLK
Symbol tSMMDMCK tHMMDMCK tAMMDMCK tDMMDMCK tFMMDMCK
Condition
MIN.
MAX.
Unit
Load Load Load
Data Sheet S15894EJ2V0DS
µPD98503
Interface Parameter External Circuitry line output signals (refer chapter interface) need external resistors adjust output impedance each), code full speed mode protect output driver USBDM following figure shows typical connection diagram.
Connector USBDM EVDD
PD98503
USBDP
Parameter: USBDM, USBDP <Data Signal Rise Fall>
Rise time Differential Data Lines Fall time
<Differential Data Jitter>
tPERIOD 1/tDRATE Crossover points Differential Data Lines tPERIOD tDJ1 Next transitions Paired transitions
tPERIOD tDJ2
<Differential-to-EOP Transition Skew Width>
tPERIOD 1/tDRATE Crossover points extended
Differential Data Lines
Crossover points
tPERIOD tDEOP
tEOPT, tEOPR
Data Sheet S15894EJ2V0DS
µPD98503
<Differential Transition Interval Width>
tPERIOD 1/tDRATE
Differential Data Lines
tFST
<Receiver Jitter Tolerance>
tPERIOD 1/tDRATE
Differential Data Lines tJR1 Next transitions tPERIOD tJR1 Paired transitions tPERIOD tJR2 Parameter Rise Time Fall Time Differential Rise Fall Time Matching Full-speed Data Rate Source Jitter Total (including frequency tolerance): Next Transition Paired Transitions Source Jitter Differential Transition Transition Receiver Jitter: Next Transition Paired Transitions Source interval Receiver interval Width interval during differential transition tJR1 tJR2 tEOPT tEOPR tFST -18.5 +18.5 tDJ1 tDJ2 tDEOP -3.5 +3.5 tFRFM tDRATE tR/tF Symbol Condition MIN. 11.9700 MAX. 111.11 12.0300 Unit Mbps tJR2
Data Sheet S15894EJ2V0DS
µPD98503
(10) UART Interface Parameter
BAUDOUT (internal) tWLUDO URSDO (output) START tWLUDI URSDI (input) START DATA(5-8) PARITY STOP START DATA(5-8) PARITY STOP START
Remark
BAUDOUT equal transmisson baud rate (1/T Baud Rate). Customize Baud Rates achieved selecting proper divisor values baud rate generator.
Parameter Symbol fCYUCK tWLUDO tWLUDI Conditions MIN. MAX. 18.432 Unit
URCLK input frequency URSDO level width URSDI level width
Data Sheet S15894EJ2V0DS
µPD98503
(11) Micro Wire Interface Parameter
tWHWSK
MWSK
tWLWSK
tCYWSK
tSWSKWC
MWCS
tSWCSWS
tHWCSWS
tAWDOWS
MWDO
tDWDOWS
tDWDOWS
tFWDOWS
tSWDIWSK
MWDI (Read)
tHWDIWSK
Hi-Z
tAWDIWSK tFWDIWSK
Hi-Z
MWDI (Status)
Hi-Z
Hi-Z
Parameter MWSK Clock Frequency MWSK High Time MWSK Time MWSK Setup MWCS MWCS Setup MWSK MWCS Hold from MWSK MWDO Output Active Floating Delay from MWSK MWDO Output Delay from MWSK MWDO Output Floating Active Delay from MWSK MWDI Setup MWSK MWDI Hold from MWSK MWCS Status Time from MWSK MWCS MWDO 3-State
Symbol tCYWSK tWHWSK tWLWSK tSWSKWCS tSWCSWSK tHWCSWSK tAWDOWSK tDWDOWSK tFWDOWSK tSWDIWSK tHWDIWSK tAWDIWSK tFWDIWSK
Conditions Load Load Load Load Load Load Load Load Load
MIN. tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0
MAX.
Unit
tCYSK0 tCYSK0
Data Sheet S15894EJ2V0DS
µPD98503
(12) JTAG Boundary-Scan
(input)
tSJMS tHJMS
(input)
tSJDI tHJDI
(input)
tDJDO
(output)
tWLJRT
JRSTB_B (input)
Parameter Setup Time Hold Time Setup Time Hold Time Output Delay JRSTB_B Pulse Width
Symbol tSJMS tHJMS tSJDI tHJDI tDJDO tWLJRT
Conditions
MIN.
MAX.
Unit
Load tCYJCK
Data Sheet S15894EJ2V0DS
µPD98503
PACKAGE DRAWING
256-PIN TAPE (HEAT SPREADER TYPE) (27x27)
C1.5
Index area
ITEM MILLIMETERS 27.00±0.20 15.50 MAX. 15.50 MAX. 26.60±0.15 26.60±0.15 27.00±0.20 1.435 1.27 (T.P.) 0.60±0.10 0.80 1.40 +0.30 -0.20 0.15
detail part
detail part
0.75±0.15
0.30 0.25MIN. 0.10 15.11 15.11 0.20 P256N7-127-B6
Data Sheet S15894EJ2V0DS
µPD98503
RECOMMENDED SOLDERING CONDITIONS
PD98503 should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact your Electronics sales representative. Table 4-1. Surface Mounting Type Soldering Conditions PD98503N7-B6: 256-pin tape (heat spreader type)
Method Infrared reflow Conditions Package peak temperature: 235°C, Time: sec. Max. 210°C higher), Count: three times less, Exposure limit: days Note (after that, prebake 125°C hours) Package peak temperature: 215°C, Time: sec. Max. 200°C higher), Count: three times less, Exposure limit: days Note (after that, prebake 125°C hours) Symbol IR35-107-3
VP15-107-3
Note After opening pack, store 25°C less less allowable storage period. Caution different soldering methods together (except partial heating).
Data Sheet S15894EJ2V0DS
µPD98503
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet S15894EJ2V0DS
µPD98503
VR4120A trademark Electronics Corporation. Micro Wire trademark National Semiconductor Corp. Ethernet trademark Xerox Corp. MIPS trademark MIPS Technologies, Inc.
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