µPD98502 NETWORK CONTROLLER µPD98502 network controller netw

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µPD98502 NETWORK CONTROLLER µPD98502 network controller netw

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INTEGRATED CIRCUIT
µPD98502
NETWORK CONTROLLER
µPD98502 network controller network terminal applications such ADSL systems. functions such ATM, Ethernet, chip.
controller integrates VR4120A MIPS RISC core, memory interface, PCI, other network interface
Detailed function descriptions provided following user's manual. sure read manual before designing.
µPD98502 User's Manual: S15543E
FEATURES
Includes high performance MIPS based 64-bit RISC processor VR4120A perform RTOS network middleware (M/W) chip Includes interface PROM flash used storing boot program Includes 32-bit RISC controller ACell Processor Software processing RISC controller affords flexibility specification update Supports CBR/VBR/UBR service classes Include 2-channel 10/100-Mbps Ethernet controllers compliant IEEE802.3, IEEE 802.3u IEEE802.3x directly connect external Ethernet device through interface Includes full speed function controller compliant specification Supports operation conforming Communication Device Class Specification directly connect 64-Mbit 128-Mbit SDRAM external memory Includes 32-bit 33-MHz Master compliant Specification Rev. Includes 8-bit 16.5/25/33-MHz UTOPIA level interface compliant AForum af-phy-0039 Includes boundary scan function (JTAG) compliant IEEE 1149.1 Include UART Micro Wireinterfaces Include 2-ch general purpose timers Using advanced CMOS technology Power supply 2.5V(Core)/3.3V(I/O) Package 500-pin T-BGA
ORDERING INFORMATION
Part Number Package 500-pin tape (Heat spreader type)
µPD98502N7-H6
information this document subject change without notice. Before using this document, please confirm that this latest version.
devices/types available every country. Please check with local representative availability additional information.
Document S15409EJ2V0DS00 (2nd edition) Date Published July 2002 Printed Japan
mark
shows major revised points.
2001
µPD98502
INTERNAL BLOCK DIAGRAM
IBUS
Full-Speed Controller
VR4120A RISC Processor Core
PROM/Flash
3.3V
Ethernet Controller System Controller
SDRAM
16.5/25/33 UTOPIA
RS-232C/ Micro Wire Parallel Port
Management
ACell Processor
JTAG
JTAG Control
Clock Control
Controller
32-bit Interface
Data Sheet S15409EJ2V0DS
µPD98502
CONFIGURATION (Bottom View)
500-pin tape (Heat spreader type)
PD98502N7-H6
Index Mark
Data Sheet S15409EJ2V0DS
µPD98502
TABLE
(1/3)
Name SMA13 SMD0 SMD4 SMD7 SMD19 SMD22 SRMCS_B URDSR_B URDCD_B URDTR_B MWSK MWDI EXNMI_B POM6 EXINT_B IVDD IC-PUpR IC-PDnR IC-OPEN IC-OPEN IC-PDn EVDD EVDD PUAVD IC-OPEN PSERI_B SMA12 SMA14 SMD1 SMD5 SMD17 SMD20 SMD23 URCTS_B URSDI Name URSDO RMSL1 MWDO POM3 POM5 EVDD IC-OPEN IC-OPEN IC-PUpR IC-OPEN IC-PDn USBDP PUDVD IC-OPEN PUMD_B PHINT_B PRSTO_B PGTO0_B SMA2 SMA16 SMD2 SMD18 SMD21 SRMOE_B URRTS_B EVDD MWCS POM2 POM4 ENDCEN IC-PDnR IC-OPEN Name IC-PDnR IC-OPEN USBDM IC-OPEN PUDGND IVDD PMODE PGTO3_B PGTO1_B PRQI0_B SDWE_B SMA1 SMA11 IVDD SMD3 SMD6 EVDD IVDD URCLK IVDD IVDD POM1 IVDD IC-PDnR IVDD IC-OPEN IVDD IC-OPEN IVDD JRSTB_B IVDD PUAGND PUSTBY PARBN IVDD Name PGTO2_B PRQI1_B PAD0 SDRAS_B SMA0 SMA10 EVDD SMD16 EVDD RMSL0 POM0 POM7 IC-OPEN IC-PDn EVDD USBCLK EVDD PRQI3_B PRQI2_B PAD2 PAD4 SMA17 SDCKE1 SDCS_B EVDD EVDD Name PAD5 PAD6 SMA8 SMA15 SDCLK1 EVDD SDCAS_B PAD1 PAD3 EVDD PAD7 PAD8 SMA4 SMA7 SMA9 IVDD IVDD PCBE0_B PAD9 SMA18 SMA3 SMA5 SMA6 EVDD EVDD PAD10 PAD11 PAD12 PAD13 SMD31 SMA20 SMA19 IVDD
Data Sheet S15409EJ2V0DS
µPD98502
(2/3)
Name IVDD PAD14 PAD15 EVDD SDCLK0 SDCKE0 SMD30 EVDD PCBE1_B PSERO_B PER_B EVDD SMD28 SMD29 IVDD IVDD PSTP_B PDSEL_B EVDD SMD24 SMD25 SMD26 SMD27 PTRY_B PIRY_B PFRA_B PCBE2_B SMD13 SMD14 SMD15 IVDD Name IVDD PAD16 PAD17 PAD18 EVDD SMD12 SMD9 SMD10 SMD11 EVDD PAD19 PAD20 PAD21 SMD8 CLKUSL1 CLKUSL0 EVDD PAD22 IVDD PAD23 PCBE3_B CLKSL IC-PUp IVDD IVDD PIDSEL EVDD SCLK IC-PUp AA26 AA27 AA28 AA29 AA30 Name IVDD PAD26 PAD25 PAD24 PSCLK IC-PUp IVDD IC-PUp IVDD IVDD PAD28 EVDD PAD27 IC-OPEN PSDGND PSAGND PSAVD PSDVD PAD31 PME_B PRQO_B PAD30 PAD29 IC-OPEN PSTBY PSMD_B IVDD IVDD PGTI_B EVDD IC-OPEN AB26 AB27 AB28 AB29 AB30 AC26 AC27 AC28 AC29 AC30 AD26 AD27 AD28 AD29 AD30 AE26 AE27 AE28 AE29 AE30 Name IC-PUp IC-PDn EVDD EVDD IC-OPEN IC-OPEN RST_B IC-PUp MIRD3 IVDD IVDD IC-OPEN IC-OPEN PINT_B MIRD2 MIRD1 MIRCLK MIRER MIRDV EVDD IC-PDnR IC-OPEN MIRD0 MITER IVDD EVDD EVDD IC-PDnR IC-PDnR IC-PDnR IC-PDnR MITE AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AF27 AF28 AF29 AF30 AG10 Name MICRS MIMCLK MITD3 EVDD MI2TE EVDD UDRD1 UDRAD2 UDTAD3 UDTD7 EVDD UMWR_B EVDD EVDD IC-PDnR IC-PDnR IC-PDnR MIMD MITD2 IVDD MI2COL IVDD MI2CRS IVDD UDRSC IVDD
Data Sheet S15409EJ2V0DS
µPD98502
(3/3)
AG11 AG12 AG13 AG14 AG15 AG16 AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AG28 AG29 AG30 Name UDRD0 IVDD UDRAD1 IVDD UDTAD2 UDTAD0 IVDD UDTD1 IVDD UMMD IVDD UMD10 IVDD UMD2 UMAD11 UMAD9 IVDD UMAD2 UMAD0 IVDD MITCLK MITD1 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 Name MICOL MI2RD0 MI2MD MI2TER MI2TD3 UDRCLV UDRD4 UDTCLV IC-OPEN EVDD UDTSC EVDD UDTAD1 UDTD4 UDTD2 UMINT_B UMSL_B UMD15 UMD11 UMD5 AH25 AH26 AH27 AH28 AH29 AH30 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 Name EVDD IVDD UMAD8 UMAD7 UMAD3 UMAD1 MITD0 MI2MCLK MI2RD1 MI2RER MI2TD1 UDRE_B UDRD6 UDRD3 UDRAD4 IC-OPEN IVDD AJ17 AJ18 AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AJ30 Name UDTD5 UMRDY_B EVDD UMD13 UMD9 UMD7 UMD4 UMD1 UMAD6 UMAD4 MI2RD3 MI2RD2 MI2RCLK MI2RDV MI2TCLK MI2TD2 MI2TD0 UDRD7 AK10 AK11 AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 Name UDRD5 UDRD2 UDRCLK UDRAD3 UDRAD0 UDTE_B UDTAD4 UDTCLK UDTD6 UDTD3 UDTD0 UMRST_B UMRD_B UMD14 UMD12 UMD8 UMD6 UMD3 UMD0 UMAD10 IC-PUp UMAD5
Special name description: IC-PDn: IC-PDnR: IC-PUp: IC-PUpR: Pull Down Pull Down with Resistor Pull Pull with Resistor
Remark this document, XXX_B stands active pin.
Data Sheet S15409EJ2V0DS
µPD98502
CONTENTS FUNCTIONS Power Supply System Power Supply Power Supply System Control Interface Memory Interface Interface. AInterface
1.7.1 1.7.2 UTOPIA Management Interface UTOPIA Data Interface Ethernet Interface (Channel Ethernet Interface (Channel
Ethernet Interface
1.8.1 1.8.2
1.10 1.11 1.12 1.13 1.14 1.15 1.16 1.17 1.18
Interface UART Interface. Micro Wire Interface Parallel Port Interface. Boundary SCAN Interface. I.C. open. I.C.- pull down I.C. pull down with resistor. I.C. pull I.C. pull with resistor.
ELECTRICAL SPECIFICATIONS PACKAGE DRAWING. RECOMMENDED SOLDERING CONDITIONS
Data Sheet S15409EJ2V0DS
µPD98502
FUNCTIONS
Symbol column indicates following status this section. I/OZ Input Output Bidirection Bidirection (Include Hi-Z state) Output (Include Hi-Z state) Output (Open drain)
Power Supply
Name A27, A29, B20, B23, C16, C22, D11, E10, E12, E14, E16, E17, E19, E21, E23, E26, F27, F28, H26, H30, K26, L27, M26, N28, P26, R29, T28, U26, U29, V29, W26, AA5, AA26, AA29, AB2, AB29, AC3, AC5, AC26, AD26, AD30, AE2, AF5, AF8, AF10, AF12, AF14, AF17, AF19, AF21, AF23, AF24, AF26, AF27, AG2, AH8, AH23, AJ4, AJ6, AJ13, AJ14, AJ16, AJ18, AJ20, AJ27, AJ28 A16, C26, D10, D12, D14, D17, D19, D21, D23, D27, H27, K27, M27, P27, T27, U27, W27, AA4, AA27, AC4, AC27, AE4, AG4, AG6, AG8, AG10, AG12, AG14, AG17, AG19, AG21, AG23, AG27, AG30, AH26, AJ15 A24, A25, B15, C11, E22, E25, F26, G28, J26, K30, M30, R26, U30, W29, AA30, AB5, AB26, AD27, AE5, AE26, AF6, AF9, AF18, AF22, AF25, AH13, AH15, AH25, AJ21 Active Level Function
IVDD
Internal logic core power supply (+2.5
EVDD
External (I/O) power supply (+3.3
System Power Supply
Name PSAGND PSAVD PSDGND PSDVD Active Level Analog ground Analog power supply (+2.5 Digital ground Digital power supply (+2.5 Function
Power Supply
Name PUAGND PUAVD PUDGND PUDVD Active Level Analog ground Analog power supply (+2.5 Digital ground Digital power supply (+2.5 Function
Data Sheet S15409EJ2V0DS
µPD98502
System Control Interface
Name SCLK CLKSL PSMD_B PSTBY PUMD_B PUSTBY ENDCEN EXINT_B EXNMI_B RST_B RMSL0, RMSL1 AB30 E11, Active Level System clock MHz) Clock select MHz/H: MHz) VR4120A SDRAM System mode control normal, through)
Note
Function
System standby mode control active, standby) mode control normal, through)
Note
standby mode control active, standby) VR4120A endian mode Endian converter enable External interrupt External non-maskable interrupt System reset access width select (RMSL1/0 L/L: 32-bit, L/H: 16-bit, H/L: 8-bit)
Note PSMD_B PUMD_B pins shall connected GND. Memory Interface
Name SDCLK0, SDCLK1 SDCKE0, SDCKE1 SDCS_B SDRAS_B SDCAS_B SDWE_B SRMCS_B SRMOE_B SMA0 SMA20 Active Level SDRAM clock SDRAM clock enable Chip select address strobe Column address strobe Write enable PROM/FLASH chip select PROM/FLASH output enable Memory address Function
SMD0 SMD31
Memory data
Data Sheet S15409EJ2V0DS
µPD98502
Interface (1/2)
Name PSCLK PARBN Active Level clock MHz) arbiter enable Mode available (Connect GND) Function
Host Mode Control Internal Arbiter High Enable Disable PMODE PIDSEL mode select host, NIC) Initialization device select Mode Available
Host Mode Available (Connect GND) PDSEL_B PER_B PFRA_B PHINT_B I/OZ I/OZ I/OZ Device select Parity error Cycle frame host interrupt Mode available (Connect EVDD)
Host Mode Available PINT_B AC30 Interrupt_A Mode Available
Host Mode Available (Leave open) PIRY_B PME_B I/OZ Initiator ready Power management event Mode Available
Host Mode Available (Leave open) PRSTO_B system reset Mode Available (Leave open)
Host Mode Available PSERI_B System error Mode available (Connect EVDD)
Host Mode Available PSERO_B System error Mode Available
Host Mode Available (Leave open) PTRY_B PSTP_B PCBE[0:3]_B PRQO_B H28, L26, N30, I/OZ I/OZ I/OZ Target ready Stop request from target command byte enable request Mode Available
Host Mode Available (Leave open) PRQI[0:3]_B C30, D29, E28, request Mode available (Connect EVDD)
Host Mode Available PGTI_B AA28 grant Mode Available
Host Mode available (Connect EVDD)
Data Sheet S15409EJ2V0DS
µPD98502
(2/2)
Name PGTO[0:3]_B B30, C29, D28, Active Level grant Mode Available (Leave open) Function
Host Mode Available PAD0 PAD31 D30, G26, E29, G27, E30, F29, F30, G29, G30, H29, J27, J28, J29, J30, K28, K29, P28, P29, P30, R27, R28, R30, T26, T29, V28, V27, V26, W30, W28, Y30, Y29, I/OZ I/OZ Parity address/data address data
Data Sheet S15409EJ2V0DS
µPD98502
AInterface 1.7.1 UTOPIA Management Interface
Name UMMD UMINT_B UMRD_B UMRDY_B UMRST_B UMSL_B UMWR_B UMAD0 UMAD11 AG20 AH19 AK21 AJ19 AK20 AH20 AF20 AG29, AH30, AG28, AH29, AJ30, AK30, AJ29, AH28, AH27, AG26, AK28, AG25 AK27, AJ26, AG24, AK26, AJ25, AH24, AK25, AJ24, AK24, AJ23, AG22, AH22, AK23, AJ22, AK22, AH21 Active Level Function Management mode select Interrupt from Management read enable Management data ready reset select Management write enable address
UMD0 UMD15
Management data
1.7.2 UTOPIA Data Interface
Name CLKUSL0, CLKUSL1 Active Level UTOPIA clock select (CLKUSL1/0 L/L: MHz, H/L: MHz, L/H: 16.5 MHz) UDRCLK UDRCLV UDRE_B UDRSC UDRAD0 UDRAD4 UDRD0 UDRD7 AK11 AK13, AG13, AF13, AK12, AJ11 AG11, AF11, AK10, AJ10, AH10, AK9, AJ9, AK16 AH11 AK14 AH14 AG16, AH16, AG15, AF15, AK15 AK19, AG18, AH18, AK18, AH17, AJ17, AK17, AF16 Receive clock Receive cell available Receive enable Receive cell start Receive address Receive data Function
UDTCLK UDTCLV UDTE_B UDTSC UDTAD0 UDTAD4 UDTD0 UDTD7
Transmit clock Transmit cell available Transmit enable Transmit cell start position Transmit address Transmit data
Data Sheet S15409EJ2V0DS
µPD98502
Ethernet Interface 1.8.1 Ethernet Interface (Channel
Name MIMCLK MIMD MICOL MICRS MIRCLK MIRDV MIRER MIRD0 MIRD3 MITCLK MITE MITER MITD0 MITD3 AE1, AD2, AD1, AJ1, AH2, AG3, Active Level management clock management data Collision Carrier sense Receive clock (2.5 MHz/25 MHz) Receive data valid Receive error Receive data Transmit clock (2.5 MHz/25 MHz) Transmit enable Transmit error Transmit data Function
1.8.2 Ethernet Interface (Channel
Name MI2MCLK MI2MD MI2COL MI2CRS MI2RCLK MI2RDV MI2RER MI2RD0 MI2RD3 MI2TCLK MI2TE MI2TER MI2TD0 MI2TD3 AH4, AJ3, AK2, AK7, AJ7, AK6, Active Level management clock management data Collision Carrier sense Receive clock (2.5 MHz/25 MHz) Receive data valid Receive error Receive data Transmit clock (2.5 MHz/25 MHz) Transmit enable Transmit error Transmit data Function
Data Sheet S15409EJ2V0DS
µPD98502
Interface
Name USBCLK USBDM USBDP Active Level Function External clock MHz) data(-) data(+)
1.10 UART Interface
Name URCLK URCTS_B URDCD_B URDSR_B URDTR_B URRTS_B URSDI URSDO Active Level Function UART external clock (18.432 MHz) UART clear send UART data carrier detect UART data ready UART data terminal ready UART data request send UART serial data input UART serial data output
1.11 Micro Wire Interface
Name MWCS MWDI MWDO MWSK Active Level Micro Wire chip select Micro Wire data Micro Wire data Micro Wire sampling clock Function
1.12 Parallel Port Interface
Name POM0 POM7 E13, D13, C13, B13, C14, B14, A14, Active Level Function Parallel port signal output
1.13 Boundary SCAN Interface
Name JRSTB_B Active Level B-SCAN clock B-SCAN input-data B-SCAN output-data B-SCAN mode select B-SCAN reset Function
Data Sheet S15409EJ2V0DS
µPD98502
1.14 I.C. open
Name IC-OPEN A19, A20, A28, B16, B17, B19, B26, C18, C20, C24, D18, D20, E18, AA1, AB1, AB27, AB28, AC28, AC29, AD29, AH12, AJ12 Active Level Function Leave open
1.15 I.C.- pull down
Name IC-PDn A21, B21, E20, Active Level Function Connect
1.16 I.C. pull down with resistor
Name IC-PDnR A18, C17, C19, D15, AD28, AE27, AE28, AE29, AE30, AF28, AF29, AF30 Active Level Function Connect pull-down resistor
1.17 I.C. pull
Name IC-PUp AB3, AC1, AK29 Active Level Function Connect EVDD
1.18 I.C. pull with resistor
Name IC-PUpR A17, Active Level Function Connect EVDD pull-up resistor
Data Sheet S15409EJ2V0DS
µPD98502
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Symbol IVDD EVDD Input/output voltage VI1/VO1 VI2/VO2 VI3/VO3 Output current Storage temperature Tstg Conditions Internal logic core buffer LVTTL-level buffer buffer LVTTL-level pin; IOL= buffer buffer; IOL= Rating -0.5 +3.6 -0.5 +4.6 -0.5 +4.6 -0.5 +4.6 -0.5 +3.6 +150 Unit
Caution Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. Recommended Operating Conditions
Parameter Supply voltage Symbol IVDD EVDD Low-level input voltage VIL1 VIL2 VIL3 LVTTL-level buffer buffer, refer (10) interface parameters (Single-end operation) High-level input voltage VIH1 VIH2 VIH3 LVTTL-level buffer buffer, refer (10) interface parameters (Single-end operation) differential input voltage VIDF buffer, refer (10) interface parameters (Differential operation) Operating ambient temperature 0.5EVDD EVDD Conditions Min. 3.15 Typ. Max. 3.45 0.3EVDD Unit
Data Sheet S15409EJ2V0DS
µPD98502
Characteristics (IVDD ±0.2 EVDD ±0.15 +70°C)
Parameter Supply current Symbol IIDD EIDD Input leakage current state output current Low-level output voltage VOL1 VOL2 VOL3 High-level output voltage VOH1 VOH2 VOH3 EVDD LVTTL-level pin; buffer buffer, refer (10) interface parameters LVTTL-level pin; buffer buffer, refer (10) interface parameters 0.1EVDD EVDD Conditions Min. Typ. Max. 1310 0.1EVDD Unit
Capacitance 25°C,
Parameter Input Capacitance Output Capacitance Capacitance Symbol Conditions MHz, Unmeasured pins returned Min. Typ. Max. Unit
Data Sheet S15409EJ2V0DS
µPD98502
Classifications Input pins
Type LVTTL-level VI1, VIL1/VIH1 Names SCLK, CLKSL, PSMD, PSTBY, PUMD, PUSTBY, BIG, ENDCEN, EXINT_B, EXNMI_B, RMSL[1:0], SMD[31:0], UMINT_B, UMRDY_B, UMD[15:0], UDRCLV, UDRSC, UDRD[7:0], UDTCLV, USBCLK, URCLK, URSDI, MWDI, URCTS_B, URDCD_B, URDSR_B, JCK, JDI, JMS, JRSTB_B, MIRCLK, MIMD, MICOL, MICRS, MIRDV, MIRER, MIRD[3:0], MITCLK, MI2RCLK, MI2MD, MI2COL, MI2CRS, MI2RDV, MI2RER, MI2RD[3:0], MI2TCLK PARBN, PMODE, PSERI_B, PHINT_B, PRQI[3:0]_B, PAD[31:0], PCBE[3:0]_B, PFRA_B, PDSEL_B, PTRY_B, PIRY_B, PSTP_B, PAR, PER_B, PIDSEL, RST_B, PGTI_B, PSCLK USBDP USBDM Number Pins
buffer
VI2, VIL2/VIH2
buffer
VI3, VIL3/VIH3, VIDF
Output pins
Type LVTTL-level pins VO1, VOL1/VOH1 Names SDCLK0, SDCLK1, SDCKE0, SDCKE1, SDCS_B, SDRAS_B, SDCAS_B, SDWE_B, SRMCS_B, SRMOE_B, SMA[20:0], SMD[31:0], UMMD, UMRD_B, UMRST_B, UMSL_B, UMWR_B, UMAD[11:0], UMD[15:0], UDRCLK, UDRE_B, UDRAD[4:0], UDTCLK, UDTE_B, UDTSC, UDTAD[4:0], UDTD[7:0], URSDO, URDTR_B, URRTS_B, MWSK, MWCS, MWDO, POM[7:0], JDO, MIMCLK, MIMD, MITE, MITER, MITD[3:0], MI2MCLK, MI2MD, MI2TE, MI2TER, MI2TD[3:0] PRSTO_B, PGTO[3:0]_B, PAD[31:0], PCBE[3:0]_B, PFRA_B, PDSEL_B, PTRY_B, PIRY_B, PSTP_B, PAR, PER_B, PINT_B, PSERO_B, PME_B, PRQO_B USBDP USBDM Number Pins
buffer
VO2, VOL2/VOH2
buffer
VO3, VOL3/VOH3
Data Sheet S15409EJ2V0DS
µPD98502
Characteristics (IVDD ±0.2 EVDD ±0.15 +70°C) test waveform
Input signal 0.5EVDD Test points 0.5EVDD
Ouput signal
0.5EVDD
Test points
0.5EVDD
Clock parameters Clock timing (except clock)
Clock Cycle Clock High Width Clock Width
Clock input parameters (except clock)
Parameter SCLK input cycle SCLK input high width SCLK input width MITCLK input cycle MITCLK input high width MITCLK input width MIRCLK input cycle MIRCLK input high width MIRCLK input width MI2TCLK input cycle MI2TCLK input high width MI2TCLK input width MI2RCLK input cycle MI2RCLK input high width MI2RCLK input width USBCLK input cycle USBCLK input high width USBCLK input width input cycle input high width input width Symbol tCYSCK tWHSCK tWLSCK tCYMTK tWHMTK tWLMTK tCYMRK tWHMRK tWLMRK tCY2TK tWH2TK tWL2TK tCY2RK tWH2RK tWL2RK tCYUBK tWHUBK tWLUBK tCYJCK tWHJCK tWLJCK Conditions Min. 30.00 tCYSCK tCYSCK 40.00 tCYMTK tCYMTK 40.00 tCYMRK tCYMRK 40.00 tCY2TK tCY2TK 40.00 tCY2RK tCY2RK 83.1 tCYUBK tCYUBK 150.00 tCYJCK tCYJCK Max. 33.00 tCYSCK tCYSCK 400.00 tCYMTK tCYMTK 400.00 tCYMRK tCYMRK 400.00 tCY2TK tCY2TK 400.00 tCY2RK tCY2RK 84.6 tCYUBK tCYUBK 1000.00 tCYJCK tCYJCK Unit
Data Sheet S15409EJ2V0DS
µPD98502
Clock timing (PCI clock)
Clock Cycle Clock High Width 0.5VDD 0.4VDD 0.3VDD Clock Width
Clock input parameters (PCI clock)
Parameter PSCLK input cycle PSCLK input high width PSCLK input width Symbol tCYpCK tWHpCK tWLpCK Conditions Min. 30.00 tCYSCK tCYSCK Max. 60.00 Unit
Clock output parameters
Parameter SDCLK0 output cycle SDCLK0 output high width SDCLK0 output width SDCLK1 output cycle SDCLK1 output high width SDCLK1 output width UDTCLK output cycle UDTCLK output high width UDTCLK output width UDRCLK output cycle UDRCLK output high width UDRCLK output width MIMCLK output cycle MIMCLK output high width MIMCLK output width MI2MCLK output cycle MI2MCLK output high width MI2MCLK output width Symbol tCYSK0 tWHSK0 tWLSK0 tCYSK1 tWHSK1 tWLSK1 tCYUTK tWHUTK tWLUTK tCYURK tWHURK tWLURK tCYMCK tWHMCK tWLMCK tCYM2K tWHM2K tWLM2K Conditions Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Min. 10.00 tCYSK0 tCYSK0 10.00 tCYSK1 tCYSK1 30.00/40.00/ 60.00 tCYUTK tCYUTK 30.00/40.00/ 60.00 tCYURK tCYURK 420.00 tCYMCK tCYMCK 420.00 tCYM2K tCYM2K Max. 15.00 tCYSK0 tCYSK0 15.00 tCYSK1 tCYSK1 Unit
Data Sheet S15409EJ2V0DS
µPD98502
Reset, parameters
IVDD, EVDD
PSTBY (System PLL), PUSTBY (USB PLL) SCLK (System Clock) External Unstable Period Internal
tWHPSY, tWHUSY
tWLPLK, tWLULK RST_B (System Reset)
Stable Period
tWLRSB
Parameter RST_B Input Level Width PSTBY Hold High Level Width PSTBY Lookup Time PUSTBY Hold High Level Width PUSTBY Lookup Time
Symbol tWLRSB tWHPSY tWLPLK tWHUSY tWLULK
Conditions
Min.
Max. 4000
Note
Unit
1000
Load Load
1000
Note RST_B applied longer, operation PD98502 will start anyhow. Therefore shall made sure, that other logic also RESET state after even RST_B applied longer period.
Data Sheet S15409EJ2V0DS
µPD98502
Interrupt interface parameters
tWLEIN tWLENM EXINT_B, EXNMI_B (input)
Parameter EXINT_B input width EXNMI_B input width
Symbol tWLEIN tWLENM
Conditions
Min. tCYSK0/1 tCYSK0/1
Max.
Unit
Data Sheet S15409EJ2V0DS
µPD98502
Memory interface parameters SDCLK0 memory interface parameters
SDCLK0 (output)
tDSE0SK0
SDCKE0 (output)
tDSE0SK0
tDSCSSK0
SDCS_B (output)
tDSCSSK0
tDSRASK0
SDRAS_B (output)
tDSRASK0
tDSCASK0
SDCAS_B (output)
tDSCASK0
tDSW ESK0
SDWE_B (output)
tDSW ESK0
tDSMASK0
SMA[20:0] (output)
tDSMASK0
tDSMDSK0 Hi-Z
SMD[31:0] (output)
tDSMDSK0
tDSMDSK0 Hi-Z
tASMDSK0 tSSMDSK0 tHSMDSK0 Hi-Z
SMD[31:0] (input)
tFSMDSK0
Hi-Z
Parameter SDCKE0 output delay from SDCLK0 SDCS_B output delay from SDCLK0 SDRAS_B output delay from SDCLK0 SDCAS_B output delay from SDCLK0 SDWE_B output delay from SDCLK0 SMA[20:0] output delay from SDCLK0 SMD[31:0] output floating active delay from SDCLK0 SMD[31:0] output delay from SDCLK0 SMD[31:0] output active floating delay from SDCLK0 SMD[31:0] input setup SDCLK0 SMD[31:0] input hold from SDCLK0
Symbol tDSE0SK0 tDSCSSK0 tDSRASK0 tDSCASK0 tDSWESK0 tDSMASK0 tASMDSK0 tDSMDSK0 tFSMDSK0 tSSMDSK0 tHSMDSK0
Conditions Load Load Load Load Load Load Load Load Load
Min.
Max.
Unit
1.00
Data Sheet S15409EJ2V0DS
µPD98502
SDCLK1 memory interface parameters
SDCLK1 (output)
tDSE1SK1
SDCKE1 (output)
tDSE0SK1
tDSCSSK1
SDCS_B (output)
tDSCSSK1
tDSRASK1
SDRAS_B (output)
tDSRASK1
tDSCASK1
SDCAS_B (output)
tDSCASK1
tDSWESK1
SDWE_B (output)
tDSWESK1
tDSMASK1
SMA[20:0] (output)
tDSMASK1
tDSMDSK1 Hi-Z
SMD[31:0] (output)
tDSMDSK1
tDSMDSK1 Hi-Z
tASMDSK1 tSSMDSK1 tHSMDSK1 Hi-Z
SMD[31:0] (input)
tFSMDSK1
Hi-Z
Parameter SDCKE1 output delay from SDCLK1 SDCS_B output delay from SDCLK1 SDRAS_B output delay from SDCLK1 SDCAS_B output delay from SDCLK1 SDWE_B output delay from SDCLK1 SMA[20:0] output delay from SDCLK1 SMD[31:0] output floating active delay from SDCLK1 SMD[31:0] output delay from SDCLK1 SMD[31:0] output active floating delay from SDCLK1 SMD[31:0] input setup SDCLK1 SMD[31:0] input hold from SDCLK1
Symbol tDSE1SK1 tDSCSSK1 tDSRASK1 tDSCASK1 tDSWESK1 tDSMASK1 tASMDSK1 tDSMDSK1 tFSMDSK1 tSSMDSK1 tHSMDSK1
Conditions Load Load Load Load Load Load Load Load Load
Min.
Max.
Unit
Data Sheet S15409EJ2V0DS
µPD98502
Flash interface parameters Flash interface read cycle parameters
tSSMAROE
SMA[20:0] (output)
tHSMAROE
tSRCSROE
SRMCS_B (output)
tHRCSROE
tSSWEROE
SDWE_B (output)
tHSWEROE
tWLROE
SRMOE_B (output)
tWHROE
tSSMDROE Hi-Z
SMD[31:0] (input)
tHSMDROE Hi-Z
Parameter SMA[20:0] setup SRMOE_B SMA[20:0] hold from SRMOE_B SRMCS_B setup SRMOE_B SRMCS_B hold from SRMOE_B SDWE_B setup time SRMOE_B SDWE_B hold time from SRMOE_B SRMOE_B pulse width SRMOE_B high pulse width SMD[31:0] setup SRMOE_B SMD[31:0] hold from SRMOE_B
Symbol tSSMAROE tHSMAROE tSRCSROE tHRCSROE tSSWEROE tHSWEROE tWLROE tWHROE tSSMDROE tHSMDROE
Conditions Load Load Load Load Load Load Load Load
Min. tCYSK0/1
Max.
Unit
tCYSK0/1 tCYSK0/1 tCYSK0/1 tCYSK0/1 tCYSK0/1 tCYSK0/1
Data Sheet S15409EJ2V0DS
µPD98502
Flash interface write cycle parameters
tSSMASWE
SMA[20:0] (output)
tHSMASWE
tSRCSSWE
SRMCS_B (output)
tHRCSSWE
tWLSWE
SDWE_B (output)
tWHSWE
tSROESWE
SRMOE_B (output)
tHROESWE
tSSMDSWE Hi-Z
SMD[31:0] (output)
tHSMDSWE Hi-Z
tASMDSWE
tFSMDSWE
Parameter SMA[20:0] setup SDWE_B SMA[20:0] hold from SDWE_B SRMCS_B setup SDWE_B SRMCS_B hold from SDWE_B SRMOE_B setup time SDWE_B SRMOE_B hold time from SDWE_B SDWE_B pulse width SDWE_B high pulse width SMD[31:0] setup SDWE_B SMD[31:0] hold from SDWE_B SMD[31:0] output Hi-Z valid delay SMD[31:0] output valid Hi-Z delay
Symbol tSSMASWE tHSMASWE tSRCSSWE tHRCSSWE tSROESWE tHROESWE tWLSWE tWHSWE tSSMDSWE tHSMDSWE tASMDSWE tFSMDSWE
Conditions Load Load Load Load Load Load Load Load Load Load Load Load
Min. tCYSK0/1 tCYSK0/1 tCYSK0/1 tCYSK0/1 tCYSK0/1 tCYSK0/1 tCYSK0/1
Max.
Unit
tCYSK0/1 tCYSK0/1 tCYSK0/1
Data Sheet S15409EJ2V0DS
µPD98502
interface parameters Output timing measurement conditions
V_th Clock V_pcitest V_pcitest tDPCIPCK tDPCIPCK V_pcitfall Output V_pcitrise tFPCIPCK tAPCIPCK 3-state output V_tl
Input timing measurement conditions
V_th Clock V_pcitest V_tl tSPCIPCK Input Inputs valid tHPCIPCK V_th V_pcitest V_pcitest V_tl
Symbol V_th V_tl V_pcitest V_pcitrise V_pcitfall
Voltage Level 0.6EVDD 0.2EVDD 0.4EVDD 0.285EVDD 0.615EVDD
Unit
Parameter output delay active delay floating delay setup time hold time
Symbol tDPCIPCK tAPCIPCK tFPCIPCK tSPCIPCK tHPCIPCK
Conditions Load Load Load
Min.
Max.
Unit
Data Sheet S15409EJ2V0DS
µPD98502
Ainterface parameters UTOPIA2 interface parameters Data transmission parameters
UDTCLK (output) tSUTLUTK tHUTLUTK
UDTCLV (input) tDUTAUTK UDTAD[4:0] (output) tDUTDUTK UDTD[7:0] (output) tDUTEUTK UDTE_B (output) tDUTSUTK UDTSC (output)
Parameter UDTCLV setup time UDTCLV hold time UDTAD[4:0] output delay UDTD[7:0] output delay UDTE_B output delay UDTSC output delay
Symbol tSUTLUTK tHUTLUTK tDUTAUTK tDUTDUTK tDUTEUTK tDUTSUTK
Conditions
Min.
Max.
Unit
Load Load Load Load
Data Sheet S15409EJ2V0DS
µPD98502
Data reception parameters
UDRCLK (output) tSURLURK tHURLURK
UDRCLV (input) tDURAURK UDRAD[4:0] (output) tSURDURK tHURDURK
UDRD[7:0] (input) tDUREURK UDRE_B (output) tSURSURK tHURSURK
UDRSC (input)
Parameter UDRCLV setup time UDRCLV hold time UDRAD[4:0] output delay UDRD[7:0] setup time UDRD[7:0] hold time UDRE_B output delay UDRSC setup time UDRSC hold time
Symbol tSURLURK tHURLURK tDURAURK tSURDURK tHURDURK tDUREURK tSURSURK tHURSURK
Conditions
Min.
Max.
Unit
Load
Load
Data Sheet S15409EJ2V0DS
µPD98502
UTOPIA management interface parameters
tWLURT UMRST_B (output)
tWLUIT UMINT_B (input)
Parameter UMRST_B pulse width UMINT_B pulse width
Symbol tWLURT tWLUIT
Conditions
Min. tCYSCK tCYSCK
Max.
Unit
Data Sheet S15409EJ2V0DS
µPD98502
Intel Mode Read cycle parameters
tSUMAURD
UMAD[11:0] (output)
tHUMAURD
tSUSLURD
UMSL_B (output)
tHUSLURD
tSUWRURD
UMWR_B (output)
tHUWRURD
tWLURD
UMRD_B (output)
tSURYURD
UMRDY_B (input)
tHURYURD
tSUMDURD
UMD[15:0] (input)
tHUMDURD Hi-Z
Hi-Z
Parameter UMAD[11:0] setup UMRD_B UMAD[11:0] hold from UMRD_B UMSL_B setup UMRD_B UMSL_B hold from UMRD_B UMWR_B setup UMRD_B UMWR_B hold from UMRD_B UMRD_B pulse width UMRDY_B setup UMRD_B UMRDY_B hold from UMRD_B UMD[15:0] setup UMRD_B UMD[15:0] hold from UMRD_B
Symbol tSUMAURD tHUMAURD tSUSLURD tHUSLURD tSUWRURD tHUWRURD tWLURD tSURYURD tHURYURD tSUMDURD tHUMDURD
Conditions Load Load Load Load Load Load Load
Min.
Max.
Unit
Data Sheet S15409EJ2V0DS
µPD98502
Write cycle parameters
tSUMAUWR
UMAD[11:0] (output)
tHUMAUWR
tSUSLUWR
UMSL_B (output)
tHUSLUWR
tWLUWR
UMWR_B (output)
tSURDUWR
UMRD_B (output)
tHURDUWR
tSURYUWR
UMRDY_B (input)
tHURYUWR
tSUMDUWR
UMD[15:0] (output)
tHUMDUWR Hi-Z
Hi-Z tAUMDUWR tFUMDUWR
Parameter UMAD[11:0] setup UMWR_B UMAD[11:0] hold from UMWR_B UMSL_B setup UMWR_B UMSL_B hold from UMWR_B UMRD_B setup UMWR_B UMRD_B hold from UMWR_B UMWR_B pulse width UMRDY_B setup UMWR_B UMRDY_B hold from UMWR_B UMD[15:0] setup UMWR_B UMD[15:0] hold from UMWR_B UMD[15:0] active time UMWR_B UMD[15:0] floating time from UMWR_B
Symbol tSUMAUWR tHUMAUWR tSUSLUWR tHUSLUWR tSURDUWR tHURDUWR tWLUWR tSURYUWR tHURYUWR tSUMDUWR tHUMDUWR tAUMDUWR tFUMDUWR
Conditions Load Load Load Load Load Load Load
Min.
Max.
Unit
Load Load
Data Sheet S15409EJ2V0DS
µPD98502
Motorola Mode Read cycle parameters
tSUMADSR
UMAD[11:0] (output)
tHUMADSR
tSUSLDSR
UMSL_B (output)
tHUSLDSR
tSRWDSR
UMWR_B output)
tHRWDSR
tWLDSR
UMRD_B output)
tSDAKDSR
UMRDY_B DACK input)
tHDAKDSR
tSUMDDSR
UMD[15:0] (input)
tHUMDDSR Hi-Z
Hi-Z
Parameter UMAD[11:0] setup UMAD[11:0] hold from UMSL_B setup UMSL_B hold from setup hold from pulse width DACK setup DACK hold from UMD[15:0] setup UMD[15:0] hold from
Symbol tSUMADSR tHUMADSR tSUSLDSR tHUSLDSR tSRWDSR tHRWDSR tWLDSR tSDAKDSR tHDAKDSR tSUMDDSR tHUMDDSR
Conditions Load Load Load Load Load Load Load
Min.
Max.
Unit
Data Sheet S15409EJ2V0DS
µPD98502
Write cycle parameters
tSUMADSW
UMAD[11:0] (output)
tHUMADSW
tSUSLDSW
UMSL_B (output)
tHUSLDSW
tSRWDSW
UMWR_B output)
tHRWDSW
tWLDSW
UMRD_B output)
tSDAKDSW
UMRDY_B DACK: input)
tHDAKDSW
tSUMDDSW
UMD[15:0] (output)
tHUMDDSW Hi-Z
Hi-Z tAUMDDSW tFUMDDSW
Parameter UMAD[11:0] setup UMAD[11:0] hold from UMSL_B setup UMSL_B hold from setup hold from pulse width DACK setup DACK hold from UMD[15:0] setup UMD[15:0] hold from UMD[15:0] active time UMD[15:0] floating time from
Symbol tSUMADSW tHUMADSW tSUSLDSW tHUSLDSW tSRWDSW tHRWDSW tWLDSW tSDAKDSW tHDAKDSW tSUMDDSW tHUMDDSW tAUMDDSW tFUMDDSW
Conditions Load Load Load Load Load Load Load
Min.
Max.
Unit
Load Load
Data Sheet S15409EJ2V0DS
µPD98502
Ethernet interface parameters Ethernet interface data transmission parameters
MITCLK (input)
tDMTEMTK
MITE (output)
tDMTEMTK
tDMTDMTK
MITD[3:0] (output)
tDMTDMTK
tDMTRMTK
MITER (output)
tDMTRMTK
Parameter MITE output delay MITD[3:0] output delay MITER output delay
Symbol tDMTEMTK tDMTDMTK tDMTRMTK
Conditions Load Load Load
Min.
Max.
Note Note Note
Unit
Note specification, maximum output delay specified
Data Sheet S15409EJ2V0DS
µPD98502
data reception parameters
MIRCLK (input)
tSMRVMRK
MIRDV (input)
tHMRVMRK
tSMRDMRK
MIRD[3:0] (input)
tHMRDMRK
tSMRRMRK
MIRER (input)
tHMRRMRK
Parameter MIRDV setup time MIRDV hold time MIRD[3:0] setup time MIRD[3:0] hold time MIRER setup time MIRER hold time
Symbol tSMRVMRK tHMRVMRK tSMRDMRK tHMRDMRK tSMRRMRK tHMRRMRK
Conditions
Min.
Max.
Unit
interface signal parameters
tWHMCL MICOL (input) tWHMCS MICRS (input)
Parameter MICOL high pulse width MICRS high pulse width
Symbol tWHMCL tWHMCS
Conditions
Min. tCYMTK tCYMTK
Max.
Unit
Data Sheet S15409EJ2V0DS
µPD98502
management interface parameters
MIMCLK (output)
tSMMDMCK tHMMDMCK
MIMD (input)
tAMMDMCK
MIMD (output)
tDMMDMCK
tFMMDMCK Hi-Z
Hi-Z
Parameter MIMD setup MIMCLK MIMD hold from MIMCLK MIMD active delay from MIMCLK MIMD output delay from MIMCLK MIMD floating delay from MIMCLK
Symbol tSMMDMCK tHMMDMCK tAMMDMCK tDMMDMCK tFMMDMCK
Conditions
Min.
Max.
Unit
Load Load Load
Data Sheet S15409EJ2V0DS
µPD98502
Ethernet Interface data transmission parameters
MI2TCLK (input)
tD2TE2TK
MI2TE (output)
tD2TE2TK
tD2TD2TK
MI2TD[3:0] (output)
tD2TD2TK
tD2TR2TK
MI2TER (output)
tD2TR2TK
Parameter MI2TE output delay MI2TD[3:0] output delay MI2TER output delay
Symbol tD2TE2TK tD2TD2TK tD2TR2TK
Conditions Load Load Load
Min.
Max.
Note Note Note
Unit
Note specification, maximum output delay specified
Data Sheet S15409EJ2V0DS
µPD98502
data reception parameters
MI2RCLK (input)
tS2RV2RK
MI2RDV (input)
tH2RV2RK
tS2RD2RK
MI2RD[3:0] (input)
tH2RD2RK
tS2RR2RK
MI2RER (input)
tH2RR2RK
Parameter MI2RDV setup time MI2RDV hold time MI2RD[3:0] setup time MI2RD[3:0] hold time MI2RER setup time MI2RER hold time
Symbol tS2RV2RK tH2RV2RK tS2RD2RK tH2RD2RK tS2RR2RK tH2RR2RK
Conditions
Min.
Max.
Unit
interface signal parameters
tWH2CL MI2COL (input) tWH2CS MI2CRS (input)
Parameter MI2COL high pulse width MI2CRS high pulse width
Symbol tWH2CL tWH2CS
Conditions
Min. tCY2TK tCY2TK
Max.
Unit
Data Sheet S15409EJ2V0DS
µPD98502
management interface parameters
MI2MCLK (output)
tS2MD2CK tH2MD2CK
MI2MD (input)
tA2MD2CK
MI2MD (output)
tD2MD2CK
tF2MD2CK Hi-Z
Hi-Z
Parameter MI2MD setup MI2MCLK MI2MD hold from MI2MCLK MI2MD active delay from MI2MCLK MI2MD output delay from MI2MCLK MI2MD floating delay from MI2MCLK
Symbol tS2MD2CK tH2MD2CK tA2MD2CK tD2MD2CK tF2MD2CK
Conditions
Min.
Max.
Unit
Load Load Load
Data Sheet S15409EJ2V0DS
µPD98502
(10) interface parameters External circuitry line signals (refer chapter interface) need external resistors adjust output impedance each), code full speed mode protect output driver USBDM following figure shows typical connection diagram.
Connector USBDM EVDD
PD98502
USBDP
Data signal rise fall time
Rise time Differential Data Lines Fall time
Differential data jitter
tPERIOD 1/tDRATE
Differential Data Lines
Crossover points
tDJ1 tPERIOD tJR1
Next transitions Paired transitions
tDJ2 (n+1) tPERIOD tJR1
Differential-to-EOP transition skew width
tPERIOD 1/tDRATE Crossover points extended
Crossover point Differential Data Lines
tPERIOD tDEOP
tEOPT, tEOPR
Data Sheet S15409EJ2V0DS
µPD98502
Differential transition interval width
tPERIOD 1/tDRATE
Differential Data Lines
tFST
Receiver jitter tolerance
tPERIOD 1/tDRATE
Differential Data Lines
tJR1
tJR2
Next transitions tPERIOD tJR1 Paired transitions (n+1) tPERIOD tJR2
interface parameters (USBDM USBDP)
Parameter Rise time Fall time Differential rise fall time matching Full-speed data rate Source jitter total (including frequency tolerance): next transition paired transitions Source jitter differential transition transition Receiver jitter: next transition paired transitions Source interval Receiver interval Width interval during differential transition tJR1 tJR2 tEOPT tEOPR tFST -18.5 +18.5 tDJ1 tDJ2 tDEOP -3.5 +3.5 Symbol tFRFM tDRATE tR/tF Conditions Min. 11.97 Max. 111.11 12.03 Unit Mbps
Data Sheet S15409EJ2V0DS
µPD98502
(11) Parallel port interface parameters
SDCLK0
tDPOM
POM[7:0] (output)
Parameter POM[7:0] output delay
Symbol tDPOM
Conditions Load
Min.
Max.
Unit
Data Sheet S15409EJ2V0DS
µPD98502
(12) UART interface parameters
BAUDOUT (internal) tWLUDO URSDO (output) START tWLUDI URSDI (input) START DATA(5-8) PARITY STOP START DATA(5-8) PARITY STOP START
Remark
BAUDOUT equal transmisson baud rate (1/T Baud Rate). Customize Baud Rates achieved selecting proper divisor values baud rate generator.
Parameter Symbol tCYUCK tWLUDO tWLUDI Conditions Min. Max. 18.432 Unit
URCLK input frequency URSDO level width URSDI level width
Data Sheet S15409EJ2V0DS
µPD98502
(13) Micro Wire interface parameters
tWHWSK
MWSK (output)
tWLWSK
tCYWSK
tSWSKWCS
MWCS (output)
tSWCSWSK
tHWCSWSK
tAWDOWSK
MWDO (output)
tDWDOWSK
tDWDOWSK
tFWDOWSK
tSWDIWSK Hi-Z
tHWDIWSK Hi-Z
MWDI (Read) (input)
tAWDIWSK Hi-Z
MWDI (Status) (input)
tFWDIWSK Hi-Z
Parameter MWSK clock frequency MWSK high time MWSK time MWSK setup MWCS MWCS setup MWSK MWCS hold from MWSK
Symbol tCYWSK tWHWSK tWLWSK tSWSKWCS tSWCSWSK tHWCSWSK
Conditions Load Load Load Load Load Load Load Load Load
Min. tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0
Max.
Unit
MWDO output active floating delay from MWSK tAWDOWSK MWDO output delay from MWSK tDWDOWSK
MWDO output floating active delay from MWSK tFWDOWSK MWDI setup MWSK MWDI hold from MWSK MWCS status time from MWSK MWCS MWDO 3-state tSWDIWSK tHWDIWSK tAWDIWSK tFWDIWSK
tCYSK0 tCYSK0
Data Sheet S15409EJ2V0DS
µPD98502
(14) JTAG boundary scan parameters
(input) tSJMS (input) tSJDI (input) tDJDO (output) tWLJRT JRSTB_B (input) tDJDO tHJDI tHJMS
Parameter setup time hold time setup time hold rime output delay JRSTB_B pulse width
Symbol tSJMS tHJMS tSJDI tHJDI tDJDO tWLJRT
Conditions
Min.
Max.
Unit
Load tCYJCK
Data Sheet S15409EJ2V0DS
µPD98502
PACKAGE DRAWING
500-PIN TAPE (HEAT SPREADER TYPE) (40x40)
Index area
ITEM
MILLIMETERS 40.00±0.20 23.00 MAX. 23.00 MAX. 39.60±0.15 39.60±0.15 40.00±0.20 1.585 1.27 (T.P.) 0.60±0.10 0.80 +0.20 -0.10 1.40 +0.30 -0.20 0.15 0.75±0.15 0.30 0.25 MIN. 0.10 22.73 22.73 0.40 0.20
detail part
detail part
S500N7-127-H6-1
Data Sheet S15409EJ2V0DS
µPD98502
RECOMMENDED SOLDERING CONDITIONS
µPD98502 should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact your sales representative. Table 4-1. Surface Mounting Type Soldering Conditions
µPD98502N7-H6:
Soldering Method Infrared reflow
500-pin tape (Heat spreader type)
Soldering Conditions Package peak temperature: 235°C, Time: sec. Max. 210°C higher), Count: three times less, Exposure limit: days hours)
Note
Recommended Condition Symbol IR35-107-3
(after that, prebake 125°C
Package peak temperature: 215°C, Time: sec. Max. 200°C higher), Count: three times less, Exposure limit: days hours)
Note
VP15-107-3
(after that, prebake 125°C
Note After opening pack, store 25°C less less allowable storage period. Caution different soldering methods together.
Data Sheet S15409EJ2V0DS
µPD98502
[MEMO]
Data Sheet S15409EJ2V0DS
µPD98502
[MEMO]
Data Sheet S15409EJ2V0DS
µPD98502
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet S15409EJ2V0DS
µPD98502
VR4120A trademark Corporation. Micro Wire trademark National Semiconductor Corp. Ethernet trademark Xerox Corp. MIPS trademark MIPS Technologies, Inc.
information this document current July, 2002. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

µPD98502 NETWORK CONTROLLER µPD98502 network controller netw

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