µPD98501 NETWORK CONTROLLER µPD98501 high performance contro

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µPD98501 NETWORK CONTROLLER µPD98501 high performance contro

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INTEGRATED CIRCUIT
µPD98501
NETWORK CONTROLLER
µPD98501 high performance controller which perform protocol conversion between packets Acells, which especially suitable ADSL modem. includes high performance MIPS based 64-bit RISC processor VR4120A core, Acell processor, Ethernet controller, controller block, UTOPIA2 interface SDRAM interface. Detailed function descriptions provided following user's manual. sure read manual before designing. µPD98501 User's Manual: S14767E
FEATURES
Includes high performance MIPS based 64-bit RISC processor VR4120A perform RTOS network middleware (M/W) chip Includes interface PROM flash used storing boot program Includes 32-bit RISC controller, Acell processor Software processing RISC controller affords flexibility specification update Supports CBR/VBR/UBR service classes Includes 2-channel 10/100 Mbps Ethernet controllers compliant IEEE802.3, IEEE802.3u IEEE802.3x directly connect external Ethernet device through 3.3-V interface Includes full speed function controller compliant specification Supports operation conforming Communication Device Class Specification directly connect 64M-bit 128M-bit SDRAM external memory Includes 8-bit UTOPIA level interface compliant AForum af-phy-0039 Includes boundary scan function (JTAG) compliant IEEE 1149.1 Includes Micro Wire interface Includes 2-channel general purpose timers Using advanced CMOS technology Power supply voltage: (I/O), (Core) Package 352-pin T-BGA
ORDERING INFORMATION
Part Number Package 352-pin tape (heat spreader type)
µPD98501N7-F6
information this document subject change without notice. Before using this document, please confirm that this latest version.
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Document S14828EJ5V0DS00 (5th edition) Date Published August 2002 Printed Japan
mark
shows major revised points.
2000
µPD98501
BLOCK DIAGRAM
µPD98501
Full-speed Controller
VR4120A RISC Processor Core
PROM Flash SDRAM 3.3-V Ethernet Controller IBUS
System Controller
RS-232C/Micro Wire
Parallel Port
33-MHz UTOPIA-2
ACell Processor Management
JTAG
JTAG Controller
Clock Control Unit
Data Sheet S14828EJ5V0DS
µPD98501
CONFIGURATION (Bottom View)
352-pin tape (head spreader type)
µPD98501N7-F6
Data Sheet S14828EJ5V0DS
µPD98501
Name
Name IC-Open IVDD PUAGND EVDD EVDD IC-PUpR IC-Open IVDD IVDD EVDD UDRD1 IVDD UDRAD3 UDRAD0 UDTE_B UDTAD3 UDTD5 UDTCLK UMRST_B UDTD0 UMINT_B UMAD11 UMMD IC-PDn IC-Open IC-Open PUDVD PUDGND PUSTBY EVDD IC-Open UDRSC UDRD5 UDRD2 UDRAD2 IVDD UDTSC UDTAD2 UDTAD0 EVDD UDTD2 UDTD1 UMSL_B UMWR_B UMAD9 UMAD8 Name SCLK CLKSL IC-PDn PUMD_B PUAVD IC-PDn IC-PDn USBDP IC-PDnR IVDD UDRCLV UDRD6 UDRD3 UDRD0 UDRCLK UDTAD4 UDTAD1 UDTD7 UDTD4 IVDD UMRDY_B UMRD_B EVDD UMAD7 PSAVD PSDGND IC-PDn USBCLK IC-PDn IC-Open USBDM IC-PDnR UDRE_B UDRD7 UDRD4 UDRAD4 UDRAD1 UDTCLV EVDD IVDD UDTD6 UDTD3 UMAD10 UMAD6 UMAD5 UMAD3 Name EVDD PSDVD PSAGND IVDD UMAD4 UMAD2 EVDD SRMCS_B SRMOE_B PSTBY PSMD_B UMAD1 UMAD0 IC-PUpR IC-PUpR SMD30 SMD31 IVDD IC-PUpR IC-PUpR IC-PUpR IC-PUpR SMD27 SMD28 SMD29 IC-PUpR IC-PUpR UMD7 IVDD SMD25 SMD26 IVDD UMD6 UMD5 UMD4 SMD22 SMD23 EVDD SMD24 UMD3 EVDD UMD2 UMD1 SMD18 SMD19 SMD20 SMD21 Name UMD0 IC-PUp IVDD SMD16 SMD17 IVDD IC-PUpR IC-PUpR IC-PUpR IC-PUpR SMA19 SMA20 EVDD IC-PUpR IC-PUpR IC-PUpR IC-PUpR SMA18 SMA17 SMA16 SMA15 MI2TD1 MI2TD0 IVDD SMA14 EVDD SMA13 SMA12 MI2TCLK MI2COL MI2TD3 MI2TD2 SMA11 IVDD SMA10 MI2TER MI2CRS IVDD SMA9 SMA8 SMA7 EVDD MI2TE MI2RCLK EVDD MI2RER AA01 AA02 AA03 AA04 AA23 AA24 AA25 AA26 AB01 AB02 AB03 AB04 AB23 AB24 AB25 AB26 AC01 AC02 AC03 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 Name SMA6 SMA5 IVDD MI2RD1 MI2RD0 MI2MD MI2RDV SMA4 SMA3 SMA2 IVDD MI2MCLK MI2RD3 MI2RD2 SMA1 EVDD SMA0 SDCKE1 IC-PDnR IC-PDnR IVDD SDCLK1 SDCS_B EVDD MITD1 MITD0 IVDD SDRAS_B SDCAS_B EVDD SDCLK0 MICRS MITD3 MITD2 SDWE_B SDCKE0 SMD15 SMD10 SMD6 EVDD SMD1 EXNMI_B POM5 POM2 POM0 URSDI
Data Sheet S14828EJ5V0DS
µPD98501
AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25 AC26 AD01 AD02 AD03 AD04 AD05 AD06 AD07 AD08 AD09
Name EVDD IC-Open EVDD IC-PUpR JRSTB_B IC-PDn ROMSEL0 MIRD2 MITER MITCLK MICOL SMD11 SMD14 SMD8 SMD4 IVDD EXINT_B POM7
AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25 AD26 AE01 AE02 AE03 AE04 AE05 AE06
Name IVDD URCLK URDSR_B/MWDO URRTS_B/MWDI IVDD IC-Open IC-PDn IC-Open IC-Open EVDD ROMSEL1 MIMCLK MIRD0 MIMD MIRER IVDD IVDD EVDD SMD9 SMD3 SMD2
AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AE26 AF01 AF02 AF03
Name ENDCEN POM6 POM3 URDCD_B/MWCS URDTR_B IC-Open IC-PUpR IC-PUpR IVDD IC-PDn IC-PDn MIRD3 IVDD MIRCLK MITE SMD13 SMD12
AF04 AF05 AF06 AF07 AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26
Name SMD5 SMD7 SMD0 RST_B EVDD POM4 POM1 IVDD URCTS_B/MWSK URSDO IC-PDn IC-Open IC-Open IVDD IC-PUpR SSEL IC-PDn MIRD1 MIRDV
Special name description: IC-PDn: IC-PDnR: IC-PUp: IC-PUpR: Pull Down Pull Down with Resistor Pull Pull with Resistor
Remark this document, XXX_B stands active pin.
Data Sheet S14828EJ5V0DS
µPD98501
CONTENTS
FUNCTIONS. Power Supply System Power Supply. Power Supply System Control Interface. Memory Interface AInterface Ethernet Interface. Interface. UART/Micro Wire Interface. 1.10 Parallel Port Interface 1.11 Boundary Scan Interface. 1.12 I.C. Open 1.13 I.C. Pull Down 1.14 I.C. Pull Down with Resistor 1.15 I.C. Pull 1.16 I.C. Pull with Resistor ELECTRICAL SPECIFICATIONS. PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS.
Data Sheet S14828EJ5V0DS
µPD98501
FUNCTIONS
Symbol column indicates following status this section. :Input :Output :Bidirection
I/OZ :Bidirection (Include Hi-Z state) I/OD :Bidirection (Open drain output) :Output (Include Hi-Z state) :Output (Open drain)
Power Supply
Name A03, A05, AB23, AC16, AC23, AD01, AE02, AE07, AE14, AF01, AF19, AF23, C16, C26, D10, D21, D22, E04, G04, H02, H26, P26, T03, T26, W03, Y23, Y26, A19, AA02, AD05, AE11, AF25, B07, B10, B14, D03, J02, L25, M04, N03, A02, A10, A14, AA01, AA26, AD14, AE24, AF11, B16, D18, E23, J01, J23, L26, M03, P25, V03, A11, AD07, AD10, AD26, AE01, AE19, AF17, C10, C21, G03, T02, T25, A07, A12, AA23, AB03, AC06, AC13, AC15, AD20, AE03, AF08, B08, B20, C24, E01, E26, K24, N04, R02, U04, U25, Y02, A06, D17, Active Level Function
IVDD
Internal logic core power supply (+2.5
EVDD
External (I/O) power supply (+3.3
System Power Supply
Name PSAGND PSAVD PSDGND PSDVD Active Level Analog ground Analog power supply (+2.5 Digital ground Digital power supply (+2.5 Function
Power Supply
Name PUAGND PUAVD PUDGND PUDVD Active Level Analog ground Analog power supply (+2.5 Digital ground Digital power supply (+2.5 Function
Data Sheet S14828EJ5V0DS
µPD98501
System Control Interface
Name Active Level System clock MHz) Clock select MHz/H: MHz) VR4120A SDRAM System mode control input normal, through) Note System standby mode control input active, standby) mode control normal, through) Note standby mode control active, standby) VR4120A endian mode Endian conversion enable External interrupt External non-maskable interrupt System reset access width (ROMSEL1/0 L/L: 32-bit, L/H: 16-bit, H/L: 8-bit) UART/Micro Wire Select UART, Micro Wire) Function
SCLK CLKSL PSMD_B PSTBY PUMD_B PUSTBY ENDCEN EXINT_B EXNMI_B RST_B ROMSEL0, ROMSEL1
AE18 AE08 AD08 AC08 AF07 AC21, AD21
SSEL
AF21
Note PSMD_B PUMD_B pins shall connected GND.
Memory Interface
Name SDCLK0, SDCLK1 SDCKE0, SDCKE1 SDCS_B SDRAS_B SDCAS_B SDWE_B SRMCS_B SRMOE_B SMA0 SMA20 AB04, AA03 AC02, AA04 AB01 AB02 AC01 Y03, Y01, W04, W02, W01, V02, V01, U03, U02, U01, T04, T01, R04, R03, R01, P04, P03, P02, P01, N01, AF06, AC07, AE06, AE05, AD06, AF04, AC05, AF05, AD04, AE04, AC04, AD02, AF03, AF02, AD03, AC03, M01, M02, L01, L02, L03, L04, K01, K02, K04, J03, J04, H01, H03, H04, G01, Active Level SDRAM clock SDRAM clock enable SDRAM chip select SDRAM address strobe SDRAM column address strobe SDRAM/PROM/FLASH write enable PROM/FLASH chip select PROM/FLASH output enable Memory address Function
SMD0-SMD31
Memory data
Data Sheet S14828EJ5V0DS
µPD98501
AInterface
UTOPIA management interface
Name UMMD UMINT_B UMRD_B UMRDY_B UMRST_B UMSL_B UMWR_B UMAD0 UMAD11 F24, F23, E25, D26, E24, D25, D24, C25, B26, B25, D23, L23, K26, K25, K23, J26, J25, J24, Active Level Function Management mode select Interrupt from Management read enable Management data ready reset select Management write enable address
UMD0 UMD7
Management data
UTOPIA data interface
Name UDRCLK UDRCLV UDRE_B UDRSC UDRAD0 UDRAD4 UDRD0 UDRD7 A16, D15, B15, A15, C14, A13, B13, C13, D13, B12, C12, B19, C18, B18, A18, A23, B22, B21, D20, C20, A20, D19, Active Level Receive clock Receive cell available Receive enable Receive cell start Receive address Receive data Function
UDTCLK UDTCLV UDTE_B UDTSC UDTAD0 UDTAD4 UDTD0 UDTD7
Transmit clock Transmit Cell Available Transmit enable Transmit Cell start position Transmit address Transmit data
Data Sheet S14828EJ5V0DS
µPD98501
Ethernet Interface
Ethernet interface (Channel
Name MIRCLK MIMCLK MIMD MICOL MICRS MIRDV MIRER MIRD0 MIRD3 MITCLK MITE MITER MITD0 MITD3 AE25 AD22 AD24 AC26 AB24 AF26 AD25 AD23, AF24, AC22, AE23 AC25 AE26 AC24 AA25, AA24, AB26, AB25 Active Level Function Receive clock (2.5 MHz/25 MHz) Management clock Management data Collision Carrier sense Receive data valid Receive error Receive data Transmit clock (2.5 MHz/25 MHz) Transmit enable Transmit error Transmit data
Ethernet interface (Channel
Name MI2RCLK MI2MCLK MI2MD MI2COL MI2CRS MI2RDV MI2RER MI2RD0 MI2RD3 MI2TCLK MI2TE MI2TER MI2TD0 MI2TD3 V24, V23, W26, P24, P23, R26, Active Level Function Receive clock (2.5 MHz/25 MHz) Management clock Management data Collision Carrier sense Receive data valid Receive error Receive data Transmit clock (2.5 MHz/25 MHz) Transmit enable Transmit error Transmit data
Data Sheet S14828EJ5V0DS
µPD98501
Interface
Name USBCLK USBDM USBDP Active Level Function External clock MHz) data data
UART/Micro Wire Interface
Name URCLK URSDO URSDI URDTR_B URRTS_B /MWDI URCTS_B /MWSK URDCD_B /MWCS URDSR_B /MWDO AD12 AE12 AF12 AD11 AF13 AC12 AE13 AD13 Active Level Function UART external clock (18.432 MHz) UART serial data output UART serial data input UART data terminal ready UART data request send Micro Wire data UART clear send Micro Wire sampling clock UART data carrier detect Micro Wire chip select UART data ready Micro Wire data
Remark function multiplexed pins (AD13, AF12, AE12, AD12), function determined follows. SSEL UART operation mode SSEL Micro Wire operation mode
1.10 Parallel Port Interface
Name POM0 POM7 AC11, AF10, AC10, AE10, AF09, AC09, AE09, AD09 Active Level Function Parallel port signal output
1.11 Boundary Scan Interface
Name JRSTB_B AE20 AF20 AC19 AD19 AC18 Active Level B-SCAN clock B-SCAN input-data B-SCAN output-data B-SCAN mode select B-SCAN reset Function
Data Sheet S14828EJ5V0DS
µPD98501
1.12 I.C. Open
Name IC-Open A09, B09, A01, B02, D07, B03, AC14, AD15, AD17, AD18, AE15, AF15, AF16 Active Level Function Leave open
1.13 I.C. Pull Down
Name IC-PDn AF22, C03, B01, D04, C06, D06, C07, AE21, AC20, AD16, AE22, AF14 Active Level Function Connect
1.14 I.C. Pull Down with Resistor
Name IC-PDnR C09, D09, Y24, Active Level Function Connect pulldown resistor
1.15 I.C. Pull
Name IC-PUp Active Level Function Connect EVDD
1.16 I.C. Pull with Resistor
Name IC-PUpR A08, H24, H23, G26, G25, G24, G23, F26, F25, N26, N25, N24, N23, M26, M25, M23, M24, AC17, AE16, AE17, AF18 Active Level Function Connect EVDD pull-up resistor
Data Sheet S14828EJ5V0DS
µPD98501
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Symbol IVDD EVDD Input/output voltage VI1/VO1 VI2/VO2 Output current Storage temperature Tstg Conditions Internal logic core buffer LVTTL-level buffer LVTTL-level pin, buffer, Ratings -0.5 +3.6 -0.5 +4.6 -0.5 +4.6 -0.5 +4.6 +150 Unit
Caution Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. Recommended Operating Conditions
Parameter Supply voltage Symbol IVDD EVDD level input voltage VIL1 VIL2 LVTTL-level I/O/ buffer, refer Interface Parameter (Single-end operation) LVTTL-level I/O/ buffer, refer Interface Parameter (Single-end operation) buffer, refer Interface Parameter (Differential operation) Conditions MIN. 2.35 3.15 TYP. MAX. 2.65 3.45 Unit
High level input voltage
VIH1 VIH2
differential input voltage
VIDF
Operating ambient temperature
Data Sheet S14828EJ5V0DS
µPD98501
Characteristics (IVDD 0.15 EVDD 0.15
Parameter Supply current Symbol IIDD EIDD Input leakage current state output current level output voltage VOL1 VOL2 EVDD EVDD LVTTL-level pin, buffer, refer Interface Parameter LVTTL-level pin, IOH= buffer, refer Interface Parameter EVDD Conditions MIN. TYP. MAX. 1100 Unit
High level output voltage
VOH1 VOH2
Capacitance 25°C,
Parameter Input Capacitance Output Capacitance Capacitance Symbol MHz, Unmeasured pins returned Conditions MIN. TYP. MAX. Unit
Data Sheet S14828EJ5V0DS
µPD98501
Classifications Input pins
Number Pins
Category LVTTL-level VI1, VIL1/VIH1
Application Pins BIG, CLKSL, ENDCEN, EXINT_B, EXNMI_B, JCK, JDI, JMS, JRSTB_B, MI2COL, MI2CRS, MI2MD, MI2RCLK, MI2RD[3:0], MI2RDV, MI2RER, MI2TCLK, MICOL, MICRS, MIMD, MIRCLK, MIRD[3:0], MIRDV, MIRER, MITCLK, MWDI, PSMD_B, PSTBY, PUMD_B, PUSTBY, ROMSEL[1:0], RST_B, SCLK, SMD[31:0], SSEL, UDRCLV, UDRD[7:0], UDRSC, UDTCLV, UMD[7:0], UMINT_B, UMRDY_B, URCLK, URCTS_B, URDCD_B, URDSR_B, URSDI, USBCLK USBDP, USBDM
buffer
VI2, VIL2/VIH2, VIDF
Output pins
Number Pins
Category LVTTL-level VO1, VOL1/VOH1
Application Pins JDO, MI2MCLK, MI2MD, MI2TD[3:0], MI2TE, MI2TER, MIMCLK, MIMD, MITD[3:0], MITE, MITER, MWCS, MWDO, MWSK, POM[7:0], SDCAS_B, SDCKE0, SDCKE1, SDCLK0, SDCLK1, SDCS_B, SDRAS_B, SDWE_B, SMA[20:0], SMD[31:0], SRMCS_B, SRMOE_B, UDRAD[4:0], UDRCLK, UDRE_B, UDTAD[4:0], UDTCLK, UDTD[7:0], UDTE_B, UDTSC, UMAD[11:0], UMD[7:0], UMMD, UMRD_B, UMRST_B, UMSL_B, UMWR_B, URDTR_B, URRTS_B, URSDO USBDP, USBDM
buffer
VO2, VOL2/VOH2
Characteristics (IVDD 0.15 EVDD 0.15 Test Waveform
Input signal
0.5EVDD
Test points
0.5EVDD
Ouput signal
0.5EVDD
Test points
0.5EVDD
Data Sheet S14828EJ5V0DS
µPD98501
Clock parameter
Clock Cycle Clock High Width Clock Width
(2)-1 Clock input
Parameter SCLK input cycle SCLK input high level width SCLK input level width MITCLK input cycle MITCLK input high level width MITCLK input level width MIRCLK input cycle MIRCLK input high level width MIRCLK input level width MI2TCLK input cycle MI2TCLK input high level width MI2TCLK input level width MI2RCLK input cycle MI2RCLK input high level width MI2RCLK input level width USBCLK input cycle USBCLK input high level width USBCLK input level width input cycle input high level width input level width Symbol tCYSCK tWHSCK tWLSCK tCYMTK tWHMTK tWLMTK tCYMRK tWHMRK tWLMRK tCY2TK tWH2TK tWL2TK tCY2RK tWH2RK tWL2RK tCYUBK tWHUBK tWLUBK tCYJCK tWHJCK tWLJCK Conditions MIN. 30.0 tCYSCK tCYSCK 40.0 tCYMTK tCYMTK 40.0 tCYMRK tCYMRK 40.0 tCY2TK tCY2TK 40.0 tCY2RK tCY2RK 83.1 tCYUBK tCYUBK 100.0 tCYJCK tCYJCK MAX. 40.0 tCYSCK tCYSCK 400.0 tCYMTK tCYMTK 400.0 tCYMRK tCYMRK 400.0 tCY2TK tCY2TK 400.0 tCY2RK tCY2RK 84.6 tCYUBK tCYUBK 1000.0 tCYJCK tCYJCK Unit
Data Sheet S14828EJ5V0DS
µPD98501
(2)-2 Clock output
Parameter SDCLK0 output cycle SDCLK0 output high level width SDCLK0 output level width SDCLK1 output cycle SDCLK1 output high level width SDCLK1 output level width UDTCLK output cycle UDTCLK output high level width UDTCLK output level width UDRCLK output cycle UDRCLK output high level width UDRCLK output level width MIMCLK output cycle MIMCLK output high level width MIMCLK output level width MI2MCLK output cycle MI2MCLK output high level width MI2MCLK output level width Symbol tCYSK0 tWHSK0 tWLSK0 tCYSK1 tWHSK1 tWLSK1 tCYUTK tWHUTK tWLUTK tCYURK tWHURK tWLURK tCYMCK tWHMCK tWLMCK tCYM2K tWHM2K tWLM2K Conditions Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load Load MIN. 10.0 tCYSK0 tCYSK0 10.0 tCYSK1 tCYSK1 30.0 tCYUTK tCYUTK 30.0 tCYURK tCYURK 420.0 tCYMCK tCYMCK 420.0 tCYM2K tCYM2K MAX. 15.0 tCYSK0 tCYSK0 15.0 tCYSK1 tCYSK1 Unit
Data Sheet S14828EJ5V0DS
µPD98501
Reset, parameter
IVDD, EVDD
PSTBY (System PLL), PUSTBY (USB PLL)
tWHPSY, tWHUSY SCLK (System clock) External Unstable Period Internal
tWLPLK, tWLULK
Stable Period
RST_B (System Reset) tWLRSB
Parameter RST_B input level width PSTBY hold high level width PSTBY lookup time PUSTBY hold high level width PUSTBY lookup time
Symbol tWLRSB tWHPSY tWLPLK tWHUSY tWLULK
Conditions
MIN. tCYSCK
MAX.
Unit
Load
1000
Load
1000
Interrupt interface parameter
tWLEIT, tWLENM
EXINT_B EXNMI_B (input)
Parameter EXINT_B input level width EXNMI_B input level width
Symbol tWLEIN tWLENM
Conditions
MIN. tCYSK0 tCYSK0
MAX.
Unit
Data Sheet S14828EJ5V0DS
µPD98501
SDRAM interface parameter
SDCLK0 (output)
tDSE0SK0
SDCKE0 (output)
tDSE0SK0
tDSCSSK0
SDCS_B (output)
tDSCSSK0
tDSRASK0
SDRAS_B (output)
tDSRASK0
tDSCASK0
SDCAS_B (output)
tDSCASK0
tDSW ESK0
SDWE_B (output)
tDSW ESK0
tDSMASK0
SMA[20:0] (output)
tDSMASK0
tDSMDSK0
SMD[31:0] (output)
tDSMDSK0
tDSMDSK0
Hi-Z
tASMDSK0 tSSMDSK0 tHSMDSK0 tFSMDSK0
Hi-Z
SMD[31:0] (input)
Hi-Z
Hi-Z
Parameter SDCKE0 output delay from SDCLK0 SDCS_B output delay from SDCLK0 SDRAS_B output delay from SDCLK0 SDCAS_B output delay from SDCLK0 SDWE_B output delay from SDCLK0 SMA[20:0] output delay from SDCLK0 SMD[31:0] output floating active delay from SDCLK0 SMD[31:0] output delay from SDCLK0 SMD[31:0] output active floating delay from SDCLK0 SMD[31:0] input setup SDCLK0 SMD[31:0] input hold from SDCLK0
Symbol tDSE0SK0 tDSCSSK0 tDSRASK0 tDSCASK0 tDSWESK0 tDSMASK0 tASMDSK0
Conditions Load Load Load Load Load Load Load
MIN.
MAX.
Unit
tDSMDSK0 tFSMDSK0
Load Load
tSSMDSK0 tHSMDSK0
Data Sheet S14828EJ5V0DS
µPD98501
SDCLK1 (output)
tDSE1SK1
SDCKE1 (output)
tDSE0SK1
tDSCSSK1
SDCS_B (output)
tDSCSSK1
tDSRASK1
SDRAS_B (output)
tDSRASK1
tDSCASK1
SDCAS_B (output)
tDSCASK1
tDSWESK1
SDWE_B (output)
tDSWESK1
tDSMASK1
SMA[20:0] (output)
tDSMASK1
tDSMDSK1
SMD[31:0] (output)
tDSMDSK1
tDSMDSK1
Hi-Z
tASMDSK1 tSSMDSK1 tHSMDSK1 tFSMDSK1
Hi-Z
SMD[31:0] (input)
Hi-Z
Hi-Z
Parameter SDCKE1 output delay from SDCLK1 SDCS_B output delay from SDCLK1 SDRAS_B output delay from SDCLK1 SDCAS_B output delay from SDCLK1 SDWE_B output delay from SDCLK1 SMA[20:0] output delay from SDCLK1 SMD[31:0] output floating active delay from SDCLK1 SMD[31:0] output delay from SDCLK1 SMD[31:0] output active floating delay from SDCLK1 SMD[31:0] input setup SDCLK1 SMD[31:0] input hold from SDCLK1
Symbol tDSE1SK1 tDSCSSK1 tDSRASK1 tDSCASK1 tDSWESK1 tDSMASK1 tASMDSK1
Conditions Load Load Load Load Load Load Load
MIN.
MAX.
Unit
tDSMDSK1 tFSMDSK1
Load Load
tSSMDSK1 tHSMDSK1
Data Sheet S14828EJ5V0DS
µPD98501
Flash interface parameter <Read cycle>
(=4)
SDCLK (internal) tSSMAROE SMA[20:0] (output) tSRCSROE SRMCS_B (output) tSSWEROE SDWE_B (output) tWLROE SRMOE_B (output) tSSMDROE SMD[31:0] (input) Hi-Z tHSMDROE Hi-Z tWHROE tHSWEROE tHRCSROE tHSMAROE
Parameter SMA[20:0] setup SRMOE_B SMA[20:0] hold from SRMOE_B SRMCS_B setup SRMOE_B SRMCS_B hold from SRMOE_B SDWE_B setup time SRMOE_B SDWE_B hold time from SRMOE_B SRMOE_B level pulse width SRMOE_B high level pulse width SMD[31:0] setup SRMOE_B SMD[31:0] hold from SRMOE_B
Symbol tSSMAROE tHSMAROE tSRCSROE tHRCSROE tSSWEROE tHSWEROE tWLROE tWHROE tSSMDROE tHSMDROE
Condition Load Load Load Load Load Load Load Load
MIN. tCYSK0 tCYSK0 tCYSK0
MAX.
Unit
tCYSK0 tCYSK0 tCYSK0 tCYSK0 10.0
Data Sheet S14828EJ5V0DS
µPD98501
<Write cycle>
(=4)
SDCLK (internal) tSSMASWE SMA[20:0] (output) tSRCSSWE SRMCS_B (output) tWLSWE SDWE_B (output) tSROESWE SRMOE_B (output) tSSMDSWE SMD[31:0] (output) Hi-Z tHSMDSWE Hi-Z tHROESWE tWHSWE tHRCSSWE tHSMASWE
tASMDSWE
tFSMDSWE
Parameter SMA[20:0] setup SDWE_B SMA[20:0] hold from SDWE_B SRMCS_B setup SDWE_B SRMCS_B hold from SDWE_B SRMOE_B setup time SDWE_B SRMOE_B hold time from SDWE_B SDWE_B level pulse width SDWE_B high level pulse width SMD[31:0] setup SDWE_B SMD[31:0] hold from SDWE_B SMD[31:0] output floating active delay from SDWE_B SMD[31:0] output active floating delay from SDWE_B
Symbol tSSMASWE tHSMASWE tSRCSSWE tHRCSSWE tSROESWE tHROESWE tWLSWE tWHSWE tSSMDSWE tHSMDSWE tASMDSWE
Condition Load Load Load Load Load Load Load Load Load Load Load
MIN. tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0
MAX.
Unit
tCYSK0 tCYSK0 tCYSK0
tFSMDSWE
Load
Data Sheet S14828EJ5V0DS
µPD98501
Ainterface parameter (7)-1 UTOPIA2 interface <Data transmission>
UDTCLK (output)
tSUTLUTK
tHUTLUTK
UDTCLV (input)
tDUTAUTK
UDTAD[4:0] (output)
tDUTDUTK
UDTD[7:0] (output)
tDUTEUTK
UDTE_B (output)
tDUTSUTK
UDTSC (output)
Parameter UDTCLV setup time UDTCLK UDTCLV hold time from UDTCLK UDTAD[4:0] output delay from UDTCLK UDTD[7:0] output delay from UDTCLK UDTE_B output delay from UDTCLK UDTSC output delay from UDTCLK
Symbol tSUTLUTK tHUTLUTK tDUTAUTK tDUTDUTK tDUTEUTK tDUTSUTK
Conditions
MIN.
MAX.
Unit
Load Load Load Load
15.0 15.0 15.0 15.0
Data Sheet S14828EJ5V0DS
µPD98501
<Data reception>
UDRCLK (output)
tSURLURK tHURLURK
UDRCLV (input)
tDURAURK
UDRAD[4:0] (output)
tSURDURK tHURDURK
UDRD[7:0] (input)
tDUREURK
UDRE_B (output)
tSURSURK tHURSURK
UDRSC (input)
Parameter UDRCLV setup time UDRCLK UDRCLV hold time from UDRCLK UDRAD[4:0] output delay from UDRCLK UDRD[7:0] setup from UDRCLK UDRD[7:0] hold time from UDRCLK UDRE_B output delay from UDRCLK UDRSC setup time UDRCLK UDRSC hold time from UDRCLK
Symbol tSURLURK tHURLURK tDURAURK
Conditions
MIN.
MAX.
Unit
Load
15.0
tSURDURK tHURDURK tDUREURK tSURSURK tHURSURK Load
15.0
Data Sheet S14828EJ5V0DS
µPD98501
(7)-2 UTOPIA management interface <Interface signals>
tWLURT UMRST_B (output) tWLUIT UMINT_B (input)
Parameter UMRST_B level pulse width UMINT_B level pulse width
Symbol tWLURT tWLUIT
Conditions
MIN. tCYSCK tCYSCK
MAX.
Unit
Data Sheet S14828EJ5V0DS
µPD98501
<Read cycle Intel mode>
tSUMAURD
UMAD[11:0] (output)
tHUMAURD
tSUSLURD
UMSL_B (output)
tHUSLURD
tSUW RURD
UMWR_B (output)
tHUWRURD
LURD
UMRD_B (output)
tSURYURD
UMRDY_B (input)
tHURYURD
tSUMDURD
UMD[7:0] (input)
tHUMDURD
Hi-Z
Hi-Z
Parameter UMAD[11:0] setup UMRD_B UMAD[11:0] hold from UMRD_B UMSL_B setup UMRD_B UMSL_B hold from UMRD_B UMWR_B setup UMRD_B UMWR_B hold from UMRD_B UMRD_B level pulse width UMRDY_B setup UMRD_B UMRDY_B hold from UMRD_B UMD[7:0] setup UMRD_B UMD[7:0] hold from UMRD_B
Symbol tSUMAURD tHUMAURD tSUSLURD tHUSLURD tSUWRURD tHUWRURD tWLURD tSURYURD tHURYURD tSUMDURD tHUMDURD
Conditions Load Load Load Load Load Load Load
MIN.
MAX.
Unit
Data Sheet S14828EJ5V0DS
µPD98501
<Read cycle Motorola mode>
tSUMADSR
UMAD[11:0] (output)
tHUMADSR
tSUSLDSR
UMSL_B (output)
tHUSLDSR
tSRWDSR
UMWR_B output)
tHRW
LDSR
UMRD_B output)
tSDAKDSR
UMRDY_B DACK input)
tHDAKDSR
tSUMDDSR
UMD[7:0] (input)
tHUMDDSR
Hi-Z
Hi-Z
Parameter UMAD[11:0] setup UMAD[11:0] hold from UMSL_B setup UMSL_B hold from setup hold from level pulse width DACK setup DACK hold from UMD[7:0] setup UMD[7:0] hold from
Symbol tSUMADSR tHUMADSR tSUSLDSR tHUSLDSR tSRWDSR tHRWDSR tWLDSR tSDAKDSR tHDAKDSR tSUMDDSR tHUMDDSR
Conditions Load Load Load Load Load Load Load
MIN.
MAX.
Unit
Data Sheet S14828EJ5V0DS
µPD98501
<Write cycle Intel mode>
tSUMAUW
UMAD[11:0] (output)
tHUMAUW
tSUSLUW
UMSL_B (output)
tHUSLUW
LUWR
UMWR_B (output)
tSURDUW
UMRD_B (output)
tHURDUW
tSURYUW
UMRDY_B (input)
tHURYUW
tSUMDUW
UMD[7:0] (output)
tHUMDUW
Hi-Z
tAUMDUW tFUMDUW
Hi-Z
Parameter UMAD[11:0] setup UMWR_B UMAD[11:0] hold from UMWR_B UMSL_B setup UMWR_B UMSL_B hold from UMWR_B UMRD_B setup UMWR_B UMRD_B hold from UMWR_B UMWR_B level pulse width UMRDY_B setup UMWR_B UMRDY_B hold from UMWR_B UMD[7:0] setup UMWR_B UMD[7:0] hold from UMWR_B UMD[7:0] active time UMWR_B UMD[7:0] floating time from UMWR_B
Symbol tSUMAUWR tHUMAUWR tSUSLUWR tHUSLUWR tSURDUWR tHURDUWR tWLUWR tSURYUWR tHURYUWR tSUMDUWR tHUMDUWR tAUMDUWR tFUMDUWR
Conditions Load Load Load Load Load Load Load
MIN.
MAX.
Unit
Load Load
Data Sheet S14828EJ5V0DS
µPD98501
<Write cycle Motorola mode>
tSUMADSW
UMAD[11:0] (output)
tHUMADSW
tSUSLDSW
tHUSLDSW
UMSL_B (output)
tSRWDSW
tHRWDSW
UMWR_B output)
tWLDSW
UMRD_B output)
tSDAKDSW
UMRDY_B DACK input)
tHDAKDSW
tSUMDDSW
UMD[7:0] (output)
tHUMDDSW
Hi-Z
tAUMDDSW tFUMDDSW
Hi-Z
Parameter UMAD[11:0] setup UMAD[11:0] hold from UMSL_B setup UMSL_B hold from setup hold from level pulse width DACK setup DACK hold from UMD[7:0] setup UMD[7:0] hold from UMD[7:0] active time UMD[7:0] floating time from
Symbol tSUMADSW tHUMADSW tSUSLDSW tHUSLDSW tSRWDSW tHRWDSW tWLDSW tSDAKDSW tHDAKDSW tSUMDDSW tHUMDDSW tAUMDDSW tFUMDDSW
Conditions Load Load Load Load Load Load Load
MIN.
MAX.
Unit
Load Load
Data Sheet S14828EJ5V0DS
µPD98501
Ethernet interface parameter (8)-1 Ethernet <MII data transmission>
MITCLK (input)
tDMTEMTK
MITE (output)
tDMTEMTK
tDMTDMTK
MITD[3:0] (output)
tDMTDMTK
tDMTRMTK
MITER (output)
tDMTRMTK
Parameter MITE output delay from MITCLK MITD[3:0] output delay from MITCLK MITER output delay from MITCLK
Symbol tDMTEMTK tDMTDMTK
Conditions Load Load
MIN.
MAX. Note
Note
Unit
tDMTRMTK
Load
Note
Note Spec., Maximum output delay specified
Data Sheet S14828EJ5V0DS
µPD98501
<MII data reception>
MIRCLK (input)
tSMRVMRK
MIRDV (input)
tHMRVMRK
tSMRDMRK
MIRD[3:0] (input)
tHMRDMRK
tSMRRMRK
MIRER (input)
tHMRRMRK
Parameter MIRDV setup time MIRCLK MIRDV hold time from MIRCLK MIRD[3:0] setup time MIRCLK MIRD[3:0] hold time from MIRCLK MIRER setup time MIRCLK MIRER hold time from MIRCLK
Symbol tSMRVMRK tHMRVMRK tSMRDMRK tHMRDMRK tSMRRMRK tHMRRMRK
Conditions
MIN.
MAX.
Unit
<MII interface signals>
tWHMCL MICOL (input) tWHMCS MICRS (input)
Parameter MICOL high level pulse width MICRS high level pulse width
Symbol tWHMCL tWHMCS
Conditions
MIN. tCYMTK tCYMTK
MAX.
Unit
Data Sheet S14828EJ5V0DS
µPD98501
<MII management interface>
MIMCLK (output)
tSMMDMCK tHMMDMCK
MIMD (input)
tAMMDMCK
MIMD (output)
tDMMDMCK
tFMMDMCK
Parameter MIMD setup MIMCLK MIMD hold from MIMCLK MIMD active delay from MIMCLK MIMD output delay from MIMCLK MIMD floating delay from MIMCLK
Symbol tSMMDMCK tHMMDMCK tAMMDMCK tDMMDMCK tFMMDMCK
Condition
MIN.
MAX.
Unit
Load Load Load
Data Sheet S14828EJ5V0DS
µPD98501
(8)-2 Ethernet <MII data transmission>
MI2TCLK (input)
tD2TE2TK
MI2TE (output)
tD2TE2TK
tD2TD2TK
MI2TD[3:0] (output)
tD2TD2TK
tD2TR2TK
MI2TER (output)
tD2TR2TK
Parameter MI2TE output delay from MI2TCLK MI2TD[3:0] output delay from MI2TCLK MI2TER output delay from MI2TCLK
Symbol tD2TE2TK tD2TD2TK tD2TR2TK
Conditions Load Load Load
MIN.
MAX.
Note
Unit
Note
Note
Note Spec., Maximum output delay specified
Data Sheet S14828EJ5V0DS
µPD98501
<MII data reception>
MI2RCLK (input)
tS2RV2RK
MI2RDV (input)
tH2RV2RK
tS2RD2RK
MI2RD[3:0] (input)
tH2RD2RK
tS2RR2RK
MI2RER (input)
tH2RR2RK
Parameter MI2RDV setup time MI2RCLK MI2RDV hold time from MI2RCLK MI2RD[3:0] setup time MI2RCLK MI2RD[3:0] hold time from MI2RCLK MI2RER setup time MI2RCLK MI2RER hold time from MI2RCLK
Symbol tS2RV2RK tH2RV2RK tS2RD2RK tH2RD2RK tS2RR2RK tH2RR2RK
Conditions
MIN.
MAX.
Unit
<MII interface signals>
tWH2CL MI2COL (input) tWH2CS MI2CRS (input)
Parameter MI2COL high level pulse width MI2CRS high level pulse width
Symbol tWH2CL tWH2CS
Conditions
MIN. tCY2TK tCY2TK
MAX.
Unit
Data Sheet S14828EJ5V0DS
µPD98501
<MII management interface>
MI2MCLK (output)
tS2MD2CK tH2MD2CK
MI2MD (input)
tA2MD2CK
MI2MD (output)
tD2MD2CK
tF2MD2CK
Parameter MI2MD setup MI2MCLK MI2MD hold from MI2MCLK MI2MD active delay from MI2MCLK MI2MD output delay from MI2MCLK MI2MD floating delay from MI2MCLK
Symbol tS2MD2CK tH2MD2CK tA2MD2CK tD2MD2CK tF2MD2CK
Condition
MIN.
MAX.
Unit
Load Load Load
Data Sheet S14828EJ5V0DS
µPD98501
interface parameter External Circuitry line signals (refer chapter interface) need external resistors adjust output impedance each), code full speed mode protect output driver USBDM following figure shows typical connection diagram.
Connector USBDM EVDD
PD98501
USBDP
Parameter: USBDM, USBDP <Data signal rise fall>
Rise time Differential Data Lines Fall time
<Differential data jitter>
tPERIOD 1/tDRATE Crossover points Differential Data Lines tPERIOD tDJ1 Next transitions Paired transitions
tPERIOD tDJ2
<Differential-to-EOP transition skew width>
tPERIOD 1/tDRATE Crossover points extended
Differential Data Lines
Crossover points
tPERIOD tDEOP
tEOPT, tEOPR
Data Sheet S14828EJ5V0DS
µPD98501
<Differential transition interval width>
tPERIOD 1/tDRATE
Differential Data Lines
tFST
<Receiver jitter tolerance>
tPERIOD 1/tDRATE
Differential Data Lines
tJR1
tJR2
Next transitions tPERIOD tJR1 Paired transitions (n+1) tPERIOD tJR2
Parameter Rise time Fall time Differential rise fall time matching Full-speed data rate Source jitter total (including frequency tolerance): next transition paired transitions Source jitter differential transition transition Receiver jitter: next transition paired transitions Source interval Receiver interval Width interval during differential transition
Symbol tFRFM tDRATE
Condition Load Load tR/tF
MIN. 90.0 11.97
MAX. 20.0 20.0 111.1 12.13
Unit Mbps
tDJ1 tDJ2 tDEOP
-3.5 -4.0 -2.0
+3.5 +4.0 +5.0
tJR1 tJR2 tEOPT tEOPR tFST -18.5 -9.0 160.0 82.0 14.0 +18.5 +9.0 175.0
Data Sheet S14828EJ5V0DS
µPD98501
(10) Parallel port interface parameter SDCLK0
tDPOM
POM[7:0] (output)
Parameter POM[7:0] output delay
Symbol tDPOM
Conditions Load
MIN.
MAX.
Unit
(11) UART interface parameter
BAUDOUT (internal) tWLUDO URSDO (output) START tWLUDI URSDI (input) START DATA(5-8) PARITY STOP START DATA(5-8) PARITY STOP START
Remark
BAUDOUT equal transmisson baud rate (1/T Baud Rate). Customize Baud Rates achieved selecting proper divisor values baud rate generator.
Parameter Symbol fCYUCK tWLUDO tWLUDI Conditions MIN. MAX. 18.432 Unit
URCLK input frequency URSDO level width URSDI level width
Data Sheet S14828EJ5V0DS
µPD98501
(12) Micro Wire interface parameter
tWHWSK
URCTS_B MWSK output)
tWLWSK
tCYWSK
tSWSKWCS
tSWCSWSK
tHWCSWSK
URDCD_B MWCS :output)
tAWDOWSK
tDWDOWSK
tDWDOWSK
tFWDOWSK
URDSR_B MWDO output)
tSWDIWSK
tHWDIWSK
URRTS_B (Read) MWDI input)
Hi-Z
tAWDIWSK tFWDIWSK
Hi-Z
URRTS_B (Status) MWDI input)
Hi-Z
Hi-Z
Parameter MWSK clock cycle MWSK high time MWSK time MWSK setup MWSK MWCS setup MWSK MWCS hold from MWSK MWDO output active floating delay from MWSK MWDO output delay from MWSK MWDO output floating active delay from MWSK MWDI setup MWSK MWDI hold from MWSK MWCS status time from MWSK MWCS MWDO 3-state
Symbol tCYWSK tWHWSK tWLWSK tSWSKWCS tSWCSWSK tHWCSWSK tAWDOWSK
Conditions Load Load Load Load Load Load Load
MIN. tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0 tCYSK0
MAX.
Unit
tDWDOWSK tFWDOWSK
Load Load
tSWDIWSK tHWDIWSK tAWDIWSK tFWDIWSK
tCYSK0 tCYSK0
Data Sheet S14828EJ5V0DS
µPD98501
(13) JTAG boundary-scan
(input) tSJMS (input) tSJDI (input) tDJDO (output) tWLJRT JRST_B (input) tDJDO tHJDI tHJMS
Parameter Setup Time Hold Time Setup Time Hold Time Output Delay JRSTB_B Pulse Width
Symbol tSJMS tHJMS tSJDI tHJDI tDJDO tWLJRT
Conditions
MIN.
MAX.
Unit
Load tCYJCK
Data Sheet S14828EJ5V0DS
µPD98501
PACKAGE DRAWING
352-PIN TAPE (HEAT SPREADER TYPE) (35x35)
Index area
ITEM MILLIMETERS 35.00±0.20 23.00 MAX. 23.00 MAX. 34.60±0.15 34.60±0.15 35.00±0.20 1.625 1.27 (T.P.) 0.60±0.10 0.80 +0.20 -0.10 1.40 +0.30 -0.20 0.15
detail part
detail part
0.75±0.15
0.30 0.25 MIN. 0.10 20.19 20.19 C0.4 0.20 S352N7-127-F6-2
Data Sheet S14828EJ5V0DS
µPD98501
RECOMMENDED SOLDERING CONDITIONS
µPD98501 should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact your sales representative. Table 4-1. Surface Mounting Type Soldering Conditions
µPD98501N7-F6: 352-pin tape (heat spreader type)
Recommended Condition Symbol IR35-107-3
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235°C, Time: sec. Max. 210°C higher), Count: three times less, Exposure limit: daysNote (after that, prebake 125°C hours) Package peak temperature: 215°C, Time: sec. Max. 200°C higher), Count: three times less, Exposure limit: daysNote (after that, prebake 125°C hours)
VP15-107-3
Note
After opening pack, store 25°C less less allowable storage period.
Caution different soldering methods together.
Data Sheet S14828EJ5V0DS
µPD98501
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet S14828EJ5V0DS
µPD98501
VR4120A trademark Corporation. Micro Wire trademark National Semiconductor Corp. Ethernet trademark Xerox Corp. MIPS trademark MIPS Technologies, Inc.
information this document current August, 2002. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

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