µPD98431 10/100 Mbps Ethernet CONTROLLER DESCRIPTION

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µPD98431 10/100 Mbps Ethernet CONTROLLER DESCRIPTION

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INTEGRATED CIRCUIT
µPD98431
10/100 Mbps Ethernet
CONTROLLER
DESCRIPTION
µPD98431 10/100 Mbps Ethernet controller having eight Media Access Control (MAC) ports conforming IEEE 802.3 IEEE 802.3u. Each port store packet receive data since each port receive FIFO. This reduce generation receive packet loss. Both 32-bit dual 64-bit single FIFO interface supported interfacing with higher systems. Both provide high-speed interface. This controller suitable applications such switches routers since statistics counter provided each port support RMON/SNMP. Detailed function descriptions provided following User's Manual. sure read them before designing.
µPD98431 User's Manual: (S14054E)
FEATURES
Eight 10/100 Mbps Ethernet ports conforming IEEE 802.3 IEEE 802.3u Supports Mbps serial interface interface with physical layer devices Each port receive FIFO bytes transmit FIFO. High-speed FIFO data interface 32/64 bits Full-duplex operation IEEE 802.3x flow control Statistics counter supporting RMON/SNMP Filtering conditions according address type VLAN frame detection function Mirror port function JTAG support Supply voltage:
ORDERING INFORMATION
Part Number Package 352-pin plastic
µPD98431S1-F6
Remark Active pins/signals indicated (symbol after pin/signal names) this document.
information this document subject change without notice. Before using this document, please confirm that this latest version.
devices/types available every country. Please check with local representative availability additional information.
Document S14150EJ4V0DS00 (4th edition) Date Published March 2002 CP(K) Printed Japan
mark
shows major revised points.
1999
µPD98431
BLOCK DIAGRAM
FIFO DATA
PORT#7 PORT#6 PORT#5 PORT#4 PORT#3 PORT#2 PORT#1 PORT#0 FIFO DATA Common Interface TX-FIFO RX-FIFO 10/100M
MII/10M serial
Interface TEST port JTAG
Register/Statistics Counter serial management management Interface
SYSTEM CONFIGURATION EXAMPLE SWITCH/ROUTER
Line Interface Module (LIM) 10/100M Multi-MAC Address Search Control Module Memory
µPD98421
Optical Module
10/100M Multi-PHY
PD98431
Forwarding Engine
Switch Chip
Line Interface Module (LIM) 10/100/1000M Multi-MAC
Address Search
µPD98421
Optical Module
10/100/1000M Multi-PHY
PD98433
Forwarding Engine
Switch Chip Switching Module
Data Sheet S14150EJ4V0DS
µPD98431
CONFIGURATION
352-pin plastic
µPD98431S1-F6
µPD98431
352-pin plastic View
Index mark
PD98431
352-pin plastic Bottom View
Index mark
Data Sheet S14150EJ4V0DS
µPD98431
NAMES
(1/2)
(A1) (B1) (C1) (D1) (E1) (F1) (G1) (H1) (J1) (K1) (L1) (M1) (N1) (P1) (R1) (T1) (U1) (V1) (W1) (Y1) (AA1) (AB1) (AC1) (AD1) (AE1) (AF1) (AF2) (AF3) (AF4) (AF5) (AF6) (AF7) (AF8) (AF9) (AF10) (AF11) (AF12) (AF13) (AF14) (AF15) (AF16) (AF17) (AF18) (AF19) (AF20) (AF21) (AF22) (AF23) (AF24) (AF25) Name TXFD30/FD62 TXFD29/FD61 TXFD26/FD58 TXFD23/FD55 TXFD20/FD52 TXFD17/FD49 TXFD14/FD46 TXFD10/FD42 TXFD7/FD39 TXFD4/FD36 TXFD0/FD32 RXFDQ2/FDQ2 RXFD31/FD31 RXFD30/FD30 RXFD29/FD29 RXFD27/FD27 RXFD24/FD24 RXFD21/FD21 RXFD18/FD18 RXFD14/FD14 RXFD11/FD11 RXFD8/FD8 RXFD4/FD4 RXFD0/FD0 TEST0 CRS4 TXER4 TXD42 TXCLK4 RXD43 RXD40 CRS5 TXD53 TXD50 RXD53 RXD50 CRS6 TXD62 TXD61 TXD60 RXER6 RXD61 COL7 TXEN7 TXD71 RXER7 RXD72 RESET# (AF26) (AE26) (AD26) (AC26) (AB26) (AA26) (Y26) (W26) (V26) (U26) (T26) (R26) (P26) (N26) (M26) (L26) (K26) (J26) (H26) (G26) (F26) (E26) (D26) (C26) (B26) (A26) (A25) (A24) (A23) (A22) (A21) (A20) (A19) (A18) (A17) (A16) (A15) (A14) (A13) (A12) (A11) (A10) (A9) (A8) (A7) (A6) (A5) (A4) (A3) (A2) Name TXFBA6 TXFBA3 RXFPT2 RXFPT1 RXFPT0 TXFPT1 TXFDQ2 RXFEN#/FEN# SKIP TRST# COL0 TXEN0 TXD01 RXER0 RXD02 RXCLK0 TXER1 TXD11 RXER1 RXD12 COL2 CRS2 TXER2 TXD23 TXCLK2 RXD23 RXD20 CRS3 TXD33 TXD30 RXD33 RXCLK3 TEST1 (B2) (C2) (D2) (E2) (F2) (G2) (H2) (J2) (K2) (L2) (M2) (N2) (P2) (R2) (T2) (U2) (V2) (W2) (Y2) (AA2) (AB2) (AC2) (AD2) (AE2) (AE3) (AE4) (AE5) (AE6) (AE7) (AE8) (AE9) (AE10) (AE11) (AE12) (AE13) (AE14) (AE15) (AE16) (AE17) (AE18) (AE19) (AE20) (AE21) (AE22) (AE23) (AE24) (AE25) (AD25) (AC25) (AB25) Name TXFD27/FD59 TXFD28/FD60 TXFD24/FD56 TXFD21/FD53 TXFD18/FD50 TXFD15/FD47 TXFD11/FD43 TXFD8/FD40 TXFD5/FD37 TXFD1/FD33 RXFDQ1/FDQ1 FCLK RXFA RXFD28/FD28 RXFD26/FD26 RXFD23/FD23 RXFD20/FD20 RXFD17/FD17 RXFD13/FD13 RXFD10/FD10 RXFD7/FD7 RXFD5/FD5 RXFD1/FD1 TXD43 TXEN4 TXD40 RXDV4 RXD41 COL5 TXEN5 TXD51 RXDV5 RXD51 COL6 TXD63 TXEN6 TXCLK6 RXDV6 RXD60 CRS7 TXD73 TXD70 RXDV7 RXD71 RXCLK7 TEST2 (AA25) (Y25) (W25) (V25) (U25) (T25) (R25) (P25) (N25) (M25) (L25) (K25) (J25) (H25) (G25) (F25) (E25) (D25) (C25) (B25) (B24) (B23) (B22) (B21) (B20) (B19) (B18) (B17) (B16) (B15) (B14) (B13) (B12) (B11) (B10) (B9) (B8) (B7) (B6) (B5) (B4) (B3) (C3) (D3) (E3) (F3) (G3) (H3) (J3) (K3) Name TXFBA7 TXFBA4 TXFBA0 TXFBA1 TXFPT2 TXFPT0 TXFDQ1 TXFEN#/FRW ACK# TEST3 MDIO TXER0 TXD02 TXCLK0 RXD03 RXD00 CRS1 TXD12 TXCLK1 RXD13 RXCLK1 RXD10 TXEN2 TXD22 RXER2 RXD22 RXCLK2 TXER3 TXD32 TXCLK3 RXDV3 RXD30 TXFD31/FD63 TXFD25/FD57 TXFD22/FD54 TXFD19/FD51 TXFD16/FD48 TXFD12/FD44 TXFD9/FD41 TXFD6/FD38
Remark Active pins/signals indicated (symbol after pin/signal names) this document.
Data Sheet S14150EJ4V0DS
µPD98431
(2/2)
(L3) (M3) (N3) (P3) (R3) (T3) (U3) (V3) (W3) (Y3) (AA3) (AB3) (AC3) (AD3) (AD4) (AD5) (AD6) (AD7) (AD8) (AD9) (AD10) (AD11) (AD12) (AD13) (AD14) (AD15) (AD16) (AD17) (AD18) (AD19) (AD20) (AD21) (AD22) (AD23) (AD24) (AC24) (AB24) (AA24) Name TXFD3/FD35 TXFD2/FD34 RXFDQ0/FDQ0 RXFDQ3/FDQ3 RXFD25/FD25 RXFD22/FD22 RXFD19/FD19 RXFD16/FD16 RXFD12/FD12 RXFD9/FD9 RXFD6/FD6 RXFD3/FD3 RXFD2/FD2 COL4 TXD41 RXER4 RXD42 RXCLK4 TXER5 TXD52 RXER5 TXCLK5 RXD52 RXCLK5 TXER6 RXD63 RXCLK6 TXER7 TXD72 TXCLK7 RXD73 RXD70 TEST4 TEST5 (Y24) (W24) (V24) (U24) (T24) (R24) (P24) (N24) (M24) (L24) (K24) (J24) (H24) (G24) (F24) (E24) (D24) (C24) (C23) (C22) (C21) (C20) (C19) (C18) (C17) (C16) (C15) (C14) (C13) (C12) (C11) (C10) (C9) (C8) (C7) (C6) (C5) (C4) Name TXFBA5 TXFBA2 TXFDQ3 TXFDQ0 PASS HCLK CRS0 TXD03 TXD00 RXDV0 RXD01 COL1 TXD13 TXEN1 TXD10 RXDV1 RXD11 TXD21 RXDV2 RXD21 COL3 TXEN3 TXD31 RXER3 RXD32 RXD31 (D4) (E4) (F4) (G4) (H4) (J4) (K4) (L4) (M4) (N4) (P4) (R4) (T4) (U4) (V4) (W4) (Y4) (AA4) (AB4) (AC4) (AC5) (AC6) (AC7) (AC8) (AC9) (AC10) (AC11) (AC12) (AC13) (AC14) (AC15) (AC16) (AC17) (AC18) (AC19) (AC20) (AC21) (AC22) Name TXFD13/FD45 RXFD15/FD15 CLAMP CLAMP CLAMP RXD62 CLAMP CLAMP (AC23) (AB23) (AA23) (Y23) (W23) (V23) (U23) (T23) (R23) (P23) (N23) (M23) (L23) (K23) (J23) (H23) (G23) (F23) (E23) (D23) (D22) (D21) (D20) (D19) (D18) (D17) (D16) (D15) (D14) (D13) (D12) (D11) (D10) (D9) (D8) (D7) (D6) (D5) Name INT# CLAMP CLAMP CLAMP TXD20 CLAMP CLAMP
Remark Active pins/signals indicated (symbol after pin/signal names) this document.
Data Sheet S14150EJ4V0DS
µPD98431
FUNCTIONS
Register interface
Name Input Function Chip select. When this signal low, internal registers chip accessed. Host read/write. This used host system access register bus. When high level input this pin, register accessed read. When level input, register accessed write. Register address. address necessary selecting port register accessed when internal register µPD98431 accessed given A[10:0]. µPD98431 32-bit register each port. A[10:8] specifies port, [A7:0] specifies register address. relationship between setting A[10:8] port number follows: Port A[10:8] 000B Port A[10:8] 001B Port A[10:8] 010B Port A[10:8] 011B Port A[10:8] 100B Port A[10:8] 101B Port A[10:8] 110B Port A[10:8] 111B D[31:0] 235, 148, 147, 236, 149, 237, 150, 238, 151, 239, 152, 320, 240, 153, 241, 154, 242, 155, 243, I/O, 3-state Register data. These pins form bidirectional data through which internal registers µPD98431 accessed.
Input
A[10:0]
251, 166, 252, 167, 253, 168, 254,
Input
INT#
Output, open drain
Interrupt signal. Interrupt request signal. This signal goes interrupt source generated. kept until interrupt statuses cleared interrupt occurs. This signal open-drain output signal. Hardware reset. Active-low asynchronous reset signal. Immediately after hardware reset, registers their default values, FIFOs counters cleared. Register data acknowledge. This signal indicates that data D[31:0] valid when register read. When this signal low, data read from register exists D[31:0]. When register written, this signal indicates completion writing. Register interface clock. This inputs synchronization clock used access register. maximum frequency input clock MHz. Caution HCLK that frequency always exceeds frequency RXCLK TXCLK.
RESET#
Input
ACK#
Output, 3-state
HCLK
Input
Data Sheet S14150EJ4V0DS
µPD98431
FIFO interface (1/3)
Name RXFEN#/ FEN# Input Function FIFO reception enable/FIFO enable. function this signal differs follows depending FIFO mode: 32-bit dual mode this mode, this signal functions RXFEN#. this signal goes low, receive FIFO interface enabled, data read from receive FIFO. 64-bit single mode this mode, this signal functions FEN#. this signal goes low, FIFO interface enabled, data read from receive FIFO written transmit FIFO. TXFEN#/ Input FIFO transmission enable/FIFO direction. function this signal differs follows depending FIFO mode: 32-bit dual mode this mode, this signal functions TXFEN#. this signal goes low, transmit FIFO interface enabled, data written transmit FIFO. 64-bit single mode this mode, this signal functions FRW, specifies direction FIFO access. While this signal high, FIFO accessed receive FIFO read. While low, accessed transmit FIFO write. FCLK Input FIFO clock. FIFO synchronized with FCLK. maximum frequency input clock MHz. Caution FCLK that frequency always exceeds frequency RXCLK TXCLK. RXFPT[2:0] Output, 3-state Receive port number. These signals indicate port number from which receive data output when receive FIFO accessed read. relation between RXFPT[2:0] port number follows: Port RXFPT[2:0] 000B Port RXFPT[2:0] 001B Port RXFPT[2:0] 010B Port RXFPT[2:0] 011B Port RXFPT[2:0] 100B Port RXFPT[2:0] 101B Port RXFPT[2:0] 110B Port RXFPT[2:0] 111B
Data Sheet S14150EJ4V0DS
µPD98431
(2/3)
Name TXFPT[2:0] 160, Input Function Transmit port number. These signals indicate port number transmit FIFO which transmit data written when transmit FIFO accessed write. relation between TXFPT[2:0] port number follows: Port TXFPT[2:0] 000B Port TXFPT[2:0] 001B Port TXFPT[2:0] 010B Port TXFPT[2:0] 011B Port TXFPT[2:0] 100B Port TXFPT[2:0] 101B Port TXFPT[2:0] 110B Port TXFPT[2:0] 111B TXFD[31:0], RXFD[31:0]/ FD[63:0] 193, 102, 101, 194, 103, 195, 104, 196, 105, 197, 106, 282, 198, 107, 199, 108, 200, 109, 201, 202, 110, 114, 115, 205, 116, 206, 117, 207, 118, 208, 291, 119, 209, 120, 210, 121, 211, 122, 212, 213, 123, 247, 162, Input, Output, I/O, 3-state 32-bit transmit FIFO data bus, 32-bit receive FIFO data bus/64-bit FIFO data bus. These signals provide data FIFO interface. functions these signals differ follows depending FIFO mode. 32-bit dual mode These signals function TXFD[31:0] RXFD[31:0]. This 64-bit data divided into unidirectional buses, TXFD[31:0] RXFD[31:0], when BUSWTH MISCR register cleared 64-bit single mode These signals function FD[63:0]. This 64-bit data used 64-bit bidirectional access FIFO when BUSWTH MISCR register
TXFDQ[3:0]
Input
Transmit data attribute. These signals indicate attribute transmit data FIFO 32-bit dual mode. They indicate attribute transmit data FD[63:0] when transmit FIFO accessed write. These signals meaningless 64-bit single mode. Receive data attribute/FIFO attribute. These signals indicate attribute data FIFO bus. functions these signals differ follows depending mode: 32-bit dual mode These signals function RXFDQ[3:0] output attribute receive data output onto RXFD[31:0] when FIFO accessed receive FIFO read. 64-bit single mode These signals function FDQ[3:0] input attribute transmit data FD[63:0] when transmit FIFO accessed write. When receive FIFO accessed read, attribute receive data output onto FD[63:0] output.
RXFDQ[3:0]/ FDQ[3:0]
204, 111,
Output, I/O, 3-state
Data Sheet S14150EJ4V0DS
µPD98431
(3/3)
Name TXFBA[7:0] 156, 245, 157, 246, 159, Output, 3-state Function Transmit FIFO buffer available. When these signals high, transmit FIFO space which transmit data written. quantity data transmit FIFO exceeds value TFDMH field TFIC register, these signals low. TXFBA signal provided each port, TXFBA[n] TXFBA signal port Receive frame available. When this signal high, port indicated RXFPT least packet from receive data stream that ready transferred host system. Receive frame pass. This signal input start transfer receive data currently FIFO when accessed receive FIFO read. Receive frame skip. This signal input skip port currently FIFO read data from next port when FIFO accessed receive FIFO read.
RXFA
Output, 3-state
PASS
Input
SKIP
Input
Data Sheet S14150EJ4V0DS
µPD98431
(Media Independent Interface) (1/3)
Name TXCLK[7:0] 230, 137, 222, 190, 179, Input Function transmit clock. These pins input transmit clock (duty: 50%) necessary outputting data device connected each port. Transmit data from each port, TXD7[3:0] through TXD0[3:0], TXEN[7:0] that indicates that transmit data valid output each port synchronization with this clock. mode, clock input Mbps operation, clock input Mbps operation. this mode, TXEN output synchronization with rising TXCLK. Mbps serial mode, clock input. this mode, TXEN output synchronization with rising TXCLK. unused ports, TXCLK high level. transmit data (port These pins output transmit data device connected port mode, transmit data nibble width bits wide) output rising edge TXCLK0. Mbps serial mode, only TXD0[0] used output serial transmit data rising edge TXCLK0. transmit data (port These pins output transmit data device connected port mode, transmit data nibble width bits wide) output rising edge TXCLK1. Mbps serial mode, only TXD1[0] used output serial transmit data rising edge TXCLK1. transmit data (port These pins output transmit data device connected port mode, transmit data nibble width bits wide) output rising edge TXCLK2. Mbps serial mode, only TXD2[0] used output serial transmit data rising edge TXCLK2. transmit data (port These pins output transmit data device connected port mode, transmit data nibble width bits wide) output rising edge TXCLK3. Mbps serial mode, only TXD3[0] used output serial transmit data rising edge TXCLK3. transmit data (port These pins output transmit data device connected port mode, transmit data nibble width bits wide) output rising edge TXCLK4. Mbps serial mode, only TXD4[0] used output serial transmit data rising edge TXCLK4. transmit data (port These pins output transmit data device connected port mode, transmit data nibble width bits wide) output rising edge TXCLK5. Mbps serial mode, only TXD5[0] used output serial transmit data rising edge TXCLK5.
TXD0[3:0]
258, 173,
Output
TXD1[3:0]
263, 178,
Output
TXD2[3:0]
184, 268,
Output
TXD3[3:0]
189, 273,
Output
TXD4[3:0]
124, 215,
Output
TXD5[3:0]
220, 131,
Output
Data Sheet S14150EJ4V0DS
µPD98431
(2/3)
Name TXD6[3:0] 135, Output Function transmit data (port These pins output transmit data device connected port mode, transmit data nibble width bits wide) output rising edge TXCLK6. Mbps serial mode, only TXD6[0] used output serial transmit data rising edge TXCLK6. transmit data (port These pins output transmit data device connected port mode, transmit data nibble width bits wide) output rising edge TXCLK7. Mbps serial mode, only TXD7[0] used output serial transmit data rising edge TXCLK7. transmission enable. These signals indicate whether transmit data (TXD) each port valid. Mbps serial mode, they remain high starting from fist preamble, until last transmit frame output. mode, they remain high starting from first nibble data indicating preamble, until last nibble data transmit frame output. receive clock. These pins input clock (duty: 50%) received from device. RXD7[3:0] through RXD0[3:0] that data received from each port, TXEN[7:0] that indicates existence transmit data output synchronization with this clock. mode, clock input Mbps operation, clock input Mbps operation. this mode, RXDV input rising edge RXCLK. Mbps serial mode, clock input. this mode, input rising edge RXCLK. RXCLK unused port high level. receive data (port These pins input data received from device connected port mode, receive data nibble width bits wide) input rising edge RXCLK0. Mbps serial mode, only RXD0[0] used serial receive data input rising edge RXCLK0. receive data (port These pins input data received from device connected port mode, receive data nibble width bits wide) input rising edge RXCLK1. Mbps serial mode, only RXD1[0] used serial receive data input rising edge RXCLK1. receive data (port These pins input data received from device connected port mode, receive data nibble width bits wide) input rising edge RXCLK2. Mbps serial mode, only RXD2[0] used serial receive data input rising edge RXCLK2. receive data (port These pins input data received from device connected port mode, receive data nibble width bits wide) input rising edge RXCLK3. Mbps serial mode, only RXD3[0] used serial receive data input rising edge RXCLK3.
TXD7[3:0]
141, 229,
Output
TXEN[7:0]
136, 130, 125, 272, 183, 264,
Output
RXCLK[7:0]
145, 227, 224, 218, 187, 181,
Input
RXD0[3:0]
175, 261,
Input
RXD1[3:0]
180, 267,
Input
RXD2[3:0]
186, 270,
Input
RXD3[3:0]
275, 276,
Input
Data Sheet S14150EJ4V0DS
µPD98431
(3/3)
Name RXD4[3:0] 217, 128, Input Function receive data (port These pins input data received from device connected port mode, receive data nibble width bits wide) input rising edge RXCLK4. Mbps serial mode, only RXD4[0] used serial receive data input rising edge RXCLK4. receive data (port These pins input data received from device connected port mode, receive data nibble width bits wide) input rising edge RXCLK5. Mbps serial mode, only RXD5[0] used serial receive data input rising edge RXCLK5. receive data (port These pins input data received from device connected port mode, receive data nibble width bits wide) input rising edge RXCLK6. Mbps serial mode, only RXD6[0] used serial receive data input rising edge RXCLK6. receive data (port These pins input data received from device connected port mode, receive data nibble width bits wide) input rising edge RXCLK7. Mbps serial mode, only RXD7[0] used serial receive data input rising edge RXCLK7. Carrier sense. These carrier sense signals input from device connected each port. unused port level. receive data valid. These signals indicate, mode, that data valid each port. When these signals high, data valid. RXDV unused port high level. Collision. These pins input collision signals detected device connected each port. unused port level. transmission error. These signals indicate that error occurs each port µPD98431 during transmission. RXER[7:0] 221, 216, 274, 185, Input reception error. These input signals detect errors occurring each port device during reception. RXER unused port level. management clock. This transfer clock serial management data. management data. This bidirectional serial management data signal.
RXD5[3:0]
223, 133,
Input
RXD6[3:0]
226, 306,
Input
RXD7[3:0]
231, 144,
Input
CRS[7:0]
140, 177,
Input
RXDV[7:0]
143, 138, 132, 127, 191, 269, 266,
Input
COL[7:0]
134, 129, 214, 271, 262,
Input
TXER[7:0]
228, 225, 219, 188,
Output
Output
MDIO
Data Sheet S14150EJ4V0DS
µPD98431
JTAG pins (These functions supported upon request.)
Name Input Function JTAG test mode select. This signal controls boundary scan state machine. This internally pulled (pull-up resistor: JTAG test data input. This signal serial data input boundary scan. This internally pulled (pull-up resistor: JTAG test data output. This signal serial data output boundary scan. JTAG test clock. This clock input used synchronize test data input output. This internally pulled (pull-up resistor: JTAG reset. When this signal deasserted low, boundary scan operation reset. This signal must kept high during boundary scan operation. When using JTAG function, pins low. This internally pulled (pull-up resistor:
Input
Output 3-state Input
TRST#
Input
Test pins power pins
Name TEST 234, 233, 170, 146, 100, 279, 283, 285, 288, 290, 294, 297, 300, 303, 307, 308, 311, 314, 317, 321, 323, 326, 328, 332, 335, 338, 341, 345, 346, 349, 277, 278, 280, 281, 284, 286, 287, 289, 292, 293, 295, 296, 299, 302, 305, 309, 312, 315, 316, 318, 319, 322, 324, 325, 327, 330, 331, 333, 334, 337, 340, 343, 347, 298, 301, 304, 310, 313, 336, 339, 342, 348, Input Function Test pins. These pins used test device. Always these pins low. Power supply (+3.3
Ground
CLAMP
Clamp power supply. This supplies clamp voltage buffer circuit. Supply this when external device used. Supply +3.3 when external device used.
Data Sheet S14150EJ4V0DS
µPD98431
µPD98431 output signal connection When connecting device output signals (TXD, TTEN, TXER, MDC, MDIO), connect serial resistor each output signal follows that drivability output buffer accords with IEEE802.3u standard.
PD98431
External device
TXD/TXEN/TXER/MDC/MDIO
TXD/TXEN/TXER/MDC/MDIO
Data Sheet S14150EJ4V0DS
µPD98431
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Clamp supply voltage Input/output voltage Symbol VCLAMP Except signal signal Maximum power consumption Operating temperature Storage temperature PMAX Tstg Conditions Ratings -0.5 +4.6 -0.5 +6.6 -0.5 +4.6 -0.5 +7.3 2.60 +150 Unit
Caution Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. Recommended Operating Conditions
Parameter Supply voltage Clamp supply voltage Operating temperature Symbol VCLAMP Conditions MIN. 3.135 3.135 TYP. VDD/5.0 MAX. 3.465 Unit
Data Sheet S14150EJ4V0DS
µPD98431
Characteristics +70°C, +3.3 ±5%)
Parameter Input leakage current Output leakage current Operating current Clock input voltage, Clock input voltage, high Input voltage, Input voltage, high Symbol Except interface interface Output voltage, FD[63:0], FDQ[3:0], TXFBA[7:0], RXFPT[2:0], RXFA TXDn [0:3], TXEN[7:0], TXER[7:0] signals other than above Output voltage, high FD[63:0], FDQ[3:0], TXFBA[7:0], RXFPT[2:0], RXFA TXDn [0:3], TXEN[7:0], TXER[7:0] signals other than above HCLK, FCLK HCLK, FCLK +0.8 Conditions MIN. TYP. MAX. Unit
Capacitance 25°C, MHz)
Parameter Input capacitance capacitance Symbol Conditions MIN. TYP. MAX. Unit
Characteristics +70°C, +3.3 ±5%) characteristics values based following conditions. test conditions Load condition: Schottky gate Input pulse level: Test reference level:
Data Sheet S14150EJ4V0DS
µPD98431
Register Interface Timing
Parameter HCLK clock width
Note
Symbol tCYHK tHKL tHKH tRSL tSHKA tHHKA tSHKRW tHHKRW tSHKCS tHHKCS tDHKAC tFHKAC tDHKD tSHKD tHHKD tFHKD
Conditions
MIN. tCYHK
TYP.
MAX.
Unit
HCLK low-level width HCLK high-level width RESET# pulse width A[10:0] setup time A[10:0] hold time setup time hold time setup time hold time ACK# output delay time ACK# float time D[31:0] output delay time D[31:0] setup time D[31:0] hold time D[31:0] float time
tCYHK
Note HCLK clock width must always shorter than both RXCLK clock width TXCLK clock width.
Data Sheet S14150EJ4V0DS
µPD98431
HCLK timing
tHKL HCLK tCYHK tHKH
HCLK
RESET#
tRSL
Register interface write timing
HCLK tSHKA A[10:0] tSHKRW tSHKCS tDHKAC ACK# tDHKAC tDHKAC tFHKAC tHHKCS tHHKRW tHHKA
Hi-Z
tSHKD
tHHKD
Hi-Z
D[31:0]
Hi-Z
Hi-Z
Register interface read timing
HCLK tSHKA A[10:0] tSHKRW tSHKCS tDHKAC ACK# tDHKAC tDHKAC tFHKAC tHHKCS tHHKRW tHHKA
Hi-Z tDHKD
tDHKD
XXXXXXXX Valid data
tDHKD
tFHKD
Hi-Z
D[31:0]
Hi-Z
XXXXXXXX
Hi-Z
Data Sheet S14150EJ4V0DS
µPD98431
Ethernet Transmit Interface Timing
Parameter TXDn[3:0] delay time Transmit signal assert delay time Transmit signal deassert delay time TXCLK clock width Symbol tDTKTD tDTKTE tFTKTE tCYTK mode Mbps serial mode TXCLK high-level width tTKH mode Mbps serial mode TXCLK low-level width tTKL mode Mbps serial mode 40/400 20/200 20/200 Conditions MIN. TYP. MAX. Unit
Mbps serial mode
tCYTK TXCLK tDTKTD TXDn tDTKTE TXEN tFTKTE
TXEN TXDn [3:0]
mode
tCYTK TXCLK tDTKTD tTKH tTKL
tTKH
tTKL
tDTKTE
tFTKTE
tDTKTE TXER
tFTKTE
Data Sheet S14150EJ4V0DS
µPD98431
Ethernet Receive Interface Timing
Parameter RXDn[3:0] setup time RXDn[3:0] hold time Receive signal setup time Receive signal hold time RXCLK clock width Symbol tSRDRK tHRKRD tSRSRK tHRKRS tCYRK mode Mbps serial mode RXCLK high-level width tRKH mode Mbps serial mode RXCLK low-level width tRKL mode Mbps serial mode Conditions MIN. 40/400 20/200 20/200 TYP. MAX. Unit
Mbps serial mode
tCYRK RXCLK tSRDRK RXDn tHRKRD tRKH tRKL
mode
tCYRK RXCLK tSRDRK RXDn [3:0] tHRKRD RXDV tSRSRK RXER tSRSRK tHRKRS tHRKRS tRKH tRKL
Data Sheet S14150EJ4V0DS
µPD98431
Management Interface Timing
Parameter cycle MDIO delay time MDIO setup time MDIO hold time Symbol tCYM tDMCMD tSMDMC tHMCMD Conditions MIN. tCYHK-5 tCYHK+20 TYP. MAX. 1080 tCYHK+10 Unit
tCYM
Output
tDMCMD MDIO (output) MDIO (input)
Input
tSMDMC tHMCMD
FIFO Interface Write Timing
Parameter FCLK clock width
Note
Symbol tCYFK tFKH tFKL tSFKTE tHFKTE tDFKBA tFFKBA tSFKDQ tHFKDQ tSFKTP tHFKTP tSFKFD tHFKFD tSFKRE tHFKRE
Conditions
MIN.
TYP.
MAX.
Unit
FCLK high-level width FCLK low-level width TXFEN#/FRW setup time TXFEN#/FRW hold time TXFBA[N] output delay time TXFBA[N] float time TXFDQ[3:0]/FDQ[3:0] setup time TXFDQ[3:0]/FDQ[3:0] hold time TXFPT[2:0] setup time TXFPT[2:0] hold time TXFD[31:0]/FD[63:0] setup time TXFD[31:0]/FD[63:0] hold time RXFEN#/FEN# setup time RXFEN#/FEN# hold time
Note FCLK clock width must always shorter than both RXCLK clock width TXCLK clock width. Remark TXFBA[N]:
Data Sheet S14150EJ4V0DS
µPD98431
FIFO interface write timing (32-bit dual mode)
tCYFK FCLK tSFKTE
TXFEN#
tFKH
tFKL
tHFKTE
tDFKBA
TXFBA[N]
tFFKBA
Hi-Z
tHFKDQ
Hi-Z
TXFDQ[3]
tSFKDQ
TXFDQ[2]
tSFKDQ tHFKDQ
TXFDQ[1]
tHFKDQ tSFKDQ
TXFDQ[0]
tSFKTP
TXFPT[2:0]
tHFKTP Port enable
tSFKFD
TXFD[31:0]
word bits
tHFKFD
word bits word bits word bits word bits word bits word bits
Idle
Start
Middle
3-byte ending
Idle
Remark TXFBA[N]:
Data Sheet S14150EJ4V0DS
µPD98431
FIFO interface write timing (64-bit single mode)
FCLK tSFKRE
FEN#
tHFKRE
tSFKTE
tHFKTE
tDFKBA
TXFBA[N]
tFFKBA
Hi-Z tSFKDQ tHFKDQ
Hi-Z
FDQ[3]
tSFKDQ
FDQ[2]
tHFKDQ
tSFKDQ
FDQ[1]
tHFKDQ
tHFKDQ tSFKDQ
FDQ[0]
tSFKTP
TXFPT[2:0]
tHFKTP Port enable
tSFKFD
FD[63:0]
word bits
tHFKFD
word bits word bits word bits word bits word bits word bits
Idle
Start
Middle
7-byte ending
Idle
Remark TXFBA[N]:
Data Sheet S14150EJ4V0DS
µPD98431
FIFO Interface Read Timing
Parameter RXFA output delay time RXFA float time RXFDQ[3:0]/FDQ[3:0] output delay time RXFDQ[3:0]/FDQ[3:0] float time RXFPT[2:0] output delay time RXFPT[2:0] float time RXFD[31:0]/FD[63:0] output delay time RXFD[31:0]/FD[63:0] float time PASS setup time PASS hold time SKIP setup time SKIP hold time Symbol tDFKFA tFFKFA tDFKDQ tFFKDQ tDFKRP tFFKRP tDFKFD tFFKFD tSFKPS tHFKPS tSFKSP tHFKSP Conditions MIN. TYP. MAX. Unit
FIFO interface read timing (32-bit dual mode)
FCLK tSFKRE
RXFEN#
tHFKRE
tDFKFA
RXFA
tDFKFA
tFFKFA
Hi-Z
tDFKDQ
tDFKDQ
Hi-Z tFFKDQ
RXFDQ[3]
Hi-Z
Hi-Z tDFKDQ tFFKDQ Hi-Z tFFKDQ
RXFDQ[2]
Hi-Z
tDFKDQ
tDFKDQ
RXFDQ[1]
Hi-Z
tDFKDQ
tDFKDQ
Hi-Z tFFKDQ
RXFDQ[0]
Hi-Z
tDFKRP Port number tDFKFD
Dword bits Dword bits Dword bits Dword bits Dword bits Dword bits
Hi-Z tFFKRP Hi-Z tFFKFD Hi-Z
RXFPT[2:0]
Hi-Z
RXFD[31:0]
Hi-Z
tHFKPS
PASS
tSFKPS
SKIP
Idle Start Middle 3-byte ending Idle
Data Sheet S14150EJ4V0DS
µPD98431
FIFO interface read timing (32-bit dual mode)
FCLK
RXFEN#
RXFA
Hi-Z
RXFDQ[3]
Hi-Z
RXFDQ[2]
Hi-Z
RXFDQ[1]
Hi-Z
RXFDQ[0]
Hi-Z
RXFPT[2:0]
Hi-Z
Port number
Port number
RXFD[31:0]
Hi-Z
Dword
Dword
Dword
Dword
PASS
tHFKPS
SKIP
tSFKPS Skip frame Idle Start Middle
Data Sheet S14150EJ4V0DS
µPD98431
FIFO interface read timing (32-bit dual mode)
FCLK tSFKRE
RXFEN#
tDFKFA
RXFA
tDFKFA
Hi-Z
tDFKDQ
RXFDQ[3]
Hi-Z
tDFKDQ
tDFKDQ
RXFDQ[2]
Hi-Z
tDFKDQ
tDFKDQ
RXFDQ[1]
Hi-Z
tDFKDQ
tDFKDQ
RXFDQ[0]
Hi-Z
tDFKRP Port number tDFKFD
Length Status Dword Dword Dword Dword
RXFPT[2:0]
Hi-Z
RXFD[31:0]
Hi-Z
tHFKPS
PASS
tSFKPS
SKIP
Idle Length Start Status Middle
Data Sheet S14150EJ4V0DS
µPD98431
FIFO interface read timing (32-bit dual mode)
FCLK tHFKRE
RXFEN#
tFFKFA
RXFA
Hi-Z tDFKDQ tFFKDQ Hi-Z tFFKDQ
RXFDQ[3]
tDFKDQ
RXFDQ[2]
tDFKDQ
RXFDQ[1]
Hi-Z tFFKDQ
tDFKDQ
RXFDQ[0]
Hi-Z tFFKDQ
Hi-Z tFFKRP Port number Hi-Z tFFKFD
Dword Length Status Dword
RXFPT[2:0]
RXFD[31:0]
Dword
Dword
Dword
Hi-Z
PASS
SKIP
Middle 3-byte Length ending Status Idle
Data Sheet S14150EJ4V0DS
µPD98431
FIFO interface read timing (64-bit single mode)
FCLK tSFKRE
FEN#
tHFKRE
tSFKTE
tHFKTE
tDFKFA
RXFA
tDFKFA
tFFKFA
Hi-Z
tDFKDQ
tDFKDQ
Hi-Z tFFKDQ
FDQ[3]
Hi-Z
tDFKDQ
tDFKDQ
Hi-Z tFFKDQ
FDQ[2]
Hi-Z
tDFKDQ
tDFKDQ
Hi-Z tFFKDQ
FDQ[1]
Hi-Z
tDFKDQ
tDFKDQ
Hi-Z tFFKDQ
FDQ[0]
Hi-Z
tDFKRP Port number tDFKFD
Dword bits bits bits bits bits bits
Hi-Z tFFKRP Hi-Z tFFKFD Hi-Z
RXFPT[2:0]
Hi-Z
FD[63:0]
Hi-Z
tHFKPS
PASS
tSFKPS
SKIP
Idle Start Middle 7-byte ending Idle
Data Sheet S14150EJ4V0DS
µPD98431
FIFO interface read timing (64-bit single mode)
FCLK
FEN#
RXFA
Hi-Z
FDQ[3]
Hi-Z
FDQ[2]
Hi-Z
FDQ[1]
Hi-Z
FDQ[0]
Hi-Z
RXFPT[2:0]
Hi-Z
Port number
Port number
FD[63:0]
Hi-Z
bits
bits
bits
bits
PASS
tHFKPS
SKIP
tSFKPS Skip frame Idle Start Middle
Data Sheet S14150EJ4V0DS
µPD98431
FIFO interface read timing (64-bit single mode)
FCLK tSFKRE
FEN#
tSFKTE
tDFKFA
RXFA
tDFKFA
Hi-Z
tDFKDQ
FDQ[3]
Hi-Z
tDFKDQ
tDFKDQ
FDQ[2]
Hi-Z
tDFKDQ
tDFKDQ
FDQ[1]
Hi-Z
tDFKDQ
tDFKDQ
FDQ[0]
Hi-Z
tDFKRP Port number tDFKFD
Length Status Dword bits bits bits bits
RXFPT[2:0]
Hi-Z
FD[63:0]
Hi-Z
tHFKPS
PASS
tSFKPS
SKIP
Idle Length Start Status Middle
Data Sheet S14150EJ4V0DS
µPD98431
FIFO interface read timing (64-bit single mode)
FCLK tHFKRE
FEN#
tHFKTE
tFFKFA
RXFA
Hi-Z tDFKDQ tFFKDQ Hi-Z tFFKDQ
FDQ[3]
tDFKDQ
FDQ[2]
tDFKDQ
FDQ[1]
Hi-Z tFFKDQ
tDFKDQ
FDQ[0]
Hi-Z tFFKDQ
Hi-Z tFFKRP Port number Hi-Z tFFKFD
bits Length Status bits
RXFPT[2:0]
FD[63:0]
bits
bits
bits
Hi-Z
PASS
SKIP
Middle 3-byte Length ending Status Idle
Data Sheet S14150EJ4V0DS
µPD98431
Boundary Scan (JTAG) Timing
Parameter clock width low-level width high-level width setup time hold time output delay time setup time hold time Symbol tCYJK tJKL tJKH tSJKI tHJKI tDJKO tSJKM tHJKM Conditions MIN. TYP. MAX. Unit
tCYJK tJKL tSJKI tDJKO tSJKM tHJKM tHJKI tJKH
Data Sheet S14150EJ4V0DS
µPD98431
PACKAGE DRAWING
352-PIN PLASTIC (35x35)
Index mark
ITEM
MILLIMETERS 35.00±0.20 32.0 32.0 35.00±0.20 1.62 1.27 (T.P.) 0.6±0.1 0.56 1.73±0.15 2.33±0.25 0.15
0.75±0.15
0.30 0.10 C4.0 Y352S1-127-F6-4
Data Sheet S14150EJ4V0DS
µPD98431
RECOMMENDED SOLDERING CONDITIONS
This product should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended, contact your sales representative. Surface mounting type
µPD98431S1-F6: 352-pin plastic
Recommended Condition Symbol IR30-203-3
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 230°C, Time: seconds max. 210°C higher), Count: Three times less, Exposure limit: daysNote (after that, prebake 125°C hours)
Note After opening pack, store 25°C less less allowable storage period.
Data Sheet S14150EJ4V0DS
µPD98431
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Ethernet trademark Xerox Corporation.
Data Sheet S14150EJ4V0DS
µPD98431
information this document current March, 2002. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

µPD98431 10/100 Mbps Ethernet CONTROLLER DESCRIPTION

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