µPD98421 HIGH-SPEED ADDRESS SEARCH ENGINE DESCRIPTION µ

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INTEGRATED CIRCUIT
µPD98421
HIGH-SPEED ADDRESS SEARCH ENGINE
DESCRIPTION
µPD98421 (Content Addressable Memory) with capacity bits 8192 entries. Equipped with three types search modes, this memory search data high speeds. these search modes, Longest Prefix Match mode, mask data entry units output address with longest match search data. This function effective searching addresses Layer
FEATURES
bits entries High-speed synchronous operation. Maximum operating frequency: (normal mode)/50 mode) Mask register masking 64-bit search data Three search modes supported high-speed searching.
Full Match mode:
MHz)
Full Match with Mask mode: Longest Prefix Match mode:
Number entries expanded connecting multiple µPD98421s. read/write data high-speed synchronous operation (memory operation). Supply voltage: 0.15 240-pin plastic FBGA
ORDERING INFORMATION
Part Number Package 240-pin plastic FBGA
µPD98421F1-GA1
Remark this document, active-low pins expressed xxx_B suffixed name).
information this document subject change without notice. Before using this document, please confirm that this latest version.
devices/types available every country. Please check with local representative availability additional information.
Document S13650EJ5V0DS00 (5th edition) Date Published January 2002 Printed Japan
mark
shows major revised points.
1998
µPD98421
BLOCK DIAGRAM
RESET_B CE_B WAIT_B
Sequencer block
block DATA63 DATA0 WE_B OE_B
Search engine block FULL FMSK ENHIT_B HAD0 HAD12 HIT_B ERR_B SMD63 SMD0
Search data register Search mask data register Mode register
Memory block
Entry data memory bits 4096 words)
Mask data memory bits 4096 words)
Data Sheet S13650EJ5V0DS
µPD98421
SYSTEM CONFIGURATION EXAMPLE
Router Synchronous SRAM SRAM_CE CE_B, DATA63 DATA0 OE_B, WE_B
PD98421 µPD98421_CE0
CE_B, DATA63 DATA0 OE_B, WE_B MEM, FULL, FMSK
ENHIT_B HIT_B HAD12 HAD0 ERR_B SMD63 SMD0
ENHIT_B0 HIT_B0
PD98421 µPD98421_CE1
CE_B, DATA63 DATA0 OE_B, WE_B MEM, FULL, FMSK
ENHIT_B HIT_B HAD12 HAD0 ERR_B SMD63 SMD0
ENHIT_B1 HIT_B1
DATA63 DATA0 OE_B, WE_B MEM, FULL, FMSK
Glue logic
PD98421 µPD98421_CEn
CE_B, DATA63 DATA0 OE_B, WE_B MEM, FULL, FMSK
ENHIT_B HIT_B HAD12 HAD0 ERR_B SMD63 SMD0
ENHIT_Bn HIT_Bn
address12 address14, ERR_B HADOUT ERROUT_B
HIT_B
HITOUT_B
Data Sheet S13650EJ5V0DS
µPD98421
CONFIGURATION
240-pin plastic FBGA
µPD98421F1-GA1
(Top view)
Index mark
µPD98421F1-GA1
(Bottom view)
Index mark
Data Sheet S13650EJ5V0DS
µPD98421
(A1) (B1) (C1) (D1) (E1) (F1) (G1) (H1) (J1) (K1) (L1) (M1) (N1) (P1) (R1) (T1) (U1) (V1) (V2) (V3) (V4) (V5) (V6) (V7) (V8) (V9) (V10) (V11) (V12) (V13) (V14) (V15) (V16) (V17) (V18) (U18) (T18) (R18) (P18) (N18) (M18) (L18) (K18) (J18) (H18) (G18) (F18) (E18) Name I.C. DATA63 DATA60 SMD59 DATA57 SMD55 SMD53 SMD50 DATA48 DATA46 DATA45 SMD44 DATA42 SMD40 SMD39 DATA37 SMD34 DATA33 WAIT_B N.C. N.C. HAD10 HAD8 HAD5 HAD1 ERR_B DATA30 SMD29 DATA27 DATA24 (D18) (C18) (B18) (A18) (A17) (A16) (A15) (A14) (A13) (A12) (A11) (A10) (A9) (A8) (A7) (A6) (A5) (A4) (A3) (A2) (B2) (C2) (D2) (E2) (F2) (G2) (H2) (J2) (K2) (L2) (M2) (N2) (P2) (R2) (T2) (U2) (U3) (U4) (U5) (U6) (U7) (U8) (U9) (U10) (U11) (U12) (U13) (U14) Name DATA23 SMD22 DATA21 SMD20 DATA18 DATA17 SMD15 SMD13 SMD10 SMD9 DATA7 SMD4 SMD3 DATA0 I.C. DATA62 SMD61 SMD58 DATA56 DATA54 DATA52 SMD51 DATA49 SMD46 DATA44 DATA43 SMD42 SMD41 DATA39 DATA36 SMD35 SMD33 FMSK (U15) (U16) (U17) (T17) (R17) (P17) (N17) (M17) (L17) (K17) (J17) (H17) (G17) (F17) (E17) (D17) (C17) (B17) (B16) (B15) (B14) (B13) (B12) (B11) (B10) (B9) (B8) (B7) (B6) (B5) (B4) (B3) (C3) (D3) (E3) (F3) (G3) (H3) (J3) (K3) (L3) (M3) (N3) (P3) (R3) (T3) (T4) (T5) Name HAD12 HAD6 HAD3 ENHIT_B SMD30 DATA28 DATA26 DATA25 DATA20 DATA19 SMD18 DATA16 DATA15 SMD12 SMD11 DATA8 SMD7 SMD5 SMD2 SMD0 SMD63 DATA61 DATA59 SMD56 SMD54 SMD52 DATA50 SMD49 DATA47 SMD45 DATA41 (T6) (T7) (T8) (T9) (T10) (T11) (T12) (T13) (T14) (T15) (T16) (R16) (P16) (N16) (M16) (L16) (K16) (J16) (H16) (G16) (F16) (E16) (D16) (C16) (C15) (C14) (C13) (C12) (C11) (C10) (C9) (C8) (C7) (C6) (C5) (C4) (D4) (E4) (F4) (G4) (H4) (J4) (K4) (L4) (M4) (N4) (P4) (R4) Name SMD36 DATA34 DATA32 WE_B HAD11 HAD9 HAD7 HAD2 RESET_B SMD28 SMD26 SMD25 SMD23 SMD21 SMD17 DATA13 DATA10 SMD8 DATA6 DATA4 DATA3 DATA1 SMD60 SMD62 SMD57 DATA55 SMD48 SMD47 SMD43 (R5) (R6) (R7) (R8) (R9) (R10) (R11) (R12) (R13) (R14) (R15) (P15) (N15) (M15) (L15) (K15) (J15) (H15) (G15) (F15) (E15) (D15) (D14) (D13) (D12) (D11) (D10) (D9) (D8) (D7) (D6) (D5) (H5) (J5) (K5) (L5) (P8) (P9) (P10) (P11) (L14) (K14) (J14) (H14) (E11) (E10) (E9) (E8) Name DATA38 DATA40 SMD38 DATA35 SMD32 OE_B CE_B HAD4 HIT_B SMD31 SMD24 DATA22 SMD19 DATA14 SMD16 SMD14 DATA11 DATA9 SMD6 DATA2 SMD1 DATA58 DATA53 DATA51 SMD37 FULL HAD0 DATA31 DATA29 SMD27 DATA12 DATA5
Remarks Figures parentheses indicate coordinates configuration. I.C.: Internal Connection Fixed level N.C.: Connection
Data Sheet S13650EJ5V0DS
µPD98421
NAMES
CE_B: CLK: ENHIT_B: ERR_B: FMSK: FULL: GND: HAD12 HAD0: HIT_B: MEM: OE_B: RESET_B: SMD63 SMD0: VDD: WAIT_B: WE_B: Address Chip Select Clock Enable Error Full Match Mask Mode Full Match Mode Ground Address Memory Output Enable Reset Search Mask Data Supply Voltage Wait Write Enable
DATA63 DATA0: Data
Data Sheet S13650EJ5V0DS
µPD98421
CONTENTS
FUNCTIONS MEMORY/REGISTER CONFIGURATION. Memory Configuration.
2.1.1 2.1.2 Full Match mode.11 Full Match with Mask/Longest Prefix Match mode Search data register Mask data register.12 Mode register register.13
Register Configuration
2.2.1 2.2.2 2.2.3 2.2.4
FUNCTIONAL DESCRIPTION. Memory Operation Search Operation
3.2.1 3.2.2 3.2.3 3.2.4 Full Match mode.14 Full Match with Mask mode.15 Longest Prefix Match mode.17 Other points noted.19
ELECTRICAL SPECIFICATIONS RECOMMENDED SOLDERING CONDITIONS. PACKAGE DRAWING
Data Sheet S13650EJ5V0DS
µPD98421
FUNCTIONS
Name Input Description Clock. System clock input pin. Inputs clock (normal mode)/50 mode). Wait. Wait input pin. Asserted active level. WAIT_B signal active rising edge CLK, µPD98421 placed wait status duration cycle from next rising CLK. wait status, pins retain status immediately before wait status set. However, output control CE_B, ENHIT_B valid. Chip select. Asserted active level. When signal CE_B signal chip asserted active same time, chip selected. DATA, HAD, ERR_B, unselected chip enter high-impedance state. Chip select. Asserted active level. When signal CE_B signal chip asserted active same time, chip selected. DATA, HAD, ERR_B, unselected chip enter high-impedance state. Address. 13-bit address signals. Signals input through ignored access mode.
WAIT_B
Input
CE_B
Input
Input
201, 153, 202, 154, 155, 100, 132, 133, 225, 186, 227, 228, 138, 140, 144, 194, 193, 196, 148, 149, 234, 235, 108, 109, 110, 213, 113, 115, 117, 118, 215, 172, 237, 218, 174, 219, 122, 176, 240, 177, 178, 223, 179,
Input
DATA63 DATA0
Data. DATA63 DATA0 data signals that input/output 64-bit data to/from internal memory registers.
WE_B
Input
Write enable. Enables writing DATA63 DATA0. When WE_B signal active, DATA63 DATA0 enter high-impedance state. Output enable. Enables output data from DATA63 DATA0.
OE_B
Input
Data Sheet S13650EJ5V0DS
µPD98421
Name Input Description Memory. Specifies access right memory/register. When signal high, µPD98421 performs same operations SRAM (refer FUNCTIONAL DESCRIPTION). When this signal low, internal registers accessed input/output. Access function Memory access access FULL Input Full Match Mode. Sets search mode with FMSK signals (refer FUNCTIONAL DESCRIPTION). Full Match with Mask mode. Sets search mode with FULL signals (refer FUNCTIONAL DESCRIPTION). address. HAD12 through HAD0 output matched valid address HIT_B signal goes ERR_B goes high during search operation. ERR_B asserted active (low level), output invalid. HAD12 meaningless except Full Match mode. These pins internally pulled Hit. Data searched after written search data register during search operation. HIT_B low-active signal that indicates that data matching search data been found. Match data found, Match data found Error. This signal goes more sets entry data having same mask data found during search operation. Because this open-drain signal, pull This signal inactive (high-impedance) during memory operation. Enable hit. This signal controls output HAD12 HAD0 ERR_B signals. ENHIT_B HAD[12:0] ERR_B SMD63 SMD0 131, 183, 182, (Internal 185, 135, 136, 137, pull-up) 139, 190, 191, 142, 192, 195, 229, 147, 198, 208, 107, 163, 236, 164, 165, 212, 166, 168, 214, 116, 170, 216, 217, 120, 121, 175, 123, 221, 124, 126, 224, Hi-Z Output enabled Hi-Z
FMSK
Input
HAD12 HAD0
101, 156, 157, 158, 103, 206, 104, 159,
Output state (Internal pull-up)
HIT_B
Output
ERR_B
Output (Open drain)
ENHIT_B
Input
Search mask data. SMD63 SMD0 signals used temporary with other µPD98421s Longest Prefix Match mode. Connect each these pins corresponding other µPD98421s.
Data Sheet S13650EJ5V0DS
µPD98421
Name RESET_B Input Description Reset. When this signal low, chip initialized. Only internal sequencer mode register initialized; memory area cleared. sure create external circuit which RESET_B becomes level after power application. addition, input least more commands continuously after releasing reset. power supply
125, 143, 160, 167, 171, 184, 188, 205, 209, 211, 230, 102, 105, 111, 112, 114, 119, 130, 134, 141, 145, 146, 152, 162, 169, 173, 180, 187, 189, 197, 204, 210, 220, 222, 226, 231,
Ground
N.C.
connection. Leave open. Internally connected. Leave open. Always these pins level.
I.C.
128, 129,
Data Sheet S13650EJ5V0DS
µPD98421
MEMORY/REGISTER CONFIGURATION
Memory Configuration µPD98421 memory area bits 8192 entries. types memory configurations selected accordance with search mode. this selection, special setting chip necessary.
µPD98421 also used synchronous SRAM.
2.1.1 Full Match mode bits 8192 entries: Entry data Full Match mode, 8192 entries used data area. Table 2-1. Memory Mapping Full Match Mode
Address 0000h 0001h 0FFFh 1000h 1FFEh 1FFFh Contents Entry data Entry data Entry data Entry data Entry data Entry data
2.1.2 Full Match with Mask/Longest Prefix Match mode bits 4096 entries: Entry data bits 4096 entries: Entry mask data Full Match with Mask Longest Prefix Match modes, 4096 entries addresses 0000h 0FFFh used data area, addresses 1000h 1FFFh used mask data area. mask data 1000h 1FFFh mask each corresponding entry data shown Table 2-2. mask data corresponding entry data ignored during search. mask data must successively masked, starting from LSB, Longest Prefix Match mode. Example FFFF0000 Correct, FF00F000 Incorrect
Data Sheet S13650EJ5V0DS
µPD98421
Table 2-2. Memory Mapping Full Match with Mask/Longest Prefix Match Modes
Address 0000h 0001h 0FFFh 1000h 1FFEh 1FFFh Contents Entry data Entry data Entry data Mask data 0000h Mask data 0FFEh Mask data 0FFFh
Register Configuration µPD98421 allocates internal registers words addresses. Each register bits long. Address signal lines through used specify address access register. through used. When register accessed, signal line made low. write data register, WE_B asserted active; read data from register, OE_B asserted active. Data written register clock cycle both normal modes (except search operation writing data search data register). When register read normal mode, read data output clock cycle after address been input. mode, read data output clock cycles after address input. details normal modes, refer 2.2.3 Mode register. Table 2-3. Internal Registers
Address Register Search data register Mask data register Mode register Reserved access this register.) register Reserved access this register.)
2.2.1 Search data register search data stored this register. When 64-bit search data written search data register,
µPD98421 starts search operation.
search data register initialized even when chip reset. 2.2.2 Mask data register mask data register stores value mask search data stored search data register. Store valid value this register before value written search data register. mask data register corresponding search data register masked ignored. masking specified this register valid entries search modes. mask data register initialized even when chip reset. When width entries less than bits, recommended mask unused bits using this function reduce current consumption chip). However, mask
Data Sheet S13650EJ5V0DS
µPD98421
2.2.3 Mode register mode register selects search timing mode (normal/FF mode) µPD98421 controls operations µPD98421 without using FULL, FMSK, WAIT_B signal lines. This register initialized after chip been reset.
reserved full fmsk wait_b2 wait_b1 enbl
enbl
Validates invalidates full, fmsk, wait_b2, wait_b1 bits mode register. Invalidates full, fmsk, wait_b2, wait_b1 bits, validates FULL, FMSK, WAIT_B signal lines. Validates full, fmsk, wait_b2, wait_b1 bits, invalidates FULL, FMSK, WAIT_B signal lines.
wait_b1
Specifies whether wait cycle inserted after first clock. Inserts wait cycle after search operation. Longest Prefix Match mode, wait cycle inserted between first search clock second search clock. operation
wait_b2
Specifies whether wait cycle inserted after second clock. Inserts wait cycle after second search clock Longest Prefix Match mode. operation
full, fmsk
Selects search mode ([full, fmsk] [xx]). Longest Prefix Match mode Reserved Full Match mode Full Match with Mask mode
Selects search timing mode (normal mode). Normal mode. address output clock after data been input Full Match Full Match with Mask mode MHz. Longest Prefix Match mode, address output clocks after data been input. mode address output clocks after data been input Full Match Full Match with Mask mode MHz. Longest Prefix Match mode, address output four clocks after data been input.
reserved
Reserved access these bits.
Remark execute another operation immediately after write access mode register mask data register. sure perform (write register) duration least clock before executing another operation. 2.2.4 register When data written register, µPD98421 no-operation status, which performs nothing. Keep µPD98421 this status when operations such search memory access being performed. undefined value read from register read.
Data Sheet S13650EJ5V0DS
µPD98421
FUNCTIONAL DESCRIPTION
µPD98421 select operation mode memory operation search operation using combinations MEM, FULL, FMSK signals, combinations full fmsk bits. Table 3-1. Operation Modes
FULL
FMSK
Function Memory operation Full Match mode Full Match with Mask mode Longest Prefix Match mode None (setting prohibited)
Memory Operation µPD98421 read write 64-bit data from internal memory cell during operation, like synchronous SRAM. During memory operation, high. When data written, WE_B signal asserted active; when data read, OE_B signal asserted active. Data written within clock both normal modes. When data read, read data output clock after address input normal mode. mode, read data output clocks after address input. Note, however, that outputting read data delayed inserting WAIT cycle. Search Operation search operation started when search mode search data written search data register. search mode setting MEM, FULL, FMSK signal lines search mode (refer Table 3-1) using mode register (refer 2.2.3 Mode register). 3.2.1 Full Match mode Full Match mode, data that completely matches searched. this mode, entry data entries mask register used. search data Full Match mode, signal lines shown Table mode register), write search data search data register. value search data register masked value mask data register compared with 64bit value words memory cells. search data register corresponding mask data register that used comparison. clock after search data been written search data register normal mode mode, clocks after), HIT_B signal asserted active. address match data output HAD12 HAD0 ENHIT_B more match data items found during search operation, ERR_B goes low, output HAD12 HAD0 invalid. timing output address delayed inserting WAIT_B. When ENHIT_B signal ERR_B HAD12 HAD0 enter high-impedance state.
Data Sheet S13650EJ5V0DS
µPD98421
Example search data Table from data shown Table Full Match mode (for sake convenience, 64-bit values indicated hexadecimal form units bits). Because bits mask data register Table data corresponding bits search register compared when data memory cells compared. Bits (ABh) (78h) data stored 0003h different from values search data register, this ignored depending mask data register setting. other bits match values search data register. This data match data, address 0003h match address. Table 3-2. Example Search Data
Search Data Register 11.22.33.44.55.66.77.88
Mask Data Register FF.FF.00.FF.FF.FF.00.FF
Table 3-3. Example Data
Address 0000h 0001h 0002h 0003h
Data FF.FF.FF.FF.FF.FF.FF.FF. 11.11.22.33.44.55.66.77 11.22.33.44.55.66.77.99 11.22.AB.44.55.66.77.88
3.2.2 Full Match with Mask mode Full Match with Mask mode, data masked entry units, data that completely matches searched. this mode, entry data used, mask register valid. Full Match with Mask mode, signal line shown Table mode register), write search data search data register. Write mask data that masks search data mask data register. This must completed before search data written search data register. Each search data register compared ignored, depending value mask data register same position. mask data register that compared with corresponding search data register; mask register that reset compared with corresponding search data register ignored. search data compared with 64-bit value words memory cells. data memory cells addresses 0000h 0FFFh masked data memory cells 1000h 1FFFh. match data found, clock after search data written search data register normal mode (two clocks after mode), signal asserted active. address match data output HAD12 HAD0 ENHIT_B timing output address delayed inserting WAIT_B.
Data Sheet S13650EJ5V0DS
µPD98421
Example search data Table from data Table value search data register ignored when bits searched from value mask data register. Data 0000h masked mask 1000h compared when bits searched. this way, data 0001h match data because relationship between each data mask. match address 0001h. value 1003h exactly same value search data register, used match data because this area used mask data area Full Match with Mask mode. Table 3-4. Example Search Data
Search Data Register 11.22.33.44.55.66.77.88
Mask Data Register FF.FF.FF.FF.00.FF.00.FF
Table 3-5. Example Data
Address 0000h 0001h 0002h 0003h
Data 11.22.33.44.55.66.77.BB 11.22.AA.44.55.66.77.88 CC.22.33.44.55.66.77.88 99.AA.BB.CC.DD.EE.FF.00
Address 1000h 1001h 1002h 1003h
Mask 00.00.FF.FF.FF.FF.FF.FF. FF.FF.00.FF.FF.FF.FF.FF FF.FF.FF.FF.FF.FF.00.00 11.22.33.44.55.66.77.88
Data Sheet S13650EJ5V0DS
µPD98421
3.2.3 Longest Prefix Match mode Longest Prefix Match mode search data with longest match search data, means masking entry units. 4K-word area addresses 0000h 0FFFh used entry data area, 1000h 1FFFh used mask data area corresponding entry data. Longest Prefix Match mode, contiguous bits, starting from least significant bit, must masked mask data (refer 2.1.2 Full Match with Mask/Longest Prefix Match mode). mask data register valid, masking this register valid entries. contiguous bits mask data register must also masked, starting from least significant bit. connect more µPD98421 chips, values mask data registers chips must same. Searching Longest Prefix Match mode started setting signal lines shown Table setting mode register) writing search data search data register. clocks after search been started normal mode (four clocks after mode), HIT_B asserted active. address match data output HAD12 HAD0 pins ENHIT_B timing output address delayed inserting WAIT_B. more match data found during search operation, ERR_B goes low, output HAD12 HAD0 pins invalid. match data found, both HIT_B ERR_B pins high. mask data that masks search data written mask data register. This must completed before search data written search data register. search data compared with 64-bit value words memory cells. data memory cells addresses 0000h 0FFFh masked data memory cells addresses 1000h 1FFFh. Unlike other modes, data memory cell having string with longest successive match search data, starting from MSB, match data. Example search with only chip data shown Table searched from data memory cells shown Table 3-7. value mask data register masked after value been written search data register. Because bits mask data bits search data register compared when searched. data stored each memory cell compared same manner Full Match with Mask mode. matching data, that which longest number bits that match final match data. this example, data 0001h.
Data Sheet S13650EJ5V0DS
µPD98421
Table 3-6. Example Search Data
Search Data Register 11.22.33.44.55.66.77.88
Mask Data Register FF.FF.FF.FF.FF.FF.FF.FF
Table 3-7. Example Data
Address 0000h 0001h 0002h 0003h
Data 11.22.33.44.00.00.00.00 11.22.33.44.55.66.77.00 11.22.33.44.55.00.00.00 11.22.33.44.55.66.77.AA
Address 1000h 1001h 1002h 1003h
Mask FF.FF.FF.FF.00.00.00.00 FF.FF.FF.FF.FF.FF.FF.00 FF.FF.FF.FF.FF.00.00.00 FF.FF.FF.FF.FF.FF.00.00
Even when more µPD98421 chips connected, data with longest match search data searched from µPD98421s. This done connecting SMD63 SMD0 pins chips. When more chips connected, make sure that values mask data registers chips same. Example search with more chips Data Table searched from data memory cells shown Tables 3-11. These tables show different µPD98421 chips. When searching started, 0001h chip 0002h chip 0001h chip match match addresses. this case, 0002h chip Table 3-10 shortest mask bit. Therefore, data 0002h chip match data. this time, only HIT_B chip goes low; HIT_B pins chips high. Table 3-8. Search Data
Search Data Register 6E.13.01.22.5F.C2.77.E8
Mask Data Register FF.FF.FF.FF.FF.FF.FF.FF
Table 3-9. Memory Cells Chip
Address 0000h 0001h 0002h 0003h
Data 11.22.33.44.55.00.00.00 6E.13.01.22.5F.C2.77.00 6E.13.01.22.00.00.00.00 6F.FF.FF.FF.FF.00.00.00
Address 1000h 1001h 1002h 1003h
Mask FF.FF.FF.FF.FF.00.00.00 FF.FF.FF.FF.FF.FF.00.00 FF.FF.FF.FF.00.00.00.00 FF.FF.FF.FF.FF.00.00.00
Data Sheet S13650EJ5V0DS
µPD98421
Table 3-10. Memory Cells Chip
Address 0000h 0001h 0002h 0003h
Data 11.22.33.44.00.00.00 6E.13.01.22.5F.C2.00.00 6E.13.01.22.5F.C2.77.00 6D.FF.FE.EF.FF.FF.00.00
Address 1000h 1001h 1002h 1003h
Mask FF.FF.FF.FF.00.00.00.00 FF.FF.FF.FF.FF.FF.00.00 FF.FF.FF.FF.FF.FF.FF.00 FF.FF.FF.FF.FF.FF.00.00
Table 3-11. Memory Cells Chip
Address 0000h 0001h 0002h 0003h
Data 6E.13.01.22.5F.C2.AA.00 6E.13.01.22.5F.C2.00.00 6E.13.01.22.5F.BF.00.00 6E.13.01.22.61.01.00.00
Address 1000h 1001h 1002h 1003h
Mask FF.FF.FF.FF.FF.FF.FF.00 FF.FF.FF.FF.FF.FF.00.00 FF.FF.FF.FF.FF.FF.00.00 FF.FF.FF.FF.FF.FF.00.00
3.2.4 Other points noted change mode using MEM, FULL, FMSK pins mode that operates with more clock cycles. Similarly, change Remark Modes that operate with more clock cycles normal mode Longest Prefix Match mode mode: Memory/register read, Full Match mode, Full Match with Mask mode, Longest Prefix Match mode Write register more clocks when changing operation search mode. Create external circuit which RESET_B becomes after power application. After releasing reset, input least more commands continuously. When search operation stopped temporarily using (CE_B) during continuous search operation, almost same power consumed during search operation. this case, shift into no-operation mode writing register inserting wait. When performing continuous search operation normal mode, make total search frequency below.
Data Sheet S13650EJ5V0DS
µPD98421
Cautions when connecting multiple µPD98421s output load capacitance characteristics described later load capacitance exceeds through connection multiple devices, delay amount shown figure below must added output delay. Reference this delay value when designing external circuits. delay value figure only that output buffer. Note also that level which output delay value determined (2.0 rising delay (0.8 falling delay.
Output Buffer Load Dependence (typ.) Rising Delay
5.00E-09 4.50E-09 4.00E-09 3.50E-09
Delay
3.00E-09 2.50E-09 2.00E-09 1.50E-09 1.00E-09 5.00E-10 0.00E+00 Load exceeding [pF]
Output Buffer Load Dependence (typ.) Falling Delay
5.00E-09 4.50E-09 4.00E-09 3.50E-09
Delay
3.00E-09 2.50E-09 2.00E-09 1.50E-09 1.00E-09 5.00E-10 0.00E+00 Load exceeding [pF]
Data Sheet S13650EJ5V0DS
µPD98421
ELECTRICAL SPECIFICATIONS
rated values below when µPD98421 cooled wind velocity m/s. Absolute Maximum Ratings
Parameter Supply voltage Input voltage voltage Operating ambient temperature Storage temperature Symbol Conditions Rating -0.5 +4.6 -0.5 +VDD -0.5 +VDD Unit
Tstg
+150
Caution Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. Recommended Operating Conditions
Parameter Supply voltage Input voltage, high Symbol VIH1 VIH2 Input voltage, VIL1 VIL2 Operating ambient temperature Other than CLK, RESET_B CLK, RESET_B Other than CLK, RESET_B CLK, RESET_B Cooled wind velocity more Conditions MIN. 3.15 TYP. MAX. 3.45 Unit
Characteristics +70°C, ±0.15
Parameter Output voltage, high Output voltage, Operating current Symbol
Note
Conditions -4.0 fclk (normal mode) fclk mode)
MIN.
TYP.
MAX.
Unit
1150 1150
Input leakage current Output leakage current
Output: selected
Pull-up resistance (HAD pins)
Note When performing continuous search operation normal mode, make total search frequency below.
Data Sheet S13650EJ5V0DS
µPD98421
Capacitance
Parameter Input capacitance Output capacitance capacitance
Symbol COUT CI/O
Conditions
MIN.
TYP.
MAX.
Unit
Characteristics 70°C, ±0.15 values below output load capacitance input
Parameter cycle time
Symbol tCYCLK Normal mode mode
Conditions
MIN.
TYP.
MAX.
Unit
high-level width
tCLKH
Normal mode mode
low-level width
tCLKL
Normal mode mode
rise time fall time
tCLKR tCLKF
tCLKR
tCLKF (MIN.)
VPPCLK (MAX.) tCLKH tCYCLK tCLK
RESET input
Parameter RESET_B low-level width
Symbol tWRSTL
Conditions
MIN. tCYCLK
TYP.
MAX.
Unit
Data Sheet S13650EJ5V0DS
µPD98421
CE_B operations
Parameter DATA valid time CE_B DATA valid time valid time CE_B valid time ERR_B valid time CE_B ERR_B valid time valid time CE_B valid time DATA float time CE_B DATA float time float time CE_B float time ERR_B float time CE_B ERR_B float time float time CE_B float time
Symbol tDCEDATA
Conditions
MIN.
TYP.
MAX.
Unit
tDCEHAD
tDCEERR
tDCESMD
tFCEDATA
tFCEHAD
tFCEERR
tFCESMD
Data Sheet S13650EJ5V0DS
µPD98421
Search/memory operations (1/2)
Parameter Address setup time Address hold time Data setup time Data hold time CE_B setup time CE_B hold time setup time hold time WE_B setup time WE_B hold time WAIT_B setup time WAIT_B hold time FULL, FMSK setup time FULL, FMSK hold time Delay time from DATA
Symbol tSDATA tHDATA tSCE tHCE tSMEM tHMEM tSWE tDWE tSWAIT tHWAIT tSMODE tHMODE tDDATA
Conditions
MIN.
TYP.
MAX.
Unit
Normal mode mode
DATA invalid time WE_B DATA valid time WE_B DATA float time OE_B DATA valid time OE_B DATA float time ENHIT_B valid time ENHIT_B float time ENHIT_B ERR_B valid time ENHIT_B ERR_B float time valid time
tDDATAX tDWEDATA tFWEDATA tDOEDATA tFOEDATA tDEHHAD tFEHHAD tDEHERR tFEHERR tDHAD
Normal mode
Normal mode mode
float time
tFHAD
Normal mode mode
invalid time HIT_B delay time
tDHADX tDHIT Normal mode mode
HIT_B invalid time ERR_B valid time
tDHITX tDERR Normal mode mode
ERR_B float time
tFERR
Normal mode mode
ERR_B invalid time setup time
tDERRX tSSMD
Data Sheet S13650EJ5V0DS
µPD98421
Search/memory operations (2/2)
Parameter hold time low-level valid time
Symbol tHSMD tDSMDL1
Note
Conditions
MIN.
TYP.
MAX.
Unit
Normal mode mode
low-level valid time high-level valid time high-level valid time float time
tDSMDL2
Note
Normal mode Normal mode mode
tDSMDH1 tDSMDH2 tFSMD
Note
low-level valid time satisfies either tDSMDL1 tDSMDL2 value.
Memory access (normal mode)
tCYCLK tCLKH A[12:0] tSDATA DATA[63:0]
Memory write Memory write
tCLKL
address
Memory read
Memory read
address
address Memory read data Memory read data
Memory write
Memory write
address
address
tHDATA
data
Memory write
Memory write
data
data
tDDATA CE_B tSCE tHMEM tSMEM tSWE tHWE WE_B tDWEDATA OE_B tSWAIT tHWAIT WAIT_B tFOEDATA tHCE
tDDATAX tDDATA tFCEDATA
tDCEDATA timing identical CE_B.
tFWEDATA
tDOEDATA
FULL,FMSK tDCEHAD HAD[12:0] tFEHHAD tFCEHAD tDEHHAD
HIT_B tFEHERR tDCEERR ERR_B tFCEERR Hi-Z tDEHERR
ENHIT_B
Hi-Z SMD[63:0]
Remark inversion CE_B.
Data Sheet S13650EJ5V0DS
µPD98421
Memory access mode)
tCYCLK A[12:0] tSDATA DATA[63:0]
Memory write Memory write
tCLKH
address
tCLKL
Memory read
address
Memory write
Memory write
address
address
tHDATA
data
Memory read data
Memory write
Memory write
data
data
tDDATA CE_B tSCE tHMEM tSMEM tSWE tHWE WE_B tDWEDATA OE_B tSWAIT tHWAIT WAIT_B tFWEDATA tHCE timing identical CE_B.
FULL,FMSK tDCEHAD HAD[12:0] tFEHHAD tFCEHAD tDEHHAD
HIT_B tFEHERR tDCEERR ERR_B tFCEERR Hi-Z tDEHERR
ENHIT_B
Hi-Z SMD[63:0]
Remark inversion CE_B.
Data Sheet S13650EJ5V0DS
µPD98421
access (normal mode)
tCYCLK A[12:0] tSDATA DATA[63:0]
write data write address
tCLKH
tCLKL
read address
read address
read data
write address
write address
tHDATA
read data
write data
write data
tDDATA CE_B tSCE tHMEM tSMEM tSWE tHWE WE_B tDWEDATA OE_B tSWAIT tHWAIT WAIT_B tFOEDATA tHCE
tDDATAX tDDATA tFCEDATA
tDCEDATA timing identical CE_B.
tFWEDATA
tDOEDATA
FULL,FMSK tDCEHAD HAD[12:0] tFEHHAD tFCEHAD tDEHHAD
HIT_B tFEHERR tDCEERR ERR_B tFCEERR Hi-Z tDEHERR
ENHIT_B Hi-Z SMD[63:0]
Remark inversion CE_B.
Data Sheet S13650EJ5V0DS
µPD98421
access mode)
tCYCLK A[12:0] tSDATA DATA[63:0]
write data write address
tCLKH
tCLKL
read address
write address
write address
tHDATA
read data
write data write data
tDDATA CE_B tSCE tHMEM tSMEM tSWE tHWE WE_B tDWEDATA OE_B tSWAIT tHWAIT WAIT_B tFWEDATA tHCE timing identical CE_B.
FULL,FMSK tDCEHAD HAD[12:0] tFEHHAD tFCEHAD tDEHHAD
HIT_B tFEHERR tDCEERR ERR_B tFCEERR Hi-Z tDEHERR
ENHIT_B
Hi-Z SMD[63:0]
Remark inversion CE_B.
Data Sheet S13650EJ5V0DS
µPD98421
Full Match search (normal mode)
tCYCLK A[12:0] tSDATA DATA[63:0]
Search data
tCLKH
tCLKL
tHDATA
Search data Search data Search data Search data Search data Search data
CE_B tHMEM tSMEM tSWE tHWE WE_B
timing identical CE_B.
OE_B tSWAIT tHWAIT WAIT_B tSMODE FULL,FMSK tDHAD HAD[12:0] tDHIT HIT_B
High
tHMODE
Full match search mode
tFHAD
address
tDEHHAD tDHAD tDHITX tFEHHAD
address address address
tDHADX
ERR_B
tFEERR
Hi-Z
tDERR
tFEHERR
tDEHERR
Hi-Z
tDERRX ENHIT_B
Hi-Z SMD[63:0]
Remark inversion CE_B.
Data Sheet S13650EJ5V0DS
µPD98421
Full Match search with Mask (normal mode)
tCYCLK A[12:0] tSDATA DATA[63:0]
Search data
tCLKH
tCLKL
tHDATA
Search data Search data Search data Search data Search data Search data
CE_B tHMEM tSMEM tSWE tHWE WE_B
timing identical CE_B
OE_B tSWAIT tHWAIT WAIT_B tSMODE FULL,FMSK tDHAD HAD[12:0] tDHIT HIT_B
High
tHMODE
Full match with mask
tFHAD
address
tDEHHAD tDHAD tDHITX tFEHHAD
address address address
tDHADX
ERR_B
tFEERR
Hi-Z
tDERR
tFEHERR
tDEHERR
Hi-Z
tDERRX ENHIT_B
Hi-Z SMD[63:0]
Remark inversion CE_B.
Data Sheet S13650EJ5V0DS
µPD98421
Longest Prefix Match search (normal mode)
tCYCLK A[12:0] tSDATA DATA[63:0] tHDATA
Search data Search data Search data
tCLKH
tCLKL
CE_B tHMEM tSMEM tSWE tHWE WE_B
timing identical CE_B.
OE_B tSWAIT tHWAIT WAIT_B tSMODE FULL,FMSK tDHAD HAD[12:0] tDHIT HIT_B
High
tHMODE
Longest prefix match search mode
tFHAD
address
tDHAD
tDHADX
tDHITX
ERR_B
tFEERR
tDERR Hi-Z
tDERRX ENHIT_B Hi-Z SMD[63:0] tDSMDL1 tDSMDL2 tFSMD
temp data
tDSMDH tFSMD
high temp data high temp data
Remark inversion CE_B.
Data Sheet S13650EJ5V0DS
µPD98421
Full Match search mode)
tCYCLK A[12:0] tSDATA DATA[63:0]
Search data
tCLKH
tCLKL
tHDATA
Search data Search data Search data
CE_B tHMEM tSMEM tSWE tHWE WE_B
timing identical CE_B.
OE_B tSWAIT tHWAIT WAIT_B tSMODE FULL,FMSK tDHAD HAD[12:0] tDHIT HIT_B
High
tHMODE
Full match search mode
tFHAD
address
tDHAD tDHITX
tDHADX
ERR_B
tFEERR
Hi-Z
tDERR
tDERRX ENHIT_B
Hi-Z SMD[63:0]
Remark inversion CE_B.
Data Sheet S13650EJ5V0DS
µPD98421
Full Match search with Mask mode)
tCYCLK A[12:0] tSDATA DATA[63:0]
Search data
tCLKH
tCLKL
tHDATA
Search data Search data Search data
CE_B tHMEM tSMEM tSWE tHWE WE_B
timing identical CE_B.
OE_B tSWAIT tHWAIT WAIT_B tSMODE FULL,FMSK tDHAD HAD[12:0] tDHIT HIT_B
High
tHMODE
Full match with mask search mode
tFHAD
address
tDHAD tDHITX
tDHADX
ERR_B
tFEERR
Hi-Z
tDERR
tDERRX ENHIT_B
Hi-Z SMD[63:0]
Remark inversion CE_B.
Data Sheet S13650EJ5V0DS
µPD98421
(10) Longest Prefix Match search mode)
tCYCLK A[12:0] tSDATA DATA[63:0]
Search data
tCLKH
tCLKL
tHDATA
CE_B tHMEM tSMEM tSWE tHWE WE_B
timing identical CE_B.
OE_B tSWAIT tHWAIT WAIT_B tSMODE FULL,FMSK
High
tHMODE
Longest prefix match search mode
tDHAD HAD[12:0] tDHIT HIT_B
tFHAD
address
tDHADX
ERR_B
tFEERR
Hi-Z
ENHIT_B Hi-Z SMD[63:0] tDSMDL1
tFSMD
temp data
tDSMDH
tFSMD
high
Remark inversion CE_B.
Data Sheet S13650EJ5V0DS
µPD98421
(11) Full Match search (normal mode, insertion wait)
tCYCLK A[12:0] tSDATA DATA[63:0]
Search data
tCLKH
tCLKL
tHDATA
Search data Search data Search data
CE_B tHMEM tSMEM tSWE tHWE WE_B
timing identical CE_B.
OE_B tSWAIT tHWAIT WAIT_B tSMODE FULL,FMSK tDHAD HAD[12:0] tDHIT HIT_B
High
tHMODE
Full match search mode
tFHAD
address
tDHAD tDHITX tDHADX
tDHAD
address
ERR_B
tFEERR
Hi-Z
tDERR
tFEERR
tDERRX ENHIT_B
Hi-Z
SMD[63:0]
Remark inversion CE_B.
Data Sheet S13650EJ5V0DS
µPD98421
(12) Longest Prefix Match search (normal mode, insertion wait)
tCYCLK tCLKH A[12:0] tSDATA DATA[63:0]
Search data
tCLKL
tHDATA
Search data
CE_B tHMEM tSMEM tSWE tHWE WE_B
timing identical CE_B.
OE_B tSWAIT tHWAIT WAIT_B tSMODE FULL,FMSK
High
tHMODE
Longest prefix match search mode
tDHAD HAD[12:0] tDHIT HIT_B
address
tDHAD
address
tDHADX
tDHADX
tDHIT
ERR_B
tFEERR
Hi-Z
ENHIT_B tDSMDL2
tFSMD
temp data
tDSMDH
tFSMD
high temp data
Hi-Z SMD[63:0]
high
tDSMDL1
Remark inversion CE_B.
Data Sheet S13650EJ5V0DS
µPD98421
(13) Search Memory access Search (normal mode)
tCYCLK tCLKH A[12:0] tSDATA DATA[63:0]
Search data
tCLKL
Memory write address
tHDATA
Search data Memory data Search data
CE_B tHMEM tSMEM tSWE tHWE WE_B
timing identical CE_B.
OE_B tSWAIT tHWAIT WAIT_B tSMODE FULL,FMSK
Full match search mode
High
tHMODE
Longest prefix search mode
Full match with mask
tDHAD HAD[12:0] tDHIT HIT_B
address address
tDHADX
ERR_B
tFEERR
Hi-Z
ENHIT_B
Hi-Z SMD[63:0]
temp data
high
Remark inversion CE_B.
Data Sheet S13650EJ5V0DS
µPD98421
RECOMMENDED SOLDERING CONDITIONS
µPD98421 should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact your sales representative. Surface-mount type µPD98421F1-GA1: 240-pin plastic FBGA
Recommended Condition Symbol IR30-103-2
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 230°C, Time: seconds max. 210°C higher), Count: times less, Exposure limit: days 125°C hours)
Note
(after that, prebake
Note After opening pack, store 25°C less less allowable storage period.
Data Sheet S13650EJ5V0DS
µPD98421
PACKAGE DRAWING
240-PIN PLASTIC FBGA (16x16)
VUTRPNML EDCBA
Index mark 4-R0.3MAX.
4-C1.0
240-
ITEM
MILLIMETERS 16.00±0.10 15.4 16.00±0.10 15.4 0.20 0.80 1.31±0.15 0.35±0.10 0.96 0.50 +0.05 -0.10 0.08 0.10 0.20 0.40 0.40 P240F1-80-GA1
Data Sheet S13650EJ5V0DS
µPD98421
[MEMO]
Data Sheet S13650EJ5V0DS
µPD98421
[MEMO]
Data Sheet S13650EJ5V0DS
µPD98421
[MEMO]
Data Sheet S13650EJ5V0DS
µPD98421
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet S13650EJ5V0DS
µPD98421
information this document current January, 2002. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

µPD98421 HIGH-SPEED ADDRESS SEARCH ENGINE DESCRIPTION µ

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