µPD98414 Gbps ASONET FRAMER µPD98414 (NEASCOT-P70) ALSIs pro

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µPD98414 Gbps ASONET FRAMER µPD98414 (NEASCOT-P70) ALSIs pro

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INTEGRATED CIRCUIT
µPD98414
Gbps ASONET FRAMER
µPD98414 (NEASCOT-P70) ALSIs provides functions sublayer SONET/SDH-base physical layer Aprotocol specified AForum. main functions include transmission function mapping Acell passed from high-end Alayer device payload Gbps SONET STS-48c/SDH STM-16c frame transmitting cell device circuit, reception function separating overhead Acell from data string received from DEMUX device transmitting Acell Alayer device. This ideal systems that constitute Anetwork WAN, such transmission system, Aswitch, high-speed backbone switch. Detailed descriptions functions, etc., given following user's manual. sure read design purposes.
µPD98414 User's Manual: S14166E
FEATURES
Supplies functions (Transmission Convergence) sublayer recommended AForum ITU-T. Supports concatenation frame Gbps SONET STS-48c/SDH STM-16c. Alayer interface 32-bit, 104-MHz LVTTL FIFO interface 15-cell transmit/receive FIFO Supports 52-byte/56-byte cell formats. Prefixes one-word area receive cell. Circuit side interface 16-bit PECL level Either modes selected interface 16-bit data Intel-compatible mode [RD, RDY-type]/Motorola-compatible mode [DS, R/W, ACK-type] Supports types overhead interfaces (that access overhead areas). Incorporates overhead byte insert/drop registers. Incorporates dedicated overhead byte insert/extract interfaces.
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Document S14242EJ2V0DS00 (2nd edition) Date Published July 2001 CP(K) Printed Japan
mark
shows major revised points.
1999, 2001
µPD98414
Many functions Fault: Detection LOS, OOF, LOF, LOP, OCD, Alarm: Detection transmission APS, Line AIS, Line RDI, Path AIS, Path Receive signal Signal Label byte) monitoring functions error rate monitoring function Transmit/receive message buffer J0/J1 trace messages bytes bytes long) Supports loopback function. Remote: modes (Alayer loopback circuit side loopback) Supports error generation pseudo frame transmission function testing. Three general-purpose input five general-purpose output ports Supports JTAG boundary scan test (IEEE1149.1). 0.35-µm CMOS process +3.3 single power source
ORDERING INFORMATION
Part Number Package 352-pin plastic (cavity down advanced type)
µPD98414F2-RN1
Data Sheet S14242EJ2V0DS
SYSTEM CONFIGURATION
Clock generator 16-bit 156M
Clock generator
Data Sheet S14242EJ2V0DS
(AMCC S3043, etc.)
µPD98414 NEASCOT-P70
DEMUX (AMCC S3044, etc.)
16-bit 156M
Acell interface Switch
Microprocessor interface Overhead interface
µPD98414
Overhead Extract Interface (19M) POUT0 POUT1 POUT2 POUT3 POUT4 PIN0 PIN1 PIN2 LOSS OOFS LOFS LOPS LCDS LAISS PAISS LRDIS PRDIS B1ERS B2ERS Processor Block Overhead Extraction Block Output Input RSOHCK (25M) RSOHFP RSOHD[4] RSOHAV RPOHCK (576K) RPOHFP RPOHD RPOHAV Alarm Detection Connect peripheral devices Framer Block Processor Cell Synchronization verification Frame Descramble Idle Cell Drop Cell Descramble
FIFO Control FIFO Control
BLOCK DIAGRAM
Cell Processor Block Compare/Control FIFO cells)
Processor
RXPLD[16] RCLK_N (155M) RCLK_P (155M) Serial Parallel
ALayer Interface
VREF[3]
RXCLAV RXSOC PRTY RXENB_B RXCLK RXCLK_O RXSEL_B RXDATA[32]
Line Interface Framer Block Processor Processor
Cell Processor Block Generation Cell Mapping
Data Sheet S14242EJ2V0DS
ALayer Device
MUX/DEMUX Chip Parallel Serial Generation Frame Scramble Cell Scramble JTAG Overhead Insertion Block Processor Block TLAIS TPAIS TLRDI TPRDI JRST_B (77M) TSOHCK (25M) TSOHFP TSOHD[4] TSOHAV Overhead Insert Interface TPOHCK (576K) TPOHFP TPOHD TPOHAV Alarm Instruction
FIFO cells) Idle Cell insertion
ALayer Interface
TXPLD[16] TPCLK_N (155M) TPCLK_P (155M) TCLK_N (155M) TCLK_P (155M)
TXCLAV TXSOC TXPRTY TXENB_B TXCLK TXCLK_O TXSEL_B TXDATA[32] Registers Management Interface
MADD[8] MD[16] BMODE DS_B/RD_B ACK2S_B/ RDY2S_B ACK3S_B/ RDY3S_B RW/WR_B CS_B PHINT_B RESET_B Processor
µPD98414
µPD98414
CONFIGURATION
ALayer Interface
RXCLK RXCLK_O RXCLAV RXSOC RXPRTY RXDATA[31:0] RXENB_B RXSEL_B TXCLK TXCLK_O TXCLAV TXDATA[31:0] TXENB_B TXSOC TXPRTY TXSEL_B
RCLK_N RCLK_P TCLK_N TCLK_P TPCLK_N TPCLK_P
TXPLD[15:0]
Line Interface
RXPLD[15:0] VREF[3:1] TSOHCK TSOHFP TSOHD[3:0]
TSOHAV MADD[7:0]
MD[15:0] CS_B RW/WR_B Management Interface
µPD98414 NEASCOT-P70
TPOHCK TPOHFP TPOHD TPOHAV RSOHCK RSOHFP RSOHD[3:0] RSOHAV RPOHCK
DS_B/RD_B ACK2S_B/RDY2S_B ACK3S_B/RDY3S_B RESET_B PHINT_B BMODE
Overhead Insert/ Extract Interface
Alarm Signals Pins
LOSS OOFS LOFS LOPS LCDS LAISS PAISS LRDIS PRDIS B1ERS B2ERS
RPOHFP RPOHD RPOHAV
POUT[4:0]
PIN[2:0] JRST_B
General Ports
JTAG Interface
Alarm Instruction Pins
TLAIS TPAIS TLRDI TPRDI
Power Ground
Others (Leave open)
Data Sheet S14242EJ2V0DS
µPD98414
CONFIGURATION (BOTTOM VIEW)
352-pin plastic (cavity down advanced type)
µPD98414F2-RN1
Index mark
Data Sheet S14242EJ2V0DS
µPD98414
ARRANGEMENT TABLE (1/4)
Serial Address AA01 AB01 AC01 AD01 AE01 AF01 AF02 AF03 AF04 AF05 AF06 AF07 AF08 AF09 AF10 Name RXPLD15 RXPLD13 RXPLD10 RXPLD8 RXPLD4 RCLK_P RPOHFP RSOHD2 RSOHAV TPOHAV TSOHD2 TSOHD0 POUT4 PIN1 TLRDI POUT2 RXDATA1 RXDATA10 RXDATA12 Serial Address AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AE26 AD26 AC26 AB26 AA26 Name RXDATA15 RXDATA17 RXDATA19 RXDATA24 RXDATA28 RXDATA30 RXPRTY RXCLAV POUT1 PRDIS LAISS OOFS TXDATA1 TXDATA10 TXDATA12 TXDATA15 TXDATA17 TXDATA19 TXDATA24 TXDATA28 TXDATA30 TXPRTY Serial Address Name TXCLAV POUT0 PHINT_B RW/WR_B MADD6 MADD4 MADD1 MD13 MD10 TXPLD13 TXPLD3 TPCLK_P
Data Sheet S14242EJ2V0DS
µPD98414
(2/4)
Serial Address AA02 AB02 AC02 AD02 AE02 AE03 AE04 AE05 AE06 AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 Name RXPLD12 RXPLD11 RXPLD9 VREF2 RXPLD3 RXPLD2 RXPLD0 RCLK_N RPOHD RSOHD3 RSOHD1 RSOHFP TPOHFP TSOHD1 TSOHFP PIN2 PIN0 TPAIS RXDATA3 RXDATA5 RXDATA6 RXDATA9 RXDATA16 RXDATA18 RXDATA22 RXDATA25 RXDATA27 Serial Address AE19 AE20 AE21 AE22 AE23 AE24 AE25 AD25 AC25 AB25 AA25 Name RXDATA31 RXENB_B RXCLK_O B2ERS PAISS LOSS LCDS TXDATA3 TXDATA5 TXDATA6 TXDATA9 TXDATA16 TXDATA18 TXDATA22 TXDATA25 TXDATA27 TXDATA31 TXENB_B TXCLK_O RESET_B DS_B/RD_B ACK3S_B/RDY3S_B MADD5 MADD2 MD14 MD11 Serial Address Name TXPLD12 TXPLD11 TXPLD9 TXPLD7 TXPLD1 TCLK_N TPCLK_N JRST_B VREF3 RXPLD7 RXPLD5 RXPLD1 RPOHAV RSOHD0 TPOHD
Data Sheet S14242EJ2V0DS
µPD98414
(3/4)
Serial Address AA03 AB03 AC03 AD03 AD04 AD05 AD06 AD07 AD08 AD09 AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AC24 AB24 AA24 Name TSOHD3 TSOHAV POUT3 RXDATA0 RXDATA4 RXDATA8 RXDATA11 RXDATA13 RXDATA21 RXDATA23 RXDATA26 RXSEL_B RXCLK TLAIS LRDIS LOPS TXDATA0 TXDATA4 TXDATA8 TXDATA11 TXDATA13 Serial Address Name TXDATA21 TXDATA23 TXDATA26 TXSEL_B TXCLK CS_B ACK2S_B/RDY2S_B MADD3 MADD0 MD12 TXPLD14 TXPLD10 TXPLD6 TXPLD5 TXPLD2 TXPLD0 RXPLD14 Serial Address AA04 AB04 AC04 AC05 AC06 AC07 AC08 AC09 AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 Name RXPLD6 VREF1 RPOHCK RSOHCK TPOHCK TSOHCK TPRDI RXDATA2 RXDATA7 RXDATA14 RXDATA20 RXDATA29 RXSOC B1ERS
Data Sheet S14242EJ2V0DS
µPD98414
(4/4)
Serial Address AB23 AA23 Name LOFS TXDATA2 TXDATA7 TXDATA14 TXDATA20 TXDATA29 Serial Address Name TXSOC BMODE MADD7 MD15 TXPLD15 TXPLD8 Serial Address Name TXPLD4 TCLK_P
Data Sheet S14242EJ2V0DS
µPD98414
NAME ACK2S_B ACK3S_B B1ERS B2ERS BMODE CS_B DS_B JRST_B LAISS LCDS LOFS LOPS LOSS LRDIS MADD0-MADD7 MD0-MD15 OOFS PAISS PHINT_B PIN0-PIN2 POUT0-POUT4 PRDIS RCLK_N RCLK_P RD_B RDY2S_B RDY3S_B RESET_B RPOHAV RPOHCK RPOHD RPOHFP RSOHAV RSOHCK RSOHD0-RSOHD3 Acknowledge State Acknowledge State Error Rate Degrade Error Rate Degrade Mode Carrier Detect Chip Select Data Strobe Ground Internal Circuits Connection JTAG Test Clock JTAG Test Data JTAG Test Data JTAG Test Mode Select JTAG Test Reset Line State State State State State Line State Management Address Management Data State Path State Interrupt General General Path State Line Clock (155 MHz) Line Clock (155 MHz) Read Ready 2-State Ready 3-State Reset Insert Available Insert Clock Insert Data Insert Frame Pulse Insert Available Insert Clock Insert Data RSOHFP RXCLAV RXCLK RXCLK_O RXDATA0RXDATA31 RXENB_B RXPLD0-RXPLD15 RXPRTY RXSEL_B RXSOC TCLK_N TCLK_P TLAIS TLRDI TPAIS TPCLK_N TPCLK_P TPOHAV TPOHCK TPOHD TPOHFP TPRDI TSOHAV TSOHCK TSOHD0-TSOHD3 TSOHFP TXCLAV TXCLK TXDATA0TXDATA31 TXENB_B TXPLD0-TXPLD15 TXPRTY TXSEL_B TXSOC VREF1-VREF3 WR_B Cell Enable Line Data Parity Cell Select Start Cell Voltage Reference PECL Write Cell Enable Line Data Parity Cell Select Start Cell Clock (155 MHz) Clock (155 MHz) Line Clock Signal MHz) Line Frame Send Line Frame Send Path Frame Send Clock (155 MHz) Clock (155 MHz) Insert Available Insert Clock Insert Data Insert Frame Pulse Path Frame Send Insert Available Insert Clock Insert Data Insert Frame Pulse Cell Available UTOPIA Clock UTOPIA Clock UTOPIA Data Insert Frame Pulse Management Data Read/Write Cell Available UTOPIA Clock UTOPIA Clock UTOPIA Data
Line Clock Signal MHz) TXCLK_O
Data Sheet S14242EJ2V0DS
µPD98414
CONTENTS
FUNCTION Line Interface ALayer Interface Management Interface Overhead Interface.18 General-Purpose Port Alarm Signal Input/Output.20 JTAG Boundary Scan Power Grounding Pins Others.22 1.10 Handling Unused Pins 1.11 Initial States Each CONNECTION EXAMPLE MUX/DEMUX DEVICE.25 ELECTRIC CHARACTERISTICS PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS
Data Sheet S14242EJ2V0DS
µPD98414
FUNCTION Line Interface
line interface connects DEMUX devices circuit.
Name RCLK_N RCLK_P TCLK_N TCLK_P TPCLK_N TPCLK_P RXPLD15RXPLD0 Serial 280, 106, 107, 108, 201, 285, 202, 112, 113, 204, 342, 265, 181, 182, 267, 183, 345, 184, 269, 270, 347, 272, 188, Address E01, G04, F01, G02, H02, H01, J02, J01, L03, M04, M03, M01, N02, P02, P03, D15, C15, A15, B14, B13, C13, B12, D12, B11, C11, C10, D10, A08, C08, B07, PECL PECL PECL I/O, Level PECL Function Receive clock input (155.52 MHz). These pins input 155.52-MHz clock, synchronized with receive data. Transmit clock input (155.52 MHz). These pins input transmit clock. µPD98411 updates transmit data TXPLD15 through TXPLD0 rising edge this clock. Transmit clock output (155.52 MHz). clocks input TCLK_N TCLK_P internally inverted output from these pins. Receive 16-bit parallel data input.
TXPLD15TXPLD0
PECL
Transmit 16-bit parallel data output.
LVTTL
Transmit system clock output (77.76 MHz). transmit clocks input TCLK_N TCLK_P divided µPD98414 output from this pin. Receive system clock output (19.44 MHz). receive clocks input RCLK_N RCLK_P divided eight µPD98414 output from this pin. Receive framer function reset. While input level this low, receive framer block (from circuit receive FIFO) reset. transition this signal from high used condition detection. optical input failure alarm signal output receive optical link module input this pin. These pins input reference potentials (intermediate potentials) single-end PECL input signals (RXPLD[15:0]).
LVTTL
AD04
LVTTL tolerant)
VREF3VREF1
195, 109,
E03, K02,
VREF
Data Sheet S14242EJ2V0DS
µPD98414
ALayer Interface
(1/3)
Name RXCLK Serial Address AD21 I/O, Level LVTTL Function Receive FIFO clock input. This inputs clock, from MHz, used transfer receive data. Receive FIFO clock return output. This returns outputs clock input RXCLK. Receive cell start position signal output. This goes high during clock cycle which first byte receive cell output RXDATA, post notification Alayer device. Receive FIFO cell data transfer enable signal output. µPD98414 drives RXCLAV high more cells receive data transferred exists receive FIFO, post notification Alayer device. RXCLAV held high more cells valid data exists receive FIFO seventh clock cycle later after start output cell; otherwise, RXCLAV goes low. RXENB_B AE20 LVTTL Receive enable signal input (byte unit control). Alayer device enables disables receive cell data output µPD98414 byte units. µPD98414 samples RXENB_B rising edge RXCLK. When detects level RXENB_B, updates output RSOC RXDATA starting from next clock cycle, then transfers receive cell data. RXENB_B high, µPD98414 stops output RSOC RXDATA, starting from next clock cycle. Caution This signal cannot used with RXSEL_B same time. this signal level when used. RXSEL_B AD20 LVTTL Receive enable signal input (cell unit control). Alayer device enables µPD98414 output receive cell data cell units. µPD98414 samples RXSEL_B rising edge, clock cycle before RXSOC goes high, starts outputting receive cell data from next clock cycle RXSEL_B low. Once µPD98414 detected that RXSEL_B gone low, does sample RXSEL_B until next sampling timing (one clock before RXSOC goes high). When µPD98414 detects that RXSEL_B gone high sampling timing, continues sampling RXSEL_B every clock, starts outputting cells from clock cycle next that which level RXSEL_B detected. Caution This signal cannot used with RXENB_B same time. this signal level when used.
Alayer interface transfers cells from high-end Alayer device.
RXCLK_O
AE22
LVTTL LVTTL
RXSOC
AC20
RXCLAV
AF21
LVTTL
Data Sheet S14242EJ2V0DS
µPD98414
(2/3)
Name RXPRTY Serial Address AF20 I/O, Level LVTTL Function Parity output. This generates parity output data RXDATA outputs from RXPRTY. parity always output. parity generated changed even parity depending setting RRPM MDR5 register. Receive cell data output bus. These pins form 32-bit data through which receive cell data output Alayer device. data this updated rising edge RXCLK.
RXDATA31RXDATA0
141, 309, 139, 227, 138, 226, 137, 225, 306, 135, 134, 304, 222, 221, 131, 220, 301, 130, 129, 218, 128, 299,
AE19, AF19, AC17, AF18, AE17, AD16, AE16, AF16, AD15, AE15, AD14, AC14, AF14, AE13, AF12, AE12, AF11, AC12, AD11, AF10, AD10, AF09, AE09, AD09, AC09, AE08, AE07, AD07, AE06, AC07, AF05, AD05
LVTTL
TXCLK
LVTTL
Transmit FIFO clock input. This inputs clock, from MHz, used transfer transmit data. Transmit FIFO clock return output. This returns outputs clock input TXCLK. Transmit cell start position signal input. This inputs signal that indicates start position transmit cell. µPD98414 recognizes clock cycle which TXSOC high first word cell.
TXCLK_O
LVTTL LVTTL
TXSOC
TXCLAV
LVTTL
Transmit FIFO cell data reception enable signal output. This signal posts notification vacancy transmit FIFO Alayer device. number cells stored transmit FIFO reached threshold value TCAV[1:0] bits MDR5 register, µPD98414 drives TXCLAV low. threshold value selected from cells. default value cells, which point transmit FIFO full. µPD98414 keeps receiving cells, even TXCLAV driven low, until transmit FIFO full (i.e., cells). 16th subsequent cells dropped µPD98414 reports overflow transmit FIFO.
Data Sheet S14242EJ2V0DS
µPD98414
(3/3)
Name TXENB_B Serial Address I/O, Level LVTTL Function Transmit enable signal input (byte unit control). This signal indicates, byte units, that Alayer device output valid transmit cell data TXDATA. µPD98414 samples TXENB_B rising edge TXCLK. TXENB_B low, loads data TXSOC TXDATA transmit FIFO edge TXCLK. TXENB_B high, data TXSOC TXDATA loaded transmit FIFO. Caution This signal cannot used with RXSEL_B same time. this signal level when used. TXSEL_B LVTTL Transmit enable signal input (cell unit control). This signal informs µPD98414, cell units, that Alayer device outputting valid transmit cell data TXDATA. µPD98414 samples TXSEL_B rising edge TXCLK clock immediately before high level input TXSOC when receives transmit cell from Alayer device. TXSEL_B low, µPD98414 loads cell input next clock cycle transmit FIFO. Once µPD98414 detected level TXSEL_B started loading cell, does sample TXSEL_B until next sampling timing (i.e., clock immediately before next TXSOC input). TXSEL_B high clock immediately before high level input TXSOC, µPD98414 loads next cell transmit FIFO. Caution This signal cannot used with RXSEL_B same time. this signal level when used. TXPRTY LVTTL (Internal pull-up) Parity input. This inputs parity data input TXDATA. µPD98414 calculates parity based input data parity bit. detects error, sets UPED UEDR register report error. µPD98414 calculates parity only within range bytes transmit cell P48). even parity also used depending setting TRPM MDR5 register. TXDATA31TXDATA0 164, 328, 162, 248, 161, 247, 160, 246, 325, 158, 157, 323, 243, 242, 154, 241, 320, 153, 152, 239, 151, 318, H25, H26, K23, J26, K25, L24, L25, L26, M24, M25, N24, N23, N26, P25, R26, R25, T26, R23, T24, U26, U24, V26, V25, V24, V23, W25, Y25, Y24, AA25, Y23, AB26, AB24 LVTTL Transmit cell data input bus. These pins form 32-bit data through which transmit cell data input. µPD98414 inputs data this rising edge TXCLK.
Data Sheet S14242EJ2V0DS
µPD98414
Management Interface
(1/2)
Name RESET_B Serial Address I/O, Level LVTTL tolerant) LVTTL tolerant) LVTTL tolerant) Function System reset input. This signal initializes µPD98414. Input low-pulse signal having width least Interrupt signal output. This signal informs host occurrence interrupt cause. mode select input. mode management interface determined from input level this signal after reset. BMODE Low: <DS, R/W, ACK> -type selected. High: <RD, RDY> -type selected. Address input. These pins form 8-bit used input addresses internal registers. 16-bit data bus. This 16-bit data used exchange data with internal registers.
management interface used access registers µPD98414.
PHINT_B
BMODE
MADD7MADD0
335, 172, 258, 173, 337, 174, 260, 175, 176, 339, 262, 177, 340, 263, 178,
D22, A24, B23, A23, C22, B22, A22, D20, B21, A21, C20, B20, A20, B19, D18, A19, C18, B18, D17, A18, C17, B17,
LVTTL tolerant) LVTTL tolerant)
MD15-MD0
(WR_B)
LVTTL tolerant)
Read/write signal input write signal input. function this signal differs depending mode BMODE. When BMODE low, functions read/write control signal (RW). High: Ready cycle Low: Write cycle When BMODE high, functions write signal (WR_B) that specifies write access. Acknowledge signal output ready signal two-state output. This indicates that data ready when accessed read. outputs acknowledge ready signal, which indicates that data received, states during write cycle. Acknowledge signal output ready signal tristate output. This indicates that data ready when accessed read. outputs acknowledge ready signal, which indicates that data received, tristate during write cycle. Chip select signal input. When this signal low, access internal registers µPD98414 enabled.
ACK2S_B (RDY2S_B)
LVTTL tolerant)
ACK3S_B (RDY3S_B)
3-state LVTTL tolerant)
CS_B
LVTTL tolerant)
Data Sheet S14242EJ2V0DS
µPD98414
(2/2)
Name DS_B (RD_B) Serial Address I/O, Level LVTTL tolerant) Function Data strobe signal input read signal input. function this differs depending management interface mode selected input BMODE pin. BMODE low: Functions data strobe signal (DS_B) that indicates that data output BMODE high: Functions read signal (RD_B) that specifies read access.
Overhead Interface
overhead interface used transfer contents section overhead (SOH) path overhead (POH) that exchanged between peripheral device µPD98414. (1/2)
Name TSOHCK Serial Address AB04 I/O, Level LVTTL Function Transmit interface clock output (25.92 MHz). This outputs 25.92-MHz clock obtained internally dividing transmit clock TCLK (155.52 MHz) six. TSOHFP TSOHD output sync with this divided clock. Transmit frame pulse output. TSOHFP driven high clock cycle before input transmit data started. Transmit data input 4-bit bus. This 4-bit data that inputs transmit data. inputs data TSOHD byte clock cycles, starting from clock cycle next that which TSOHFP output. Transmit data validity indication signal input. This signal informs µPD98414 that valid data been output TSOHD. µPD98414 samples TSOHAV rising edge TSOHCK during first clock cycles which data input. TSOHAV high, µPD98414 inputs data TSOHD that cycle next; when TSOHAV low, µPD98414 does input data. TPOHCK LVTTL Transmit interface clock output (576 kHz). This outputs 576-kHz clock resulting from internally dividing transmit clock TCLK (155.52 MHz) 270. TPOHFP TPOHD output sync with this divided clock. Transmit frame pulse output. This signal driven high cycle before clock cycle which input transmit data started. Transmit data input. This inputs serial transmit data. inputs transmit data TPOHD byte eight clock cycles, starting from clock cycle next that which TPOHFP output.
TSOHFP
AC02
LVTTL
TSOHD3TSOHD0
211, 121,
AA03, AB01, AB02, AC01
LVTTL tolerant/ Internal pull-down) LVTTL tolerant/ Internal pull-down)
TSOHAV
AB03
TPOHFP
AA02
LVTTL
TPOHD
LVTTL tolerant/ Internal pull-down)
Data Sheet S14242EJ2V0DS
µPD98414
(2/2)
Name TPOHAV Serial Address AA01 I/O, Level LVTTL tolerant/ Internal pull-down) Function Transmit data validity indication signal input. This signal informs µPD98414 that valid data been output TPOHD. µPD98414 samples TPOHAV rising edge TPOHCK first eight clock cycles which data input. TPOHAV high, µPD98414 inputs TPOHD data duration eight clock cycles, starting from cycle which TPOHAV goes high; TPOHAV low, µPD98414 does input TPOHD data. RSOHCK LVTTL Receive interface clock output (25.92 MHz) This outputs 25.92-MHz clock obtained internally dividing receive clock RCLK (155.52 MHz) six. RSOHFP RSOHAV output sync with this divided clock. Receive frame pulse output. This signal goes high cycle before clock cycle which output receive data started. Receive data output 4-bit bus. This 4-bit data outputs receive data. starts output receive data onto RSOHD starting from clock cycle next that which RSOHFP output. Receive data validity indication signal output. This signal indicates that valid receive data output RSOHD. clock cycle which valid data output RSOHD, RSOHAV goes high. clock cycle which valid data output, RSOHAV goes low. Receive interface clock output (576 kHz). This outputs 576-kHz clock obtained internally dividing receive clock RCLK (155.52 MHz) 270. RPOHFP RPOHAV output sync with this divided clock. Receive frame pulse output. This signal goes high cycle before clock cycle which output receive data started. Receive data output. This outputs serial receive data. outputs receive data RPOHD byte eight clock cycles, starting from clock cycle next that which RPOHFP output. Receive data validity indication signal output. This signal indicates that valid receive data been output RPOHD. clock cycle which valid data output RPOHD, RPOHAV goes high; cycle which valid data output, goes low.
RSOHFP
LVTTL
RSOHD3RSOHD0
117, 118,
V02, W01, W02,
LVTTL
RSOHAV
LVTTL
RPOHCK
LVTTL
RPOHFP
LVTTL
RPOHD
LVTTL
RPOHAV
LVTTL
Data Sheet S14242EJ2V0DS
µPD98414
General-Purpose Port
Serial Address AD02 I/O, Level LVTTL (Internal pulldown) LVTTL tolerant/ Internal pull-down) LVTTL Function General-purpose input port. These general-purpose input pins that input state signals external peripheral devices. signal levels these pins reflected bits internal GPSR register. Changes statuses these bits used interrupt causes. Caution PIN2 PIN0, only PIN2 tolerant pin.
Name PIN2
PIN1, PIN0
AF02, AE03
POUT4POUT0
213,
AD01, AC03, AF04, AF23,
General-purpose output port. setting bits internal POUTR register output these pins signal levels. These pins used control external peripheral devices.
Alarm Signal Input/Output
Serial 314, 145, 149, 316, 236, 148, 234, 146, Address AC22, AE23, AE26, AC25, AB23, AC24, AD25, AD23, AD26, AE24, AF24 I/O, Level LVTTL Function Alarm signal output. µPD98414 detects event such fault alarm reception side, sets corresponding internal ESTR register. these alarm signals goes high post notification occurrence event external device. event cleared ESTR register reset, signal goes low. LVTTL tolerant/ Internal pull-down) Alarm transmit command input. While these signals goes high, corresponding alarm frame (Line AIS, Line RDI, Path AIS, Path RDI) transmitted. transmission alarm frame also specified setting CMR1 register.
Name B1ERS, B2ERS, LAISS, LCDS, LOFS, LOPS, LOSS, LRDIS, OOFS, PAISS, PRDIS
TLAIS, TLRDI, TPAIS, TPRDI
233, 126,
AD22, AF03, AE04, AC05
Data Sheet S14242EJ2V0DS
µPD98414
JTAG Boundary Scan
Serial Address I/O, Level LVTTL tolerant) LVTTL tolerant) LVTTL 3-state tolerant) LVTTL tolerant) LVTTL tolerant) Function Boundary scan clock input. Ground this when used.
Name
Boundary scan data input. Ground this when used.
Boundary scan data output. Open this when used.
Boundary scan mode select signal input. Ground this when used.
JRST_B
Boundary scan reset signal input. Ground this when used.
Remark About treatment JTAG boundary scan pins normal operation pulse input RESET_B does reset JTAG logic. JTAG logic been reset, PD98414 operate normally. Either following methods used reset JTAG logic. JRST_B connected ground, sure reset JTAG logic, using either method, after power switched Resetting JTAG logic without using JRST_B pins reset JTAG logic keep reset (with JRST_B pulled up). (pulled up), input five more clock cycles pin. Using JRST_B reset JTAG logic pulse input JRST_B pin, JRST_B pins pulled kept high level, JTAG logic kept reset, does affect normal operations. pins, keep input level pulled down
Data Sheet S14242EJ2V0DS
µPD98414
Power Grounding Pins
Serial 100, 101, 104, 111, 124, 127, 132, 136, 143, 147, 150, 155, 159, 166, 170, 180, 186, 193, 197, 198, 199, 203, 208, 214, 219, 223, 224, 228, 229, 230, 235, 240, 244, 245, 249, 250, 251, 256, 261, 264, 266, 271, 274, 279, 283, 287, 289, 298, 307, 308, 317, 326, 327, 336, 344, 105, 110, 133, 140, 156, 163, 179, 185, 187, 196, 200, 205, 206, 217, 238, 268, 277, 281, 282, 284, 286, 291, 294, 296, 300, 302, 303, 305, 310, 311, 313, 315, 319, 321, 322, 324, 329, 330, 332, 334, 338, 341, 343, 348, 349, Address K01, N01, T01, AF06, AF08, AF25, AA26, W26, A12, A11, A09, A07, A02, B02, E02, M02, AE02, AE05, AE10, AE14, AE21, AE25, AB25, U25, N25, F25, B25, B15, B09, C03, G03, H03, J03, N03, V03, AD03, AD08, AD12, AD13, AD17, AD18, AD19, AD24, W24, R24, P24, K24, J24, H24, C24, C19, C16, C14, C09, C06, F04, K04, P04, T04, AC06, AC15, AC16, AA23, M23, L23, D21, D13, A01, G01, L01, P01, R01, AE01, AF01, AF07, AF13, AF15, AF17, AF22, AF26, AC26, Y26, P26, M26, K26, E26, B26, A26, A16, A14, A13, A10, A06, F02, L02, AE11, AE18, T25, J25, B16, B10, B08, F03, K03, R03, T03, AD06, AA24, C12, D04, H04, J04, L04, N04, V04, AA04, AC04, AC08, AC10, AC11, AC13, AC18, AC19, AC21, AC23, W23, U23, T23, P23, J23, H23, F23, D23, D19, D16, D14, D09, D08, Function Power supply pins (+3.3 ±5%)
Name
Ground pins
Others
Serial 103, 194, 254, 275, Address C01, D01, A04, D02, D03, E24, C05, I/O, Level Function Internal circuit connection test pins. These pins must kept open.
Name
Data Sheet S14242EJ2V0DS
µPD98414
1.10 Handling Unused Pins
Depending mode, some pins used. These pins must handled listed below.
Name RCLK_N, TCLK_N RCLK_P, TCLK_P RXPLD[15:0], TXPLD[15:0] RXCLK, RXENB_B, RXSEL_B, TXCLK, TXENB_B, TXSOC, TXSEL_B TXPRTY CS_B MADD[7:0] DS_B, TSOHD[3:0], TSOHAV, TPOHD, TPOHAV, PIN[2:0] TLAIS, TPAIS, TLRDI, TPRDI JCK, JMS, JDI, JRST_B Output pins Leave open. Ground. Pulled Pulled Pulled Ground. Handling
Leave open. Pulled Ground. Ground.
Leave open. Ground. Ground. Leave open.
Data Sheet S14242EJ2V0DS
µPD98414
1.11 Initial States Each
Name During Reset Immediately After Reset Receive framer function reset
TPCLK_N/TPCLK_P TXPLD15-TXPLD0 RXCLK_O RXSOC RXCLAV RXPRTY RXDATA31-RXDATA0 TXCLK_O TXCLAV PHINT_B MD15-MD0 ACK2S_B/RDY2S_B ACK3S_B/RDY3S_B TSOHCK TSOHFP TPOHCK TPOHFP RSOHCK RSOHFP RSOHD3-RSOHD0 RSOHAV RPOHCK RPOHFP RPOHD RPOHAV POUT4-POUT0 B1ERS, B2ERS, LAISS, LCDS, LOFS, LOPS, LOSS, LRDIS, OOFS, PAISS, PRDIS
reset. Depends TCLK_N/P input.
reset. Depends TCLK_N/P input.
reset. Depends RXCLK input.
Outputs parity RXDATA[31:0].
reset. Depends TXCLK input. Input mode (undefined) Hi-Z Hi-Z Other than LOPS, OOFS LOPS, OOFS LOSS, OOFS, LOFS: Note LOPS, LCDS: B1ERS, B2ERS, LAISS, LRDIS, PAISS, PRDIS:
Undefined
Undefined
Note detection circuits LOS, OOF, reset when states LOSS, OOFS, LOFS pins depend input states line.
Data Sheet S14242EJ2V0DS
µPD98414
CONNECTION EXAMPLE MUX/DEMUX DEVICE
Recommended MUX/DEMUX device Connecting following DEMUX devices µPD98414 recommended: AMCC SONET/SDH OC-48 16:1 TRANSMITTER S3043 1:16 RECEIVER Clock Recovery S3044 S3040
µPD98414 (TX)
S3043
S3040 clock recovery
S3044 DEMUX
µPD98414 (RX)
(The S3040 unnecessary optical link module (OE) clock recovery function.) Circuit connection example Examples connecting AMCC's S3043 S3044 shown below. Figure 2-1. Example Connecting µPD98414 S3043 (Transmission Circuit)
S3043 (AMCC) (3.3 PIN[15:0]
µPD98414 (NEC)
TXPLD[15:0]
PCLK
TPCLK_P/N
PICLKN 0.01 REFCLK REFCLK 0.01
TCLK_P/N
Oscillator
PULSE READ
Data Sheet S14242EJ2V0DS
µPD98414
Figure 2-2. Example Connecting µPD98414 S3044 (Reception Circuit)
S3044 (AMCC)
µPD98414 (NEC)
OVREF
VREF1
VREF2
VREF3
POUT[15:0]
RXPLD[15:0]
POCLK
RCLK_P/N
Data Sheet S14242EJ2V0DS
µPD98414
ELECTRIC CHARACTERISTICS
When seeing "Absolute Maximum Ratings," "Recommended Operating Conditions," Characteristics," also "Pin Classifications" described below.
ABSOLUTE MAXIMUM RATINGS
Parameter Power supply voltage Input/output voltage Symbol VI1/VO1 VI2/VO2 VI3/VO3 Output current Operating ambient temperature Storage temperature Tstg LVTTL level LVTTL level, tolerant PECL-level Conditions Rating -0.5 +4.6 -0.5 +4.6 -0.5 +6.6 -0.5 +4.6 +150 Unit
Caution Absolute maximum ratings rated values beyond which physical damage will caused product; rated value parameters above table exceeded, even momentarily, quality product deteriorate. Always product within rated values.
RECOMMENDED OPERATING CONDITIONS
Parameter Power supply voltage Operating ambient temperature High-level input voltage Symbol VIH1 VIH2 VIH3 VIH4 Low-level input voltage VIL1 VIL2 VIL3 VIL4 VREF1-VREF3 input voltage PECL differential input voltage VIREF VIDFF PECL-level (differential) LVTTL-level LVTTL level, tolerant PECL-level (single-ended) PECL-level (differential) LVTTL-level LVTTL level, tolerant PECL-level (single-ended) PECL-level (differential) Conditions MIN. 3.135 VIREF 0.15 VDD-1.2 VDD-2.0 VDD/2-0.5 TYP. MAX. 3.465 VDD-0.55 VIREF-0.15 VDD-1.4 VDD/2+0.5 Unit
Caution Make sure that product air-cooled velocity least during operation.
Data Sheet S14242EJ2V0DS
µPD98414
CHARACTERISTICS -40°C +85°C, ±5%)
Parameter Off-state output current Input leakage current Low-level output current Symbol IOL1 IOL2 IOL3 IOL4 IOL5 High-level output current IOH1 IOH2 IOH3 IOH4 IOH5 Low-level output voltage VOL1 VOL2 VOL3 LVTTL level, tolerant LVTTL-level pin, LVTTL level, tolerant pin, PECL-level pin, When terminated shown Figure 2-1. LVTTL-level pin, LVTTL level, tolerant pin, PECL-level pin, When terminated shown Figure 2-1. Normal operation 0.37 LVTTL level, tolerant LVTTL-level Conditions LVTTL-level 0.45 MIN. TYP. MAX. Unit
High-level output voltage
VOH1 VOH2 VOH3
VDD-0.1 VDD-0.2 0.66 0.75
Supply current
1.05
CAPACITANCE
Parameter Output capacitance Input capacitance capacitance Symbol Conditions Frequency Frequency Frequency MIN. TYP. MAX. Unit
Data Sheet S14242EJ2V0DS
µPD98414
CLASSIFICATIONS Input pins
Category LVTTL-level VIH1 VIL1 LVTTL level tolerant VIH2 VIL2 3-state PECL-level (single-ended) VIH3 VIL3 PECL-level (differential) VIH4 VIL4 VIDFF RCLK_P, RCLK_N, TCLK_P, TCLK_N With pull-up With pull-down With pull-down TXPRTY PIN2 RXCLK, RXENB_B, RXDEL_B, TXCLK, TXDATA[31:0], TXENB_B, TXSEL_B, TXSOC PIN0, PIN1, TLAIS, TLRDI, TPAIS, TPOHAV, TPOHD, TPRDI, TSOHAV, TSOHD[3:0] MD15-MD0 BMODE, CS_B, DS_B/RD_B, MADD[7:0], RESET_B, RW/WR_B, JCK, JDI, JMS, JRST_B RXPLD[15:0] Applicable Pins Number Pins
Caution general-purpose input pins PIN2 PIN0, only PIN2 tolerant. Output pins
Category LVTTL-level VOL1/VOH1 IOL1/IOH1 Applicable Pins B1ERS, B2ERS, LAISS, LCDS, LOFS, LOPS, LOSS, LRDIS, OOFS, PAISS, POUT[4:0], PRDIS, RPOHAV, RPOHCK, RPOHD, RPOHFP, RSOHAV, RSOHCK, RSOHD[3:0], RSOHFP, TPOHCK, TPOHFP, TSOHCK, TSOHFP RCS, RXCLAV, RXDATA[31:0], RXPRTY, RXSOC, TCS, TXCLAV RXCLK_O, TXCLK_O ACK3S_B/RDY3S_B, ACK2S_B/RDY3S_B, PHINT_B, MD[15:0] (3-state) TXPLD[15:0] Number Pins
IOL2/IOH2 IOL3/IOH3 LVTTL level tolerant PECL-level (single-ended) PECL-level (differential) VOL2/VOH2 VOL3/VOH3 VOL3/VOH3 IOL4/IOH4 IOL5/IOH5
TPCLK_P, TPCLK_N
Data Sheet S14242EJ2V0DS
µPD98414
CHARACTERISTICS -40°C +85°C, ±5%)
Test Conditions Delay time definition
Input
Output
Load definition
D.U.T (Device under test)
RESET_B input
Parameter Symbol tWRST Conditions MIN. TYP. MAX. Unit
RESET_B pulse width
tWRST RESET_B
Data Sheet S14242EJ2V0DS
µPD98414
Management interface Write timing (BMODE
Parameter Address setup time (referred DS_B) CS_B setup time (referred DS_B) setup time (referred DS_B) Data setup time (referred DS_B) Address hold time (referred DS_B) CS_B hold time (referred DS_B) hold time (referred DS_B) Data hold time (referred DS_B) Delay from DS_B ACK2S_B output Delay from DS_B ACK3S_B output Delay from DS_B ACK2S_B float Delay from DS_B ACK3S_B float DS_B pulse width Minimum interval from DS_B DS_B Minimum interval from DS_B DS_B Symbol tSADDS tSCSDS tSRWDS tSDADS tHADDS tHCSDS tHRWDS tHDADS tVAK2W tVAK3W tIAK2W tVAK3W tWDS tDSINT1 tDSINT2 Load capacitance Note Load capacitance Note Note Conditions MIN. TYP. MAX. Unit
Note tDSINT2 minimum interval when following registers continuously accessed. shorter interval continuous access will cause ACK2S_B (ACK3S_B) output delay exceed maximum value tVAK2W (tVAK3W). tDSINT1 value when register other than following registers accessed, when following registers first accessed. Registers: RJ0ARR, RJ0APR, RJ0BRR, RJ0BPR, RJ1ARR, RJ1APR, RJ1BRR, RJ1BPR, TJ0ARR, TJ0APR, TJ0BRR, TJ0BPR, TJ1ARR, TJ1APR, TJ1BRR, TJ1BPR
MADD[7:0] tSADDS CS_B tSCSDS tHCSDS MD[15:0] tSDADS DS_B tWDS tDSINT1, tDSINT2 tSRWDS tHRWDS Data tHDADS tHADDS
ACK2S_B
tVAK2W tIAK2W
ACK3S_B tVAK3W tIAK3W
Data Sheet S14242EJ2V0DS
µPD98414
Write timing (BMODE
Parameter Address setup time (referred WR_B) CS_B setup time (referred WR_B) RD_B setup time (referred WR_B) Data setup time (referred WR_B) Address hold time (referred WR_B) CS_B hold time (referred WR_B) RD_B hold time (referred WR_B) Data hold time (referred WR_B) Delay from WR_B RDY2S_B output Delay from WR_B RDY3S_B output Delay from WR_B RDY2S_B float Delay from WR_B RDY3S_B float WR_B pulse width Minimum interval from WR_B WR_B Minimum interval from WR_B WR_B Symbol tSADWR tSCSWR tSRDWR tSDAWR tHADWR tHCSWR tHRDWR tHDAWR tVRY2W tVRY3W tIRY2W tIRY3W tWWR tWRINT1 tWRINT2 Load capacitance Note Load capacitance Note Note Conditions MIN. TYP. MAX. Unit
Note tWRINT2 minimum interval when following registers continuously accessed. shorter interval continuous access will cause RDY2S_B (RDY3S_B) output delay exceed maximum value tVRY2W (tVRY3W). tWRINT1 value when register other than following registers accessed, when following registers first accessed. Registers: RJ0ARR, RJ0APR, RJ0BRR, RJ0BPR, RJ1ARR, RJ1APR, RJ1BRR, RJ1BPR, TJ0ARR, TJ0APR, TJ0BRR, TJ0BPR, TJ1ARR, TJ1APR, TJ1BRR, TJ1BPR
MADD[7:0] tSADWR tSCSWR tHADWR tHCSWR
CS_B
MD[15:0] tWWR tSDAWR
Data tHDAWR tWRINT1, tWRINT2
WR_B
RD_B tSRDWR RDY2S_B tVRY2W tIRY2W RDY3S_B tVRY3W tIRY3W tHRDWR
Data Sheet S14242EJ2V0DS
µPD98414
Read timing (BMODE
Parameter Address setup time (referred DS_B) CS_B setup time (referred DS_B) setup time (referred DS_B) Address hold time (referred DS_B) CS_B hold time (referred DS_B) hold time (referred DS_B) Delay from DS_B ACK2S_B output Delay from DS_B ACK3S_B output Delay from DS_B data output Delay from DS_B ACK2S_B float Delay from DS_B ACK3S_B float Delay from DS_B data float Delay from ACK2S_B[ACK3S_B] data output DS_B pulse width Minimum interval from DS_B DS_B Minimum interval from DS_B DS_B Symbol tSADDS tSCSDS tSRWDS tHADDS tHCSDS tHRWDS tVAK2R tVAK3R tVDADS tIAK2R tIAK3R tIDADS tDDAAK tWDS tDSINT1 tDSINT2 Load capacitance Note Load capacitance Note Note Conditions MIN. TYP. MAX. Unit
Note tDSINT2 minimum interval when following registers continuously accessed. shorter interval continuous access will cause ACK2S_B (ACK3S_B) output delay exceed maximum value tVAK2R (tVAK3R). tDSINT1 value when register other than following registers accessed, when following registers first accessed. Registers: RJ0ARR, RJ0APR, RJ0BRR, RJ0BPR, RJ1ARR, RJ1APR, RJ1BRR, RJ1BPR, TJ0ARR, TJ0APR, TJ0BRR, TJ0BPR, TJ1ARR, TJ1APR, TJ1BRR, TJ1BPR
MADD[7:0] tSADDS CS_B tSCSDS MD[15:0] tVDADS DS_B tWDS tDSINT1, tDSINT2 tSRWDS ACK2S_B tVAK2R tIAK2R ACK3S_B tVAK3R tIAK3R tHRWDS Invalid data Valid data tDDAAK tIDADS tHCSDS tHADDS
Data Sheet S14242EJ2V0DS
µPD98414
Read timing (BMODE
Parameter Address setup time (referred RD_B) CS_B setup time (referred RD_B) WR_B setup time (referred RD_B) Address hold time (referred RD_B) CS_B hold time (referred RD_B) WR_B hold time (referred RD_B) Delay from RD_B RDY2S_B output Delay from RD_B RDY3S_B output Delay from RD_B data output Delay from RD_B RDY2S_B float Delay from RD_B RDY3S_B float Delay from RD_B data float Delay from RDY2S_B[RDY3S_B] data output RD_B pulse width Minimum interval from RD_B RD_B Minimum interval from RD_B RD_B Symbol tSADRD tSCSRD tSWRRD tHADRD tHCSRD tHWRRD tVRY2R tVRY3R tVDARD tIRY2R tIRY3R tIDARD tDDARY tWRD tRDINT1 tRDINT2 Load capacitance Note Load capacitance Note Note Conditions MIN. TYP. MAX. Unit
Note tRDINT2 minimum interval when following registers continuously accessed. shorter interval continuous access will cause RDY2S_B (RDY3S_B) output delay exceed maximum value tVRY2R (tVRY3R). tRDINT1 value when register other than following registers accessed, when following registers first accessed. Registers: RJ0ARR, RJ0APR, RJ0BRR, RJ0BPR, RJ1ARR, RJ1APR, RJ1BRR, RJ1BPR, TJ0ARR, TJ0APR, TJ0BRR, TJ0BPR, TJ1ARR, TJ1APR, TJ1BRR, TJ1BPR
MADD[7:0] tSADRD CS_B tSCSRD MD[15:0] tVDARD RD_B tWRD tDDARY tRDINT1, tRDINT2 WR_B tSWRRD RDY2S_B tVRY2R RDY3S_B tVRY3R tIRY3R tIRY2R Invalid data Valid data tIDARD tHCSRD tHADRD
tHWRRD
Data Sheet S14242EJ2V0DS
µPD98414
Overhead interface Insert
Parameter TSOHCK frequency TSOHCK cycle time Delay from TSOHCK TSOHFP output TSOHD setup time (referred TSOHCK) TSOHD hold time (referred TSOHCK) TSOHAV setup time (referred TSOHCK) TSOHAV hold time (referred TSOHCK) TPOHCK frequency TPOHCK cycle time Delay from TPOHCK TPOHFP output TPOHD setup time (referred TPOHCK) TPOHD hold time (referred TPOHCK) TPOHAV setup time (referred TPOHCK) TPOHAV hold time (referred TPOHCK) Symbol fWSCKT tWSCKT tDSHPT tSSHDT tHSHDT tSSHAT tHSHAT fWPCKT tWPCKT tDPHPT tSPHDT tHPHDT tSPHAT tHPHAT Note Note Load capacitance: Note Note Load capacitance: 1.74 Conditions MIN. TYP. 25.92 38.6 MAX. Unit
Note TSOHCK TPOHCK divided clocks TCLK_P/N. insert
TSOHCK tDSHPT TSOHFP tSSHDT TSOHD[3:0] tSSHAT TSOHAV tHSHAT tHSHDT tWSCKT tDSHPT
insert
TPOHCK tDPHPT TPOHFP tSPHDT TPOHD tSPHAT TPOHAV tHPHAT tHPHDT tWPCKT tDPHPT
Data Sheet S14242EJ2V0DS
µPD98414
Extract
Parameter RSOHCK frequency RSOHCK cycle time Delay from RSOHCK RSOHFP output Delay from RSOHCK RSOHDT output Delay from RSOHCK RSOHAV output RPOHCK frequency RPOHCK cycle time Delay from RPOHCK RPOHFP output Delay from RPOHCK RPOHDT output Delay from RPOHCK RPOHAV output Symbol fWSCKR tWSCKR tDSHPR tDSHDR tDSHAR fWPCKR tWPCKR tDPHPR tDPHDR tDPHAR Note Note Load capacitance: Load capacitance: Load capacitance: Note Note Load capacitance: Load capacitance: Load capacitance: 1.74 Conditions MIN. TYP. 25.92 38.6 MAX. Unit
Note RSOHCK RPOHCK divided clocks RCLK_P/N. extract
RSOHCK tDSHPR RSOHFP tDSHDR RSOHD tDSHAR RSOHAV tDSHAR tDSHDR tDSHPR tWSCKR
extract
RPOHCK tDPHPR RPOHFP tDPHDR RPOHD tDPHAR RPOHAV tDPHAR tDPHDR tDPHPR tWPCKR
Data Sheet S14242EJ2V0DS
µPD98414
Alayer interface Transmit Alayer interface
Parameter TXCLK frequency TXCLK cycle time TXCLK high level width TXCLK level width Delay from TXCLK TXCLK_O output Delay from TXCLK TXCLAV output TXDATA[31:0] setup time (referred TXCLK) TXDATA[31:0] hold time (referred TXCLK) TXSOC setup time (referred TXCLK) TXSOC hold time (referred TXCLK) TXPRTY setup time (referred TXCLK) TXPRTY hold time (referred TXCLK) TXENB_B setup time (referred TXCLK) TXENB_B hold time (referred TXCLK) TXSEL_B setup time (referred TXCLK) TXSEL_B hold time (referred TXCLK) Symbol fCYTK tCYTK tWTKH tWTKL tDTKO tDCATK tSDITK tHDITK tSSOTK tHSOTK tSPRTK tHPRTK tSENTK tHENTK tSSLTK tHSLTK Load capacitance: pF,Note Load capacitance: Conditions MIN. TYP. MAX. Unit
Note TXCLK_O logic inversion output TXCLK.
tCYTK tWTKL TXCLK tWTKH
TXCLK_O tDTKO TXCLAV tDCATK tDCATK TXENB_B tSENTK tHENTK
TXSEL_B tSSOTK TXSOC_B tHSOTK tSSLTK tHSLTK
TXDATA[31:0] tSDITK TXPRTY tSPRTK tHPRTK tHDITK
Data Sheet S14242EJ2V0DS
µPD98414
Recieve Alayer interface
Parameter RXCLK frequency RXCLK cycle time RXCLK high level width RXCLK level width Delay from RXCLK RXCLK_O output Delay from RXCLK RXCLAV output Delay from RXCLK RXDATA[31:0] output Delay from RXCLK RXSOC output Delay from RXCLK RXPRTY output RXENB_B setup time (referred RXCLK) RXENB_B hold time (referred RXCLK) RXSEL_B setup time (referred RXCLK) RXSEL_B hold time (referred TXCLK) Symbol fCYRK tCYRK tWRKH tWRKL tDRKO tDCARK tDDORK tDSORK tDPRRK tSENRK tHENRK tSSLRK tHSLRK Load capacitance: pF,Note Load capacitance: Load capacitance: Load capacitance: Load capacitance: Conditions MIN. TYP. MAX. Unit
Note RXCLK_O logic inversion output RXCLK.
tCYRK tWRKH RXCLK tWRKL
RXCLK_O tDRKO RXCLAV tDCARK RXENB_B tSENRK RXSEL_B tSSLRK RXSOC_B tDSORK RXDATA[31:0] tDDORK RXPRTY tDPRRK tDPRRK tDDORK tDSORK tHSLRK tHENRK tDCARK
Data Sheet S14242EJ2V0DS
µPD98414
Line interface
Parameter TCLK_P[TCLK_N] frequency TCLK_P[TCLK_N] cycle time TCLK_P[TCLK_N] high level width TCLK_P[TCLK_N] level width RCLK_P[RCLK_N] frequency RCLK_P[RCLK_N] cycle time RCLK_P[RCLK_N] high level width RCLK_P[RCLK_N] level width Delay from TCLK_P TXPLD[15:0] Delay from TCLK_P[TCLK_N] TPCLK_P[TPCLK_N] RXPLD[15:0] setup time (referred RXCLK) RXPLD[15:0] hold time (referred RXCLK) Symbol fCYTC tCYTC tWTCH tWTCL fCYRC tCYRC tWRCH tWRCL tDTDO tDTPCO tSRDI tHRDI Note 155.52 6.43 Conditions MIN. TYP. 155.52 6.43 MAX. Unit
Note TPCLK_P, TPCLK_N logic inversion outputs TCLK_P, TCLK_N.
tCYTC tWTCL TCLK_P tWTCH
TXPLD[15:0] tDTDO TPCLK_P tDTPCO
TCLK_P (TCLK_N)
TPCLK_P (TPCLK_N) tDTPCO tCYRC tWRCL RCLK_P tWRCH
RXPLD[15:0] tSRDI tHRDI
Data Sheet S14242EJ2V0DS
µPD98414
JTAG boundary scan
Parameter cycle time high level width level width setup time hold time setup time hold time Capture_DR data input setup time Capture_DR data input hold time Delay from Date_DR output Delay from JRST_B level width Symbol tCYJCK tJCKH tJCKL tSJMS tHJMS tSJDI tHJDI tSJIN tHJIN tDJOUT tDJDO tJRSTL Conditions MIN. tCYJCK TYP. MAX. Unit
tCYJCK tJCKH tJRSTL JRST_B tSJMS tSJDI tDJDO tSJIN input tDJOUT output tHJIN tHJDI tHJMS tJCKL
Data Sheet S14242EJ2V0DS
µPD98414
PACKAGE DRAWING
352-PIN PLASTIC (CAVITY DOWN ADVANCED TYPE) (35x35)
Index area C1.25
3-C0.5
352-
detail part
ITEM
MILLIMETERS 35.00±0.20 35.00±0.20 1.27 1.50±0.30 0.60±0.10 0.90 0.25 MIN. 0.75±0.15 0.30 0.15 0.20 1.625 1.625 P352F2-127-RN1-1
Data Sheet S14242EJ2V0DS
µPD98414
RECOMMENDED SOLDERING CONDITIONS
conditions listed below shall when soldering µPD98414. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). Please consult with sales offices case other soldering process used, case soldering done under different conditions. Surface-Mount Type µPD98414F2-RN1: 352-pin plastic (cavity down advanced type)
Soldering Process Infrared reflow Soldering Conditions Peak package's surface temperature: 220°C Reflow time: seconds less (210°C more) Maximum allowable number reflow processes: Exposure limit: days <Caution> Non-heat-resistant trays, such magazine taping trays, cannot baked before unpacking.
Note
Symbol IR20-202-2
hours pre-baking required 125°C afterward)
Note Maximum number days during which product stored temperature 25°C relative humidity less after dry-pack package opened.
Data Sheet S14242EJ2V0DS
µPD98414
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet S14242EJ2V0DS
µPD98414
NEASCOT-P70 trademark Corporation.
information this document current July, 2001. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

µPD98414 Gbps ASONET FRAMER µPD98414 (NEASCOT-P70) ALSIs pro

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