µPD98412 1.5G ASWITCH DESCRIPTION µPD98412 (NEASCOT-X15

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µPD98412 1.5G ASWITCH DESCRIPTION µPD98412 (NEASCOT-X15

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INTEGRATED CIRCUIT
µPD98412
1.5G ASWITCH
DESCRIPTION
µPD98412 (NEASCOT-X15) integrating Aswitch functions single chip. UTOPIA Level2 interfaces switch circuits connecting multiple devices. This employs shared buffer non-blocking type switch realizes switch capacity 1.5G using externally connected SRAM buffering cells. detailed description functions controller, refer following User's Manual:
µPD98412 User's Manual: S14169E
FEATURES
Conforms AFORUM Version Traffic Management Realizes switch functions with single chip Non-blocking type with switch capacity 1.5G UTOPIA Level2 interface allowing select widths ports bits, ports bits port bits, ports bits) Various polling modes UTOPIA Level2 interface switch logical ports Multi-speed (622M bps, 155M bps, bps, bps, etc.) Microprocessor connecting port signaling processing cell processing Supports 16K/32K/64K uni-cast VP/VC 1K/2K/4K multi-cast VP/VC Shared buffer architecture using standard SRAM Cell buffer capacity: 12.8K/25.6K/51.2K cells Supports four classes (CBR, VBR, ABR, UBR) traffic control (binary mode) Supports (Early Packet Discard) (Partial Packet Discard) +3.3-V single power source (directly connectable with +5-V level signals) Test function: Supports JTAG (IEEE 1149.1) Remark Active pins indicated (symbol_B after names) this document.
ORDERING INFORMATION
Part Number Package 576-pin tape
µPD98412N7-H6
information this document subject change without notice. Before using this document, please confirm that this latest version.
devices/types available every country. Please check with local representative availability additional information.
Document S14237EJ2V0DSJ1 (2nd edition) Date Published October 2000 CP(K) Printed Japan
mark
shows major revised points.
1999
µPD98412
EXAMPLE SYSTEM CONFIGURATION (APPLICATION)
µPD98412 used realize Alayer cell switching function connecting microprocessor, SRAM cell buffer, header translation table (HTT)/SRAM storing control information shown below.
16-bit
Microprocesser
16-bit
UTOPIA level
Logical inport
UTOPIA level
Physical inport
Physical outport
Logical outport
PD98412 NEASCOT/X15
8-bit
UTOPIA level
8-bit
UTOPIA level
32-bit +parity control memory
92-bit
Cell buffer (Memory HTT: Header Translation Table
Data Sheet S14237EJ2V0DS00
µPD98412
BLOCK DIAGRAM
Cell Buffer Memory
UTOPIA receive port
Output payload selector
Input payload separator
Cell buffer interface
UTOPIA transmit port
Input port interface
Input header selector
Queue controller
Output header selector
UTOPIA receive port
Output interface
UTOPIA receive port
UTOPIA transmit port
UTOPIA transmit port
Test interface
UTOPIA receive port
Microprocessor interface
Control memory interface
Output arbiter
UTOPIA transmit port
Microprocessor
Control Memory
TEST
Data Sheet S14237EJ2V0DS00
µPD98412
CONFIGURATION
8-bit 12-PHY polling mode/15-PHY polling mode
Control Memory Interface
RESET_B SWCLK HTWE_B [31:0] [3:0] HTOE_B
Control
Microprocessor Interface
[31:0] UWE_B R/W_B MCS_B IOCS_B
HTCS_B [1:0] [17:0]
JTAG JRST_B
RDY_B HCLK
RXDATA3 [7:0] UCLK3 RXENB3_B RXSOC3 UTOPIA Interface RXCLAV3 RXADDR3 [3:0] TXADDR3 [3:0] TXCLAV3 TXSOC3 TXENB3_B TXDATA3 [7:0]
TXDATA2 [7:0] TXENB2_B TXSOC2 TXCLAV2 TXADDR2 [3:0] RXADDR2 [3:0] RXCLAV2
UTOPIA Interface
NEASCOT-X15 PD98412
RXSOC2 RXENB2_B UCLK2 RXDATA2 [7:0]
RXDATA1 [7:0] UCLK1 RXENB1_B RXSOC1 RXCLAV1 RXADDR1 [3:0] TXADDR1 [3:0] TXCLAV1
CBCS_B [1:0] CBWE_B CBOE_B [17:0] [91:0]
TXDATA0 [7:0] TXENB0_B TXSOC0 TXCLAV0 TXADDR0 [3:0] RXADDR0 [3:0] RXCLAV0 RXSOC0 RXENB0_B UCLK0 RXDATA0 [7:0]
UTOPIA Interface
UTOPIA Interface
TXSOC1 TXENB1_B TXDATA1 [7:0]
Cell Buffer Interface
Data Sheet S14237EJ2V0DS00
µPD98412
16-bit multiplexed status polling mode
Control Memory Interface
RESET_B SWCLK HTWE_B [31:0] [3:0] HTOE_B
Control
Microprocessor Interface
[31:0] UWE_B R/W_B MCS_B IOCS_B
HTCS_B [1:0] [17:0]
JTAG JRST_B
RDY_B HCLK
NEASCOT-X15 PD98412
RXDATA1 [15:0] UCLK1 RXENB1_B RXSOC1 RXCLAV1 RXADDR1 [4:0] TXADDR1 [4:0] TXCLAV1
CBCS_B [1:0] CBWE_B CBOE_B [17:0] [91:0]
TXDATA0 [15:0] TXENB0_B TXSOC0 TXCLAV0 TXADDR0 [4:0] RXADDR0 [4:0] RXCLAV0 RXSOC0 RXENB0_B UCLK0 RXDATA0 [15:0]
UTOPIA Interface
UTOPIA Interface
TXSOC1 TXENB1_B TXDATA1 [15:0]
Cell Buffer Interface
Data Sheet S14237EJ2V0DS00
µPD98412
16-bit 2-group weighted polling mode
Control Memory Interface
Control
Microprocessor Interface
RESET_B SWCLK
[31:0] [3:0]
HTOE_B
HTWE_B
HTCS_B [1:0] [17:0]
[31:0] UWE_B
R/W_B MCS_B
JTAG JRST_B
IOCS_B
RDY_B HCLK
Group
RXENB1A_B RXDATA1 [15:0] UCLK1 RXSOC1
TXENB0A_B TXDATA0 [15:0] TXSOC0 TXCLAV0B TXADDR0B [3:0] TXENB0B_B
UTOPIA Interace
Group Group Group
Group UTOPIA Interace
RXCLAV1A RXADDR1A [3:0]
TXCLAV0A TXADDR0A [3:0]
Group
RXCLAV1B RXADDR1B [3:0] RXENB1B_B
NEASCOT-X15 PD98412
RXADDR0A [3:0] RXCLAV0A RXENB0A_B RXSOC0 UCLK0 RXDATA0 [15:0] RXADDR0B [3:0] RXCLAV0B RXENB0B_B
TXADDR1A [3:0] TXCLAV1A TXENB1A_B TXSOC1 TXDATA1 [15:0] TXADDR1B [3:0] TXCLAV1B TXENB1B_B
Group
Group
CBCS_B [1:0] CBWE_B
Cell Buffer Interface
Data Sheet S14237EJ2V0DS00
CBOE_B [17:0] [91:0]
µPD98412
16-bit 1-group weighted polling mode
Control Memory Interface
RESET_B SWCLK HTWE_B [31:0] [3:0] HTOE_B
Control
Microprocessor Interface
[31:0] UWE_B R/W_B MCS_B IOCS_B
HTCS_B [1:0] [17:0]
JTAG JRST_B
RDY_B HCLK
NEASCOT-X15 PD98412
RXDATA1 [15:0] UCLK1 RXENB1_B RXSOC1 RXCLAV1 [3:0] RXADDR1 [4:0] TXADDR1 [4:0] TXCLAV1 [3:0]
CBCS_B [1:0] CBWE_B CBOE_B [17:0] [91:0]
TXDATA0 [15:0] TXENB0_B TXSOC0 TXCLAV0 [3:0] TXADDR0 [4:0] RXADDR0 [4:0] RXCLAV0 [3:0] RXSOC0 RXENB0_B UCLK0 RXDATA0 [15:0]
UTOPIA Interface
UTOPIA Interface
TXSOC1 TXENB1_B TXDATA1 [15:0]
Cell Buffer Interface
Data Sheet S14237EJ2V0DS00
µPD98412
CONFIGURATION (BOTTOM VIEW)
576-pin tape
µPD98412N7-H6
Note
Index area
Note index area shown View.
Data Sheet S14237EJ2V0DS00
µPD98412
NAME Power Supply Voltage Ground JTAG JTAG Data Input JTAG Data Output JTAG Data Clock JTAG Mode Select JTAG Reset
Memory Interface Memory Address Memory Data Memory Data Parity Memory Write Enable Memory Output Enable Cell Buffer Memory Address Cell Buffer Memory Data Cell Buffer Memory Write Enable Cell Buffer Memory Output Enable
HTA17 HTA0 HTD31 HTD0 HTP3 HTP0 HTWE_B HTOE_B CBA17 CBA0 CBD91 CBD0 CBWE_B CBOE_B Interface
JRST_B Other
HTCS1_B, HTCS0_B Memory Chip Select
SWCLK RESET_B
System Clock Hardware Reset Internal Connected Connect Ground Pull-up
CBCS1_B, CBCS0_B: Cell Buffer Memory Chip Select
IOCS_B MCS_B RDY_B HCLK R/W_B UWE_B
Chip Select Memory Chip Select Ready, Memory Ready Interrupt Request Host Clock Read/Write Upper Word Enable
AD31 AD00 Address Data
Data Sheet S14237EJ2V0DS00
µPD98412
UTOPIA
8-bit 12-PHY Polling Mode/15-PHY Polling Mode UCLK0 RXADDR03-RXADDR00 RXSOC0 RXENB0_B RXCLAV0 TXADDR03-TXADDR00 TXSOC0 TXENB0_B TXCLAV0 UCLK1 RXADDR13-RXADDR10 RXSOC1 RXENB1_B RXCLAV1 TXADDR13-TXADDR10 TXSOC1 TXENB1_B TXCLAV1 UCLK2 RXADDR23-RXADDR20 RXSOC2 RXENB2_B RXCLAV2 TXADDR23-TXADDR20 TXSOC2 TXENB2_B TXCLAV2 UCLK3 UTOPIA Clock Receive Address Receive Start Cell Receive Enable Data Transfers Receive Cell Buffer Available Transmit Address Transmit Start Cell Transmit Enable Data Transfers Transmit Cell Buffer Available UTOPIA Clock Receive Address Receive Start Cell Receive Enable Data Transfers Receive Cell Buffer Available Transmit Address TXADDR04-TXADDR00 TXSOC0 TXENB0_B Transmit Start Cell Transmit Enable Data Transfers Transmit Cell Buffer Available UTOPIA Clock Receive Address Receive Start Cell Receive Enable Data Transfers Receive Cell Buffer Available Transmit Address TXADDR14-TXADDR10 TXSOC1 TXENB1_B Transmit Start Cell Transmit Enable Data Transfers Transmit Cell Buffer Available UTOPIA Clock TXDATA207-TXDATA200 Transmit Data UCLK1 RXADDR14-RXADDR10 RXSOC1 RXENB1_B TXDATA107-TXDATA100 Transmit Data 16-bit Multiplexed Status Polling Mode UCLK0 RXADDR04-RXADDR00 RXSOC0 RXENB0_B UTOPIA Clock Receive Address Receive Start Cell Receive Enable Data Transfers RXCLAV0[3]-RXCLAV0[0] Receive Cell Buffer Available Transmit Address Transmit Start Cell Transmit Enable Data Transfers TXCLAV0[3]-TXCLAV0[0] Transmit Cell Buffer Available UTOPIA Clock Receive Address Receive Start Cell Receive Enable Data Transfers RXCLAV1[3]-RXCLAV1[0] Receive Cell Buffer Available Transmit Address Transmit Start Cell Transmit Enable Data Available TXDATA115-TXDATA100 Transmit Data TXDATA015-TXDATA000 Transmit Data TXCLAV3 TXDATA007-TXDATA000 Transmit Data TXADDR33-TXADDR30 TXSOC3 TXENB3_B RXCLAV3 RXADDR33-RXADDR30 RXSOC3 RXENB3_B Receive Address Receive Start Cell Receive Enable Data Transfers Receive Cell Buffer Available Transmit Address Transmit Start Cell Transmit Enable Data Transfers Transmit Cell Buffer Available TXDATA307-TXDATA300 Transmit Data RXDATA307-RXDATA300 Receive Data
RXDATA007-RXDATA000 Receive Data
RXDATA107-RXDATA100 Receive Data
RXDATA015-RXDATA000 Receive Data
RXDATA207-RXDATA200 Receive Data
RXDATA115-RXDATA100 Receive Data
TXCLAV1[3]-TXCLAV1[0] Transmit Cell Buffer
Data Sheet S14237EJ2V0DS00
µPD98412
16-bit 2-Group Weighted Polling Mode UCLK0 UTOPIA Clock RXADDR0A3-RXADDR0A0 Receive Address RXADDR0B3-RXADDR0B0 Receive Address RXDATA015-RXDATA000 Receive Data RXSOC0 Receive Start Cell RXENB0A_B, RXENB0B_B Receive Enable Data Transfers RXCLAV0A, RXCLAV0B Receive Cell Buffer Available TXADDR0A3-TXADDR0A0 Transmit Address TXADDR0B3-TXADDR0B0 Transmit Address TXDATA015-TXDATA000 TXSOC0 Transmit Data Transmit Start Cell TXCLAV0 UCLK1 RXADDR14-RXADDR10 RXSOC1 RXENB1_B RXCLAV1 TXADDR14-TXADDR10 TXSOC1 TXENB1_B TXCLAV1 Transfers TXCLAV0A, TXCLAV0B UCLK1 Transmit Cell Buffer Available UTOPIA Clock RXADDR1A3-RXADDR1A0 Receive Address RXADDR1B3-RXADDR1B0 Receive Address RXDATA115-RXDATA100 Receive Data RXSOC1 Receive Start Cell RXENB1A_B, RXENB1B_B Receive Enable Data Transfers RXCLAV1A, RXCLAV1B Receive Cell Buffer Available TXADDR1A3-TXADDR1A0 Transmit Address TXADDR1B3-TXADDR1B0 Transmit Address TXDATA115-TXDATA100 TXSOC1 Transmit Data Transmit Start Cell Transfers TXCLAV1A, TXCLAV1B Transmit Cell Buffer Available TXADDR04-TXADDR00 TXSOC0 TXENB0_B 16-bit 1-Group Weighted Polling Mode UCLK0 RXADDR04-RXADDR00 RXSOC0 RXENB0_B RXCLAV0 UTOPIA Clock Receive Address Receive Start Cell Receive Enable Data Transfers Receive Cell Buffer Available Transmit Address Transmit Start Cell Transmit Enable Data Transfers Transmit Cell Buffer Available UTOPIA Clock Receive Address Receive Start Cell Receive Enable Data Transfers Receive Cell Buffer Available Transmit Address Transmit Start Cell Transmit Enable Data Transfers Transmit Cell Buffer Available TXDATA115-TXDATA100 Transmit Data TXDATA015-TXDATA000 Transmit Data
RXDATA015-RXDATA000 Receive Data
TXENB0A_B, TXENB0B_B Transmit Enable Data
RXDATA115-RXDATA100 Receive Data
TXENB1A_B, TXENB1B_B Transmit Enable Data
Data Sheet S14237EJ2V0DS00
µPD98412
LAYOUT
(1/15)
Address AA01 AB01 AC01 AD01 AE01 AF01 AG01 AH01 AJ01 AK01 AK02 AK03 AK04 AK05 AK06 AK07 AK08 AK09 AK10 AK11 12-PHY Polling Mode/ 15-PHY Polling Mode AD30 AD24 AD20 AD16 AD10 AD06 AD01 HTA17 HTA13 HTA09 HTA06 HTA02 HTCS0_B HTD31 HTD29 HTD24 HTD21 HTD17 HTP1 HTD06 HTD05 HTD01 RXDATA307 RXDATA301 RXCLAV3 TXADDR33 Multiplexed Status Polling Mode RXDATA115 RXDATA109 RXCLAV1[2] 2-Group Weighted Polling Mode RXDATA115 RXDATA109 RXCLAV1B TXADDR1B3 1-Group Weighted Polling Mode RXDATA115 RXDATA109
Data Sheet S14237EJ2V0DS00
µPD98412
(2/15)
Address AK12 AK13 AK14 AK15 AK16 AK17 AK18 AK19 AK20 AK21 AK22 AK23 AK24 AK25 AK26 AK27 AK28 AK29 AK30 AJ30 AH30 AG30 AF30 AE30 AD30 AC30 AB30 AA30 12-PHY Polling Mode/ 15-PHY Polling Mode TXDATA307 TXDATA304 TXDATA300 RXDATA104 RXDATA100 UCLK1 RXCLAV1 RXADDR12 TXADDR12 TXCLAV1 TXDATA107 TXDATA103 CBD87 CBD84 CBD77 CBD68 CBD64 CBD58 CBD54 CBD49 CBD47 CBCS1_B CBA17 CBA14 CBA10 CBA06 CBA02 CBA00 CBD39 CBD35 Multiplexed Status Polling Mode TXCLAV1[3] TXDATA115 TXDATA112 TXDATA108 RXDATA104 RXDATA100 UCLK1 RXCLAV1[0] RXADDR12 TXADDR12 TXCLAV1[0] TXDATA107 TXDATA103 2-Group Weighted Polling Mode TXDATA115 TXDATA112 TXDATA108 RXDATA104 RXDATA100 UCLK1 RXCLAV1A RXADDR1A2 TXADDR1A2 TXCLAV1A TXDATA107 TXDATA103 1-Group Weighted Polling Mode TXDATA115 TXDATA112 TXDATA108 RXDATA104 RXDATA100 UCLK1 RXCLAV1 RXADDR12 TXADDR12 TXCLAV1 TXDATA107 TXDATA103
Data Sheet S14237EJ2V0DS00
µPD98412
(3/15)
Address 12-PHY Polling Mode/ 15-PHY Polling Mode CBD29 CBD25 CBD18 CBD11 CBD05 CBD01 RXDATA005 RXDATA003 RXCLAV0 TXADDR03 TXADDR01 TXSOC0 TXDATA005 TXDATA001 RXDATA205 RXDATA201 RXENB2_B RXCLAV2 RXADDR21 TXADDR22 TXCLAV2 TXDATA203 R/W_B UWE_B AD29 AD27 AD19 Multiplexed Status Polling Mode RXDATA005 RXDATA003 RXCLAV0[0] TXADDR03 TXADDR01 TXSOC0 TXDATA005 TXDATA001 RXDATA013 RXDATA009 RXCLAV0[2] TXCLAV0[2] TXDATA011 2-Group Weighted Polling Mode RXDATA005 RXDATA003 RXCLAV0A TXADDR03 TXADDR01 TXSOC0 TXDATA005 TXDATA001 RXDATA013 RXDATA009 RXENB0B_B RXCLAV0B RXADDR0B1 TXADDR0B2 TXCLAV0B TXDATA011 1-Group Weighted Polling Mode RXDATA005 RXDATA003 RXCLAV0 TXADDR03 TXADDR01 TXSOC0 TXDATA005 TXDATA001 RXDATA013 RXDATA009 TXDATA011
Data Sheet S14237EJ2V0DS00
µPD98412
(4/15)
Address AA02 AB02 AC02 AD02 AE02 AF02 AG02 AH02 AJ02 AJ03 AJ04 AJ05 AJ06 AJ07 AJ08 AJ09 AJ10 AJ11 AJ12 AJ13 AJ14 AJ15 AJ16 AJ17 AJ18 12-PHY Polling Mode/ 15-PHY Polling Mode AD15 AD11 AD09 AD05 AD04 AD00 HTA14 HTA10 HTA05 HTA01 HTWE_B HTD30 HTD26 HTD25 HTD22 HTD20 HTD16 HTD13 HTD10 HTD07 HTD02 CBD91 RXDATA306 RXDATA302 RXDATA300 RXENB3_B RXADDR30 TXADDR30 TXENB3_B TXDATA303 RXDATA107 RXDATA103 Multiplexed Status Polling Mode RXDATA114 RXDATA110 RXDATA108 RXADDR14 TXADDR14 TXDATA111 RXDATA107 RXDATA103 2-Group Weighted Polling Mode RXDATA114 RXDATA110 RXDATA108 RXENB1B_B RXADDR1B0 TXADDR1B0 TXENB1B_B TXDATA111 RXDATA107 RXDATA103 1-Group Weighted Polling Mode RXDATA114 RXDATA110 RXDATA108 RXADDR14 TXADDR14 TXDATA111 RXDATA107 RXDATA103
Data Sheet S14237EJ2V0DS00
µPD98412
(5/15)
Address AJ19 AJ20 AJ21 AJ22 AJ23 AJ24 AJ25 AJ26 AJ27 AJ28 AJ29 AH29 AG29 AF29 AE29 AD29 AC29 AB29 AA29 12-PHY Polling Mode/ 15-PHY Polling Mode TXADDR13 TXADDR10 TXENB1_B TXDATA104 TXDATA101 CBD85 CBD80 CBD76 CBD74 CBD67 CBD63 CBD59 CBD57 CBD53 CBD52 CBD48 CBD44 CBOE_B CBA13 CBA09 CBA05 CBA01 CBD41 CBD40 CBD36 CBD34 CBD30 CBD26 CBD23 CBD19 CBD14 CBD10 CBD08 CBD02 Multiplexed Status Polling Mode TXADDR13 TXADDR10 TXENB1_B TXDATA104 TXDATA101 2-Group Weighted Polling Mode TXADDR1A3 TXADDR1A0 TXENB1A_B TXDATA104 TXDATA101 1-Group Weighted Polling Mode TXADDR13 TXADDR10 TXENB1_B TXDATA104 TXDATA101
Data Sheet S14237EJ2V0DS00
µPD98412
(6/15)
Address 12-PHY Polling Mode/ 15-PHY Polling Mode CBD00 RXDATA004 RXDATA000 RXENB0_B RXADDR03 RXADDR02 TXADDR02 TXCLAV0 TXDATA006 TXDATA002 TXDATA000 RXDATA204 RXDATA200 RXSOC2 TXADDR23 TXENB2_B TXDATA204 TXDATA200 IOCS_B AD28 AD26 AD22 AD18 AD14 AD08 HTA15 HTA11 HTA07 HTA03 HTA00 HTOE_B Multiplexed Status Polling Mode RXDATA004 RXDATA000 RXENB0_B RXADDR03 RXADDR02 TXADDR02 TXCLAV0[0] TXDATA006 TXDATA002 TXDATA000 RXDATA012 RXDATA008 RXLLAV0[3] TXCLAV0[3] TXDATA012 TXDATA008 2-Group Weighted Polling Mode RXDATA004 RXDATA000 RXENB0A_B RXADDR0A3 RXADDR0A2 TXADDR0A2 TXCLAV0A TXDATA006 TXDATA002 TXDATA000 RXDATA012 RXDATA008 TXADDR0B3 TXENB0B_B TXDATA012 TXDATA008 1-Group Weighted Polling Mode RXDATA004 RXDATA000 RXENB0_B RXADDR03 RXADDR02 TXADDR02 TXCLAV0 TXDATA006 TXDATA002 TXDATA000 RXDATA012 RXDATA008 TXDATA012 TXDATA008
Data Sheet S14237EJ2V0DS00
µPD98412
(7/15)
Address AA03 AB03 AC03 AD03 AE03 AF03 AG03 AH03 AH04 AH05 AH06 AH07 AH08 AH09 AH10 AH11 AH12 AH13 AH14 AH15 AH16 AH17 AH18 AH19 AH20 AH21 AH22 AH23 AH24 AH25 AH26 AH27 AH28 AG28 AF28 AE28 AD28 AC28 12-PHY Polling Mode/ 15-PHY Polling Mode HTD23 HTD14 HTD11 HTP0 HTD03 HTD00 CBD90 RXDATA305 RXSOC3 RXADDR31 TXADDR31 TXSOC3 TXDATA305 TXDATA301 RXDATA106 RXDATA102 RXADDR13 RXADDR10 TXADDR11 TXSOC1 TXDATA105 TXDATA102 CBD86 CBD81 CBD79 CBD75 CBD73 CBD69 CBD66 CBD62 Multiplexed Status Polling Mode RXDATA113 RXCLAV1[3] TXDATA113 TXDATA109 RXDATA106 RXDATA102 RXADDR13 RXADDR10 TXADDR11 TXSOC1 TXDATA105 TXDATA102 2-Group Weighted Polling Mode RXDATA113 RXADDR1B1 TXADDR1B1 TXDATA113 TXDATA109 RXDATA106 RXDATA102 RXADDR1A3 RXADDR1A0 TXADDR1A1 TXSOC1 TXDATA105 TXDATA102 1-Group Weighted Polling Mode RXDATA113 TXDATA113 TXDATA109 RXDATA106 RXDATA102 RXADDR13 RXADDR10 TXADDR11 TXSOC1 TXDATA105 TXDATA102
Data Sheet S14237EJ2V0DS00
µPD98412
(8/15)
Address AB28 AA28 12-PHY Polling Mode/ 15-PHY Polling Mode CBD56 CBD45 CBWE_B CBA15 CBA11 CBA08 CBA04 CBD37 CBD31 CBD27 CBD24 CBD20 CBD15 CBD13 CBD09 CBD07 CBD03 RXDATA007 RXSOC0 TXDATA007 TXDATA003 RXDATA206 RXADDR20 TXADDR20 TXSOC2 TXDATA205 TXDATA201 Multiplexed Status Polling Mode RXDATA007 RXSOC0 TXCLAV0[1] TXDATA007 TXDATA003 RXDATA014 RXADDR04 TXADDR04 TXDATA013 TXDATA009 2-Group Weighted Polling Mode RXDATA007 RXSOC0 TXDATA007 TXDATA003 RXDATA014 RXADDR0B0 TXADDR0B0 TXDATA013 TXDATA009 1-Group Weighted Polling Mode RXDATA007 RXSOC0 TXDATA007 TXDATA003 RXDATA014 RXADDR04 TXADDR04 TXDATA013 TXDATA009
Data Sheet S14237EJ2V0DS00
µPD98412
(9/15)
Address AA04 AB04 AC04 AD04 AE04 AF04 AG04 AG05 AG06 AG07 AG08 AG09 AG10 AG11 AG12 AG13 AG14 AG15 AG16 12-PHY Polling Mode/ 15-PHY Polling Mode RDY_B AD25 AD17 AD07 HTA16 HTA12 HTA08 HTA04 HTP3 HTP2 HTD15 HTD12 HTD08 HTD04 RESET_B CBD89 JRST_B UCLK3 RXADDR32 TXADDR32 TXCLAV3 TXDATA306 TXDATA302 Multiplexed Status Polling Mode TXCLAV1[2] TXDATA114 TXDATA110 2-Group Weighted Polling Mode RXADDR1B2 TXADDR1B2 TXCLAV1B TXDATA114 TXDATA110 1-Group Weighted Polling Mode TXDATA114 TXDATA110
Data Sheet S14237EJ2V0DS00
µPD98412
(10/15)
Address AG17 AG18 AG19 AG20 AG21 AG22 AG23 AG24 AG25 AG26 AG27 AF27 AE27 AD27 AC27 AB27 AA27 12-PHY Polling Mode/ 15-PHY Polling Mode RXDATA101 RXENB1_B RXADDR11 TXDATA106 CBD82 CBD72 CBD70 CBD65 CBD55 CBD46 CBCS0_B CBA16 CBA12 CBA03 CBD38 CBD28 CBD21 CBD16 CBD06 RXDATA006 UCLK0 Multiplexed Status Polling Mode RXDATA101 RXENB1_B RXADDR11 TXDATA106 RXDATA006 UCLK0 RXCLAV0[1] 2-Group Weighted Polling Mode RXDATA101 RXENB1A_B RXADDR1A1 TXDATA106 RXDATA006 UCLK0 1-Group Weighted Polling Mode RXDATA101 RXENB1_B RXADDR11 TXDATA106 RXDATA006 UCLK0
Data Sheet S14237EJ2V0DS00
µPD98412
(11/15)
Address AA05 AB05 AC05 AD05 AE05 AF05 AF06 AF07 12-PHY Polling Mode/ 15-PHY Polling Mode TXADDR00 TXENB0_B TXDATA004 RXDATA207 UCLK2 RXADDR23 TXADDR21 TXDATA206 TXDATA202 AD31 AD21 AD12 AD02 HTCS1_B HTD28 HTD19 SWCLK CBD88 Multiplexed Status Polling Mode TXADDR00 TXENB0_B TXDATA004 RXDATA015 TXDATA014 TXDATA010 2-Group Weighted Polling Mode TXADDR0A0 TXENB0A_B TXDATA004 RXDATA015 RXADDR0B3 TXADDR0B1 TXDATA014 TXDATA010 1-Group Weighted Polling Mode TXADDR00 TXENB0_B TXDATA004 RXDATA015 TXDATA014 TXDATA010
Data Sheet S14237EJ2V0DS00
µPD98412
(12/15)
Address AF08 AF09 AF10 AF11 AF12 AF13 AF14 AF15 AF16 AF17 AF18 AF19 AF20 AF21 AF22 AF23 AF24 AF25 AF26 AE26 AD26 AC26 AB26 AA26 12-PHY Polling Mode/ 15-PHY Polling Mode RXDATA303 RXDATA105 RXSOC1 CBD83 CBD60 CBD50 CBA07 CBD43 CBD33 CBD17 Multiplexed Status Polling Mode RXDATA111 RXDATA105 RXSOC1 2-Group Weighted Polling Mode RXDATA111 RXDATA105 RXSOC1 1-Group Weighted Polling Mode RXDATA111 RXDATA105 RXSOC1
Data Sheet S14237EJ2V0DS00
µPD98412
(13/15)
Address AA06 AB06 AC06 AD06 AE06 12-PHY Polling Mode/ 15-PHY Polling Mode RXDATA001 RXADDR00 RXDATA202 RXADDR22 HCLK AD23 AD13 AD03 HTD27 HTD18 HTD09 Multiplexed Status Polling Mode RXDATA001 RXADDR00 RXDATA010 2-Group Weighted Polling Mode RXDATA001 RXADDR0A0 RXDATA010 RXADDR0B2 1-Group Weighted Polling Mode RXDATA001 RXADDR00 RXDATA010
Data Sheet S14237EJ2V0DS00
µPD98412
(14/15)
Address AE07 AE08 AE09 AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25 AD25 AC25 AB25 AA25 12-PHY Polling Mode/ 15-PHY Polling Mode RXDATA304 RXADDR33 TXDATA100 CBD78 CBD71 CBD61 CBD51 CBD42 CBD32 CBD22 CBD12 CBD04 Multiplexed Status Polling Mode RXDATA112 RXCLAV1[1] TXCLAV1[1] TXDATA100 2-Group Weighted Polling Mode RXDATA112 RXADDR1B3 TXDATA100 1-Group Weighted Polling Mode RXDATA112 TXDATA100
Data Sheet S14237EJ2V0DS00
µPD98412
(15/15)
Address 12-PHY Polling Mode/ 15-PHY Polling Mode RXDATA002 RXADDR01 RXDATA203 TXDATA207 MCS_B Multiplexed Status Polling Mode RXDATA002 RXADDR01 RXDATA011 TXDATA015 2-Group Weighted Polling Mode RXDATA002 RXADDR0A1 RXDATA011 TXDATA015 1-Group Weighted Polling Mode RXDATA002 RXADDR01 RXDATA011 TXDATA015
Data Sheet S14237EJ2V0DS00
µPD98412
CONTENTS FUNCTIONS Power Supply UTOPIA Interface Memory Interface Signals Microprocessor Interface Signals JTAG Others Recommended Connections Unused Pins. Status Reset
ELECTRICAL SPECIFICATIONS PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS.
Data Sheet S14237EJ2V0DS00
µPD98412
FUNCTIONS
Although µPD98412 device operating directly connected device, CPU, memory with interface.
Power Supply
Table 1-1. Power Supply
Name 112, 119, 129, 147, 152, 160, 161, 169, 230, 232, 240, 243, 283, 290, 293, 308, 315, 324, 325, 329, 332, 337, 342, 353, 360, 371, 376, 383, 393, 398, 406, 417, 418, 420, 422, 424, 426, 427, 429, 431, 433, 435, 436, 438, 441, 443, 448, 450, 456, 458, 459, 461, 462, 464, 469, 471, 473, 477, 483, 485, 490, 492, 496, 498, 499, 508, 519, 521, 101, 110, 113, 143, 144, 156, 162, 173, 183, 196, 215, 233, 241, 244, 255, 256, 265, 280, 282, 291, 304, 305, 307, 313, 314, 323, 327, 330, 339, 341, 352, 364, 365, 367, 368, 370, 375, 378, 385, 387, 388, 390, 394, 396, 401, 410, 413, 425, 434, 440, 444, 460, 479, 501, 503, 505, 507, 512, 514, 516, 518, 520, 522, 524, 531, 533, 535, 537, 539, 541, 543, 550, 552, 554, 556, 558, 560, 562, 567, 569, 571, 573, 575, Function These pins supply power +3.3
These ground pins.
Data Sheet S14237EJ2V0DS00
µPD98412
UTOPIA Interface
µPD98412 employs UTOPIA Level2 (cell level transfer) interface between layer Alayer. Symbol, number, function varied depending polling mode. 8-bit 12-PHY polling mode/15-PHY polling mode Table 1-2. Receive Interface Signals (1/2)
Symbol RXADDR03 RXADDR00 RXDATA007 RXDATA000 205, 206, 563, Function Multi-PHY select address receive interface RXADDR03 MSB. Cell data input receive interface Cell data input from layer device byte units. µPD98412 reads data rising edge UCLK0. RXDATA007 MSB. Cell transfer start signal receive interface This signal input from layer device synchronization with first byte cell data. Transfer enable signal receive interface This signal informs layer device that µPD98412 ready reception next clock cycle. Cell transfer enable signal receive interface This inputs signal that indicates that more cells will supplied µPD98412 after current cell been transferred. UTOPIA clock input receive interface Data transferred/received rising edge this clock. Multi-PHY select address receive interface RXADDR13 MSB. Cell data input receive interface Cell data input from layer device byte units. µPD98412 reads data rising edge UCLK1. RXDATA107 MSB. Cell transfer start signal receive interface This signal input from layer device synchronization with first byte cell data. Transfer enable signal receive interface This signal informs layer device that µPD98412 ready reception next clock cycle. Cell transfer enable signal receive interface This inputs signal that indicates that more cells will supplied µPD98412 after current cell been transferred. UTOPIA clock input receive interface Data transferred/received rising edge this clock.
303, 397, 202, 561, 484,
RXSOC0
RXENB0_B
RXCLAV0
UCLK0
RXADDR13 RXADDR10 RXDATA107 RXDATA100
266, 363,
158, 263, 449, 159, 264, 361,
RXSOC1
RXENB1_B
RXCLAV1
UCLK1
Data Sheet S14237EJ2V0DS00
µPD98412
Table 1-2. Receive Interface Signals (2/2)
Symbol RXADDR23 RXADDR20 RXDATA207 RXDATA200 408, 493, 107, Function Multi-PHY select address receive interface RXADDR23 MSB. Cell data input receive interface Cell data input from layer device byte units. µPD98412 reads data rising edge UCLK2. RXDATA207 MSB. Cell transfer start signal receive interface This signal input from layer device synchronization with first byte cell data. Transfer enable signal receive interface This signal informs layer device that µPD98412 ready reception next clock cycle. Cell transfer enable signal receive interface This inputs signal that indicates that more cells will supplied µPD98412 after current cell been transferred. UTOPIA clock input receive interface Data transferred/received rising edge this clock. Multi-PHY select address receive interface RXADDR33 MSB. Cell data input receive interface Cell data input from layer device byte units. µPD98412 reads data rising edge UCLK3. RXDATA307 MSB. Cell transfer start signal receive interface This signal input from layer device synchronization with first byte cell data. Transfer enable signal receive interface This signal informs layer device that µPD98412 ready reception next clock cycle. Cell transfer enable signal receive interface This inputs signal that indicates that more cells will supplied µPD98412 after current cell been transferred. UTOPIA clock input receive interface Data transferred/received rising edge this clock.
405, 312, 103, 212, 568, 491, 104,
RXSOC2
RXENB2_B
RXCLAV2
UCLK2
RXADDR33 RXADDR30 RXDATA307 RXDATA300
525, 355, 258,
148, 254, 523, 442, 149,
RXSOC3
RXENB3_B
RXCLAV3
UCLK3
Data Sheet S14237EJ2V0DS00
µPD98412
Table 1-3. Transmit Interface Signals (1/2)
Symbol TXADDR03 TXADDR00 TXDATA007 TXDATA000 207, Function Multi-PHY select address transmit interface TXADDR03 MSB. Cell data output transmit interface Cell data output layer device byte units. µPD98412 outputs data rising edge UCLK0. TXDATA007 MSB. (3-state buffer) Cell transfer start signal transmit interface This signal output layer device synchronization with first byte cell data. (3-state buffer) Transfer enable signal transmit interface This signal informs layer device that µPD98412 outputs data current clock cycle. Cell transfer enable signal transmit interface This inputs signal that indicates that µPD98412 ready receive next cell after transfer current cell completed. Multi-PHY select address transmit interface TXADDR13 MSB. Cell data output transmit interface µPD98412 outputs data rising edge UCLK1. TXDATA107 MSB. (3-state buffer) Cell transfer start signal transmit interface This signal output layer device synchronization with first byte cell data. (3-state buffer) Transfer enable signal transmit interface This signal informs layer device that µPD98412 outputs data current clock cycle. Cell transfer enable signal transmit interface This inputs signal that indicates that µPD98412 ready receive next cell after transfer current cell completed.
310, 209, 100, 404, 311, 210, 102,
TXSOC0
TXENB0_B
TXCLAV0
TXADDR13 TXADDR10 TXDATA107 TXDATA100
163, 268,
366, 270, 166, 271, 167,
TXSOC1
TXENB1_B
TXCLAV1
Data Sheet S14237EJ2V0DS00
µPD98412
Table 1-3. Transmit Interface Signals (2/2)
Symbol TXADDR23 TXADDR20 TXDATA207 TXDATA200 216, 108, 409, Function Multi-PHY select address transmit interface TXADDR23 MSB. Cell data output transmit interface µPD98412 outputs data rising edge UCLK2. TXDATA207 MSB. (3-state buffer) Cell transfer start signal transmit interface This signal output layer device synchronization with first byte cell data. (3-state buffer) Transfer enable signal transmit interface This signal informs layer device that µPD98412 outputs data current clock cycle. Cell transfer enable signal transmit interface This inputs signal that indicates that µPD98412 ready receive next cell after transfer current cell completed. Multi-PHY select address transmit interface TXADDR33 MSB. Cell data output transmit interface µPD98412 outputs data rising edge. TXDATA307 MSB. (3-state buffer) Cell transfer start signal transmit interface This signal output layer device synchronization with first byte cell data. (3-state buffer) Transfer enable signal transmit interface This signal informs layer device that µPD98412 outputs data current clock cycle. Cell transfer enable signal transmit interface This inputs signal that indicates that µPD98412 ready receive next cell after transfer current cell completed.
572, 411, 319, 219, 111, 412, 320,
TXSOC2
TXENB2_B
TXCLAV2
TXADDR33 TXADDR30 TXDATA307 TXDATA300
356, 259,
358, 261, 157, 359, 262,
TXSOC3
TXENB3_B
TXCLAV3
Data Sheet S14237EJ2V0DS00
µPD98412
16-bit multiplexed status polling mode Table 1-4. Receive Interface Signals
Symbol RXADDR04 RXADDR00 RXDATA015 RXDATA000 316, 205, 206, 563, Function Multi-PHY select address receive interface RXADDR04 MSB. Cell data input receive interface Cell data input from layer device 16-bit units. µPD98412 reads data rising edge UCLK0. RXDATA015 MSB. Cell transfer start signal receive interface This signal input from layer device synchronization with first byte cell data. Transfer enable signal receive interface This signal informs layer device that µPD98412 ready reception next clock cycle. Cell transfer enable signal receive interface This inputs signal that indicates that more cells will supplied µPD98412. Pins connected (RXCLAV0[0][3]) differ depending address connected device. UTOPIA clock input receive interface Data transferred/received rising edge this clock. Multi-PHY select address receive interface RXADDR14 MSB. Cell data input receive interface Cell data input from layer device 16-bit units. µPD98412 reads data rising edge UCLK1. RXDATA115 MSB. Cell transfer start signal receive interface This signal input from layer device synchronization with first byte cell data. Transfer enable signal receive interface This signal informs layer device that µPD98412 ready reception next clock cycle. Cell transfer enable signal receive interface This inputs signal that indicates that more cells will supplied µPD98412 after current cell been transferred. Pins connected (RXCLAV1[0]-[3]) differ depending address connected device. UTOPIA clock input receive interface Data transferred/received rising edge this clock.
405, 312, 103, 212, 568, 491, 104, 213, 303, 397, 202, 561, 484,
RXSOC0
RXENB0_B
RXCLAV0[0] RXCLAV0[3]
400, 106,
UCLK0
RXADDR14 RXADDR10 RXDATA115 RXDATA100
153, 266, 363,
148, 254, 523, 442, 149, 150, 158, 263, 449, 159, 264, 361,
RXSOC1
RXENB1_B
RXCLAV1[0] RXCLAV1[3]
532,
UCLK1
Data Sheet S14237EJ2V0DS00
µPD98412
Table 1-5. Transmit Interface Signals
Symbol TXADDR04 TXADDR00 TXDATA015 TXDATA000 317, 207, Function Multi-PHY select address transmit interface TXADDR04 MSB. Cell data output transmit interface Cell data output layer device 16-bit units. µPD98412 outputs data rising edge UCLK0. TXDATA015 MSB. (3-state buffer) Cell transfer start signal transmit interface This signal output layer device synchronization with first byte cell data. (3-state buffer) Transfer enable signal transmit interface This signal informs layer device that µPD98412 outputs data current clock cycle. Cell transfer enable signal transmit interface This inputs signal that indicates that µPD98412 ready receive next cell after transfer current cell completed. Pins connected (TXCLAV0[0]-[3]) differ depending address connected device. Multi-PHY select address transmit interface TXADDR14 MSB. Cell data output transmit interface µPD98412 outputs data rising edge UCLK1. TXDATA115 MSB. (3-state buffer) Cell transfer start signal transmit interface This signal output layer device synchronization with first byte cell data. (3-state buffer) Transfer enable signal transmit interface This signal informs layer device that µPD98412 outputs data current clock cycle. Cell transfer enable signal transmit interface This inputs signal that indicates that µPD98412 ready receive next cell after transfer current cell completed. Pins connected (TXCLAV1[0]-[3]) differ depending address connected device.
572, 411, 319, 219, 111, 412, 320, 220, 310, 209, 100, 404, 311, 210, 102,
TXSOC0
TXENB0_B
TXCLAV0[0] TXCLAV0[3]
208, 309, 109,
TXADDR14 TXADDR10 TXDATA115 TXDATA100
154, 163, 268,
358, 261, 157, 359, 262, 366, 270, 166, 271, 167,
TXSOC1
TXENB1_B
TXCLAV1[0] TXCLAV1[3]
534, 357,
Data Sheet S14237EJ2V0DS00
µPD98412
16-bit 2-group weighted polling mode Table 1-6. Receive Interface Signals (1/2)
Symbol RXADDR0A3 RXADDR0A0 RXADDR0B3 RXADDR0B0 RXENB0A_B 205, 206, 563, Function Multi-PHY select address receive interface group RXADDR0A3 MSB. Multi-PHY select address receive interface group RXADDR0B3 MSB. Transfer enable signal receive interface group This signal informs layer device that µPD98412 ready reception next clock cycle. Transfer enable signal receive interface group This signal informs layer device that µPD98412 ready reception next clock cycle. Cell transfer enable signal receive interface group This inputs signal that indicates that more cells will supplied µPD98412 after current cell been transferred. Cell transfer enable signal receive interface group This inputs signal that indicates that more cells will supplied µPD98412 after current cell been transferred. Cell data input receive interface Cell data input from layer device 16-bit units. µPD98412 reads data rising edge UCLK0. RXDATA015 MSB. Cell transfer start signal receive interface This signal input from layer device synchronization with first byte cell data. UTOPIA clock input receive interface Data transferred/received rising edge this clock.
408, 493, 107,
RXENB0B_B
RXCLAV0A
RXCLAV0B
RXDATA015 RXDATA000
405, 312, 103, 212, 568, 491, 104, 213, 303, 397, 202, 561, 484,
RXSOC0
UCLK0
Data Sheet S14237EJ2V0DS00
µPD98412
Table 1-6. Receive Interface Signals (2/2)
Symbol RXADDR1A3 RXADDR1A0 RXADDR1B3 RXADDR1B0 RXENB1A_B 266, 363, Function Multi-PHY select address receive interface group RXADDR1A3 MSB. Multi-PHY select address receive interface group RXADDR1B3 MSB. Transfer enable signal receive interface group This signal informs layer device that µPD98412 ready reception next clock cycle. Transfer enable signal receive interface group This signal informs layer device that µPD98412 ready reception next clock cycle. Cell transfer enable signal receive interface group This inputs signal that indicates that more cells will supplied µPD98412 after current cell been transferred. Cell transfer enable signal receive interface group This inputs signal that indicates that more cells will supplied µPD98412 after current cell been transferred. Cell data input receive interface Cell data input from layer device 16-bit units. µPD98412 reads data rising edge UCLK1. RXDATA115 MSB. Cell transfer start signal receive interface This signal input from layer device synchronization with first byte cell data. UTOPIA clock input receive interface Data transferred/received rising edge this clock.
525, 355, 258,
RXENB1B_B
RXCLAV1A
RXCLAV1B
RXDATA115 RXDATA100
148, 254, 523, 442, 149, 150, 158, 263, 449, 159, 264, 361,
RXSOC1
UCLK1
Data Sheet S14237EJ2V0DS00
µPD98412
Table 1-7. Transmit Interface Signals (1/2)
Symbol TXADDR0A3 TXADDR0A0 TXADDR0B3 TXADDR0B0 TXENB0A_B 207, Function Multi-PHY select address transmit interface group TXADDR0A3 MSB. Multi-PHY select address transmit interface group TXADDR0B3 MSB. Transfer enable signal transmit interface group This signal informs layer device that µPD98412 outputs data current clock cycle. Transfer enable signal transmit interface group This signal informs layer device that µPD98412 outputs data current clock cycle. Cell transfer enable signal transmit interface group This inputs signal that indicates that µPD98412 ready receive next cell after transfer current cell completed. Cell transfer enable signal transmit interface group This inputs signal that indicates that µPD98412 ready receive next cell after transfer current cell completed. Cell data output transmit interface Cell data output layer device 16-bit units. µPD98412 outputs data rising edge UCLK0. TXDATA015 MSB. (3-state buffer) Cell transfer start signal transmit interface This signal output layer device synchronization with first byte cell data. (3-state buffer)
216, 108, 409,
TXENB0B_B
TXCLAV0A
TXCLAV0B
TXDATA015 TXDATA000
572, 411, 319, 219, 111, 412, 320, 220, 310, 209, 100, 404, 311, 210, 102,
TXSOC0
Data Sheet S14237EJ2V0DS00
µPD98412
Table 1-7. Transmit Interface Signals (2/2)
Symbol TXADDR1A3 TXADDR1A0 TXADDR1B3 TXADDR1B0 TXENB1A_B 163, 268, Function Multi-PHY select address transmit interface group TXADDR1A3 MSB. Multi-PHY select address transmit interface group TXADDR1B3 MSB. Transfer enable signal transmit interface group This signal informs layer device that µPD98412 outputs data current clock cycle. Transfer enable signal transmit interface group This signal informs layer device that µPD98412 outputs data current clock cycle. Cell transfer enable signal transmit interface group This inputs signal that indicates that µPD98412 ready receive next cell after transfer current cell completed. Cell transfer enable signal transmit interface group This inputs signal that indicates that µPD98412 ready receive next cell after transfer current cell completed. Cell data output transmit interface Cell data output layer device 16-bit units. µPD98412 outputs data rising edge UCLK1. TXDATA115 MSB. (3-state buffer) Cell transfer start signal transmit interface This signal output layer device synchronization with first byte cell data. (3-state buffer)
356, 259,
TXENB1B_B
TXCLAV1A
TXCLAV1B
TXDATA115 TXDATA100
358, 261, 157, 359, 262, 366, 270, 166, 271, 167,
TXSOC1
Data Sheet S14237EJ2V0DS00
µPD98412
16-bit 1-group weighted polling mode Table 1-8. Receive Interface Signals
Symbol RXADDR04 RXADDR00 RXDATA015 RXDATA000 316, 205, 206, 563, Function Multi-PHY select address receive interface RXADDR04 MSB. Cell data input receive interface Cell data input from layer device 16-bit units. µPD98412 reads data rising edge UCLK0. RXDATA015 MSB. Cell transfer start signal receive interface This signal input from layer device synchronization with first byte cell data. Transfer enable signal receive interface This signal informs layer device that µPD98412 ready reception next clock cycle. Cell transfer enable signal receive interface This inputs signal that indicates that more cells will supplied µPD98412 after current cell been transferred. UTOPIA clock input receive interface Data transferred/received rising edge this clock. Multi-PHY select address receive interface RXADDR14 MSB. Cell data input receive interface Cell data input from layer device 16-bit units. µPD98412 reads data rising edge UCLK1. RXDATA115 MSB. Cell transfer start signal receive interface This signal input from layer device synchronization with first byte cell data. Transfer enable signal receive interface This signal informs layer device that µPD98412 ready reception next clock cycle. Cell transfer enable signal receive interface This inputs signal that indicates that more cells will supplied µPD98412 after current cell been transferred. UTOPIA clock input receive interface Data transferred/received rising edge this clock.
405, 312, 103, 212, 568, 491, 104, 213, 303, 397, 202, 561, 484,
RXSOC0
RXENB0_B
RXCLAV0
UCLK0
RXADDR14 RXADDR10 RXDATA115 RXDATA100
153, 266, 363,
148, 254, 523, 442, 149, 150, 158, 263, 449, 159, 264, 361,
RXSOC1
RXENB1_B
RXCLAV1
UCLK1
Data Sheet S14237EJ2V0DS00
µPD98412
Table 1-9. Transmit Interface Signals
Symbol TXADDR04 TXADDR00 TXDATA015 TXDATA000 317, 207, Function Multi-PHY select address transmit interface TXADDR04 MSB. Cell data output transmit interface Cell data output layer device 16-bit units. µPD98412 outputs data rising edge UCLK0. TXDATA015 MSB. (3-state buffer) Cell transfer start signal transmit interface This signal output layer device synchronization with first byte cell data. (3-state buffer) Transfer enable signal transmit interface This signal informs layer device that µPD98412 outputs data current clock cycle. Cell transfer enable signal transmit interface This inputs signal that indicates that µPD98412 ready receive next cell after transfer current cell completed. Multi-PHY select address transmit interface TXADDR14 MSB. Cell data output transmit interface µPD98412 outputs data rising edge UCLK1. TXDATA115 MSB. (3-state buffer) Cell transfer start signal transmit interface This signal output layer device synchronization with first byte cell data. (3-state buffer) Transfer enable signal transmit interface This signal informs layer device that µPD98412 outputs data current clock cycle. Cell transfer enable signal transmit interface This inputs signal that indicates that µPD98412 ready receive next cell after transfer current cell completed.
572, 411, 319, 219, 111, 412, 320, 220, 310, 209, 100, 404, 311, 210, 102,
TXSOC0
TXENB0_B
TXCLAV0
TXADDR14 TXADDR10 TXDATA115 TXDATA100
154, 163, 268,
358, 261, 157, 359, 262, 366, 270, 166, 271, 167,
TXSOC1
TXENB1_B
TXCLAV1
Data Sheet S14237EJ2V0DS00
µPD98412
Memory Interface Signals
µPD98412 types memory interfaces. them used store cell header translation table address pointer cell buffer control memory, other used store cell data cell buffer memory. Table 1-10 shows interface signals control memory. Table 1-11 shows interface signals cell buffer memory. Table 1-10. Control Memory Interface Signals
Symbol HTA17 HTA00 333, 234, 127, 334, 235, 128, 335, 236, 130, 336, 237, 131, 133, 430, 513, 134, 135, 242, 136, 137, 432, 515, 138, 343, 245, 139, 344, 246, 140, 517, 345, 141, 346, 248, 142, 338, 340, Address output Function
HTD31 HTD00
Data (32-bit/word units) (w/pull-down resistor)
HTP3 HTP0 HTCS1_B, HTCS0_B HTWE_B HTOE_B
Parity (w/pull-down resistor)
428,
Chip select signal
Write enable signal Output enable signal
Table 1-11. Cell Buffer Memory Interface Signals
Symbol CBA17 CBA00 381, 286, 184, 382, 287, 185, 288, 470, 186, 289, 384, 187, 145, 251, 349, 439, 272, 168, 457, 369, 273, 170, 274, 538, 171, 275, 172, 276, 372, 540, 373, 277, 174, 278, 374, 175, 279, 542, 463, 176, 177, 281, 377, 178, 179, 544, 465, 180, 379, 284, 181, 472, 551, 188, 189, 386, 292, 190, 191, 474, 553, 294, 192, 389, 295, 193, 296, 194, 555, 391, 297, 195, 478, 392, 298, 197, 299, 557, 198, 300, 199, 301, 395, 559, 302, 200, Address output Function
CBD91 CBD00
Data (92-bit/word units) (w/pull-down resistor)
CBCS1_B, CBCS0_B CBWE_B CBOE_B
Chip select signal
Write enable signal Output enable signal
Data Sheet S14237EJ2V0DS00
µPD98412
Microprocessor Interface Signals
µPD98412 supports 32-bit address/data multiplexed synchronous type microprocessor interface. Table 1-12. Microprocessor Interface Signal
Symbol IOCS_B MCS_B HCLK AD31 416, 117, 225, 118, 226, 326, 502, 227, 419, 120, 228, 328, 121, 229, 504, 421, 122, 123, 231, 331, 124, 125, 506, 423, chip select signal Memory chip select signal Interrupt request signal Microprocessor clock MHz) Address/data Function
R/W_B UWE_B RDY_B
Read/write select signal High-order word enable signal Ready signal (3-state buffer)
Data Sheet S14237EJ2V0DS00
µPD98412
JTAG
Table 1-13. JTAG Interface Signals
Symbol JTAG serial data input JTAG serial data output (normally open) (3-state buffer) JTAG serial clock input JTAG mode select signal JTAG reset signal Function
JRST_B
Others
Table 1-14. Other Interface Signals
Symbol SWCLK RESET_B 116, 222, 223, 321, 224, 250, 348, 350, Function System clock input MHz) Hardware reset signal (Schmitt input buffer) Always connect GND. Always pull VDD. Internally connected (always open).
Data Sheet S14237EJ2V0DS00
µPD98412
Recommended Connections Unused Pins
Table 1-15. Recommended Connections Unused Pins
Name RXDATA*** RXSOC* RXCLAV* UCLK* TXCLAV* HTD31 HTD00 HTP3 HTP0 CBD91 CBD00 IOCS_B MCS_B AD31 AD00 R/W_B UWE_B JRST_B output pins (w/pull-down resistor) (w/pull-down resistor) (w/pull-down resistor) Recommended Connections Connect GND. Connect GND. Connect GND. Connect GND. Connect GND. Open. Open. Open. Pull VDD. Pull VDD. Pull VDD. Pull VDD. Pull VDD. Connect GND. Connect GND. Connect GND. Connect GND. Open.
Data Sheet S14237EJ2V0DS00
µPD98412
Status Reset
Table 1-16. Status Reset
Name RXADDR* RXENB*_B TXADDR* TXDATA*** TXSOC* TXENB*_B HTA17 HTA00 HTCS1_B, HTCS0_B HTWE_B HTOE_B HTP3 HTP0 HTD31 HTD00 CBD91 CBD00 CBA17 CBA00 CBOE_B CBWE_B CBCS1_B, CBCS0_B RDY_B AD31 AD00 (3-state buffer) (3-state buffer) (w/pull-down resistor) (w/pull-down resistor) (w/pull-down resistor) (3-state buffer) (3-state buffer) High level High level High level Hi-Z Hi-Z High level level High level High level High level level level level level High level High level High level level Hi-Z Hi-Z Hi-Z Status Reset
Data Sheet S14237EJ2V0DS00
µPD98412
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings
Parameter Supply voltage Input voltage Output voltage Storage temperature Symbol Tstg Test Conditions Rating -0.5 +4.6 -0.5 +6.6 -0.5 +6.6 +150 Unit
Caution parameters exceeds absolute maximum ratings, even momentarily, quality product impaired. absolute maximum ratings values that physically damage product(s). sure product(s) within ratings. Capacitance
Parameter Input capacitance Output capacitance Input/output capacitance Symbol Test Conditions Frequency Frequency Frequency MIN. TYP. MAX. Unit
Recommended Operating Condition
Parameter Supply voltage Low-level input voltage Symbol Other than RESET_B signal Other than RESET_B signal RESET_B signal RESET_B signal Test Conditions MIN. 3.135 TYP. 3.300 MAX. 3.465 Unit
High-level input voltage
Negative trigger voltage Positive trigger voltage Hysteresis voltage Operating temperature
Data Sheet S14237EJ2V0DS00
µPD98412
Characteristics ±5%)
Parameter Output leakage current Input leakage current Symbol ILI1 ILI2 Low-level output leakage current IOL1 IOL2 IOL3 High-level output leakage current IOH1 IOH2 IOH2 IOH3 Low-level output leakage voltage High-level output leakage voltage VOH1 VOH2 Operating current Test Conditions GND, Note Note pull-down) Note Note Note Note Note Note (UTOPIA) Note Note Note MIN. 12.0 -3.0 -4.0 -6.0 -5.0 TYP. Note MAX. 1300 Unit
Notes RXDATA***, RXSOC*, RXCLAV*, UCLK*, TCLAV*, AD31-AD00, MCS_B, IOCS_B, R/W_B, UWE_B, HCLK, JDI, JCK, JMS, JRST_B, SWCLK, RESET_B pins HTD31-HTD00, HTP3-HTP0, CBD91-CBD00 pins INT, pins HTA17-HTA00, HTWE_B, HTOE_B, CBA17-CBA00, CBCS0_B, CBWE_B, CBOE_B, HTCS1_B, HTCS0_B, CBCS1_B, HTD31-HTD00, HTP3-HTP0, CBD91-CBD00 pins RXADDR**, TXADDR**, RXENB*_B, TXENB*_B, TXDATA***, TXSOC* pins RDY_B, AD31-AD00 pins INT, JDO, RXADDR**, TXADDR**, RXENB*_B, TXENB*_B, TXDATA***, TXSOC*, HTCS1_B, HTCS0_B, CBCS1_B, HTA17-HTA00, HTWE_B, HTOE_B, CBA17-CBA00, CBCS0_B, CBWE_B, CBOE_B, RDY_B, AD31-AD00 pins HTD31-HTD00, HTP3-HTP0, CBD91-CBD00 pins approximate TYP. value operating current (IDD) depends throughput switching. example with following conditions, calculated shown below. Conditions: 8-bit UTOPIA interface ports, SWCLK MHz, UCLK0 UCLK3 Calculation formula: (TYP.) (throughput): [Unit: Gbps]
Data Sheet S14237EJ2V0DS00
µPD98412
Test Output Waveform
Test point
Characteristics ±5%) Control Signal
Parameter SWCLK cycle time SWCLK high-level width SWCLK low-level width SWCLK rise time SWCLK fall time RESET_B low-level width Symbol tCYSL tWSKH tWSKL tSKR tSKF tWRSL Test Conditions MIN. 10.5 10.5 TYP. MAX. Unit tCYSK
Control Signal
tCYSK tWSKH SWCLK tSKR tSKF tWSKL
RESET_B tWRSL
Data Sheet S14237EJ2V0DS00
µPD98412
Processor interface (32-bit mode, read/write)
Parameter HCLK cycle time HCLK high-level width HCLK low-level width HCLK rise time HCLK fall time HCLK output delay time HCLK RDY_B output delay time HCLK RDY_B float output delay time HCLK output delay time HCLK float output delay time setup time (vs. HCLK hold time (vs. HCLK IOCS_B setup time (vs. HCLK IOCS_B hold time (vs. HCLK IOCS_B recovery time MCS_B setup time (vs. HCLK MCS_B hold time (vs. HCLK MCS_B recovery time UWE_B setup time (vs. HCLK UWE_B hold time (vs. HCLK R/W_B setup time (vs. HCLK R/W_B hold time (vs. HCLK Symbol tCYHK tWHKH tWHKL tHKR tHKF tDHKIT tDHKRY Load capacitance Load capacitance Test Conditions MIN. TYP. MAX. Unit
tFHKRY
Load capacitance
tDHKAD tFHKAD
Load capacitance Load capacitance
tSADHK tHHKAD tSIOHK tHHKIO tIORV tSMHK tHHKM tMRV tSUWHK tHHKUW tSRWHK tHHKRW
Note Note
Note
When HCLK cycle time (tCYHK) SWCLK cycle time (tCYSK): IOCS_B recovery time (tIORV) MCS_B recovery time (tMRV) tCYHK When HCLK cycle time (tCYHK) SWCLK cycle time (tCYSK): IOCS_B recovery time (tIORV) MCS_B recovery time (tMRV) tCYHK
Data Sheet S14237EJ2V0DS00
µPD98412
Processor interface (32-bit mode, read)
tCYHK tWHKH tWHKL HCLK tHKR tHKF tSADHK tHHKAD AD31 AD00 in/out address tSIOHK IOCS_B tSMHK MCS_B tSUWHK UME_B tSRWHK R/W_B RDY_B HCLK tDHKIT tDHKIT tDHKRY tDHKRY (Hi-Z) tFHKRY (Hi-Z) tHHKRW tHHKUW tHHKW tMRV tDHKAD tFHKAD data tHHKIO tIORV address
Data Sheet S14237EJ2V0DS00
µPD98412
Processor interface (32-bit mode, write)
tCYHK tWHKH tWHKL HCLK tHKR tHKF tSADHK tHHKAD AD31 AD00 in/out address tSIOHK IOCS_B tSMHK MOS_B tSUWHK UME_B tSRWHK R/W_B tDHKRY tDHKRY RDY_B (Hi-Z) tFHKRY (Hi-Z) tHHKRW tHHKUW tHHKW tMRV tSADHK data tHHKAD Don't care tHHKIO tIORV
Data Sheet S14237EJ2V0DS00
µPD98412
control memory interface
Parameter cycle time HTD, setup time (vs. HTA) HTD, hold time (vs. HTA) HTCS_B cycle time HTD, setup time (vs. HTCS_B) HTD, hold time (vs. HTCS_B) HTOE_B cycle time HTD, setup time (vs. HTOE_B) HTD, hold time (vs. HTOE_B) HTWE_B low-level width Data HTWE_B output delay time HTWE_B Data float output delay time HTWE_B output delay time HTCS_B HTWE_B output delay time HTOE_B HTWE_B output delay time HTWE_B output delay time HTWE_B HTCS_B output delay time HTWE_B HTOE_B output delay time float HTOE_B output delay time HTOE_B Data output delay time Symbol tCYHA tSHDHA tHHAHD tCYHC tSHDHC Load capacitance Test Conditions Load capacitance MIN. tCYSK tCYSK TYP. MAX. Unit
tHHCHD
tCYSK
tCYHO tSHDHO
Load capacitance
tHHOHD
tWSKL tWSKL
tWHWL tDHDHW
Load capacitance Load capacitance
tFHWHD
Load capacitance
tWSKH tCYSK tCYSK
tDHAHW
Load capacitance
tDHCHW
Load capacitance
tDHOHW
Load capacitance
tDHWHA
Load capacitance
tDHWHC
Load capacitance
tDHWHO
Load capacitance
tDHDHO
Load capacitance
tWSKH
tDHOHD
Load capacitance
Data Sheet S14237EJ2V0DS00
µPD98412
control memory interface (read)
(SWCLK) tCYHA HTA17 HTA00 HTD31 HTD00, HTP3-HTP0 in/out HTCS1_B, HTCS0_B tCYHO HTOE_B tSHDHO HTWE_B tHHOHD address tSHDHA (Hi-Z) tCYHC data tHHAHD (Hi-Z)
tSHDHC
tHHCHD
control memory interface (write)
(SWCLK) tCYHA HTA17 HTA00 tDHAHW HTD31 HTD00, HTP3 HTP0 in/out HTCS1_B, HTCS0_B HTOE_B tDHDHW HTWE_B tWHWL tDHWHO (Hi-Z) Valid tDHDHW tDHOHD address tDHWHA (Hi-Z) tFHWHD tDHDHO
tDHCHW
tDHWHC
Data Sheet S14237EJ2V0DS00
µPD98412
Cell buffer memory interface
Parameter cycle time setup time (vs. CBA) hold time (vs. CBA) CBCS_B cycle time setup time (vs. CBCS_B) hold time (vs. CBCS_B) CBOE_B cycle time setup time (vs. CBOE_B) hold time (vs. CBOE_B) CBWE_B low-level width Data CBWE_B output delay time CBWE_B Data float output delay time CBWE_B output delay time CBCS_B CBWE_B output delay time CBOE_B CBWE_B output delay time CBWE_B output delay time CBWE_B CBCS_B output delay time CBWE_B CBOE_B output delay time float CBOE_B output delay time CBOE_B Data output delay time Symbol tCYCA tSCDCA tHCACD tCYCC tSCDCC tHCCCD tCYCO tSCDCO tHCOCD tWCWL tDCDCW Load capacitance Load capacitance Load capacitance Load capacitance Test Conditions Load capacitance MIN. tCYSK tCYSK tCYSK tWSKL tWSKL TYP. MAX. Unit
tFCWCD
Load capacitance
tWSKH tCYSK tCYSK
tDCACW
Load capacitance
tDCCCW
Load capacitance
tDCOCW
Load capacitance
tDCWCA
Load capacitance
tDCWCC
Load capacitance
tDCWCO
Load capacitance
tDCDCO
Load capacitance
tWSKH
tDCOCD
Load capacitance
Data Sheet S14237EJ2V0DS00
µPD98412
Cell buffer memory interface (read)
(SWCLK) tCYCA CBA17 CBA00 CBD91 CBD00 in/out CBCS1_B, CBCS0_B tCYCO CBOE_B tSCDCO CBWE_B tHCOCD address tSCDCA (Hi-Z) tCYCC data tHCACD (Hi-Z)
tSCDCC
tHCCCD
Cell buffer memory interface (write)
(SWCLK) tCYCA CBA17 CBA00 tDCACW CBD91 CBD00, in/out CBCS1_B, CBCS0_B CBOE_B tDCOCW CBWE_B tWCWL tDCWCO (Hi-Z) Valid tDCDCW tDCOCD address tDCWCA (Hi-Z) tFCWCD tDCDCO
tDCCCW
tDCWCC
Data Sheet S14237EJ2V0DS00
µPD98412
UTOPIA interface (reception)
Parameter UCLK cycle time UCLK high-level width UCLK low-level width UCLK rise time UCLK fall time UCLK RXADDR output delay time UCLK RXENB_B output delay time RXCLAV setup time (vs. UCLK RXCLAV hold time (vs. UCLK RXDATA setup time (vs. UCLK RXDATA hold time (vs. UCLK RXSOC setup time (vs. UCLK RXSOC hold time (vs. UCLK Symbol tCYRK tWRKH tWRKL tRKR tRKF tDRKA Load capacitance Test Conditions MIN. TYP. MAX. Unit
tDRKE
Load capacitance
tSCARK tHRKCA tSDRK tHRKD tSSCRK tHRKSC
Data Sheet S14237EJ2V0DS00
µPD98412
UTOPIA interface (reception) 8-bit mode
tCYRK tWRKH tWRKL UCLKn tRKR RXADDRn3 RXADDRn0 RXCLAVn RXNBn_B tSDRK RXDATAn7 RXDATAn0 RXSOCn tHRKSC (Hi-Z) (Hi-Z) tSSCRK tHRKSC tHRKD tSSCRK (Hi-Z) tDRKE tRKF "F(h)" tDRKA "F(h)" tSCARK (Hi-Z) tDRKE tHRKCA (Hi-Z) "F(h)" tSCARK tHRKCA (Hi-Z)
16-bit mode
tCYRK tWRKH tWRKL UCLKn tRKR RXADDRn4 RXADDRn0 RXCLAVn RXENBn_B tSDRK RXDATAn15 RXDATAn8 RXDATAn7 RXDATAn0 RXSOCn (Hi-Z) tSDRK tHRKSC (Hi-Z) (Hi-Z) tSSCRK tHRKSC tHRKD tSSCRK tHRKD (Hi-Z) tDRKE tRKF "1F(h)" tDRKA "1F(h)" tSCARK (Hi-Z) tDRKE (Hi-Z) "1F(h)" tSCARK tHRKCA (Hi-Z)
Data Sheet S14237EJ2V0DS00
µPD98412
UTOPIA interface (transmission)
Parameter UCLK TXADDR output delay time UCLK TXENB_B output delay time UCLK TXDATA output delay time UCLK TXDATA float output delay time UCLK TXSOC output delay time UCLK TXSOC float output delay time TXCLAV setup time (vs. UCLK TXCLAV hold time (vs. UCLK Symbol tDTKA Test Conditions Load capacitance MIN. TYP. MAX. Unit
tDTKE
Load capacitance
tDTKD
Load capacitance
tFTKD
Load capacitance
tDTKSC
Load capacitance
tFTKSC
Load capacitance
tSCATK tHTKCA
Data Sheet S14237EJ2V0DS00
µPD98412
UTOPIA interface (transmission) 8-bit mode
UCLKn tDTKA TXADDRn3 TXADDRn0 TXCLAVn TXENBn_B tFTKD TXDATAn7 TXDATAn0 TXSOCn tFTKSC (Hi-Z) (Hi-Z) tDTKSC tDTKD tDTKSC (Hi-Z) tDTKE "F(h)" "F(h)" tSCATK (Hi-Z) tDTKE tHTKCA (Hi-Z) "F(h)" tSCATK tHTKCA (Hi-Z)
16-bit mode
UCLKn tDTKA TXADDRn4 TXADDRn0 TXCLAVn TXENBn_B tFTKD TXDATAn15 TXDATAn8 TXDATAn7TXDATAn0 TXSOCn tFTKD tFTKSC tDTKSC (Hi-Z) tDTKD tDTKSC tDTKD (Hi-Z) tDTKE "1F(h)" "1F(h)" tSCATK (Hi-Z) tDTKE tHTKCA (Hi-Z) "1F(h)" tSCATK tHTKCA (Hi-Z)
Data Sheet S14237EJ2V0DS00
µPD98412
PACKAGE DRAWING
Index area
ITEM
MILLIMETERS 40.00±0.20 23.00 MAX. 23.00 MAX. 39.60±0.15 39.60±0.15 40.00±0.20 1.585 1.27 (T.P.) 0.60±0.10 0.80 +0.20 -0.10 1.40 +0.30 -0.20 0.15
detail part
detail part
0.75±0.15
0.30 0.25 MIN. 0.10 22.73 22.73 0.40 0.20 S576N7-127-H6-1
Data Sheet S14237EJ2V0DS00
µPD98412
RECOMMENDED SOLDERING CONDITIONS
Solder this product under following recommended conditions. details recommended soldering conditions, refer information document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended, consult NEC. Surface-mount type µPD98412N7-H6: 576-pin tape
Recommended Conditions Symbol IR35-107-3
Soldering Method(s) Infrared reflow
Soldering Conditions Package peak temperature: Time: max. (210 min.), Note Number times: three times max., Number days: (after that, prebaking necessary hours) temperature: max. (per device side), Time: max. (per device side)
Partial heating
Note Number days storage after pack been opened. storage conditions MAX.
Data Sheet S14237EJ2V0DS00
µPD98412
[MEMO]
Data Sheet S14237EJ2V0DS00
µPD98412
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet S14237EJ2V0DS00
µPD98412
NEASCOT-X15 trademark Corporation.
information this document current April, 2000. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

µPD98412 1.5G ASWITCH DESCRIPTION µPD98412 (NEASCOT-X15

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