µPD98405 155M AINTEGRATED CONTROLLER DESCRIPTION µPD984

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µPD98405 155M AINTEGRATED CONTROLLER DESCRIPTION µPD984

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INTEGRATED CIRCUIT
µPD98405
155M AINTEGRATED CONTROLLER
DESCRIPTION
µPD98405 (NEASCOT-S20 high-performance chip that performs segmentation reassembly Acells. interface, SONET/SDH Mbps framer, clock recovery circuit supports function hardware. µPD98405 conforms AForum functions AAL-5 sublayer, Alayer, sublayer.
FEATURES
Conforms AForum. Host interface supporting bus/generic bus. interface (5/3.3 32/64 bits, MHz): Conforms Specification Generic interface (5/3.3 bits, MHz)
AAL-5 sublayer, Alayer, sublayer functions Hardware support AAL-5 processing Software support non-AAL-5 traffic SONET STS-3c/SDH STM-1 Mbps framer function Clock recovery/clock synthesizer function Supports virtual channels (VCs) Sixteen traffic shapers transmission scheduling Hardware support CBR/VBR/ABR/UBR service Supports multi-cell burst transfer transmission reception counter function Supports emulation function Receive FIFO cells External devices connectable: UTOPIA Level-1 interface 0.35 CMOS process, +5/3.3 power supply interface +5/3.3 power supply interface +3.3 +3.3 power supply
304-pin plastic 304-pin plastic FBGA
ORDERING INFORMATION
Part Number Package 304-pin plastic (0.5 fine pitch) 304-pin plastic FBGA (0.8 pitch)
µPD98405GL-PMU µPD98405S1-6C
information this document subject change without notice. Before using this document, please confirm that this latest version.
devices/types available every country. Please check with local representative availability additional information.
Document S12689EJ3V0DS00 (3rd edition) Date Published January 2001 CP(K) Printed Japan
mark
shows major revised points.
1997, 1999
µPD98405
SYSTEM CONFIGURATION EXAMPLE
AInterface Card
Control memory
PD98405
Anetwork
Expansion EEPROM
Data Sheet S12689EJ3V0DS
BLOCK DIAGRAM
UTOPIA interface
Receive data FIFO cells) Receive interface Receive controller Receive Ainterface FIFO cells) Receive framer
output block
interface Clock recovery Clock synthesizer
Host system
Sequencer Control memory interface Transmit controller Transmit interface Transmit data FIFO cells)
interface
Data Sheet S12689EJ3V0DS
Host command FIFO commands)
Control interface
input block
Transmit Ainterface FIFO cells)
Transmit framer
block Transmit queue buffer cells)
Control memory
µPD98405
µPD98405
OUTLINE PINS
304-pin plastic (0.5 fine pitch)
JTAG device EEPROM
Expansion
PD98405GL-PMU
Control memory
Data Sheet S12689EJ3V0DS
µPD98405
304-pin plastic FBGA (0.8 pitch) (Bottom view)
µPD98405S1-6C
Data Sheet S12689EJ3V0DS
µPD98405
NAME
ABRT_B: ACK64_B: AD63 AD0: AGND: ASEL_B: ATTN_B: AVDD3: BE3_B BE0_B: CA18 CA0: CBE3_B CBE0_B: CD31 CD0: CLK: COE_B: CPAR3 CPAR0: CWE_B: DEVSEL_B: DR/W_B: EMPTY_B/RCLAV: ERR_B: E2PCLK: E2PCS: E2PDI: E2PDO: FRAME_B: FULL_B/TCLAV: GND: GNT_B: HGND: HVDD3: IDSEL: INITD: INTR_B: IRDY_B: JCK: JDI: JDO: JMS: JRST_B: OE_B: PAR: PAR3 PAR0: PAR64: PCBE7_B PCBE0_B: PCI_MODE: Abort Acknowledge 64-bit transfer Address/data Ground analog part Slave address select Attention +3.3 power supply analog part Byte enable Control memory address Local port byte enable Control memory data Clock Control memory output enable Control memory parity Control memory write enable Device select read/write empty/Rx cell available Error Clock EEPROM EEPROM chip select Serial data input from EEPROM Serial data output EEPROM Cycle frame buffer full/Tx cell available Ground digital part Grant Ground high-speed part +3.3 power supply high-speed part select Initialization disable Interrupt Initiator ready JTAG test JTAG test JTAG test JTAG test JTAG test Output enable Parity party Parity bits command byte enables mode Rx0: SCLK: SEL_B: SERR_B: SIZE2 SIZE0: SR/W_B: STOP_B: TCLK: TDOC: TDOT: TENBL_B: TEST: TFKC: TFKT: TRDY_B: TSOC: Tx0: VDD3: VDD5: PERR_B: PHCE_B: PHINT_B: PHOE_B: PHRST_B: PHR/W_B: PHYALM: RCLK: RCIC: RCIT: RDIC: RDIT: PDY_B: REFCLK: RENBL_B: REQ64_B: REQ_B: RGND: ROMCS_B: ROMD7 ROMD0: ROMOE_B: RSOC: RST_B: RVDD3: Parity error chip enable interrupt output enable reset read/write Physical alarm Receive clock Receive clock input complement Receive clock input true Receive data input complement Receive data input true Target ready Reference clock Receive enable Request 64-bit transfer Request Ground receive part Expansion chip select Expansion input data Expansion output enable Receive start cell Reset +3.3 power supply receive part Receive data system clock Signal detect Slave select System error Burst size Slave read /write Stop Transmit clock Transmit data output complement Transmit data output true Transmit enable Test mode Transmit reference clock complement Transmit reference clock true Target ready Transmit start cell Transmit data +3.3 power supply digital part power supply digital part
ROMA15 ROMA0: Expansion address
Data Sheet S12689EJ3V0DS
µPD98405
CONFIGURATION
304-pin plastic (0.5 fine pitch) (1/2)
Mode VDD3 AD24 PCBE3_B IDSEL AD23 VDD5 AD22 Generic Mode VDD3 AD24 BE3_B AD23 VDD5 AD22 AD21 AD20 AD19 VDD3 AD18 AD17 AD16 BE2_B VDD5 SEL_B ASEL_B RDY_B SR/W_B VDD3 ABRT_B ERR_B VDD5 BE1_B AD15 AD14 AD13 Mode Generic Mode VDD3 AD12 AD11 AD10 VDD5 BE0_B VDD3 VDD5 OE_B DR/W_B VDD3 SIZE2 SIZE1 SIZE0 PAR3 VDD5 PAR2 PAR1 PAR0 VDD3 Mode Generic Mode VDD3 VDD5 VDD3 VDD5 VDD3 VDD5 VDD3 Mode Generic Mode
VDD3 AD12 AD11 AD10 VDD5 PCBE0_B VDD3 VDD5 ACK64_B REQ64_B VDD3 PCBE7_B PCBE6_B PCBE5_B PCBE4_B VDD5 AD63 AD62 AD61 VDD3 AD60 AD59
AD58 VDD3 AD57 AD56 VDD5 AD55 AD54 AD53 AD52 VDD3 AD51 AD50 AD49 AD48 VDD5 AD47 AD46 AD45 AD44 VDD3 AD43 AD42 AD41 AD40 VDD5 AD39 AD38 AD37 AD36 VDD3
AD35 AD34 AD33 AD32 PAR64
PCI_MODE PCI_MODE CD31 CD30 CD29 CD28 CD27 VDD3 CD26 CD25 CD24 CD23 CD22 CD21 CD20 CD19 CD18 CD17 VDD3 CD16 CD15 CD14 CD13 CD12 CD11 CD10 CD31 CD30 CD29 CD28 CD27 VDD3 CD26 CD25 CD24 CD23 CD22 CD21 CD20 CD19 CD18 CD17 VDD3 CD16 CD15 CD14 CD13 CD12 CD11 CD10
AD21 AD20 AD19 VDD3 AD18 AD17 AD16 PCBE2_B VDD5 FRAME_B IRDY_B TRDY_B DEVSEL_B VDD3 STOP_B PERR_B SERR_B VDD5 PCBE1_B AD15 AD14 AD13
Remark this document, active-low active-low signal represented XXX_B suffix following pin/signal name).
Data Sheet S12689EJ3V0DS
µPD98405
(2/2)
Mode Generic Mode VDD3 VDD3 CPAR3 CPAR2 CPAR1 CPAR0 CA18 CA17 CA16 CA15 Mode Generic Mode VDD3 CBE3_B CBE2_B CBE1_B CBE0_B CWE_B COE_B INITD SCLK VDD3 Mode Generic Mode VDD3 Rx1/TFKC Rx0/TFKT RCLK VDD3 RENBL_B RSOC EMPTY_B/ RCLAV/ RCIC FULL_B/ TCLAV/ RCIT TSOC TENBL_B TCLK VDD3 PHRST_B PHOE_B Mode Generic Mode PHYALM/ PHR/W_B
VDD3 VDD3 CPAR3 CPAR2 CPAR1 CPAR0 CA18 CA17 CA16 CA15
VDD3 CBE3_B CBE2_B CBE1_B CBE0_B CWE_B COE_B INITD SCLK ROMA15 ROMA14 ROMA13 ROMA12 ROMA11 ROMA10 ROMA9 ROMA8 VDD3 ROMA7
VDD3 ROMOE_B E2PDI E2PDO E2PCLK E2PCS Rx1/TFKC Rx0/TFKT RCLK VDD3 RENBL_B RSOC EMPTY_B/ RCLAV/ RCIC FULL_B/ TCLAV/ RCIT TSOC TENBL_B TCLK VDD3 PHRST_B PHOE_B
PHYALM/ PHR/W_B
SD/PHCE_B SD/PHCE_B REFCLK/ PHINT_B AVDD3 AGND TEST HGND TDOT TDOC HVDD3 HVDD3 RDIC RDIT HGND RVDD3 JRST_B RGND VDD5 REFCLK/ PHINT_B AVDD3 AGND TEST HGND TDOT TDOC HVDD3 HVDD3 RDIC RDIT HGND RVDD3 JRST_B RGND VDD5
CA14
CA14
ROMA6
INTR_B
INTR_B
CA13 CA12 VDD3 CA11 CA10
CA13 CA12 VDD3 CA11 CA10
ROMA5 ROMA4 ROMA3 ROMA2 ROMA1 ROMA0 ROMD7 ROMD6 ROMD5 ROMD4 ROMD3 ROMD2 ROMD1 ROMD0 ROMCS_B
RST_B GNT_B VDD3 REQ_B AD31 AD30 AD29 VDD5 AD28 AD27 AD26 AD25
RST_B GNT_B VDD3 REQ_B AD31 AD30 AD29 VDD5 AD28 AD27 AD26 AD25
Data Sheet S12689EJ3V0DS
µPD98405
Remarks Open pins which function allocated (pins marked Generic Mode column above table) Generic mode. (IDSEL) low/high level. this document, active-low active-low signal represented XXX_B suffix following pin/signal name).
Data Sheet S12689EJ3V0DS
µPD98405
304-pin plastic FBGA (0.8 pitch) (1/2)
Mode VDD3 AD24 PCBE3_B IDSEL AD23 VDD5 AD22 AD21 AD20 AD19 VDD3 AD18 AD17 AD16 PCBE2_B VDD5 IRDY_B TRDY_B
DEVSEL_B
Generic Mode VDD3 AD24 BE3_B
Mode PCBE0_B VDD3 VDD5 ACK64_B REQ64_B VDD3 PCBE7_B PCBE6_B PCBE5_B PCBE4_B VDD5 AD63 AD62 AD61 VDD3 AD60 AD58
Generic Mode BE0_B VDD3 VDD5 OE_B DR/W_B VDD3 SIZE2 SIZE1 SIZE0 PAR3 VDD5 PAR2 PAR1 PAR0 VDD3
Mode
Generic Mode
Mode
Generic Mode CD20 CD19 CD18 CD17 VDD3 CD16 CD15 CD14 CD13 CD12 CD11 CD10 VDD3 VDD3 CPAR3 CPAR2 CPAR1 CPAR0 CA18 CA17 CA16 CA15 CA14 CA13 CA12 VDD3 CA11
AD50 AD49 AD48 VDD5
VDD5
CD20
AB16 CD19 AA16 CD18
CD17
AB17 VDD3 AA17 CD16 AB18 CD15
AD23 VDD5 AD22 AD21 AD20 AD19 VDD3 AD18 AD17 AD16 BE2_B VDD5 ASEL_B RDY_B SR/W_B VDD3 ABRT_B ERR_B
AD47 AD46 AD45 AD44
VDD3
CD14 CD13 CD12
AB19 CD11 AA18
VDD3 AD43 AD42 AD41 AD40 VDD5
VDD5
CD10
AA19 AB20
AD39
AA10 AD38 AB10 AD37
VDD3
AA20 VDD3 AB21 AA21
FRAME_B SEL_B
AD36 VDD3
AA11 AD35 AB11 AD34
VDD3
AA22
PCI_MODE
CPAR3 CPAR2 CPAR1 CPAR0 CA18 CA17 CA16 CA15 CA14 CA13 CA12 VDD3 CA11
VDD3 STOP_B PERR_B SERR_B VDD5 PCBE1_B AD15 AD14 AD13 VDD3 AD12 AD11 AD10 VDD5
AD33 AD32
AB12 PAR64 AA12
VDD5 BE1_B AD15 AD14 AD13 VDD3 AD12 AD11 AD10 VDD5
VDD3
AD59 VDD3 AD57 AD56 VDD5 AD55 AD54
PCI_MODE CD31 CD30
AB13 CD29 AA13 CD28
CD31 CD30 CD29 CD28 CD27 VDD3 CD26 CD25 CD24 CD23 CD22 CD21
VDD5
CD27 VDD3
AB14 CD26 AA14 CD25
VDD3
AD53 AD52 VDD3 AD51
CD24
AB15 CD23 AA15 CD22
CD21
Remark
this document, active-low active-low signal represented XXX_B suffix following pin/signal name).
Data Sheet S12689EJ3V0DS
µPD98405
(2/2)
Mode Generic Mode CA10 Mode Generic Mode Mode Generic Mode Rx1/TFKC Rx0/TFKT RCLK VDD3 RENBL_B RSOC RCLAV/ RCIC ROMA0 FULL_B/ TCLAV/ RCIT TSOC TENBL_B TCLK VDD3 PHRST_B PHOE_B PHYALM/ PHR/W_B VDD5 AD28 AD27 AD26 AD25 VDD5 AD28 AD27 AD26 AD25 RGND VDD5 INTR_B RST_B GNT_B VDD3 REQ_B AD31 AD30 AD29 RGND VDD5 INTR_B RST_B GNT_B VDD3 ATTN_B AD31 AD30 AD29 JRST_B JRST_B Mode Generic Mode TDOT TDOC HVDD3 HVDD3 RDIC RDIT HGND RVDD3
CA10
ROMA7 ROMA6 ROMA5 ROMA4 ROMA3 ROMA2 ROMA1
Rx1/TFKC Rx0/TFKT RCLK VDD3 RENBL_B RSOC RCLAV/R
TDOT TDOC HVDD3 HVDD3 RDIC RDIT HGND RVDD3
EMPTY_B/ EMPTY_B
FULL_B/ TCLAV/ RCIT
VDD3 CBE3_B CBE2_B CBE1_B CBE0_B CWE_B COE_B INITD SCLK ROMA15 ROMA14 ROMA13 ROMA12 ROMA11
VDD3 CBE3_B CBE2_B CBE1_B CBE0_B CWE_B COE_B INITD SCLK
ROMD7 ROMD6 ROMD5 ROMD4 ROMD3 ROMD2 ROMD1 ROMD0 ROMCS_B VDD3 ROMOE_B E2PDI E2PDO E2PCLK E2PCS
VDD3
TSOC TENBL_B TCLK VDD3 PHRST_B PHOE_B PHYALM/ PHR/W_B
VDD3
SD/PHCE_B SD/PHCE_B REFCLK/ PHINT_B AVDD3 AGND TEST HGND REFCLK/ PHINT_B AVDD3 AGND TEST HGND
ROMA10 ROMA9 ROMA8 VDD3
Remarks Open pins which function allocated (pins marked Generic Mode column above table) Generic mode. (IDSEL) low/high level. this document, active-low active-low signal represented XXX_B suffix following pin/signal name).
Data Sheet S12689EJ3V0DS
µPD98405
CONTENTS
FUNCTIONS Layer Device Interface Signal
1.1.1 UTOPIA interface 1.1.2 device control interface (external mode, register
Interface Signals
1.2.1 Generic interface signals (PCI_MODE pin: level). 1.2.2 interface signal (PCI_MODE pin: high level).
Control Memory Interface Signals Interface Signals (internal mode, register JTAG Boundary Scan Signals Other Signals Power Ground Status during After Reset
ELECTRICAL SPECIFICATIONS PACKAGE DRAWING RECOMMENDED SOLDERING CONDITIONS.
Data Sheet S12689EJ3V0DS
µPD98405
FUNCTIONS
package µPD98405 pins. details each pin, refer µPD98405 User's Manual (S12250E).
Layer Device Interface Signal
Layer device interfaces include UTOPIA interface which µPD98405 exchanges Acells with device, control interface that used control device. µPD98405 supports types layer device interfaces: UTOPIA octet cell level. These modes selected setting register. layer device interface signals external layer device. When using internal layer, open pins except common pins. Even when internal layer used, external receive FIFO connected µPD98405 UTOPIA interface. 1.1.1 UTOPIA interface (1/2)
Name (Rx1 Rx0: Shared with TFKC TFKT) FBGA D18, B18, A19, E17, D17, E16, A18, Receive data bus. These pins constitute 8-bit input that inputs receive data from network µPD98405 from layer device byte format. µPD98405 reads data this synchronization with rising edge RCLK. internally pulled down. Open pins this when they used. Pull when used, pull down when used. Receive cell start position. This signal input from layer device synchronization with first byte cell data. high while first byte header input Rx0. This signal internally pulled down. Receive enable. This signal informs layer device that µPD98405 ready receive data next clock cycle. Level Function
RSOC
RENBL_B
Data Sheet S12689EJ3V0DS
µPD98405
(2/2)
Name EMPTY_B/ RCLAV (shared with RCIC) FBGA layer buffer empty/receive cell available. This signal informs µPD98405 that receive FIFO cell data transferred that device cannot supply receive data. This signal functions EMPTY_B when UTOPIA interface octet level handshake mode, indicate that data invalid current clock cycle. cell level handshake mode, functions RCLAV, informing µPD98405 that more cells supplied after transfer current cell completed. Pull down this when used. Receive clock. This clock used synchronization when µPD98405 transfers cell data from layer device reception side. system clock input SCLK output from this immediately after µPD98405 been reset. Transmit data bus. These pins form 8-bit output that outputs data transmitted network, layer device byte format. µPD98405 outputs data synchronization with rising edge TCLK. Transmit cell start position. This signal output synchronization with first byte transmit cell data. Transmit enable. This signal informs layer device that data been output current clock cycle. layer buffer full/transmit cell available. FULL_B signal informs µPD98405 that input buffer device full that device receive more data. When UTOPIA interface octet level handshake mode, device inputs inactive level this signal device receive cell data. cell level handshake mode, this signal functions TCLAV, informing µPD98405 that device receive next single cell after transfer current cell completed. Pull this when used. Transmit clock. This clock used synchronization when µPD98405 transfers cell data from layer device transmission side. system clock input SCLK output this clock Level Function
RCLK
258,
A14, E14, F14, D13, A13, E13, F13,
TSOC
TENBL_B
FULL_B/ TCLAV (shared with RCIT)
TCLK
Data Sheet S12689EJ3V0DS
µPD98405
1.1.2 device control interface (external mode, register
Name PHR/W_B (shared with PHYALM) FBGA read/write. µPD98405 indicates layer device control direction using this pin. Read Write layer output enable. µPD98405 enables output layer device making this signal low. PHCE_B (shared with PHINT_B (shared with REFCLK) layer chip enable. µPD98405 makes this signal when accesses layer device. layer interrupt. This inputs interrupt signal µPD98405 from layer device. layer device informs µPD98405 that interrupt source inputting level this pin. Pull this when used. layer reset. This signal used reset layer device. µPD98405 keeps this duration clock cycles when level input RST_B when software reset executed. Level Function
PHOE_B
PHRST_B
Caution PHCE_B/SD pins multiplexed pins their functions differ depending whether internal mode external mode selected using register). Because PHCE_B/SD pins change mode between input output depending selected mode, sure correctly register.
Data Sheet S12689EJ3V0DS
µPD98405
Interface Signals
µPD98405 supports interface generic interface. Whether interface generic interface supported selected PCI_MODE signal. interface directly connected bus. generic interface connected general with circuits. 1.2.1 Generic interface signals (PCI_MODE pin: level) (1/3)
Name AD31 297, 303, FBGA 3-state Address/data. These pins constitute 32-bit address/data bus. They input/output pins multiplexing address data bus. address transferred first input/output clock. From second clock onward, data transferred. When µPD98405 accessing bus, goes into high-impedance state. Level Function
BE3_B BE2_B BE1_B BE0_B
3-state
Byte enable. These pins determine byte that becomes valid master cycle µPD98405. BE3_B corresponds AD31 AD24, BE0_B corresponds AD0. BE3_B BE0_B into high-impedance state when µPD98405 accessing when accessing slave. parity. These pins indicate parity AD31 AD0. parity check mode register. Whether parity enabled disabled, whether parity even parity used, whether word parity byte parity used specified. When byte parity used, PAR3 indicates parity AD31 AD24, PAR0 indicates parity AD0. case word parity, PAR2 PAR0 function, PAR3 serves input/output pin. These pins function output pins when address output when data written, input pins when data read. When µPD98405 accessing bus, PAR3 PAR0 into high-impedance state. Pull these pins when they used.
PAR3 PAR2 PAR1 PAR0
3-state
OE_B
Output enable. When this low, µPD98405 allows AD31 PAR3 PAR0 operate normally 3-state pins. These pins into high-impedance state while high level input this pin. this level system where above pins have forcibly into high-impedance state.
Data Sheet S12689EJ3V0DS
µPD98405
(2/3) Name SIZE2 SIZE1 SIZE0 FBGA Burst size. These pins indicate size current transfer. They used interface with (such bus) that requires explicit burst size. SIZE2 SIZE1 SIZE0 Function 1-word transfer 2-word burst 4-word burst 8-word burst 16-word burst 12-word burst Undefined Level Function
Other than above
DR/W_B
read/write. This indicates direction access. Read access Write access Attention (DMA request). µPD98405 makes ATTN_B signal when execute operation. ATTN_B signal becomes inactive synchronization with rising edge when only more word data transferred means DMA. enable. GNT_B signal goes when arbiter grants µPD98405 mastership response request from µPD98405. When µPD98405 detects that GNT_B signal gone low, starts operation, assuming that mastership been granted. Target device ready. This signal informs µPD98405 cycle that target device ready input/output. µPD98405 makes RDY_B signal valid data exists AD31 when executes read operation. When executing write operation, µPD98405 makes ATTN_B signal target device ready reception. timing which µPD98405 samples RDY_B ABRT_B signals bring forward clock depending setting internal register (GMR register).
ATTN_B
GNT_B
RDY_B
Data Sheet S12689EJ3V0DS
µPD98405
(3/3) Name ABRT_B FBGA Abort. This signal used abort data transfer cycle. this signal goes middle data transfer cycle, that cycle aborted, µPD98405 resumes burst starting from aborted data. While level input ABRT_B, RDY_B signal does function. user bring forward timing which µPD98405 samples RDY_B ABRT_B signals clock (early mode) using internal register (GMR register). Pull this when used. System error. error detected system bus, device that manages uses this stop operation µPD98405. When level input this pin, µPD98405 stops operations, sets system error (bit register (when masked), generates interrupt. Pull this when used. Slave read/write. This signal determines direction slave access. Read access Write access Slave select. This signal asserted active (low) when slave access selected µPD98405. Make sure that SEL_B signal goes same time after ASEL_B signal gone low. addition, insert inactive period system clocks more after SEL_B signal become inactive before becomes active next time. Slave address select. ASEL_B signal selects direct address register µPD98405. When level input ASEL_B, µPD98405 samples first rising edge CLK. Clock. This system clock input pin. clock input. Reset. RST_B signal initializes µPD98405 starting). After reset, µPD98405 start normal operation. When level input RST_B, internal state machine registers µPD98405 reset, 3-state signals into high-impedance state. Reset input asynchronous. input during operation, operation status that time lost. Keep RST_B least duration clock cycle. Interrupt output. Pull this signal because open-drain signal. This signal informs that unmasked interrupt interrupt register been set. Level Function
ERR_B
SR/W_B
SEL_B
ASEL_B
RST_B
INTR_B
N-ch opendrain
Data Sheet S12689EJ3V0DS
µPD98405
1.2.2 interface signal (PCI_MODE pin: high level) µPD98405 32-/64-bit interface. This interface directly connected bus. addition, µPD98405 also serial EEPROM interface expansion interface. interface signals (1/2)
Name AD31 297, 303, FBGA 3-state Level Function
Address/data. AD31 constitute 32-bit multiplexed address/data bus. When µPD98405 operates master, drives address first clock transfers data second clock onward.
PCBE3_B PCBE2_B PCBE1_B PCBE0_B
3-state
command/byte enable. These signals define "bus command" (bus transaction that occurs) address phase. data phase, they indicate which byte lane holds valid data. PCBE3_B corresponds byte (bits 24), PCBE0_B corresponds byte (bits Parity. This signal indicates even parity AD31 PCBE3_B PCBE0_B pins, including signal. When µPD98405 operating master, signal becomes active address write data phases. When µPD98405 operating target, this signal becomes active read data phase. Frame. This signal indicates start period transaction. When this signal asserted active, indicates start transaction. While active, data transferred. deasserted inactive when next data transfer phase will transfer last data transaction. Target ready. This signal goes when target device ready complete transaction current data. This signal used combination with IRDY_B, read/write data transfer executed when both IRDY_B TRDY_B signals low. Initiator ready. This signal goes when initiator ready complete transaction current data. This signal used combination with TRDY_B, read/write data transfer executed when both IRDY_B TRDY_B low. FRAME_B IRDY_B both inactive, cycle executed. wait cycle inserted until both IRDY_B TRDY_B asserted active.
3-state
FRAME_B
Sustained 3-state
TRDY_B
Sustained 3-state
IRDY_B
Sustained 3-state
Data Sheet S12689EJ3V0DS
µPD98405
(2/2)
Name STOP_B FBGA Sustained 3-state Sustained 3-state Stop. This signal goes when target device requests master device stop current transaction. Device select. When µPD98405 operating target, makes this signal after FRAME_B signal been asserted active µPD98405 recognized address. When µPD98405 operating master, samples this signal check target device been selected. Initialization device select. This signal high when configuration register µPD98405 read written. Request. µPD98405 makes this signal request arbiter mastership. Grant. This signal goes when arbiter grants µPD98405 mastership. Parity error. This signal indicates that µPD98405 detected data parity error. enabled when "Parity Error Response" configuration register System error. This signal indicates that µPD98405 detected address parity error. enabled when both "Parity Error Response" "System Error Enable" bits configuration register Interrupt output. Pull this signal because open-drain signal. INTR_B informs that unmasked interrupt interrupt register been set. Clock. This system clock input pin. clock input. Reset. This signal initializes µPD98405 starting, etc.). When level input RST_B, internal state machine registers µPD98405 reset, 3-state signals into high-impedance state. reset input asynchronous. When this signal input during operation, operating status that time lost. Keep RST_B least duration clock cycle. After reset, access µPD98405 duration least clocks. Level Function
DEVSEL_B
IDSEL
REQ_B
Note
GNT_B
PERR_B
Sustained 3-state
SERR_B
N-ch open-drain
INTR_B
N-ch open-drain
RST_B
Note According "PCI Local Specification Revision 2.1", REQ_B should into high-impedance state while level input RST_B pin. REQ_B µPD98405, however, outputs high level.
Data Sheet S12689EJ3V0DS
µPD98405
64-bit expansion interface signals Open AD63 AD32, PCBE7_B PCBE4_B, PAR64 when using 32-bit interface.
Name AD63 AD32 103, 109, FBGA AA1, AB3, AA5, AB4, AB5, AA6, AB6, AA7, AB7, AB8, AA9, AB9, W10, AA10, AB10, V10, AA11, AB11, W11, 3-state Address/data. AD63 AD32 constitutes 32-bit multiplexed address/data that extends bits. This address/data transfers higher bits 64-bit address address phase. outputs higher bits 64-bit data data phase when both REQ64_B ACK64_B asserted. Level Function
PCBE7_B PCBE6_B PCBE5_B PCBE4_B
3-state
command/byte enable. These signals define "bus command" (bus transaction that occurs) address phase. data phase, they indicate which byte lane holds valid data. PCBE7_B corresponds AD63 AD56, PCBE4_B corresponds AD39 AD32. Parity This signal indicates even parity AD63 AD32 PCBE7_B PCBE4_B pins, including PAR64 signal. When µPD98405 operating master, signal becomes active address write data phases. When µPD98405 operating target, becomes active read data phase. Request This signal indicates start period 64-bit transaction. When µPD98405 operating master, asserts REQ64_B active request 64-bit data transfer. REQ64_B same FRAME_B timing. Connect external pull-up resistor when using 32-bit bus. Acknowledge When µPD98405 operating target, makes this signal after REQ64_B signal been asserted active µPD98405 recognized address. When µPD98405 operating master, samples this signal check whether target device acknowledged 64-bit transfer. ACK64_B same DEVSEL_B timing. Connect external pull-up resistor when using 32bit bus.
PAR64
AB12
3-state
REQ64_B
Sustained 3-state
ACK64_B
Data Sheet S12689EJ3V0DS
µPD98405
Serial EEPROM interface signals µPD98405 serial EEPROM interface supporting MICROWIRE
interface.
Through this serial
EEPROM interface, contents configuration register loaded from EEPROM connected. Remark recommended that National Semiconductor's "NM93C46" connected EEPROM.
Name E2PCS E2PDI FBGA EEPROM chip select. This chip select signal EEPROM. EEPROM data input. This signal connected data output EEPROM. This signal internally pulled down. E2PDO E2PCLK EEPROM data output. This signal connected data input EEPROM. EEPROM clock. This supplies clock necessary transferring data with EEPROM. divides clock input output. Level Function
Expansion interface signals. µPD98405 expansion interface option.
Name ROMA15 ROMA0 207, 213, FBGA J17, J18, J22, J21, J19, H22, H21, H19, H18, G22, G21, G19, G17, F21, E22, F19, F18, D22, E21, E19, E18, D21, address. These address signals access expansion ROM. Level Function
ROMD7 ROMD0
data. These expansion data signals internally pulled down. select. This chip select signal expansion ROM. output enable. This signal enables output buffer expansion during read operation.
ROMCS_B ROMOE_B
Data Sheet S12689EJ3V0DS
µPD98405
Control Memory Interface Signals
control memory interface used µPD98405 access external control memory external layer device. This interface consists 19-bit address bus, 32-bit data bus. control memory host system accessed only through this interface.
Name CD31 123, 130, 136, 144, 150, 159, FBGA U13, V13, AB13, AA13, W13, AB14, AA14, W14, AB15, AA15, U15, V15, AB16, AA16, W16, AA17, AB18, V16, W17, V17, AB19, W18, U17, AA19, AB20, W19, AA22, Y22, W21, V18, V19, U18, U19, T18, 3-state Control memory data. These 3-state pins constitute 32-bit data that used transfer data from control memory layer device. These signals internally pulled down. Level Function
CPAR3 CPAR0
Control memory parity. These signals indicate parity CD31 every bits. read cycle, µPD98405 checks parity (when enabled). write cycle, outputs parity. These signals internally pulled down. Control memory address. These signals constitute 19-bit address that outputs address control memory layer device during read/write operation. Control memory write enable. This signal indicates direction which control memory accessed. Read access Write access Control memory output enable. This signal enables disables data output control memory. Local port byte enable. These signals indicate byte control port read written. Initialization disable. This signal used disable automatic initialization control memory during chip test. Directly connect INITD during normal operation other than test.
CA18
166, 173, 181,
U21, T17, T19, T21, T22, R18, R17, R22, P19, P21, P22, P18, P17, N21, N22, N18, N17, M18,
CWE_B
COE_B
CBE3_B CBE0_B INITD
L19, L22, L21,
Data Sheet S12689EJ3V0DS
µPD98405
Interface Signals (internal mode, register
interface used connect module such optical transceiver/receiver.
Name RDIT RDIC FBGA P-ECL True P-ECL complement P-ECL True Receive serial data input. Pull this when used. Receive serial data input. Pull down this when used. Receive serial clock input. This used when external clock recovery/synthesizer connected (PLL register Pull this when used. Receive serial clock input. This used when external clock recovery/synthesizer connected (PLL register Pull down this when used. Reference clock. This inputs system clock (19.44 MHz) internal clock recovery/synthesizer. Pull this when used. Transmit serial data output. Transmit serial data output. Level Function
RCIT (shared with FULL_B)
RCIC (shared with EMPTY_B) REFCLK (shared with PHINT_B) TDOT TDOC
P-ECL complement
P-ECL True P-ECL complement P-ECL True
TFKT (shared with Rx0)
Transmit serial clock input. This used when external clock recovery/synthesizer connected (PLL register Pull this when used. Transmit serial clock input. This used when external clock recovery/synthesizer connected (PLL register Pull down this when used. layer alarm detection signal. This signal asserted active (high) when internally monitored error statuses (CMDARM, LOS, OOF, LOF, LOP, OCD, LCD, Line AIS, Path AIS, Line RDI, Path RDI) detected. error status reported selected using internal AMR1 AMR2 registers. more error statuses selected. Signal detect. This inputs signal detect signal (when detected, etc.) device. When level input this pin, µPD98405 assumes detection. Pull this when used.
TFKC (shared with Rx1) PHYALM (shared with PHR/W_B)
P-ECL complement
(shared with PHCE_B)
Data Sheet S12689EJ3V0DS
µPD98405
JTAG Boundary Scan Signals
Remark This function supported upon request. These signals conform IEEE1149.1 JTAG Boundary-Scan Standard.
Name FBGA 3-state Boundary scan data input. Connect this ground when used. Boundary scan data output. Open this when used. Boundary scan mode select. Connect this ground when used. Boundary scan clock input. Input clock MHz. Connect this ground when used. Boundary scan reset. Connect this ground when used. Level Function
JRST_B
Other Signals
Name SCLK FBGA system clock. This supplies clock block operation. maximum clock frequency MHz. Ver. before: MAX. Ver. 4.0: MAX. PCI/generic mode. This selects generic mode. Generic mode mode Internal test pin. Open this pin. When high level input this pin, test mode selected. This signal internally pulled down. test mode used internal testing cannot used user. Level Function
PCI_MODE
TEST
Data Sheet S12689EJ3V0DS
µPD98405
Power Ground
Name VDD5 FBGA power (digital block). Supply these pins when using interface mode. mode, supply +3.3 +3.3 power (digital block). These pins supply +3.3 chip. Function
105, 287, AA4,
VDD3
111, 125, 138, 151, 154, 175, 190, 208, 227, 245, 254,
AA3, AA8, V11, V14, AB17, AA20, Y21, R21, M19, H17, C21, D16, B14,
AVDD3
+3.3 power (analog block). Supply power with high quality this inserting filter between AVDD3 GND. +3.3 power (high-speed block). Supply power with high quality this inserting filter between HVDD3 HGND. +3.3 power (receive block). Supply power with high quality this inserting filter between RGND this pin. Ground (digital block). These pins ground chip.
HVDD3
275,
D10,
RVDD3
104, 110, 117, 124, 131, 137, 145, 152, 153, 160, 167, 174, 182, 189, 199, 214, 228, 229, 243, 252, 259, 292, 298, 272,
AA2, AB2, U10, AA12, U14, W15, U16, AA18, AB21, AA21, V21, U22, R19, N19, M22, K19, F22, B21, A21, A17, A15, B13, E10,
AGND HGND RGND
Ground (analog block) Ground (high-speed block) Ground (receive block)
Data Sheet S12689EJ3V0DS
µPD98405
Status during After Reset
(1/2)
Name RENBL_B RCLK TSOC TENBL_B TCLK PHR/W_B (external PHY)/PHYALM (internal PHY) PHOE_B PHCE_B (external PHY)/SD (internal PHY) AD31 PCBE3_B PCBE0_B (PCI)/BE3_B BE0_B (Generic) FRAME_B TRDY_B IRDY_B STOP_B DEVSEL_B REQ_B (PCI)/ATTN_B (Generic) PERR_B SERR_B INTR_B AD63 AD61 (PCI)/PAR2 PAR0 (Generic) AD60 AD56 (PCI)/(Generic) AD55 AD32 (PCI)/(Generic) PCBE7_B PCBE5_B (PCI)/SIZE2 SIZE0 (Generic) PCBE4_B (PCI)/PAR3 (Generic) PAR64 REQ64_B(PCI)/DR/W_B (Generic) E2PCS E2PDO E2PCLK ROMA15 ROMA0 ROMCS_B ROMOE_B CD31 CPAR3 CPAR0 CA18 During Reset output output Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z Hi-Z Hi-Z (input) Hi-Z (input)/Hi-Z (output) Hi-Z (input)/0 Hi-Z (input)/0 Hi-Z (input) Hi-Z (input) Hi-Z/1 After Reset output output Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z (input) Hi-Z Hi-Z Hi-Z (input) Hi-Z (input)/Hi-Z (output) Hi-Z (input)/0 Hi-Z (input)/0 Hi-Z (input) Hi-Z (input) Hi-Z/1
Data Sheet S12689EJ3V0DS
µPD98405
(2/2)
Name CWE_B COE_B TDOT TDOC
Note
During Reset Undefined Undefined Hi-Z
After Reset Undefined Undefined Hi-Z
Note During JRST_B input Remark internal mode (PHM register after reset.
Data Sheet S12689EJ3V0DS
µPD98405
ELECTRICAL SPECIFICATIONS
Some electrical specifications µPD98405 vary depending device version. version history described below explanation. Device Version History
Part Number Version V3.0 V3.1 V4.0 Register 0102H 0103H 0104H 0103H 0104H Rank
µPD98405GL-PMU
µPD98405S1-6C
V3.1 V4.0
rank assigned corresponding version. rank indicated marking actual device (see figure below).
JAPAN D98405 xxxx xxxx
number :Rank
Hereafter, electrical specification items indicated individual device version specifications vary depending device version. Ranks each version defined follows. V4.0: µPD98405GL-PMU Rank
µPD98405S1-6C
Rank
V3.1 before: µPD98405GL-PMU Ranks
µPD98405S1-6C
Rank
Data Sheet S12689EJ3V0DS
µPD98405
Absolute Maximum Ratings
Parameter Supply voltage Symbol VDD5 Input/output voltage
Note
Conditions
Rating -0.5 +4.6 -0.5 +6.5
Unit
VI/VO
Normal P-ECL
Note
-0.5 +6.6 -0.5 +6.6 -0.5 +4.6 +150
Operating ambient frequency
V4.0 V3.1 before
Storage temperature
Tstg
Notes VDD5: Clamping diode-dedicated power supply supplying clamping diode, device protected from reflection wave. Caution Product quality suffer absolute maximum rating exceeded even momentarily parameter. That absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions that ensure that absolute maximum ratings exceeded. Recommended Operating Conditions
Parameter Supply voltage Symbol Conditions +85°C +70°C VDD5
Note
MIN. +3.15 +3.0 +3.15 +3.0 +4.75 +2.0 +2.0 1.49 -0.5 -0.5 2.82
TYP. +3.3 +3.3 +3.3 +3.3 +5.00
MAX. +3.45 +3.6 +3.45 +3.6 +5.25 +5.5 VDD5 0.40 +0.8 +0.8 1.50 1900
Unit
+3.3 +85°C +3.3 +70°C
Operating ambient temperature
V4.0 V3.1 before
Input voltage, high
VIH1 VIH2 VIH3 VIH4
Input pins other than P-ECL +3.3 P-ECL Input pins other than P-ECL +3.3 P-ECL
Input voltage,
VIL1 VIL2 VIL3 VIL4
Input differential voltage
VIDIFF
Note VDD5: Clamping diode-dedicated power supply
Data Sheet S12689EJ3V0DS
µPD98405
Characteristics
Parameter Output voltage, high Symbol VOH1 VOH2 VOH3 VOH4 Output voltage, VOL1 VOL2 VOL3 VOL4 VOL5 Supply current Input leakage current (normal input) Input leakage current
Note
Conditions -3.0 -500 -2.0
Note Note Note
MIN. +2.4
TYP.
MAX.
Unit
(+3.3 PCI) PCI)
0.88 +2.4 1.140 0.690 0.144
(P-ECL)
Note Note
1500
(+3.3 PCI)
+0.4 +0.55 +0.55 2.175 1.755
Note Note
PCI) PCI)
(P-ECL) fCLK MHz, normal operation VDD, +85°C VDD, +70°C
Notes VOH1 VOL1 applied following pins (output pins other than PCI): CD31 CD0, CPAR3 CPAR0, CA18 CA0, CBE3_B CBE0_B, CWE_B, COE_B, JDO, RCLK, RENBL_B, TSOC, TENBL_B, TCLK, Tx0, PHCE_B, PHOE_B, PHRW_B, E2PCS, E2PDO, E2PCLK VOH2, VOH3, VOL2 applied following pins (PCI output pins): AD63 AD0, PCBE7_B PCBE0_B, PAR, PAR64, REQ_B, INTR_B, FRAME_B, REQ64_B, TRDY_B, IRDY_B, DEVSEL_B, STOP_B, SERR_B, PERR_B VOL3 applied following pins (with PCI): AD31 AD0, PCBE3_B PCBE0_B, PAR, REQ_B, INTR_B VOL4 applied following pins (with PCI): FRAME_B, TRDY_B, IRDY_B, DEVSEL_B, STOP_B, SERR_B, PERR_B, AD64 AD32, PCBE7_B PCBE4_B, ACK64_B, REQ64_B, PAR64 applied following pins: E2PDI, ROMD7 ROMD0, RSOC, Rx2, CPAR3 CPAR0, CD31 CD0, PCI_MODE, TEST
Data Sheet S12689EJ3V0DS
µPD98405
Capacitance +25°C,
Parameter Input capacitance input capacitance IDSEL input capacitance Output capacitance capacitance Symbol CCLK CIDSEL COUT CI/O Conditions MIN. TYP. MAX. Unit
On-chip pull-down resistor
Parameter On-chip pull-down resistance
Note
Symbol
Conditions +85°C +70°C
MIN. 18.8 21.8
TYP.
MAX. 107.1 107.1
Unit
Note applied following pins: E2PDI, ROMD7 ROMD0, RSOC, Rx2, CPAR3 CPAR0, CD31 CD0, PCI_MODE, TEST
Data Sheet S12689EJ3V0DS
µPD98405
Characteristics (Output load: input (BUS interface clock pin)
Parameter cycle time high-level width low-level width slew rate Symbol tCYCLK tCLKH tCLKL slewCLK Conditions MIN. TYP. MAX. Unit V/ns
(MIN.) tCLKH tCYCLK tCLKL (MAX.)
SCLK input (internal system clock SCLK pin)
Parameter SCLK cycle time Symbol tCYSCLK V4.0 V3.1 before SCLK high-level width tSCLKH V4.0 V3.1 before SCLK low-level width tSCLKL V4.0 V3.1 before SCLK slew rate slewSCLK Conditions MIN. TYP. MAX. Unit V/ns
(MIN.) SCLK tSCLKH tCYSCLK tSCLKL (MAX.)
input
Parameter low-level width slew rate Symbol tRSTL slewRST Conditions MIN. tCYCLK TYP. MAX. Unit mV/ns
Data Sheet S12689EJ3V0DS
µPD98405
Interface
master read
Parameter FRAME_B, REQ64_B valid time FRAME_B, REQ64_B float time (Address) valid time (Address) float time (Data) setup time (Data) hold time PCBE_B valid time PCBE_B float time IRDY_B valid time IRDY_B float time TRDY_B setup time TRDY_B hold time DEVSEL_B, ACK64_B setup time DEVSEL_B, ACK64_B hold time STOP_B setup time STOP_B hold time valid time float time setup time hold time PERR_B valid time PERR_B float time Symbol tDFRAME tDFRAMEF tDADDR tDADDRF tSDATA tHDATA tDPCBE tDPCBEF tDIRDY tDIRDYF tSTRDY tHTRDY tSDEVSEL tHDEVSEL tSSTOP tHSTOP tDPAR tDPARF tSPAR tHPAR tDPERR tDPERRF Conditions MIN. TYP. MAX. Unit
Data Sheet S12689EJ3V0DS
µPD98405
master read
tDFRAMEF FRAME_B REQ64_B tDFRAME tDADDRF
tDADDR AD31
tSDATA (Data) tSDATA
tHDATA
(Address)
tHDATA (Data)
AD63 AD32 tDPCBE PCBE3_B PCBE0_B tDPCBE PCBE7_B PCBE4_B tDIRDY IRDY_B tSTRDY TRDY_B tSDEVSEL tDPARF (Output)
tDPCBEF
tDPCBEF
tDIRDYF
tHTRDY
tHDEVSEL
DEVSEL_B ACK64_B tDPAR PAR64
tSPAR (Input)
tHPAR
tDPERR PERR_B
tDPERRF
tHSTOP STOP_B tSSTOP
Data Sheet S12689EJ3V0DS
µPD98405
master write
Parameter FRAME_B, REQ64_B valid time FRAME_B, REQ64_B float time (Address) valid time Data valid time Data float time PCBE_B valid time PCBE_B float time IRDY_B valid time IRDY_B float time TRDY_B setup time TRDY_B hold time STOP_B setup time STOP_B hold time DEVSEL_B, ACK64_B setup time DEVSEL_B, ACK64_B hold time valid time float time PERR_B setup time PERR_B hold time Symbol tDFRAME tDFRAMEF tDADDR tDDATA tDDATAF tDPCBE tDPCBEF tDIRDY tDIRDYF tSTRDY tHTRDY tSSTOP tHSTOP tSDEVSEL tHDEVSEL tDPAR tDPARF tSPERR tHPERR Conditions MIN. TYP. MAX. Unit
Data Sheet S12689EJ3V0DS
µPD98405
master write
tDFRAMF FRAME_B REQ64_B tDFRAME tDADDR AD31 (Address) tDDATA (Data) tDDATAF AD63 AD32 tDPCBE PCBE3_B PCBE0_B tDPCBE PCBE7_B PCBE4_B tDIRDY IRDY_B tSTRDY TRDY_B tSDEVSEL tDPAR PAR64 (Output) (Output) tSPERR PERR_B tHPERR tHDEVSEL tHTRDY tDIRDYF tDPCBEF (Data) tDPCBEF tDDATAF
DEVSEL_B ACK64_B
tDPARF
tHSTOP STOP_B tSSTOP
Data Sheet S12689EJ3V0DS
µPD98405
Target read
Parameter FRAME_B setup time FRAME_B hold time (Address) setup time (Address) hold time (Data) valid time (Data) float time PCBE_B setup time PCBE_B hold time IRDY_B setup time IRDY_B hold time TRDY_B valid time TRDY_B float time STOP_B valid time STOP_B float time DEVSEL_B valid time DEVSEL_B float time setup time hold time valid time float time PERR_B setup time PERR_B hold time Symbol tSFRAME tHFRAME tSADDR tHADDR tDDATA tDDATAF tSPCBE tHPCBE tSIRDY tHIRDY tDTRDY tDTRDYF tDSTOP tDSTOPF tDDEVSEL tDDEVSELF tSPAR tHPAR tDPAR tDPARF tSPERR tHPERR Conditions MIN. TYP. MAX. Unit
Data Sheet S12689EJ3V0DS
µPD98405
Target read
tSFRAME FRAME_B tSADDR AD31 tSPCBE PCBE3_B PCBE0_B tSIRDY IRDY_B tDTRDYF tDTRDY TRDY_B tDDEVSELF tDDEVSEL DEVSEL_B tSPAR
(Input)
(Address)
tHFRAME
tHADDR
tDDATA
tDDATAF (Data)
tHPCBE
tHIRDY
tHPAR
tDPAR
tDPARF (Output) tHPERR
PERR_B
tSPERR
tDSTOPF STOP_B tDSTOP
Data Sheet S12689EJ3V0DS
µPD98405
Target write
Parameter FRAME_B setup time FRAME_B hold time (Address) setup time (Address) hold time (Data) setup time (Data) hold time PCBE_B setup time PCBE_B hold time IRDY_B setup time IRDY_B hold time TRDY_B valid time TRDY_B float time STOP_B valid time STOP_B float time DEVSEL_B valid time DEVSEL_B float time setup time hold time PERR_B valid time PERR_B float time Symbol tSFRAME tHFRAME tSADDR tHADDR tSDATA tHDATA tSPCBE tHPCBE tSIRDY tHIRDY tDTRDY tDTRDYF tDSTOP tDSTOPF tDDEVSEL tDDEVSELF tSPAR tHPAR tDPERR tDPERRF Conditions MIN. TYP. MAX. Unit
Data Sheet S12689EJ3V0DS
µPD98405
Target write
tSFRAME FRAME_B tHADDR tSADDR AD31 tSPCBE PCBE3_B PCBE0_B tSIRDY IRDY_B tDTRDYF tDTRDY TRDY_B tDDEVSELF tDDEVSEL DEVSEL_B tSPAR
(Input)
(Address)
tHFRAME tSDATA tHDATA (Data) tHPCBE
tHIRDY
tHPAR (Input) tDPERRF tDPERR
PERR_B
tDSTOPF STOP_B tDSTOP
Data Sheet S12689EJ3V0DS
µPD98405
arbitration
Parameter REQ_B valid time GNT_B setup time GNT_B hold time Symbol tDREQ tSGNT tHGNT Conditions MIN. TYP. MAX. Unit
arbitration
tDREQ REQ_B tSGNT GNT_B tHGNT
64-bit expansion
Parameter REQ64_B setup time RST_B REQ64_B hold time (from RST_B Symbol Conditions
MIN.
tCYCLK
TYP.
MAX.
Unit
tSREQ64
tHREQ64
V4.0
V3.1 before
64-bit extension
RST_B tSREQ64 REQ64_B tHREQ64
Data Sheet S12689EJ3V0DS
µPD98405
Configuration read
Parameter FRAME_B setup time FRAME_B hold time (Address) setup time (Address) hold time (Data) valid time (Data) float time PCBE_B setup time PCBE_B hold time IDSEL setup time IDSEL hold time IRDY_B setup time IRDY_B hold time TRDY_B valid time TRDY_B float time DEVSEL_B valid time DEVSEL_B float time valid time float time setup time hold time PERR_B setup time PERR_B hold time Symbol tSFRAME tHFRAME tSADDR tHADDR tDDATA tDDATAF tSPCBE tHPCBE tSIDSEL tHIDSEL tSIRDY tHIRDY tDTRDY tDTRDYF tDDEVSEL tDDEVSELF tDPAR tDPARF tSPAR tHPAR tSPERR tHPERR Conditions MIN. TYP. MAX. Unit
Data Sheet S12689EJ3V0DS
µPD98405
Configuration read
tHFRAME tSFRAME FRAME_B tSADDR AD31 tSPCBE PCBE3_B PCBE0_B tSIDSEL IDSEL tHIRDY tHIDSEL
(Address)
tHADDR
tDDATA
tDDATAF (Data)
tHPCBE
tSIRDY IRDY_B
tDTRDYF tDTRDY TRDY_B tDDEVSELF tDDEVSEL DEVSEL_B tSPAR (Input) tHPAR tDPAR tDPARF (Output) tHPERR
tSPERR PERR_B
Data Sheet S12689EJ3V0DS
µPD98405
EEPROM interface
Parameter E2PCLK high-level width E2PCLK low-level width E2PCLK E2PCS valid time E2PCS E2PCLK E2PCLK E2PDO valid time E2PDI E2PCLK setup time E2PCLK E2PDI hold time E2PCS E2PDI (Status) valid delay time E2PCS E2PDI (Status) invalid delay time Symbol tWE2PCKLH tWE2PCLKL tDE2PCS tSE2PCS tDE2PDO tSE2PDI tHE2PDI tDE2PSTV tDE2PSTI Conditions MIN. TYP. MAX. Unit
tCYCLK tCYCLK tCYCLK tCYCLK tCYCLK tCYCLK
EEPROM interface
tWE2PCLKH E2PCLK tDE2PCS E2PCS tDE2PDO E2PDO tSE2PDI E2PDI (READ) tDE2PSTV E2PDI (Status) (Status) tDE2PSTI tHE2PDI tSE2PCS tDE2PCS tWE2PCLKL
Data Sheet S12689EJ3V0DS
µPD98405
Expansion interface
Parameter ROMOE_B ROMD valid time ROMCS_B ROMD valid time ROMA valid time ROMD valid time ROMOE_B ROMD float time ROMCS_B ROMD float time ROMA invalid time ROMD hold time Symbol tDROMOE tDROMCS tROMACC tHROMOE tHROMCS tHROMA Conditions ROMCS_B VOL, ROMA valid ROMOE_B VOL, ROMA valid ROMCS_B ROMOE_B ROMCS_B VOL, ROMA valid ROMOE_B VOL, ROMA valid ROMCS_B ROMOE_B MIN. TYP. MAX. Unit
Expansion interface
ROMCS_B
ROMOE_B
ROMA15 ROMA0 tDROMOE ROMD7 ROMD0 tDROMCS tHROMOE tHROMCS tROMACC tHROMA
Data Sheet S12689EJ3V0DS
µPD98405
Generic interface Slave write access
Parameter ASEL_B setup time ASEL_B hold time SEL_B setup time SEL_B hold time Address setup time Address hold time Data setup time Data hold time setup time hold time SR/W_B setup time SR/W_B hold time Symbol tSASEL tHASEL tSSEL tHSEL tSDADD tHDADD tSDDAT tHDDAT tSPAR1 tHPAR1 tSSRW tHSRW Conditions MIN. tCYCLK TYP. MAX. Unit
Slave write access
tSASEL ASEL_B tSSEL SEL_B tSDADD AD31 Address tSSRW SR/W_B tSPAR1 PAR3 PAR0 (Input) tHPAR1 tSPAR1 (Input) tHPAR1 tHSRW tHDADD tSDDAT Data tHDDAT tHSEL tHASEL
Data Sheet S12689EJ3V0DS
µPD98405
Slave read access
Parameter ASEL_B setup time ASEL_B hold time SEL_B setup time SEL_B hold time Address setup time Address hold time data delay time data float time setup time hold time delay time float time SR/W_B setup time SR/W_B hold time Symbol tSASEL tHASEL tSSEL tHSEL tSDADD tHDADD tDDDAT tFDDAT tSPAR1 tHPAR1 tDPAR1 tFPAR1 tSSRW tHSRW Conditions MIN. tCYCLK TYP. MAX. Unit
Slave read access
tSASEL ASEL_B tSSEL SEL_B tSDADD AD31 Address (input) tSSRW SR/W_B tSPAR1 PAR3 PAR0 (Input) tHPAR1 tDPAR1 (Output) tFPAR1 tHSRW tHDADD tDDDAT Data (output) tFDDAT tHSEL tHASEL
Data Sheet S12689EJ3V0DS
µPD98405
write access
Parameter ATTN_B delay time GNT_B setup time GNT_B hold time DR/W_B delay time SIZE delay time address delay time address/data float time BE_B delay time BE_B float time delay time float time RDY_B setup time RDY_B hold time Symbol tDATTN tSGNT tHGNT tDDRW tDSIZE tDSADD tFSADD tDSBE tFSBE tDPAR2 tFPAR2 tSRDY tHRDY Conditions MIN. TYP. MAX. Unit
write access (Example: 2-word burst)
tDATTN ATTN_B tSGNT GNT_B tDDRW DR/W_B tDSIZE SIZE2 SIZE0 tDSADD AD31
Address (output)
tDATTN
tHGNT
tDDRW
tDSIZE
tFSADD Data (output) tDSBE Data (output) tFSBE (output) tSRDY (output) tHRDY
BE3_B BE0_B
RDY_B (Normal mode) tSRDY RDY_B (Early mode) tDPAR2 PAR3 PAR0
(Output) (Output)
tHRDY
tDPAR2
(Output)
tFPAR2
Data Sheet S12689EJ3V0DS
µPD98405
read access
Parameter ATTN_B delay time GNT_B setup time GNT_B hold time DR/W_B delay time SIZE delay time address delay time address/data float time BE_B delay time BE_B float time delay time float time RDY_B setup time RDY_B hold time Data setup time Data hold time setup time hold time Symbol tDATTN tSGNT tHGNT tDDRW tDSIZE tDSADD tFSADD tDSBE tFSBE tDPAR2 tFPAR2 tSRDY tHRDY tSSDAT tHSDAT tSPAR2 tHPAR2 Conditions MIN. TYP. MAX. Unit
Data Sheet S12689EJ3V0DS
µPD98405
read access (Example: 2-word burst)
tDATTN ATTN_B tSGNT GNT_B tDDRW DR/W_B tDSIZE SIZE2 SIZE0 tDSADD AD31
Address (output)
tDATTN
tHGNT
tDDRW
tDSIZE
tFSADD
tSSDAT Data (input)
tHSDAT Data (input) tFSBE
tDSBE BE3_B BE0_B (output) tSRDY RDY_B (Normal mode) tSRDY RDY_B (Early mode) tDPAR2 PAR3 PAR0
(Output)
(output) tHRDY
tHRDY
tFPAR2
tSPAR2
(Input)
tHPAR2
(Input)
Data Sheet S12689EJ3V0DS
µPD98405
ABRT_B, ERR_B, OE_B pins
Parameter ABRT_B setup time ABRT_B hold time ERR_B setup time ERR_B hold time OE_B AD/PAR output determination time OE_B AD/PAR high-impedance determination time Symbol tSABRT tHABRT tSERR tHERR tDADOE tFADOE Conditions MIN. TYP. MAX. Unit
abort/ERR_B timing
ATTN_B
GNT_B tSABRT ABRT_B tHABRT
tSERR ERR_B
tHERR
OE_B timing
tFADOE AD31 PAR3 PAR0 Data (output) tDADOE Data (output)
OE_B
Data Sheet S12689EJ3V0DS
µPD98405
UTOPIA interface (external mode) Transmission operation
Parameter SCLK TCLK delay time TCLK delay time TCLK TSOC delay time TCLK TENBL_B delay time FULL_B setup time FULL_B hold time Symbol tDTCLK tDTX tDTSOC tDTEN tSFULL tHFULL Conditions MIN. TYP. MAX. Unit
Reception operation
Parameter SCLK RCLK delay time setup time hold time RSOC setup time RSOC hold time RCLK RENBL_B delay time EMPTY_B setup time EMPTY_B hold time Symbol tDRCLK tSRX tHRX tSRSOC tHRSOC tDREN tSEMPT tHEMPT Conditions MIN. TYP. MAX. Unit
SCLK
TCLK
tDTCLK
SCLK
RCLK
tDRCLK
Data Sheet S12689EJ3V0DS
UTOPIA interface Transmission timing
TCLK tDTX `00H' Invalid
Data Sheet S12689EJ3V0DS
TSOC tDTSOC tDTSOC tDTEN
tDTEN
TENBL_B
tSFULL FULL_B
tHFULL
Aheader Payload data
µPD98405
UTOPIA interface Reception timing
RCLK tSRX tHRX
Invalid
Invalid
Data Sheet S12689EJ3V0DS
RSOC tHRSOC tDREN
tSRSOC RENBL_B
tDREN
tSEMPT EMPTY_B
tHEMPT
Aheader Payload data
µPD98405
µPD98405
Control memory access Write
Parameter CWE_B setup time CBE_B CWE_B setup time CWE_B low-level width Symbol tSCWE tSCWE2 tCWEL V4.0 tCYSCLK tCYSCLK V3.1 before hold time (from CWE_ COE_B hold time (from CWE_ hold time (from CWE_B CBE_B hold time (from CWE_B output time CWE_B CPAR hold time (from CWE_B CPAR output time CWE_B tHCD tHCOE tHCA tHCBE tSCD tHCPAR tSCPAR Conditions MIN. tSCLKL tSCLKL tSCLKL TYP. MAX. Unit
Write timing
SCLK
CBE3_B CBE0_B tSCWE2 tHCBE
CA18 tSCWE CWE_B tHCOE COE_B tSCD CD31 (Output) tSCPAR CPAR3 CPAR0 (Output) tHCPAR tHCD tCWEL tHCA
Data Sheet S12689EJ3V0DS
µPD98405
Read
Parameter Permissible delay time (from CBE_B Permissible delay time (from Permissible delay time (from COE_B hold time (from CBE_B hold time (from hold time (from COE_B Permissible CPAR delay time (from CBE_B Permissible CPAR delay time (from Permissible CPAR delay time (from COE_B CPAR hold time (from CBE_B CPAR hold time (from CPAR hold time (from COE_B Symbol tDCDCB tDCDCA tDCDCO tHCDCB tHCDCA tHCDCO tDCPCB tDCPCA tDCPCO tHCPCB tHCPCA tHCPCO tCYSCLK tCYSCLK tCYSCLK Conditions MIN. TYP. MAX. tCYSCLK tCYSCLK tCYSCLK Unit
Data Sheet S12689EJ3V0DS
µPD98405
Read timing
SCLK
CBE3_B CBE0_B
CA18
CWE_B
COE_B tDCDCB tDCDCA tDCDCO CD31 (Input) tHCDCB tHCDCA tHCDCO
CPAR3 CPAR0 tDCPCO tDCPCA tDCPCB
(Input) tHCPCO tHCPCA tHCPCB
Data Sheet S12689EJ3V0DS
µPD98405
status access Write
Parameter SCLK delay time SCLK PHRW_B delay time SCLK PHCE_B delay time SCLK delay time PHCE_B delay time Symbol tDPCA tDPHRW tDPHCE tDPCD1 tDPCD2 tCYSCLK Conditions MIN. TYP. MAX. tCYSCLK Unit
Write timing
clock SCLK tDPCA CA18 tDPHRW PHRW_B tDPHCE PHCE_B tDPHCE tDPHRW tDPCA clocks clock
PHOE_B
tDPCD1 tDPCD2 (Output)
CD31
Read
Parameter setup time hold time SCLK delay time SCLK PHRW_B delay time SCLK PHCE_B delay time SCLK PHOE_B delay time Symbol tSPCD tHPOECD tDPCA tDPHRW tDPHCE tDPHOE Conditions MIN. TYP. MAX. Unit
Data Sheet S12689EJ3V0DS
Read timing
clock clocks clocks clocks SCLK tDPCA
Data Sheet S12689EJ3V0DS
tDPCA
CA18 tDPHRW PHRW_B tDPHCE PHCE_B tDPHOE PHOE_B tSPCD CD31 (Input) tHPOECD tDPHOE tDPHCE
µPD98405
µPD98405
serial interface (internal mode)
Parameter REFCLK cycle time REFCLK high-level width REFCLK low-level width Symbol tCYRF tWRFH tWRFL Conditions MIN. tCYRF tCYRF TYP. 51.4403 MAX. tCYRF tCYRF Unit
REFCLK
tWRFH tCYRF
tWRFL
Others
Parameter SEL_B recovery time SEL_B GNT_B recovery time RDY_B SEL_B recovery time RST_B input pulse width RST_B SEL_B recovery time Symbol tRVSEL tRVSM tRVMS tRSTL tRSTSL RDY_B mode during normal operation Conditions MIN. TYP. MAX. Unit tCYCLK tCYCLK tCYCLK tCYCLK tCYCLK
Others timing
SEL_B tRVSEL GNT_B tRVMS RDY_B
tRVSM
tRSTL
RST_B tRSTSL
SEL_B
Data Sheet S12689EJ3V0DS
µPD98405
PACKAGE DRAWING
PLASTIC (FINE PITCH) (40x40)
detail lead
ITEM MILLIMETERS 42.6±0.2 40.0±0.2 40.0±0.2 42.6±0.2 1.25 1.25 0.22 +0.05 -0.04 0.10 (T.P.) 1.3±0.2 0.5±0.2 0.145 +0.055 -0.045 0.10 3.7±0.1 0.4±0.1 5°±5° MAX.
NOTE
Each lead centerline located within 0.10 true position (T.P.) maximum material condition.
P304GL-50-NMU, PMU-3
Data Sheet S12689EJ3V0DS
µPD98405
304-PIN PLASTIC FBGA (19x19)
Index mark
ITEM MILLIMETERS 19.00±0.10 18.40 18.40 19.00±0.10 1.10 (T.P.) 0.35±0.1 0.36 1.16 1.51±0.15 0.10
0.50+0.05 -0.10
0.08 C1.0 R0.3 0.20 0.20 S304S1-80-6C-1
Data Sheet S12689EJ3V0DS
µPD98405
RECOMMENDED SOLDERING CONDITIONS
µPD98405 should soldered mounted under following recommended conditions. details recommended soldering conditions, refer document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended below, contact sales representative. Surface mounting type µPD98405GL-PMU: 304-pin plastic (0.5 fine pitch)
Recommended Condition Symbol IR35-203-1
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 235°C, Time: sec. max. 210°C higher), Note (after that, prebake 125°C Count: once, Exposure limit: days hours) temperature: 300°C max., Time: sec. Max. (per row)
Partial heating
Note After opening pack, store 25°C less less allowable storage period. µPD98405S1-6C: 304-pin plastic FBGA (0.8 pitch)
Recommended Condition Symbol IR30-103-3
Soldering Method Infrared reflow
Soldering Conditions Package peak temperature: 230°C, Time: sec. max. 210°C higher), Note Count: three times, Exposure limit: days (after that, prebake 125°C hours)
Note After opening pack, store 25°C less less allowable storage period.
Data Sheet S12689EJ3V0DS
µPD98405
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices HANDLING UNUSED INPUT PINS CMOS Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS devices behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices. STATUS BEFORE INITIALIZATION DEVICES Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
Data Sheet S12689EJ3V0DS
µPD98405
NEASCOT-S20 EEPROM trademarks Corporation. MICROWIRE trademark National Semiconductor Corporation.
information this document current November, 2000. information subject change without notice. actual design-in, refer latest publications NEC's data sheets data books, etc., most up-to-date specifications semiconductor products. products and/or types available every country. Please check with sales representative availability additional information. part this document copied reproduced form means without prior written consent NEC. assumes responsibility errors that appear this document. does assume liability infringement patents, copyrights other intellectual property rights third parties arising from semiconductor products listed this document other liability arising from such products. license, express, implied otherwise, granted under patents, copyrights other intellectual property rights others. Descriptions circuits, software other related information this document provided illustrative purposes semiconductor product operation application examples. incorporation these circuits, software information design customer's equipment shall done under full responsibility customer. assumes responsibility losses incurred customers third parties arising from these circuits, software information. While endeavours enhance quality, reliability safety semiconductor products, customers agree acknowledge that possibility defects thereof cannot eliminated entirely. minimize risks damage property injury (including death) persons arising from defects semiconductor products, customers must incorporate sufficient safety measures their design, such redundancy, fire-containment, anti-failure features. semiconductor products classified into following three quality grades: "Standard", "Special" "Specific". "Specific" quality grade applies only semiconductor products developed based customer-designated "quality assurance program" specific application. recommended applications semiconductor product depend quality grade, indicated below. Customers must check quality grade each semiconductor product before using particular application. "Standard": Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots "Special": Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) "Specific": Aircraft, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade semiconductor products "Standard" unless otherwise expressly specified NEC's data sheets data books, etc. customers wish semiconductor products applications intended NEC, they must contact sales representative advance determine NEC's willingness support given application. (Note) "NEC" used this statement means Corporation also includes majority-owned subsidiaries. "NEC semiconductor products" means semiconductor product developed manufactured defined above).

µPD98405 155M AINTEGRATED CONTROLLER DESCRIPTION µPD984

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