µPD78P058FY 8-BIT SINGLE-CHIP MICROCONTROLLER DESCRIPTION
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INTEGRATED CIRCUIT
µPD78P058FY
8-BIT SINGLE-CHIP MICROCONTROLLER
DESCRIPTION
µPD78P058FY Electro Magnetic Interference (EMI) noise reduction version µPD78P058Y. µPD78P058FY member µPD78058FY Subseries 78K/0 Series, which on-chip mask µPD78058FY replaced with one-time programmable (OTP) ROM. Because this device programmed users, suited applications involving small-scale production many different products, rapid development time-to-market products. Details given following User's Manuals. sure read them before starting design.
µPD78058F, 78058FY Subseries User's Manual
78K/0 Series User's Manual Instructions
U12068E U12326E
FEATURES
noise reduction version (overall peak level reduced compatible with mask versions (except pin) Internal PROM KbytesNote Programmable once only (ideal small-scale production) Internal high-speed 1024 bytes Internal expansion 1024 bytesNote Buffer bytes Connectable interface Operable same supply voltage range mask versions (VDD QTOPMicrocontrollers Notes internal PROM capacity changed with memory size switching register (IMS). internal expansion capacity changed with internal expansion size switching register (IXS). Remarks difference between PROM mask versions, DIFFERENCES BETWEEN
µPD78P058FY MASK VERSIONS.
QTOP Microcontroller general name microcontrollers with on-chip one-time PROM that totally supported writing service (from writing marking, screening testing).
information this document subject change without notice. Document U12076EJ2V0DS00 (2nd edition) Date Published September 1997 Printed Japan
mark
shows major revised points.
1997
µPD78P058FY
ORDERING INFORMATION
Part Number Package 80-pin plastic Resin thickness:
Note
Internal One-time PROM One-time PROM
µPD78P058FYGC-3B9 µPD78P058FYGC-8BT
80-pin plastic Resin thickness:
Note Under development Caution µPD78P058FYGC contains types packages (see PACKAGE DRAWINGS). packages which supplied, consult your local sales representative.
µPD78P058FY
78K/0 SERIES PRODUCT DEVELOPMENT
These products further development 78K/0 Series. designations appearing inside boxes subseries names.
Products mass production Products under development subseries products compatible with bus. Control 100-pin 100-pin 100-pin 100-pin 80-pin 80-pin 80-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 64-pin 42/44-pin
µPD78075B µPD78078 µPD78070A µPD780058 µPD78058F µPD78054 µPD780034 µPD780024 µPD78014H µPD78018F µPD78014 µPD780001 µPD78002 µPD78083
Inverter control
PD78075BY µPD78078Y µPD78070AY µPD780018AY µPD780058YNote µPD78058FY µPD78054Y µPD780034Y µPD780024Y µPD78018FY µPD78014Y µPD78002Y
noise reduction version PD78078. timer added PD78054, external interface function enhanced. ROM-less versions PD78078. Serial PD78078Y enhanced, only selected functions provided. Serial PD78054 enhanced, noise reduction version. noise reduction version PD78054. UART converter were added µPD78014, enhanced. converter PD780024 enhanced. Serial PD78018F enhanced, noise reduction version. noise reduction version µPD78018F. Low-voltage (1.8 operation versions PD78014 with several capacities available. converter 16-bit timer were added µPD78002. converter added µPD78002. Basic subseries control. On-chip UART, capable operating voltage (1.8
64-pin 64-pin 64-pin
µPD780988 µPD780964 µPD780924
FIPdrive
inverter control, timer, PD780964 were enhanced, were expanded. converter µPD780924 enhanced. On-chip inverter control circuit UART, noise reduction version.
78K/0 Series
100-pin 100-pin 80-pin 80-pin
µPD780208 PD780228 µPD78044H µPD78044F
PD78044F were enhanced, Display output total: PD78044H were enhanced, Display output total: N-ch open-drain input/output added PD78044F, Display output total: Basic subseries driving FIP, Display output total:
drive 100-pin 100-pin 100-pin
µPD780308 µPD78064B µPD78064
IEBussupported
µPD780308Y µPD78064Y
µPD78064 enhanced, were expanded. noise reduction version PD78064. Basic subseries driving LCDs, On-chip UART.
80-pin 80-pin
µPD78098B µPD78098
noise reduction version PD78098. IEBus controller added PD78054.
Meter control 80-pin
µPD780973
On-chip automobile meter driving controller/driver.
64-pin
µPD78P0914
On-chip output, digital code decoder, Hsync counter.
Note Under planning
µPD78P058FY
major functional differences among subseries shown below.
Function Subseries Name Control Capacity Serial Interface MIN.Value
µPD78075BY 3-wire/2-wire/I2C µPD78078Y µPD78070AY
3-wire with automatic transmit/receive function 3-wire/UART
µPD780018AY 3-wire with automatic transmit/receive function
Time division 3-wire (supports multimaster)
µPD780058Y 3-wire/2-wire/I
3-wire with automatic transmit/receive function 3-wire/Time division UART
µPD78058FY 3-wire/2-wire/I2C µPD78054Y µPD780034Y µPD780024Y µPD78018FY
3-wire with automatic transmit/receive function 3-wire UART UART 3-wire (supports multimaster) 3-wire/2-wire/I 3-wire with automatic transmit/receive function
µPD78014Y
3-wire/2-wire/SBI/I 3-wire with automatic transmit/receive function
µPD78002Y
driving
3-wire/2-wire/SBI/I 3-wire/2-wire/I 3-wire/Time division UART 3-wire
µPD780308Y
µPD78064Y
3-wire/2-wire/I2C 3-wire/UART
Remark functions, except serial interface, same those subseries without
µPD78P058FY
FUNCTION DESCRIPTION
Item Internal memory PROM High-speed Expansion Buffer Kbytes bits registers bits registers banks) Minimum instruction execution time variable. µs/0.8 µs/1.6 µs/3.2 µs/6.4 µs/12.8 5.0-MHz operation) 32.768-kHz operation) 16-bit operation Multiply/divide (8-bit 8-bit, 16-bit 8-bit) manipulation (set, reset, test, Boolean operation) adjust, etc. Function KbytesNote 1024 bytes 1024 bytesNote bytes
Memory space General-purpose register Minimum instruction execution time When main system clock selected When subsystem clock selected Instruction
port
Total CMOS input CMOS input/output N-ch open-drain input/output 8-bit resolution 8-bit resolution
converter converter Serial interface
3-wire serial I/O, 2-wire serial I/O, mode selectable 3-wire serial mode (with on-chip max. 32-byte automatic transmit/receive function) 3-wire serial UART mode selectable 16-bit timer/event counter 8-bit timer/event counter Watch timer Watchdog timer
Timer
Timer output Clock output
pins (14-bit output: pin) 19.5 kHz, 39.1 kHz, 78.1 kHz, kHz, kHz, kHz, 1.25 MHz, MHz, 5.0-MHz operation with main system clock) 32.768 32.768-kHz operation with subsystem clock) kHz, kHz, 5.0-MHz operation with main system clock) Maskable Non-maskable Software Internal: external: Internal: Internal: external: +85°C 80-pin plastic Resin thickness: 80-pin plastic Resin thickness: (under development)
Buzzer output Vectored interrupt source Test input Supply voltage Operating ambient temperature Package
Notes internal PROM capacity changed with memory size switching register (IMS). internal expansion capacity changed with internal expansion size switching register (IXS).
µPD78P058FY
CONFIGURATIONS (Top View)
Normal operating mode 80-pin plastic Resin thickness:
µPD78P058FYGC-3B9
80-pin plastic Resin thickness:
µPD78P058FYGC-8BTNote
P01/INTP1/TI01 P00/INTP0/TI00
P06/INTP6
P05/INTP5
P04/INTP4
P03/INTP3
P15/ANI5 P16/ANI6 P17/ANI7 AVSS P130/ANO0 P131/ANO1 AVREF1 P70/SI2/RXD P71/SO2/TXD P72/SCK2/ASCK P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P40/AD0 P41/AD1
P02/INTP2
P14/ANI4
P13/ANI3
P12/ANI2
P11/ANI1
P10/ANI0
XT1/P07
AVREF0
AVDD
RESET P127/RTP7 P126/RTP6 P125/RTP5 P124/RTP4 P123/RTP3 P122/RTP2 P121/RTP1 P120/RTP0 P36/BUZ P35/PCL P34/TI2 P33/TI1 P32/TO2 P31/TO1 P30/TO0 P67/ASTB P66/WAIT P65/WR
P56/A14
P57/A15
P42/AD2
P43/AD3
P44/AD4
P45/AD5
P46/AD6
P47/AD7
P52/A10
P53/A11
P54/A12
P55/A13
Note Under development Cautions Connect VSS. AVDD functions both converter power supply port power supply. When µPD78P058FY used applications where noise generated inside microcontroller needs reduced, connect AVDD another power supply which same potential VDD. AVSS functions both grounds converter converter port. When µPD78P058FY used applications where noise generated inside microcontroller needs reduced, connect AVSS ground line other than VSS.
P64/RD
P50/A8
P51/A9
µPD78P058FY
ANI0 ANI7 ANO0, ANO1 ASCK ASTB AVDD AVREF0, AVREF1 AVSS BUSY INTP0 INTP6 P120 P127 P130, P131 Address Address/Data Analog Input Analog Output Asynchronous Serial Clock Address Strobe Analog Power Supply Analog Reference Voltage Analog Ground Busy Buzzer Clock Interrupt from Peripherals Port Port Port Port Port Port Port Port Port Port Programmable Clock RESET RTP0 RTP7 SB0, SCK0 SCK2 SDA0, SDA1 TI00, TI01 TI1,TI2 WAIT XT1, Read Strobe Reset Real-Time Output Port Receive Data Serial Serial Clock Serial Clock Serial Data Serial Input Serial Output Strobe Timer Input Timer Input Timer Output Transmit Data Power Supply Programming Power Supply Ground Wait Write Strobe Crystal (Main System Clock) Crystal (Subsystem Clock)
µPD78P058FY
PROM programming mode 80-pin plastic Resin thickness:
µPD78P058FYGC-3B9
80-pin plastic Resin thickness:
µPD78P058FYGC-8BTNote
Open Open
RESET
Note Under development Cautions RESET Open Individually connect pull-down resistor. Connect GND. level. connection Address Chip Enable Data Output Enable Program RESET Reset Power Supply Programming Power Supply Ground
µPD78P058FY
BLOCK DIAGRAM
TO0/P30 TI00/INTP0/P00 TI01/INTP1/P01 TO1/P31 TI1/P33 16-bit TIMER/ EVENT COUNTER
PORT0
8-bit TIMER/ EVENT COUNTER
PORT1
TO2/P32 TI2/P34
8-bit TIMER/ EVENT COUNTER
PORT2
WATCHDOG TIMER
PORT3
WATCH TIMER
PORT4
SI0/SB0/SDA0/P25 SO0/SB1/SDA1/P26 SCK0/SCL/P27 SI1/P20 SO1/P21 SCK1/P22 STB/P23 BUSY/P24 SI2/RxD/P70 SO2/TxD/P71 SCK2/ASCK/P72 SERIAL INTERFACE SERIAL INTERFACE
78K/0 CORE
PROM Bytes
PORT5
PORT6
PORT7 2080 Bytes SERIAL INTERFACE PORT12
P120 P127
PORT13 ANI0/P10 ANI7/P17 AVREF0
P130, P131
CONVERTER
REAL-TIME OUTPUT PORT
RTP0/P120 RTP7/P127 AD0/P40 AD7/P47 A8/P50 A15/P57
ANO0/P130, ANO1/P131 AVREF1
CONVERTER EXTERNAL ACCESS INTERRUPT CONTROL
RD/P64 WR/P65 WAIT/P66 ASTB/P67 RESET XT1/P07
INTP0/P00 INTP6/P06
BUZ/P36
BUZZER OUTPUT SYSTEM CONTROL
PCL/P35
CLOCK OUTPUT CONTROL
AVDD AVSS
µPD78P058FY
CONTENTS DIFFERENCES BETWEEN µPD78P058FY MASK VERSIONS FUNCTIONS
Pins Normal Operating Mode Pins PROM Programming Mode Input/Output Circuits Recommended Connection Unused Pins
MEMORY SIZE SWITCHING REGISTER (IMS) INTERNAL EXPANSION SIZE SWITCHING REGISTER (IXS) PROM PROGRAMMING
Operating Modes PROM Write Procedure PROM Read Procedure
SCREENING ONE-TIME PROM VERSIONS ELECTRICAL SPECIFICATIONS PACKAGE DRAWINGS RECOMMENDED SOLDERING CONDITIONS APPENDIX DEVELOPMENT TOOLS APPENDIX RELATED DOCUMENTS
µPD78P058FY
DIFFERENCES BETWEEN µPD78P058FY MASK VERSIONS
µPD78P058FY single-chip microcontroller with on-chip one-time PROM. Setting memory size switching register (IMS) internal expansion size switching register (IXS) enables identical functions mask versions (µPD78056FY 78058FY) except functions PROM specifications mask options P63. Differences between µPD78P058FY mask versions shown Table 1-1. Table 1-1. Differences between µPD78P058FY Mask Versions
Item Internal structure Internal capacity Internal expansion capacity Change internal capacity memory size switching register (IMS) Change internal expansion capacity internal expansion size switching register (IXS) Pull-up resistor on-chip mask option pins Electrical specifications, recommended soldering conditions
µPD78P058FY
One-time PROM Kbytes 1024 bytes changedNote changedNote
Mask Versions Mask
µPD78056FY Kbytes µPD78058FY Kbytes µPD78056FY None µPD78058FY 1024 bytes
Cannot changed Cannot changed
None Provided None each Data Sheet.
Provided None Provided
Note RESET input sets internal PROM capacity internal expansion capacity Kbytes 1024 bytes, respectively. Caution PROM version mask version differ noise tolerance noise emission. When replacing PROM version with mask version when switching from experimental production mass production, make thorough evaluation with version (not version) mask version.
µPD78P058FY
FUNCTIONS
Pins Normal Operating Mode
Port pins (1/2)
Name
Note
Input/Output Input Input/output Port 8-bit input/output port
Function Input only Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software.
After Reset Input Input
Alternate Function INTP0/TI00 INTP1/TI01 INTP2 INTP3 INTP4 INTP5 INTP6
Input Input/output
Input only Port 8-bit input/output port Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software.Note Port 8-bit input/output port Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software.
Input Input
ANI0 ANI7
Input/output
Input
SCK1 BUSY SI0/SB0/SDA0 SO0/SB1/SDA1 SCK0/SCL
Input/output
Port 8-bit input/output port Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software.
Input
Notes When P07/XT1 pins used input ports, processor clock control register (PCC) (FRC) sure feedback resistor subsystem clock oscillation circuit. When P10/ANI0 P17/ANI7 pins used analog inputs converter, port input mode. on-chip pull-up resistors automatically disabled. Caution pins which also function port pins, perform following operations during conversion. these operations performed, total error ratings cannot kept. Rewrite output latch while used port pin. Change output level used output pin, even used port pin.
µPD78P058FY
Port pins (2/2)
Name Input/Output Input/output Function Port 8-bit input/output port Input/output specifiable 8-bit unit. When used input port, possible on-chip pull-up resistor software. test input flag (KRIF) falling edge detection. Port 8-bit input/output port possible directly drive LEDs. Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software. Port 8-bit input/output port Input/output specifiable bit-wise. N-ch open-drain input/output port. possible directly drive LEDs. After Reset Input Alternate Function
Input/output
Input
P120 P127
Input/output
Input
When used input port, possible on-chip pull-up resistor software.
Input
WAIT ASTB
Input/output
Port 3-bit input/output port Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software. Port 8-bit input/output port Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software. Port 2-bit input/output port Input/output specifiable bit-wise. When used input port, possible on-chip pull-up resistor software.
Input
SI2/RXD SO2/TXD SCK2/ASCK
Input/output
Input
RTP0 RTP7
P130, P131
Input/output
Input
ANO0, ANO1
Caution
pins which also function port pins, perform following operations during conversion. these operations performed, total error ratings cannot kept. Rewrite output latch while used port pin. Change output level used output pin, even used port pin.
µPD78P058FY
Non-port pins (1/2)
Name INTP0 INTP1 INTP2 INTP3 INTP4 INTP5 INTP6 SDA0 SDA1 SCK0 SCK1 SCK2 BUSY ASCK TI00 TI01 Output Output Input Input Output Input Input Automatic transmitting/receiving strobe output serial interface Automatic transmitting/receiving busy input serial interface Serial data input asynchronous serial interface Serial data output asynchronous serial interface Serial clock input asynchronous serial interface External count clock input 16-bit timer (TM0) Capture trigger signal input capture register (CR00) External count clock input 8-bit timer (TM1) External count clock input 8-bit timer (TM2) 16-bit timer (TM0) output (Can used together with 14-bit output.) 8-bit timer (TM1) output 8-bit timer (TM2) output Input Input Input Input Input Input Input Input/output Serial clock input/output serial interface Input Input/output Serial data input/output serial interface Input Output Serial data output serial interface Input Input Serial data input serial interface Input Input/Output Input Function External interrupt request inputs, with specifiable valid edges (rising edge, falling edge, both rising falling edges) After Reset Input Alternate Function P00/TI00 P01/TI01 P25/SB0/SDA0 P70/RXD P26/SB1/SDA1 P71/TXD P25/SI0/SDA0 P26/SO0/SDA1 P27/SCK0 P26/SO0/SB1 P27/SCL P72/ASCK P27/SCK0 P70/SI2 P71/SO2 P72/SCK2 P00/INTP0 P01/INTP1
µPD78P058FY
Non-port pins (2/2)
Name Input/Output Output Function Clock output (for trimming main system clock subsystem clock) Buzzer output Real-time output port which outputs data synchronization with trigger Low-order address/data when expanding memory externally High-order address when expanding memory externally Strobe signal output external memory read operation Strobe signal output external memory write operation Input Output Wait insertion when accessing external memory Strobe output externally latches address information which output ports accessing external memory Analog input converter Analog output converter Reference voltage input converter Reference voltage input converter Analog power supply converter (shared with port power supply) Ground potential converter converter (shared with port ground potential) System reset input Main system clock oscillation crystal connection After Reset Input Alternate Function
RTP0 RTP7
Output Output
Input Input
P120 P127
Input/output
Input
Output
Input
Output
Input
Input
WAIT ASTB
Input Input
ANI0 ANI7 ANO0, ANO1 AVREF0 AVREF1 AVDD
Input Output Input Input
Input Input
P130, P131
AVSS
RESET
Input Input Input
Subsystem clock oscillation crystal connection
Input
Positive power supply (except port) High-voltage applied during program write/verify. Connected normal operating mode. Ground potential (except port)
Cautions AVDD functions both converter power supply port power supply. When µPD78P058FY used applications where noise generated inside microcontroller needs reduced, connect AVDD another power supply which same potential VDD. AVSS functions both grounds converter converter port. When µPD78P058FY used applications where noise generated inside microcontroller needs reduced, connect AVSS ground line other than VSS.
µPD78P058FY
Pins PROM Programming Mode
Name RESET Input/Output Input Function PROM programming mode setting When +12.5 applied low-level signal applied RESET pin, this chip PROM programming mode. PROM programming mode setting high-voltage applied during program write/ verification Address Data PROM enable input/program pulse input Read strobe input PROM Program/program inhibit input PROM programming mode Positive power supply Ground potential
Input
Input Input/output Input Input Input
µPD78P058FY
Input/Output Circuits Recommended Connection Unused Pins
Types input/output circuits pins recommended connection unused pins shown Table 2-1. configuration each type input/output circuit, Figure 2-1. Table 2-1. Input/Output Circuit Type (1/2)
Input/Output Circuit Type Recommended Connection when Unused Connect VSS. Independently connect through resistor.
Name P00/INTP0/TI00 P01/INTP1/TI01 P02/INTP2 P03/INTP3 P04/INTP4 P05/INTP5 P06/INTP6 P07/XT1 P10/ANI0 P17/ANI7 P20/SI1 P21/SO1 P22/SCK1 P23/STB P24/BUSY P25/SI0/SB0/SDA0 P26/SO0/SB1/SDA1 P27/SCK0/SCL P30/TO0 P31/TO1 P32/TO2 P33/TI1 P34/TI2 P35/PCL P36/BUZ P40/AD0 P47/AD7
Input/Output Input Input/output
11-C 10-C
Input Input/output
Connect VDD. Independently connect through resistor.
Independently connect through resistor.
µPD78P058FY
Table 2-1. Input/Output Circuit Type (2/2)
Input/Output Circuit Type 13-H Recommended Connection when Unused Independently connect through resistor. Independently connect through resistor. Independently connect through resistor.
Name P50/A8 P57/A15 P64/RD P65/WR P66/WAIT P67/ASTB P70/SI2/RxD P71/SO2/TxD P72/SCK2/ASCK P120/RTP0 P127/RTP7 P130/ANO0, P131/ANO1 RESET AVREF0 AVREF1 AVDD AVSS
Input/Output Input/output
12-B Input Leave open. Connect VSS. Connect VDD. Connect another power supply which same potential VDD. Connect another ground line which same potential VSS. Connect VSS. Independently connect through resistor.
µPD78P058FY
Figure 2-1. Input/Output Circuits (1/2) Type Type
AVDD
pullup enable AVDD
P-ch
data
P-ch IN/OUT
output disable Schmitt-Triggered Input with Hysteresis Characteristic
N-ch AVSS
Type
AVDD
Type 10-C
AVDD
pullup enable AVDD data P-ch
P-ch
pullup enable AVDD data
IN/OUT
P-ch
P-ch IN/OUT N-ch AVSS
output disable
N-ch AVSS
open drain output disable
input enable
Type
AVDD
Type 11-C
AVDD pullup enable P-ch AVDD P-ch IN/OUT output disable N-ch P-ch AVSS AVSS N-ch
pullup enable AVDD data P-ch
P-ch
data
IN/OUT output disable N-ch AVSS
Comparator
VREF (Threshold Voltage) input enable
µPD78P058FY
Figure 2-1. Input/Output Circuits (2/2) Type 12-B
AVDD
Type
pullup enable AVDD data P-ch
feedback cut-off
P-ch
P-ch
IN/OUT output disable AVSS input enable Analog Output Voltage P-ch N-ch AVSS N-ch
Type 13-H
IN/OUT data output disable N-ch AVSS AVDD
P-ch
Middle-High Voltage Input Buffer
µPD78P058FY
MEMORY SIZE SWITCHING REGISTER (IMS)
This register disable part internal memories software. setting this memory size switching register (IMS), possible same memory mapping that mask version having different internal memories (ROM). register with 8-bit memory manipulation instruction. RESET input sets CFH. Figure 3-1. Memory Size Switching Register Format
Symbol RAM2 RAM1 RAM0 ROM3 ROM2 ROM1 ROM0 Address FFF0H After Reset
ROM3 ROM2 ROM1 ROM0 Others
Selection Internal Capacity Kbytes KbytesNote Kbytes Setting prohibited
RAM2 RAM1 RAM0 Others
Selection Internal High-Speed Capacity 1024 bytes Setting prohibited
Note internal capacity Kbytes less when external device expansion function used. Table shows setting values which make memory mapping same that mask versions. Table 3-1. Memory Size Switching Register Setting Values
Target Mask Version Setting Value
µPD78056FY µPD78058FY
µPD78P058FY
INTERNAL EXPANSION SIZE SWITCHING REGISTER (IXS)
This register internal expansion capacity software. setting this internal expansion size switching register (IXS), possible same memory mapping that mask version having different internal expansion RAM. register with 8-bit memory manipulation instruction. RESET input sets 0AH. Figure 4-1. Internal Expansion Size Switching Register Format
Symbol Address FFF4H After Reset
IXRAM3 IXRAM2 IXRAM1 IXRAM0
IXRAM3 IXRAM2 IXRAM1 IXRAM0 Others
Selection Internal Expansion Capacity byte 1024 bytes Setting prohibited
Table shows setting values which make memory mapping same that mask versions. Table 4-1. Internal Expansion Size Switching Register Setting Values
Target Mask Version Setting Value
µPD78056FY µPD78058FY
Remark Even µPD78P058FY program that includes "MOV IXS, #0CH" implemented µPD78056FY, operation will affected.
µPD78P058FY
PROM PROGRAMMING
µPD78P058FY on-chip 60-Kbyte PROM program memory. programming, PROM programming mode RESET pins. connecting unused pins, refer CONFIGURATIONS (Top View) PROM programming mode. Caution Program writing should performed address range 0000H EFFFH (the last address, EFFFH, should specified). Writing cannot performed with PROM programmer that cannot specify write addresses. Operating Modes
When +12.5 applied level signal applied RESET pin, PROM programming mode set. This mode will become operating mode shown Table when pins shown. Further, when read mode set, possible read contents PROM. Table 5-1. Operating Modes PROM Programming
RESET Operating Mode Page data latch Page write Byte write Program verify Program inhibit +12.5 +6.5 Read Output disable Standby Data output High-impedance High-impedance Data input High-impedance Data input Data output High-impedance
Remark
µPD78P058FY
Read mode Read mode set. Output disable mode Data output becomes high-impedance, output disable mode, set. Therefore, allows data read from device controlling pin, multiple µPD78P058FYs connected data bus. Standby mode Standby mode set. this mode, data outputs become high-impedance irrespective status. Page data latch mode Page data latch mode beginning page write mode. this mode, 1-page 4-byte data latched internal address/data latch circuit. Page write mode After page bytes addresses data latched page data latch mode, page write executed applying 0.1-ms program pulse (active low) with Then, program verification performed, set. programming performed one-time program pulse, write verification operations should executed repeatedly. Byte write mode Byte write executed when 0.1-ms program pulse (active low) applied with Then, program verification performed set. programming performed one-time program pulse, write verification operations should executed repeatedly. Program verify mode Program verify mode set. this mode, check write operation performed correctly after write. Program inhibit mode Program inhibit mode used when pin, pin, pins multiple µPD78P058FYs connected parallel write performed those devices. When write operation performed, page write mode byte write mode described above used. this time, write performed device which driven high.
µPD78P058FY
PROM Write Procedure Figure 5-1. Page Program Mode Flowchart
Start Address 12.5
Latch Address Address Latch Address Address Latch Address Address Address Address Latch
X=X+1 0.1-ms program pulse
Verify bytes Pass Address Pass
Fail
Verify bytes Pass writing
Fail
Defective product
Remark Start address Program last address
µPD78P058FY
Figure 5-2. Page Program Mode Timing
Page Data Latch
Page Program
Program Verify
Data Input Data Output
µPD78P058FY
Figure 5-3. Byte Program Mode Flowchart
Start Address 12.5
X=X+1 0.1-ms program pulse Address Address Fail Verify Pass Address Pass Fail
Verify bytes Pass writing
Defective product
Remark Start address Program last address
µPD78P058FY
Figure 5-4. Byte Program Mode Timing
Program
Program Verify
Data Input
Data Output
Cautions should applied before VPP, removed after VPP. must exceed +13.5 including overshoot. Reliability adversely affected removal/reinsertion performed while +12.5 being applied VPP.
µPD78P058FY
PROM Read Procedure
contents PROM readable external data according read procedure shown below. RESET level, supply pin, connect other unused pins shown CONFIGURATIONS (Top View) PROM programming mode. Supply pins. Input address read data into pins. Read mode Output data pins.
timings above steps shown Figure 5-5. Figure 5-5. PROM Read Timings
Address Input
(Input)
(Input)
Hi-Z
Data Output
Hi-Z
µPD78P058FY
SCREENING ONE-TIME PROM VERSIONS
one-time PROM version (µPD78P058FYGC-3B9, 78P058FYGC-8BT) cannot tested completely before shipped, because structure. recommended perform screening verify PROM after writing necessary data performing high-temperature storage under conditions below.
Storage Temperature 125°C
Storage Time hours
offers one-time PROM writing, marking, screening verify services products designated "QTOP Microcontrollers". details, contact sales representative.
µPD78P058FY
ELECTRICAL SPECIFICATIONS
Absolute Maximum Ratings 25°C)
Parameter Supply voltage Symbol AVDD AVREF0 AVREF1 AVSS Input voltage P07, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, XT2, RESET N-ch open-drain PROM programming mode Test Conditions Rating -0.3 +7.0 -0.3 +13.5 -0.3 -0.3 -0.3 -0.3 +0.3 -0.3 Unit
Output voltage Analog input voltage Output current, high
-0.3 -0.3 +13.5 -0.3
Analog input pins
AVSS AVREF0
Total P06, P37, P56, P57, P67, P120 P127 Total P17, P27, P47, P55, P72, P130, P131 Output current,
Note
peak value r.m.s. value
Total
peak value r.m.s. value
Total P56, P57,
peak value r.m.s. value
Total P17, P27, P47, P72, P130, P131 Total P06, P37, P67, P120 P127 Operating ambient temperature Storage temperature
peak value r.m.s. value peak value r.m.s. value
Tstg
+150
Note r.m.s. values should calculated follows: [r.m.s. value] [peak value] Duty Caution Product quality suffer absolute maximum rating exceeded even single parameter, even momentarily. other words, absolute maximum ratings rated values which product verge suffering physical damage, therefore product must used under conditions which ensure that absolute maximum ratings exceeded. Remark Unless specified otherwise, alternate-function characteristics same port characteristics.
µPD78P058FY
Main System Clock Oscillator Characteristics +85°C,
Resonator Ceramic resonator
Recommended Circuit
Parameter Oscillation frequency (fX)Note
Test Conditions Oscillation voltage range
MIN. TYP. MAX. Unit
Oscillation stabilization timeNote
After reached MIN. oscillation voltage range
Crystal resonator
Oscillation frequency (fX)Note
Oscillation stabilization timeNote
External clock
input frequency (fX)Note
PD74HCU04
input high-/low-level width (tXH/tXL)
Notes Only oscillator characteristics shown. characteristics instruction execution times. This time required oscillation stabilize after reset STOP mode release. Cautions When main system clock oscillator used, following should noted concerning wiring area figure enclosed broken lines prevent influence wiring capacitance, etc. wiring should kept short possible. other signal lines should crossed. Keep away from lines carrying high fluctuating current. oscillator capacitor grounding point should always same potential VSS. connect ground pattern carrying high current. signal should taken from oscillator. When main system clock stopped device operating subsystem clock, wait until oscillation stabilization time been secured program before switching back main system clock.
µPD78P058FY
Subsystem Clock Oscillator Characteristics +85°C,
Resonator Crystal resonator Recommended Circuit
Parameter Oscillation frequency (fXT)Note
Test Conditions
MIN. TYP. MAX. Unit 32.768
Oscillation stabilization timeNote
External clock
input frequency (fXT)Note
input high-/low-level width (tXTH/tXTL)
Notes Only oscillator characteristics shown. characteristics instruction execution times. This time required oscillation stabilize after power (VDD) turned Cautions When subsystem clock oscillator used, following should noted concerning wiring area figure enclosed broken lines prevent influence wiring capacitance, etc. wiring should kept short possible. other signal lines should crossed. Keep away from lines carrying high fluctuating current. oscillator capacitor grounding point should always same potential VSS. connect ground pattern carrying high current. signal should taken from oscillator. subsystem clock oscillator low-amplitude circuit order achieve consumption current, more prone misoperation noise than main system clock oscillator. Particular care therefore required with wiring method when subsystem clock used.
µPD78P058FY
Capacitance 25°C,
Parameter Input capacitance Input/output capacitance Symbol Test Conditions MHz, Unmeasured pins returned Unmeasured pins returned P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131 MIN. TYP. MAX. Unit
Remark Unless specified otherwise, alternate-function characteristics same port characteristics.
µPD78P058FY
Characteristics +85°C,
Parameter Input voltage, high Symbol VIH1 Test Conditions MIN. TYP. MAX. Unit
P17, P21, P23, P32, P37, P47, P57, P67, P71, P120 P127, P130, P131 P06, P20, P22, P27, P33, P34, P70, P72, RESET (N-ch open-drain) XT1/P07,
VIH2
VIH3 VIH4 VIH5
Input voltage,
VIL1
P17, P21, P23, P32, P37, P47, P57, P67, P71, P120 P127, P130, P131 P06, P20, P22, P27, P33, P34, P70, P72, RESET
VIL2
VIL3
VIL4 VIL5
XT1/P07,
Output voltage, high
-100
Output voltage,
VOL1
P57,
P06, P17, P27, P37, P47, P67, P72, P120 P127, P130, P131 VOL2 SB0, SB1, SCK0 N-ch open-drain pull-up time
VOL3 Input leakage current, high ILIH1
P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, RESET XT1/P07,
ILIH2 ILIH3
Remark Unless specified otherwise, alternate-function characteristics same port characteristics.
µPD78P058FY
Characteristics +85°C,
Parameter Input leakage current, Symbol ILIL1 Test Conditions P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131, RESET XT1/P07, VOUT MIN. TYP. MAX. Unit
ILIL2 ILIL3 Output leakage current, high Output leakage current, Software pull-up resistor ILOL VOUT ILOH
-3Note
P06, P17, P27, P37, P47, P57, P67, P72, P120 P127, P130, P131
Note P63, -200 (MAX.) low-level input leakage current passes only during 1.5-clock interval wait) when read instruction port (P6) port mode register (PM6) executed. Other than 1.5clock interval, (MAX.) passed. Remark Unless specified otherwise, alternate-function characteristics same port characteristics.
µPD78P058FY
Characteristics +85°C,
Parameter Supply currentNote Symbol IDD1 Test Conditions 5.0-MHz crystal oscillation operating mode (fXX MHz)Note 5.0-MHz crystal oscillation operating mode (fXX MHz)Note IDD2 5.0-MHz crystal oscillation HALT mode (fXX MHz)Note 5.0-MHz crystal oscillation HALT mode (fXX MHz)Note IDD3 32.768-kHz crystal oscillation operating mode IDD4 32.768-kHz crystal oscillation HALT modeNote IDD5 STOP mode Feedback resistor used IDD6 STOP mode Feedback resistor used ±10% 0.05 ±10% ±10%
Note
MIN. ±10%Note ±10%Note ±10%
Note
TYP. 0.65
MAX. 27.0 1.95
Unit
±10%Note ±10% ±10% ±10% ±10% ±10% ±10% ±10% ±10% ±10%
Notes Passed through AVDD pins. Does include current which passed through converter, converter, on-chip pull-up resistor. fX/2 operation (when oscillation mode selection register (OSMS) 00H) operation (when OSMS 01H) When main system clock stopped High-speed mode operation (when processor clock control register (PCC) 00H) Low-speed mode operation (when 04H) Remarks Main system clock frequency fX/2) Main system clock oscillation frequency
µPD78P058FY
Characteristics Basic Operation +85°C,
Parameter Cycle time (minimum instruction execution time) Operating subsystem clock TI00 input high-/low-level width TI01 input high-/low-level width TI1, input frequency TI1, input high-/low-level width Interrupt input high-/low-level width tTIH1, tTIL1 tINTH, tINTL INTP1 INTP6, RESET low-level width tRSL INTP0 tTIH00, tTIL00 tTIH01, tTIL01 fTI1 2/fsam
Note
Symbol Operating main system clock
Test Conditions fX/2Note fXNote
MIN. 2/fsam 0.1Note 2/fsam 0.2Note
TYP.
MAX.
Unit
2/fsam 0.2Note
Notes When oscillation mode selection register (OSMS) 00H. When OSMS 01H. fsam selected fXX/2N, fXX/32, fXX/64, fXX/128 bits (SCS0 SCS1) sampling clock selection register (SCS). Remarks Main system clock frequency fX/2) Main system clock oscillation frequency
µPD78P058FY
(Main System Clock, fX/2) (Main System Clock,
Cycle Time
Guaranteed Operation Range
Cycle Time
Guaranteed Operation Range
Supply Voltage
Supply Voltage
µPD78P058FY
Read/Write Operations When PCC2 PCC0 000B +85°C,
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from tRDD1 tRDD2 Read data hold time low-level width tRDH tRDL1 tRDL2 WAIT input time from tRDWT1 tRDWT2 WAIT input time from WAIT low-level width Write data setup time Write data hold time low-level width delay time from ASTB delay time from ASTB ASTBdelay time from external fetch Address hold time from external fetch Write data output time from Write data output time from Address hold time from delay time from WAIT delay time from WAIT tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST tRDADH tRDWD tWRWD tWRADH tWTRD tWTWR (1.15 2n)tCY (2.85 2n)tCY (2.85 2n)tCY 0.85tCY 0.85tCY 0.85tCY 0.85t 1.15tCY 1.15tCY 1.15tCY 3.15tCY 3.15tCY 1.15tCY 1.15tCY 2n)tCY (2.85 2n)tCY 0.85tCY 2tCY 2tCY 2n)tCY Test Conditions MIN. 0.85tCY 0.85tCY (2.85 2n)tCY 2n)tCY 2n)tCY (2.85 2n)tCY MAX. Unit
Remarks
MCS: oscillation mode selection register (OSMS) PCC2 PCC0: processor clock control register (PCC) TCY/4 indicates number waits.
µPD78P058FY
Except when PCC2 PCC0 000B +85°C,
Parameter ASTB high-level width Address setup time Address hold time Data input time from address Symbol tASTH tADS tADH tADD1 tADD2 Data input time from tRDD1 tRDD2 Read data hold time low-level width tRDH tRDL1 tRDL2 WAIT input time from tRDWT1 tRDWT2 WAIT input time from WAIT low-level width Write data setup time Write data hold time low-level width delay time from ASTB delay time from ASTB ASTBdelay time from external fetch Address hold time from external fetch Write data output time from Write data output time from Address hold time from delay time from WAIT delay time from WAIT tWRWT tWTL tWDS tWDH tWRL1 tASTRD tASTWR tRDAST tRDADH tRDWD tWRWD tWRADH tWTRD tWTWR 2n)tCY (2.4 2n)tCY (2.4 2n)tCY 0.4tCY 1.4tCY 0.4tCY 0.6tCY 0.6tCY 2.6tCY 2.6tCY (1.4 2n)tCY (2.4 2n)tCY 2tCY 2tCY 2n)tCY Test Conditions MIN. 0.4tCY 2n)tCY 2n)tCY (1.4 2n)tCY (2.4 2n)tCY MAX. Unit
Remarks
MCS: oscillation mode selection register (OSMS) PCC2 PCC0: processor clock control register (PCC) TCY/4 indicates number waits.
µPD78P058FY
Serial Interface +85°C, Serial interface channel 3-wire serial mode (SCK0 internal clock output)
Parameter SCK0 cycle time Symbol tKCY1 Test Conditions MIN. 1600 SCK0 high-/low-level width tKH1, tKL1 setup time SCK0) tSIK1 tKCY1/2 tKCY1/2 hold time (from SCK0) output delay time from SCK0 tKSI1 tKSO1 pFNote TYP. MAX. Unit
Note SCK0 output line load capacitance. (ii) 3-wire serial mode (SCK0 external clock input)
Parameter SCK0 cycle time Symbol tKCY2 Test Conditions MIN. 1600 SCK0 high-/low-level width tKH2, tKL2 setup time SCK0) hold time (from SCK0) output delay time from SCK0 SCK0 rise, fall time tSIK2 tKSI2 tKSO2 tR2, pFNote When using external device expansion function When using external device expansion function 1000 TYP. MAX. Unit
Note output line load capacitance.
µPD78P058FY
(iii) 2-wire serial mode (SCK0 internal clock output)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width Symbol tKCY3 tKH3 tKL3 Test Conditions
Note
MIN. 1600 tKCY3/2
TYP.
MAX.
Unit
tKCY3/2 tKCY3/2
SB0, setup time SCK0)
tSIK3
SB0, hold time (from SCK0) SB0, output delay time from SCK0
tKSI3 tKSO3
Note SCK0, SB0, output line load resistance load capacitance. (iv) 2-wire serial mode (SCK0 external clock input)
Parameter SCK0 cycle time SCK0 high-level width SCK0 low-level width SB0, setup time SCK0) SB0, hold time (from SCK0) SB0, output delay time from SCK0 SCK0 rise, fall time tR4, Symbol tKCY4 tKH4 tKL4 tSIK4 tKSI4 tKSO4 pFNote When using external device expansion function When using external device expansion function 1000 Test Conditions MIN. 1600 tKCY4/2 TYP. MAX. Unit
Note output line load resistance load capacitance.
µPD78P058FY
mode (SCL internal clock output)
Parameter cycle time Symbol tKCY5 Test Conditions high-level width tKH5
Note
MIN.
TYP.
MAX.
Unit
tKCY5 tKCY5
low-level width
tKL5
tKCY5 tKCY5
SDA0, SDA1 setup time SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time from SDA0, SDA1 from SDA0, SDA1 from from SDA0, SDA1 SDA0, SDA1 high-level width
tSIK5
tKSI5 tKSO5
tKSB
tSBK tSBH
Note SCL, SDA0, SDA1 output line load resistance load capacitance. (vi) mode (SCL external clock input)
Parameter cycle time high-/low-level width Symbol tKCY6 tKH6, tKL6 SDA0, SDA1 setup time SCL) SDA0, SDA1 hold time (from SCL) SDA0, SDA1 output delay time from SDA0, SDA1 from SDA0, SDA1 from from SDA0, SDA1 SDA0, SDA1 high-level width rise, fall time tSBK tSBH tR6, When using external device expansion function When using external device expansion function 1000 tKSB tSIK6 tKSI6 tKSO6
Note
Test Conditions
MIN. 1000
TYP.
MAX.
Unit
Note SDA0 SDA1 output line load resistance load capacitance.
µPD78P058FY
Serial interface channel 3-wire serial mode (SCK1 internal clock output)
Parameter SCK1 cycle time Symbol tKCY7 Test Conditions MIN. 1600 SCK1 high-/low-level width tKH7, tKL7 setup time SCK1) tSIK7 tKCY7/2 tKCY7/2 hold time (from SCK1) output delay time from SCK1 tKSI7 tKSO7
Note
TYP.
MAX.
Unit
Note SCK1 output line load capacitance. (ii) 3-wire serial mode (SCK1 external clock input)
Parameter SCK1 cycle time Symbol tKCY8 Test Conditions MIN. 1600 SCK1 high-/low-level width tKH8, tKL8 setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise, fall time tSIK8 tKSI8 tKSO8 tR8,
Note
TYP.
MAX.
Unit
When using external device expansion function When using external device expansion function
1000
Note output line load capacitance.
µPD78P058FY
(iii) Automatic transmission/reception function 3-wire serial mode (SCK1 internal clock output)
Parameter SCK1 cycle time Symbol tKCY9 Test Conditions MIN. 1600 SCK1 high-/low-level width tKH9, tKL9 setup time SCK1) tSIK9 tKCY9/2 tKCY9/2 hold time (from SCK1) output delay time from SCK1 from SCK1 Strobe signal high-level width Busy signal setup time busy signal detection timing) Busy signal hold time (from busy signal detection timing) SCK1 from busy inactive tSPS tBYH 2tKCY9 tKSI9 tKSO9 tSBD tSBW tBYS pFNote tKCY9/2 tKCY9 tKCY9/2 tKCY9 TYP. MAX. Unit
Note
SCK1 output line load capacitance. (iv) Automatic transmission/reception function 3-wire serial mode (SCK1 external clock input)
Parameter Symbol tKCY10 Test Conditions MIN. 1600 TYP. MAX. Unit
SCK1 cycle time
SCK1 high-/low-level width
tKH10, tKL10
setup time SCK1) hold time (from SCK1) output delay time from SCK1 SCK1 rise, fall time
tSIK10 tKSI10 tKSO10 tR10, tF10 pFNote When using external device expansion function When using external device expansion function
1000
Note output line load capacitance.
µPD78P058FY
Serial interface channel 3-wire serial mode (SCK2 internal clock output)
Parameter SCK2 cycle time Symbol tKCY11 Test Conditions MIN. 1600 SCK2 high-/low-level width tKH11, tKL11 setup time SCK2) tSIK11 tKCY11/2 tKCY11/2 hold time (from SCK2) output delay time from SCK2 tKSI11 tKSO11
Note
TYP.
MAX.
Unit
Note SCK2 output line load capacitance. (ii) UART mode (Dedicated baud rate generator output)
Parameter Transfer rate Symbol Test Conditions MIN. TYP. MAX. 78125 39063 Unit
(iii) UART mode (External clock input)
Parameter ASCK cycle time Symbol tKCY12 Test Conditions MIN. 1600 ASCK high-/low-level width Transfer rate tKH12, tKL12 39063 19531 ASCK rise, fall time tR12, tF12 when using external device expansion function 1000 TYP. MAX. Unit
µPD78P058FY
Timing Test Point (Excluding Inputs)
Test Points
Clock Timing
1/fX
Input
1/fXT tXTL tXTH
Input
VIH5 (MIN.) VIL5 (MAX.)
Timing
tTIL00, tTIL01
tTIH00, tTIH01
TI00, TI01
1/fTI1 tTIL1 tTIH1
TI1,
µPD78P058FY
Read/Write Operations External fetch wait):
Low-Order 8-Bit Address tADS tASTH ASTB tADH
High-Order 8-Bit Address tADD1 Hi-Z Operation Code tRDD1 tRDADH tRDAST
tASTRD tRDL1 tRDH
External fetch (wait insertion):
Low-Order 8-Bit Address ASTH ASTB
High-Order 8-Bit Address
ADD1 Hi-Z RDD1 Operation Code tRDADH tRDAST
ASTRD WAIT RDL1
RDWT1
WTRD
µPD78P058FY
External data access wait):
Low-Order 8-Bit Address tADS tASTH ASTB tADH tADD2 Hi-Z tRDD2
High-Order 8-Bit Address
Read Data
Hi-Z
Write Data
Hi-Z
tRDH
tASTRD tRDL2 tRDWD tWRWD tASTWR tWRL1 tWDS tWDH WRADH
External data access (wait insertion):
Low-Order 8-Bit Address tADD2 tADS tASTH ASTB tASTRD tRDL2 tRDWD tWRWD tASTWR WAIT tRDWT2 tWTL tWTRD tWRWT tWTL tWTWR tWRL1 tWRADH tWDS tWDH tADH tRDD2 tRDH Hi-Z Read Data Hi-Z Write Data High-Order 8-Bit Address Hi-Z
µPD78P058FY
Serial Transfer Timing 3-wire serial mode:
tKCYm
tKLm SCK0 SCK2 tSIKm tKSIm
tKHm
tKSOm
Input Data
Output Data
Remark
2-wire serial mode:
tKCY3, tKL3, SCK0 tSIK3, tKSO3, SB0, tKSI3, tKH3,
mode:
tKL5, SDA0, SDA1 tSBH tSBK tKSI5, tKH5, tSIK5, tKSO5, tKSB tSBK tKSB tKCY5,
µPD78P058FY
Automatic transmission/reception function 3-wire serial mode:
SIK9, KSO9,
KSI9, KH9,
SCK1 KL9, KCY9,
Automatic transmission/reception function 3-wire serial mode (busy processing):
SCK1
9Note
10Note
10+n Note
BUSY (Active high)
Note
signal actually here, represented this show timing.
UART mode (external clock input):
tKCY12 tKL12 ASCK tKH12
µPD78P058FY
Converter Characteristics +85°C, AVDD AVSS
Parameter Resolution Total error
Note
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
AVREF0 AVDD tCONV tSAMP VIAN AVREF0 RAIREF0 19.1 12/fXX AVSS
Conversion time Sampling time Analog input voltage Reference voltage AVREF0 AVSS resistance
AVREF0 AVDD
Note
Excluding quantization error (±1/2LSB). Shown percentage full scale value. pins which also function port pins (see Pins Normal Operating Mode Port pins), perform following operations during conversion. these operations performed, total error ratings cannot kept. Rewrite output latch while used port pin. Change output level used output pin, even used port pin.
Caution
Remarks
Main system clock frequency fX/2) Main system clock oscillation frequency
Converter Characteristics +85°C, AVSS
Parameter Resolution Total error MNote
Note Note
Symbol
Test Conditions
MIN.
TYP.
MAX.
Unit
Settling time
pFNote AVREF1 AVREF1
Output resistance Analog reference voltage AVREF1 AVSS resistance
AVREF1 RAIREF1
Note DACS0, DACS1 55HNote
Notes converter output load resistance load capacitance. Value converter channel Remark DACS0, DACS1 conversion value setting register
µPD78P058FY
Data Memory STOP Mode Supply Voltage Data Retention Characteristics +85°C)
Parameter Data retention supply voltage Data retention supply current Release signal setup time Oscillation stabilization wait time Symbol VDDDR IDDDR VDDDR Subsystem clock stopped, feedback resistor disconnected Test Conditions MIN. TYP. MAX. Unit
tSREL tWAIT
217/fX Note
Release RESET Release interrupt
Note
212/fXX, 214/fXX through 217/fXX selected bits (OSTS0 OSTS2) oscillation stabilization time selection register (OSTS).
Remark Main system clock frequency fX/2) Main system clock oscillation frequency Data Retention Timing (STOP mode release RESET)
Internal Reset Operation HALT Mode STOP Mode Operating Mode
Data Retention Mode
STOP Instruction Execution RESET
VDDDR tSREL
tWAIT
Data Retention Timing (Standby release signal: STOP mode release interrupt signal)
HALT Mode STOP Mode Operating Mode
Data Retention Mode
STOP Instruction Execution Standby Release Signal (Interrupt Request)
VDDDR tSREL
tWAIT
µPD78P058FY
Interrupt Input Timing
INTL INTP0 INTP6
INTH
RESET Input Timing
RESET
µPD78P058FY
PROM PROGRAMMING CHARACTERISTICS Characteristics PROM Write Mode ±5°C, ±0.25 12.5 ±0.3
Parameter Input voltage, high Input voltage, Output voltage, high Output voltage, Input leakage current supply voltage supply voltage supply current supply current Symbol SymbolNote 12.2 6.25 12.5 Test Conditions MIN. 12.8 6.75 TYP. MAX. Unit
PROM Read Mode ±5°C, ±0.5 ±0.6
Parameter Input voltage, high Input voltage, Output voltage, high Symbol VOH1 VOH2 Output voltage, Input leakage current Output leakage current supply voltage supply voltage supply current supply current SymbolNote VOH1 VOH2 ICCA1 VIL, -100 VOUT VDD, Test Conditions MIN. TYP. MAX. Unit
Note
Corresponding symbols µPD27C1001A.
µPD78P058FY
Characteristics PROM Write Mode Page program mode ±5°C, ±0.25 12.5 ±0.3
Parameter Address setup time setting time setup time Input data setup time Address hold time (from Symbol tOES tCES tAHL tAHV Input data hold time (from Data output float delay time from setup time setup time Program pulse width Valid data delay time from pulse width during data latching setting time hold time hold time tVPS tVDS tPGMS tCEH tOEH SymbolNote tOES tCES tAHL tAHV tVPS tVCS tPGMS tCEH tOEH Test Conditions MIN. 0.095 0.105 TYP. MAX. Unit
Byte program mode ±5°C, ±0.25 12.5 ±0.3
Parameter Address setup time PGM) setting time setup time PGM) Input data setup time PGM) Address hold time (from Input data hold time (from PGM) Data output float delay time from setup time PGM) setup time PGM) Program pulse width Valid data delay time from hold time Symbol tOES tCES tVPS tVDS tOEH SymbolNote tOES tCES tVPS tVCS Test Conditions MIN. 0.095 0.105 TYP. MAX. Unit
Note
Corresponding symbols µPD27C1001A.
µPD78P058FY
PROM Read Mode ±5°C, ±0.5 ±0.6
Parameter Data output delay time from address Data output delay time from Data output delay time from Data output float delay time from Data hold time from address Symbol tACC SymbolNote tACC Test Conditions MIN. TYP. MAX. Unit
Note
Corresponding symbols µPD27C1001A.
PROM Programming Mode Setting 25°C,
Parameter PROM programming mode setup time Symbol tSMA Test Conditions MIN. TYP. MAX. Unit
µPD78P058FY
PROM Write Mode Timing (page program mode)
Page Data Latch
Page Program
Program Verify
Hi-Z Hi-Z tPGMS Data Output Hi-Z tAHL tAHV
tVPS tVDS VDD+1.5
Data Input
tCES tOES tCEH
tOEH
µPD78P058FY
PROM Write Mode Timing (byte program mode)
Program Program Verify
Hi-Z VDD+1.5 tVDS tCES tOES tOEH tVPS Page Data Input Data Latch Hi-Z Data Output Hi-Z
Cautions should applied before VPP, removed after VPP. must exceed +13.5 including overshoot. Reliability adversely affected removal/reinsertion performed while +12.5 being applied VPP. PROM Read Mode Timing
Effective Address
tACC
Note
Note Data Output
Note Hi-Z
Hi-Z
Notes want read within tACC range, make input delay time from fall maximum tACC tOE. time from when either first reaches VIH.
µPD78P058FY
PROM Programming Mode Setting Timing
RESET
tSMA
Effective Address
µPD78P058FY
PACKAGE DRAWINGS Package Drawing µPD78P058FYGC-3B9
PLASTIC
detail lead
NOTE Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM
MILLIMETERS 17.2±0.4 14.0±0.2 14.0±0.2 17.2±0.4 0.825 0.825 0.30±0.10 0.13 0.65 (T.P.) 1.6±0.2 0.8±0.2 0.15 +0.10 -0.05 0.10 0.1±0.1 5°±5° MAX.
INCHES 0.677±0.016 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.016 0.032 0.032 0.012 +0.004 -0.005 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.006 +0.004 -0.003 0.004 0.106 0.004±0.004 5°±5° 0.119 MAX. S80GC-65-3B9-4
Remark dimensions materials product same those mass-production products.
µPD78P058FY
Package Drawing µPD78P058FYGC-8BT
PLASTIC
detail lead
NOTE Each lead centerline located within 0.13 (0.005 inch) true position (T.P.) maximum material condition.
ITEM MILLIMETERS 17.20±0.20 14.00±0.20 14.00±0.20 17.20±0.20 0.825 0.825 0.32±0.06 0.13 0.65 (T.P.) 1.60±0.20 0.80±0.20 0.17 +0.03 -0.07 0.10 1.40±0.10 0.125±0.075 1.70 MAX. INCHES 0.677±0.008 0.551 +0.009 -0.008 0.551 +0.009 -0.008 0.677±0.008 0.032 0.032 0.013 +0.002 -0.003 0.005 0.026 (T.P.) 0.063±0.008 0.031 +0.009 -0.008 0.007 +0.001 -0.003 0.004 0.055±0.004 0.005±0.003 0.067 MAX. P80GC-65-8BT
µPD78P058FY
RECOMMENDED SOLDERING CONDITIONS
µPD78P058FY should soldered mounted under conditions recommended below. details recommended soldering conditions, refer information document Semiconductor Device Mounting Technology Manual (C10535E). soldering methods conditions other than those recommended, please contact your sales representative. Table 9-1. Surface Mount Type Soldering Conditions
µPD78P058FYGC-3B9 80-pin plastic Resin thickness:
Soldering Method Infrared reflow Soldering Conditions Package peak temperature: 235°C, Reflow time: seconds below (210°C higher), Number reflow processes: max., Exposure limit: daysNote (after that, prebaking necessary 125°C hours) Package peak temperature: 215°C, Reflow time: seconds below (200°C higher), Number reflow processes: max., Exposure limit: daysNote (after that, prebaking necessary 125°C hours) Solder temperature: 260°C below, Flow time: seconds below, Number flow processes: Preheating temperature: 120°C below (package surface temperature), Exposure limit: daysNote (after that, prebaking necessary 125°C hours) temperature: 300°C below, Time: seconds below (per side device) Symbol IR35-207-3
VP15-207-3
Wave soldering
WS60-207-1
partial heating
Note
number days storage after pack been opened. Storage conditions 25°C max.
Cautions more than soldering method should avoided (except partial heating method). µPD78P058FYGC-8BT being under development, soldering conditions have been fixed.
µPD78P058FY
APPENDIX DEVELOPMENT TOOLS
following support tools available system development using µPD78P058FY. Language Processing Software
RA78K/0Notes CC78K/0
Notes Notes Notes
78K/0 Series common assembler package 78K/0 Series common compiler package
DF78054
µPD78054 Subseries common device file
78K/0 Series common compiler library source file
CC78K/0-L
PROM Writing Tools
PG-1500 PA-78P054GC PG-1500 controllerNotes PROM programmer Programmer adapter connected PG-1500 PG-1500 control program
Debugging Tools
IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78064-R-EMNote IE-780308-R-EM IE-78000-R-SV3 IE-70000-98-IF-B 78K/0 Series common in-circuit emulator 78K/0 Series common in-circuit emulator (for integrated debugger) 78K/0 Series common break board Emulation board common µPD78064 Subseries Emulation board common µPD780308 Subseries Interface adapter cable (for IE-78000-R-A) when using host machine Interface adapter (for IE-78000-R-A) when using PC-9800 Series (except notebook type computer) host machine IE-70000-98N-IF Interface adapter cable (for IE-78000-R-A) when using PC-9800 Series notebook type computer host machine IE-70000-PC-IF-B Interface adapter (for IE-78000-R-A) when using PC/ATand compatibles host machine EP-78230GC-R EV-9200GC-80 (see Figure A-1) SM78K0Notes ID78K0Notes SD78K/0Notes DF78054Notes Emulation probe common µPD78234 Subseries Socket mounting target system board created 80-pin plastic (GC-3B9, GC-8BT type) 78K/0 Series common system simulator Integrated debugger IE-78000-R-A Screen debugger IE-78000-R Device file common µPD78054 Subseries
µPD78P058FY
Real-Time
RX78K/0Notes MX78K0
Notes
78K/0 Series real-time 78K/0 Series
Fuzzy Inference Development Support System
FE9000Note 1/FE9200Note FT9080 FI78K0
Note
Fuzzy knowledge data input tool Translator Fuzzy inference module Fuzzy inference debugger
/FT9085
Note
Notes Notes
FD78K0
Notes PC-9800 Series (MS-DOSTM) based PC/AT compatibles DOSTM/IBM DOSTM/MS-DOS) based HP9000 Series 300(HP-UXTM) based HP9000 Series 700(HP-UX) based, SPARCstation(SunOSTM) based, EWS4800 Series (EWS-UX/V) based PC-9800 Series (MS-DOS WindowsTM) based PC/AT compatibles DOS/IBM DOS/MS-DOS Windows) based NEWS(NEWS-OSTM) based Maintenance product Remarks third party development tools, 78K/0 Series Selection Guide (U11126E). RA78K/0, CC78K/0, SM78K0, ID78K0, SD78K/0, RX78K/0 used combination with DF78054.
µPD78P058FY
Drawing Conversion Socket (EV-9200GC-80) Recommended Footprint Figure A-1. Drawing EV-9200GC-80 (for Reference only)
EV-9200GC-80
No.1 index
EV-9200GC-80-G1E ITEM MILLIMETERS 18.0 14.4 14.4 18.0 16.0 18.7 16.0 18.7 0.35 INCHES 0.709 0.567 0.567 0.709 0.079 0.031 0.236 0.63 0.736 0.236 0.63 0.736 0.323 0.315 0.098 0.079 0.014
0.091 0.059
µPD78P058FY
Figure A-2. Recommended Footprint EV-9200GC-80 (for Reference only)
EV-9200GC-80-P1E ITEM Caution MILLIMETERS 19.7 15.0 0.65±0.02 19=12.35±0.05 INCHES 0.776 0.591 0.026+0.001 -0.002 0.748=0.486 +0.003 -0.002
0.65±0.02 19=12.35±0.05 0.026 +0.001 0.748=0.486 +0.003 -0.002 -0.002 15.0 19.7 0.05 0.05 0.35 0.02 0.591 0.776 0.236 +0.003 -0.002 0.236 +0.003 -0.002 0.014 +0.001 -0.001
2.36 0.03 1.57 0.03
0.093+0.001 -0.002 0.091 0.062+0.001 -0.002
Dimensions mount EV-9200 that target device (QFP) different some parts. recommended mount dimensions QFP, refer "SEMICONDUCTOR DEVICE MOUNTING TECHNOLOGY MANUAL" (C10535E).
µPD78P058FY
APPENDIX RELATED DOCUMENTS
Device Documents
Document Name Document (English) U12068E This document U10121E U12326E Document (Japanese) U12068J U12076J U10121J U12326J U10904J U10903J
µPD78058F, 78058FY Subseries User's Manual µPD78P058FY Data Sheet µPD78056FY, 78058FY Data Sheet
78K/0 Series User's Manual Instructions 78K/0 Series Instruction 78K/0 Series Instruction Table
Caution
contents above documents subject change without notice. Please ensure that latest versions used design work, etc.
µPD78P058FY
Development Tool Documents (User's Manual)
Document Name RA78K Series Assembler Package Operation Language RA78K Series Structured Assembler Preprocessor RA78K0 Assembler Package Operation Assembly Language Structured Assembly Language CC78K Series Compiler Operation Language CC78K0 Compiler Operation Language CC78K/0 Compiler Application Note CC78K Series Library Source File PG-1500 PROM Programmer PG-1500 Controller PC-9800 Series (MS-DOS) based PG-1500 Controller Series DOS) based IE-78000-R IE-78000-R-A IE-78000-R-BK IE-78064-R-EM IE-780308-R-EM EP-78230 SM78K0 System Simulator Windows based SM78K Series System Simulator Reference External Part User Open Interface Specifications ID78K0 Integrated Debugger based ID78K0 Integrated Debugger based ID78K0 Integrated Debugger Windows based SD78K/0 Screen Debugger PC-9800 Series (MS-DOS) based SD78K/0 Screen Debugger PC/AT DOS) based Reference Reference Guide Introduction Reference Introduction Reference U11539E U11649E U10539E U11279E U11151J U11539J U11649J EEU-852 U10952J EEU-5024 U11279J Programming Know-how EEU-1280 EEU-1284 U11517E U11518E EEA-1208 EEU-1335 EEU-1291 U10540E U11376E U10057E EEU-1427 EEU-1443 U11362E EEU-1515 U10181E U10092E EEU-656 EEU-655 U11517J U11518J EEA-618 U12322J U11940J EEU-704 EEU-5008 U11376J U10057J EEU-867 EEU-905 U11362J EEU-985 U10181J U10092J Document (English) EEU-1399 EEU-1404 EEU-1402 U11802E U11801E U11789E Document (Japanese) EEU-809 EEU-815 U12323J U11802J U11801J U11789J
Caution
contents above documents subject change without notice. Please ensure that latest versions used design work, etc.
µPD78P058FY
Embedded Software Documents (User's Manual)
Document Name 78K/0 Series Real-time Basics Installation 78K/0 Series MX78K0 Fuzzy Knowledge Data Input Tools 78K/0, 78K/II, 87AD Series Fuzzy Inference Development Support System Translator 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Module 78K/0 Series Fuzzy Inference Development Support System Fuzzy Inference Debugger EEU-1441 EEU-1458 EEU-858 EEU-921 Basics Document (English) U11537E U11536E U12257E EEU-1438 EEU-1444 Document (Japanese) U11537J U11536J U12257J EEU-829 EEU-862
Other Documents
Document Name Package Manual Semiconductor Device Mounting Technology Manual Quality Grades Semiconductor Devices Semiconductor Device Reliability/Quality Control System Electrostatic Discharge (ESD) Test Guide Quality Assurance Semiconductor Devices Microcomputer Product Series Guide Document (English) C10943X C10535E C11531E C10983E MEI-1202 C10535J C11531J C10983J MEM-539 C11893J U11416J Document (Japanese)
Caution
contents above documents subject change without notice. Please ensure that latest versions used design work, etc.
µPD78P058FY
NOTES CMOS DEVICES
PRECAUTION AGAINST SEMICONDUCTORS
Note: Strong electric field, when exposed device, cause destruction gate oxide ultimately degrade device operation. Steps must taken stop generation static electricity much possible, quickly dissipate once, when occurred. Environmental control must adequate. When dry, humidifier should used. recommended avoid using insulators that easily build static electricity. Semiconductor devices must stored transported anti-static container, static shielding conductive material. test measurement tools including work bench floor should grounded. operator should grounded using wrist strap. Semiconductor devices must touched with bare hands. Similar precautions need taken boards with semiconductor devices
HANDLING UNUSED INPUT PINS CMOS
Note: connection CMOS device inputs cause malfunction. connection provided input pins, possible that internal input level generated noise, etc., hence causing malfunction. CMOS device behave differently than Bipolar NMOS devices. Input levels CMOS devices must fixed high using pull-up pull-down circuitry. Each unused should connected with resistor, considered have possibility being output pin. handling related unused pins must judged device device related specifications governing devices.
STATUS BEFORE INITIALIZATION DEVICES
Note: Power-on does necessarily define initial status device. Production process does define initial operation status device. Immediately after power source turned devices with reset function have been initialized. Hence, power-on does guarantee out-pin levels, settings contents registers. Device initialized until reset signal received. Reset operation must executed immediately after power-on devices having reset function.
µPD78P058FY
Regional Information
Some information contained this document vary from country country. Before using product your application, please contact office your country obtain list authorized representatives distributors. They will verify: Device availability Ordering information Product release schedule Availability related technical literature Development environment specifications (for example, specifications third-party tools components, host computers, power plugs, supply voltages, forth) Network requirements addition, trademarks, registered trademarks, export restrictions, other legal issues also vary from country country.
Electronics Inc. (U.S.)
Santa Clara, California Tel: 800-366-9782 Fax: 800-729-9288
Electronics (Germany) GmbH
Benelux Office Eindhoven, Netherlands Tel: 040-2445845 Fax: 040-2444580
Electronics Hong Kong Ltd.
Hong Kong Tel: 2886-9318 Fax: 2886-9022/9044
Electronics (Germany) GmbH
Duesseldorf, Germany Tel: 0211-65 Fax: 0211-65
Electronics Hong Kong Ltd. Electronics (France) S.A.
Velizy-Villacoublay, France Tel: 01-30-67 Fax: 01-30-67 Seoul Branch Seoul, Korea Tel: 02-528-0303 Fax: 02-528-4411
Electronics (UK) Ltd.
Milton Keynes, Tel: 01908-691-133 Fax: 01908-670-290
Electronics (France) S.A.
Spain Office Madrid, Spain Tel: 01-504-2787 Fax: 01-504-2860
Electronics Singapore Pte. Ltd.
United Square, Singapore 1130 Tel: 253-8311 Fax: 250-3583
Electronics Italiana s.r.1.
Milano, Italy Tel: 02-66 Fax: 02-66
Electronics Taiwan Ltd. Electronics (Germany) GmbH
Scandinavia Office Taeby, Sweden Tel: 08-63 Fax: 08-63 Taipei, Taiwan Tel: 02-719-2377 Fax: 02-719-5951
Brasil S.A.
Paulo-SP, Brasil Tel: 011-889-1680 Fax: 011-889-1689
J96.
µPD78P058FY
Purchase components conveys license under Philips Patent Rights these components system, provided that system conforms Standard Specification defined Philips. FIP, IEBus, QTOP trademarks Corporation. MS-DOS Windows either registered trademarks trademarks Microsoft Corporation United States and/or other countries. DOS, PC/AT, trademarks International Business Machines Corporation. HP9000 Series 300, HP9000 Series 700, HP-UX trademarks Hewlett-Packard Company. SPARCstation trademark SPARC International, Inc. SunOS trademark Microsystems, Inc. NEWS NEWS-OS trademarks Sony Corporation.
export this product from Japan regulated Japanese government. export this product prohibited without governmental license, need which must judged customer. export re-export this product from country other than Japan also prohibited without license from that country. Please call sales representative.
part this document copied reproduced form means without prior written consent Corporation. Corporation assumes responsibility errors which appear this document. Corporation does assume liability infringement patents, copyrights other intellectual property rights third parties arising from device described herein other liability arising from such device. license, either express, implied otherwise, granted under patents, copyrights other intellectual property rights Corporation others. While Corporation been making continuous effort enhance reliability semiconductor devices, possibility defects cannot eliminated entirely. minimize risks damage injury persons property arising from defect semiconductor device, customers must incorporate sufficient safety measures design, such redundancy, fire-containment, anti-failure features. devices classified into following three quality grades: "Standard", "Special", "Specific". Specific quality grade applies only devices developed based customer designated "quality assurance program" specific application. recommended applications device depend quality grade, indicated below. Customers must check quality grade each device before using particular application. Standard: Computers, office equipment, communications equipment, test measurement equipment, audio visual equipment, home electronic appliances, machine tools, personal electronic equipment industrial robots Special: Transportation equipment (automobiles, trains, ships, etc.), traffic control systems, anti-disaster systems, anti-crime systems, safety equipment medical equipment (not specifically designed life support) Specific: Aircrafts, aerospace equipment, submersible repeaters, nuclear reactor control systems, life support systems medical equipment life support, etc. quality grade devices "Standard" unless otherwise specified NEC's Data Sheets Data Books. customers intend devices applications other than those specified Standard quality grade, they should contact sales representative advance. Anti-radioactive design implemented this product.
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