TigerSHARC® Microcomputer ADSP-TS101S BENEFITS Provides High-Perf
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Preliminary Technical DatKEY FEATURES Operates MHz, Instruction Cycle Rate Bits Internal-On-Chip-SRAM Memory Comes Either (484-Ball) (625-Ball) PBGA Package Contains Dual Computation Blocks-Each Containing ALU, Multiplier, Shifter, Register File Contains Dual Integer ALUs, providing Data Addressing Pointer Manipulation Includes External Port, Four Link Ports, SDRAM Controller, Programmable Flag Pins, Timers, Timer Expired System Integration Includes 1149.1 IEEE Compliant JTAG Test Access Port On-Chip Emulation On-Chip Arbitration Glueless Multiprocessing With Eight TigerSHARC DSPs Common
TigerSHARC® Microcomputer ADSP-TS101S
BENEFITS Provides High-Performance Static Superscalar Operations, Optimized Telecommunications Infrastructure Other Large, Demanding Multiprocessor Applications Performs Exceptionally Well Algorithm Benchmarks (See Benchmarks Table Table Includes Controller Support Channels, Performing Low-Overhead Transfers Between Internal Memory, External Memory, Memory-Mapped Peripherals, Link Ports, Host Processors, Other (Multiprocessor) DSPs Eases Programming Through Extremely Flexible Instruction High-Level-Language Friendly Architecture
FUNCTIONAL BLOCK DIAGRAM
COMPUTATIONAL BLOCKS SHIFTER PROGRAM SEQUENCER DATA ADDRESS GENERATION INTEGER 32X32 INTEGER 32X32 INTERNAL MEMORY MEMORY MEMORY MEMORY JTAG PORT
MULTIPLIER
ADDR FETCH
SDRAM CONTROLLER
REGISTER FILE 32x32
ADDR DATA
EXTERNAL PORT MULTIPROCESSOR INTERFACE HOST INTERFACE
ADDR DATA INPUT FIFO
ADDR DATA
OUTPUT BUFFER ADDR OUTPUT FIFO DATA ADDRESS PROCESSOR CONTROLLER ADDRESS SHIFTER CONTROL/ STATUS/ TCB'S DATA LINK PORT CONTROLLER LINK PORTS CONTROL/ STATUS/ BUFFERS CLUSTER ARBITOR
CNTRL
REGISTER FILE 32x32 MULTIPLIER
LINK DATA
TigerSHARC TigerSHARC logo registered trademarks Analog Devices, Inc. REV.
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TABLE CONTENTS
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GENERAL DESCRIPTION
Features Benefits General Description Dual Compute Blocks Data Alignment Buffer (DAB) Dual Integer ALUs (IALUs) Program Sequencer Interrupt Controller Flexible Instruction On-Chip SRAM Memory External Port (Off-Chip Memory/Peripherals Interface) Host Interface Multiprocessor Interface SDRAM Controller EPROM Interface Controller Link Ports Timer General-Purpose Reset Booting Low-Power Operation Clock Domains Power Supplies Filtering Reference Voltage Clocks Development Tools Designing Emulator-Compatible Board (Target) Additional Information Function Descriptions Strap Function Descriptions ADSP-TS101S-Specifications ABSOLUTE MAXIMUM RATINGS SENSITIVITY Timing Specifications General Timing Link Port Data Transfer Token Switch Timing Output Drive Currents Power Dissipation Internal Power Calculation External Power Calculation Test Conditions Output Disable Time Output Enable Time Capacitive Loading Environmental Conditions Thermal Characteristics 484-Ball PBGA Configurations 625-Ball PBGA Configurations Outline Dimensions Ordering Guide
ADSP-TS101S TigerSHARC ultra-high performance, static superscalar processor optimized large signal processing tasks communications infrastructure. combines very wide memory widths with dual computation blocks-supporting 32-bit floating-point supporting 16-, 32-, 64-bit fixed-point processing-to standard performance digital signal processors. TigerSHARC static superscalar architecture lets execute four instructions each cycle, performing twenty-four 16-bit fixedpoint operations floating-point operations. Three independent 128-bit wide internal data buses, each connecting three memory banks, enable quadword data, instruction, accesses provide bytes second internal memory bandwidth. Operating MHz, ADSP-TS101S's core instruction cycle time. Using Single-Instruction, Multiple-Data (SIMD) features, ADSP-TS101S perform billion 40-bit MACs million 80-bit MACs second. Table Table show DSP's performance benchmarks.
Table General Purpose Algorithm Benchmarks Benchmark Speed Clock Cycles
32-bit Algorithm, million MACs/s peak performance 1024 Point Complex (Radix 39.34 9,835 50-tap 1024 input 27,500 Single 0.55 16-bit Algorithm, billion MACs/s peak performance Point Complex (Radix 1,100 50-tap 1024 input 28.8 7,200 Single 0.56 0.14 Single Complex 2.28 0.57 Transfer Rate External port 800M bytes/s Link ports (each) 250M bytes/s n/Table Wireless Algorithm Benchmarks Benchmark Execution (MIPS)1
Turbo Decode MIPS kbps Data Channel Viterbi Decode 0.86 MIPS 12.2 kbps AMR2 Voice Channel Complex Correlation 0.27 MIPS 3.84 Mcps3 with Spreading Factor
Execution Speed Instruction Cycles Second. Adaptive Multi Rate (AMR) Megachips second (Mcps)
ADSP-TS101S code-compatible with other TigerSHARC processors.
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ADSP-TS101S
BOOT EPROM (OPTIONAL)
Functional Block Diagram page shows ADSPTS101S's architectural blocks. These blocks include: Dual compute blocks, each consisting ALU, multiplier, 64-bit shifter, 32-word register file associated Data Alignment Buffers (DABs) Dual integer ALUs (IALUs), each with 31-word register file data addressing program sequencer with Instruction Alignment Buffer (IAB), Branch Target Buffer (BTB), interrupt controller Three 128-bit internal data buses, each connecting three memory banks On-chip SRAM bit) external port that provides interface host processors, multiprocessing space (DSPs), off-chip memorymapped peripherals, external SRAM SDRAM controller Four link ports 32-bit interval timers timer expired 1149.1 IEEE compliant JTAG test access port onchip emulation Figure page shows typical single-processor system with external SDRAM. Figure page shows typical multiprocessor system. TigerSHARC uses Static Superscalar1 architecture. This architecture superscalar that ADSP-TS101S's core execute simultaneously from four 32-bit instructions encoded Very Large Instruction Word (VLIW) instruction line using DSP's dual compute blocks. Because does perform instruction re-ordering runtime-the programmer selects which operations will execute parallel prior runtime, order instructions static. With exceptions, instruction line, whether contains one, two, three, four 32-bit instructions, executes with throughput cycle eight-deep processor pipeline. optimal program execution, programmers must follow DSP's instruction parallelism rules when encoding instruction line. general, selection instructions that execute parallel each cycle depends instruction line resources each instruction requires source destination registers used instructions. programmer direct control three core components-the IALUs, compute blocks, program sequencer. ADSP-TS101S, most cases, two-cycle execution pipeline that fully interlocked, whenever computation result unavailable another operation dependent automatically inserts more stall cycles needed.
CLOCK REFERENCE
ADSP-TS101
LCLK_P SCLK_P S/LCLK_N VREF BRST LCLKRAT2-0 SCLKFREQ ADDR31-0 IRQ3-0 FLAG3-0 ID2-0 MSSD LDQM HDQM SDWE SDCKE SDA10 FLYBY IOEN LINK DEVICES MAX) (OPTIONAL) LXDAT7-0 LXCLKIN LXCLKOUT LXDIR TMR0E BUSLOCK CONTROLIMP2-0 DS2-0 RESET JTAG DATA63-0 WRH/WRL MS1-0 BR7-0 BOFF DMAR3-0
ADDR DATA
MEMORY (OPTIONAL)
ADDR DATA
HOST PROCESSOR INTERFACE (OPTIONAL)
SDRAM MEMORY (OPTIONAL)
ADDR DATA
ADDR DATA
DEVICE (OPTIONAL)
DATA
CONTROL
ADDRESS
Figure ADSP-TS101S single-processor system with external SDRAM
Efficient programming with dependency-free instructions eliminate most computational memory transfer data dependencies. addition, ADSP-TS101S supports SIMD operations ways-SIMD compute blocks SIMD computations.The programmer direct both compute blocks operate same data (broadcast distribution) different data (merged distribution). addition, each compute block execute four 16-bit eight 8-bit SIMD computations parallel.
Dual Compute Blocks
ADSP-TS101S compute blocks, that execute computations either independently together SingleInstruction, Multiple-Data (SIMD) engine. issue compute instructions compute block each cycle, instructing ALU, multiplier, shifter perform independent, simultaneous operations.
Static Superscalaris trademark Analog Devices, Inc.
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DATA
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compute blocks referred assembly syntax, each block contains three computational units-an ALU, multiplier, 64-bit shifter-and 32-word register file. Register File-Each Compute Block multiported 32-word, fully orthogonal register file used transferring data between computation units data buses storing intermediate results. Instructions access registers register file individually (wordaligned), sets (dual-aligned) four (quadaligned). ALU-The performs standard arithmetic operations both fixed- floating-point formats. also performs logic operations. Multiplier-The multiplier performs both fixed- floating-point multiplication fixed-point multiply accumulate. Shifter-The 64-bit shifter performs logical arithmetic shifts, bitstream manipulation, field deposit extraction operations. Accelerator-128-bit unit Trellis Decoding (for example, Viterbi Turbo decoders) complex correlations communication applications Using these features, compute blocks can: Provide MACs cycle peak MACs cycle sustained 16-bit performance provide MACs cycle peak MACs cycle sustained 32-bit performance (based FIR) Execute single-precision floating-point execute twenty-four 16-bit fixed-point operations cycle, providing 1500 MFLOPS GOPS performance Performs complex 16-bit MACs cycle Executes eight Trellis butterflies cycle
Data Alignment Buffer (DAB)
address generators, IALUs perform immediate indirect (pre- post-modify) addressing. They perform modulus bit-reverse operations with constraints placed memory addresses modulus data buffer placement. Each IALU specify either single-, dual-, quad-word access from memory. IALUs have hardware support circular buffers, reverse, zero-overhead looping. Circular buffers facilitate efficient programming delay lines other data structures required digital signal processing, they commonly used digital filters Fourier transforms. Each IALU provides registers four circular buffers, applications total eight circular buffers. IALUs handle address pointer wraparound automatically, reducing overhead, increasing performance, simplifying implementation. Circular buffers start memory location. Because IALU's computational pipeline cycle deep, most cases integer results available next cycle. Hardware (register dependency check) causes stall result unavailable given cycle.
Program Sequencer
ADSP-TS101S's program sequencer supports following: fully interruptible programming model with flexible programming assembly C/C++ languages; handles hardware interrupts with high throughput aborted instruction cycles eight-cycle instruction pipeline-three-cycle fetch pipe five-cycle execution pipe-computation results available cycles after operands available Supply instruction fetch memory addresses; sequencer's Instruction Alignment Buffer (IAB) caches five fetched instruction lines waiting execute; program sequencer extracts instruction line from distributes appropriate core component execution. Management program structures program flow determined according JUMP, CALL, RTI, instructions, loop structures, conditions, interrupts, software exceptions Branch prediction 128-entry branch target buffer (BTB) reduce branch delays efficient execution conditional unconditional branch instructions zero-overhead looping; correctly predicted branches that taken occur with zero-to-two overhead cycles, overcoming three- to-six stage branch penalty Compact code without requirement align code memory; handles alignment
Interrupt Controller
quad-word FIFO that enables loading quadword data from nonaligned addresses. Normally, load instructions must aligned their data size that quad words loaded from quad-aligned address. Using significantly improves efficiency some applications, such filters.
Dual Integer ALUs (IALUs)
ADSP-TS101S IALUs that provide powerful address generation capabilities perform many generalpurpose integer operations. IALUs have following features: Provides memory addresses data update pointers Supports circular buffering bit-reverse addressing Performs general-purpose integer operations, increasing programming flexibility Includes 31-word register file each IALU
supports nested nonnested interrupts. Each interrupt type register interrupt vector table. Also, each both interrupt latch register interrupt
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ADSP-TS101S
mask register. interrupts fixed either level-sensitive edge-sensitive, except IRQ3-0 hardware interrupts, which programmable. distinguishes between hardware interrupts software exceptions, handling them differently. When software exception occurs, aborts other instructions instruction pipe. When hardware interrupt occurs, continues execute instructions already instruction pipe.
Flexible Instruction
second, enabling core access eight 32-bit data words (256 bits) four 32-bit instructions each cycle. DSP's flexible memory structure enables: core access different memory blocks same cycle core access three memory blocks parallel-one instruction data accesses Programmable partitioning program data memory Program access memory 32-, 64-, 128-bit words-16-bit words with Complete context switch less than cycles
External Port (Off-Chip Memory/Peripherals Interface)
128-bit instruction line, which contain four 32-bit instructions, accommodates variety parallel operations concise programming. example, instruction line direct conditionally execute multiply, add, subtract both computation blocks while also branches another location program. Some features instruction include: Enhanced instructions communications infrastructure govern Trellis Decoding (for example, Viterbi Turbo decoders) Despreading complex correlations Algebraic assembly language syntax Direct support DSP, imaging, video arithmetic types, eliminating hardware modes Branch prediction encoded instruction, enables zerooverhead loops Parallelism encoded instruction line Conditional execution optional instructions User defined partitioning between program data memory
On-Chip SRAM Memory
ADSP-TS101S's external port provides DSP's interface off-chip memory peripherals. word address space included DSP's unified address space. separate onchip buses-three 128-bit data buses three 32-bit address buses-are multiplexed external port create external system with single 64-bit data single 32-bit address bus. external port supports data transfer rates 800M bytes second over external bus. external configured 64-bit operation. When system configured 64-bit operation, lower bits external data connect even addresses, upper bits connect addresses. external port supports pipelined, slow, SDRAM protocols. Addressing external memory devices memorymapped peripherals facilitated on-chip decoding highorder address lines generate memory bank select signals. ADSP-TS101S provides programmable memory, pipeline depth, idle cycle synchronous accesses, external acknowledge controls support interfacing pipelined slow devices, host processors, other memory-mapped peripherals with variable access, hold, disable time requirements.
Host Interface
ADSP-TS101S bits on-chip SRAM memory, divided into three blocks bits (64K words bits). Each block-M0, M2-can store program, data, both, applications configure memory suit specific needs. Placing program instructions data different memory blocks, however, enables access data while performing instruction fetch. DSP's internal external memory organized into unified memory map, which defines location (address) elements system, shown Figure memory divided into four memory areas-host space, external memory, multiprocessor space, internal memory- each memory space, except host memory, subdivided into smaller memory spaces. Each internal memory block connects 128-bit wide internal buses-block MD0, block MD1, block MD2-enabling perform three memory transfers same cycle. DSP's internal architecture provides total memory bandwidth bytes
ADSP-TS101S provides easy configurable interface between external host processors through external port. accommodate variety host processors, host interface supports pipelined slow protocols accesses host slave. Each protocol programmable transmission parameters, such idle cycles, pipe depth, internal wait cycles. host interface supports burst transactions initiated host processor. After host issues starting address burst asserts BRST signal, increments address internally while host continues assert BRST. host interface provides deadlock recovery mechanism that enables host recover from deadlock situations involving DSP. BOFF signal provides deadlock recovery mechanism. When host asserts BOFF, backs current transaction asserts relinquishes external bus.
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0xFFFFFFFF
GLOBAL SPACE
HOST
INTERNAL SPACE
0x003FFFFF
0x10000000 BANK (MS1) 0x0C000000 BANK (MS0) 0x08000000 SDRAM 0x04000000
0x00300000
RESERVED
0x00280000
0x00200000
EXTERNAL MEMO SPACE
MULTIPROCESSOR MEMO SPACE
PROCESSOR 0x03C00000 PROCESSOR 0x03800000 PROCESSOR 0x03400000 PROCESSOR 0x03000000 PROCESSOR 0x02C00000 PROCESSOR 0x02800000 PROCESSOR 0x02400000 PROCESSOR 0x02000000 BROADCAST 0x01C00000 EACH COPY INTERNAL SPACE
0x001807FF INTERNAL REGISTERS (UREGS) 0x00180000 RESERVED 0x0010FFFF INTERNAL MEMO 0x00100000 RESERVED 0x0008FFFF INTERNAL MEMO 0x00080000
RESERVED RESERVED 0x0000FFFF INTERNAL MEMO 0x00000000 NTERNAL MEMORY 0x00000000 0x003FFFFF
Figure ADSP-TS101S memory
host directly read write internal memory ADSP-TS101S, access most registers, including control (TCB) registers. Vector interrupts support efficient execution host commands.
Multiprocessor Interface
ADSP-TS101S offers powerful features tailored multiprocessing systems through external port link ports. This multiprocessing capability provides highest bandwidth interprocessor communication, including: eight DSPs common On-chip arbitration glueless multiprocessing Link ports point point communication external port link ports provide integrated, glueless multiprocessing support.
external port supports unified address space (see Figure that enables direct interprocessor accesses each ADSPTS101S's internal memory registers. DSP's on-chip distributed arbitration logic provides simple, glueless connection systems containing eight ADSP-TS101Ss host processor. arbitration rotating priority. lock supports indivisible read-modify-write sequences semaphores. fairness feature prevents from holding external long. DSP's four link ports provide second path interprocessor communications with throughput bytes second. cluster provides 800M bytes second throughput-with total 1.8G bytes second interprocessor bandwidth.
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ADSP-TS101S
CONTROL
ADDRESS ADDRESS
ADSP-TS101 ID2-0 RESET CLKS/REFS LINK BR7-2,0 ADDR31-0 DATA63-0 CONTROL
CONTROL
RESET
ID2-0 RESET CLKS/REFS
BR7-1 ADDR31-0 DATA63-0 WRH/L MS1-0 BUSLOCK BOFF DMAR3-0 BRST FLYBY IOEN
DATA
ADSP-TS101
DATA
ADSP-TS101 ADSP-TS101 ADSP-TS101 ADSP-TS101 ADSP-TS101 ADSP-TS101
ADDR DATA ADDR DATA GLOBAL MEMORY PERIPHERALS (OPTIONAL)
SCLK_P CLOCK REFERENCE VOLTAGE LCLK_P S/LCLK_N VREF LCLKRAT2-0 SCLKFREQ IRQ3-0 FLAG3-0 LINK
BOOT EPROM (OPTIONAL)
CLOCK HOST PROCESSOR INTERFACE (OPTIONAL)
ADDR DATA ADDR DATA
LINK DEVICES MAX) (OPTIONAL)
LXDAT7-0 LXCLKIN LXCLKOUT LXDIR
MSSD LDQM HDQM SDWE SDCKE SDA10 CONTROL
SDRAM MEMORY (OPTIONAL)
TMR0E CONTROLIMP2-0 DS2-0
Figure ADSP-TS101S Shared Memory Multiprocessing System SDRAM Controller
SDRAM controller controls ADSP-TS101S's transfers data from synchronous DRAM (SDRAM) throughput bits SCLK cycle using external port SDRAM control pins. SDRAM interface provides glueless interface with standard SDRAMs-16M bit, bit, 128M bit, 256M bit. supports directly maximum words SDRAM. SDRAM interface mapped external memory DSP's unified memory map.
EPROM Interface
into internal memory. This process uses sixteen wait cycles each read access. During booting, functions EPROM chip select signal. EPROM boot procedure uses channel which packs bytes into 32-bit instructions. Applications also access EPROM (write flash memories) during normal operation through DMA. EPROM Flash Memory interface mapped DSP's unified memory map. byte address space limited maximum bytes (twenty-four address bits). EPROM Flash Memory interface used after boot DMA.
ADSP-TS101S configured boot from external 8bit EPROM reset through external port. automatic process (which follows reset) loads program from EPROM REV.
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Controller
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Link Ports
ADSP-TS101S's on-chip controller, with channels, provides zero-overhead data transfers without processor intervention. controller operates independently invisibly DSP's core, enabling operations occur while DSP's core continues execute program instructions. controller performs transfers between internal memory external memory memorymapped peripherals, internal memory other DSPs common bus, host processor, link port I/O; between external memory external peripherals link port I/O; between external master internal memory link port I/O. controller performs following operations: External port block transfers. Four dedicated bidirectional channels transfer blocks data between DSP's internal memory external memory memory-mapped peripheral external bus. These transfers support master mode handshake mode protocols. Link port transfers. Eight dedicated channels (four transmit four receive) transfer quad-word data only between link ports between link port internal external memory. These transfers only handshake mode protocol. priority rotates between four receive channels. AutoDMA transfers. dedicated unidirectional channels transfer data received from external master internal memory link port I/O. These transfers only slave mode protocol, external master must initiate transfer. controller provides these additional features: Flyby transfers. Flyby operations only occur through external port (DMA channel involve DSP's core. controller acts conduit transfer data from external device another through external memory. During transaction, relinquishes external data bus; outputs addresses, memory selects (MS1-0) FLYBY, IOEN, RD/WR strobes; responds ACK. chaining. chaining operations enable applications automatically link transfer sequence another continuous transmission. sequences occur over different channels have different transmission attributes. Two-dimensional transfers. controller access transfer two-dimensional memory arrays transmit receive channel. These transfers implemented with index, count, modify registers both dimensions.
DSP's four link ports provide additional eight-bit bidirectional capability. With ability operate double data rate-latching data both rising falling edges clock-running MHz, each link port support 250M bytes second, combined maximum throughput bytes second. link ports provide optional communications channel that useful multiprocessor systems implementing point-topoint interprocessor communications. Applications also link ports booting. Each link port double-buffered input output registers. DSP's core write directly link port's transmit register read from receive register, controller perform transfers through eight (four transmit four receive) dedicated link port channels. Each link port three signals that control operation. LxCLKOUT LxCLKIN implement clock/acknowledge handshaking. LxDIR indicates direction transfer used only when buffering LxDAT signals. example application would using differential low-swing buffers long twisted-pair wires. LxDAT provides 8-bit data input/output. Applications program separate error detection mechanisms transmit receive operations (applications checksum mechanism implement consecutive link port transfers), size data packets, speed which bytes transmitted. Under certain conditions, link port receiver initiate token switch reverse direction transfer; transmitter becomes receiver vice versa.
Timer General-Purpose
ADSP-TS101S timer (TMR0E) that generates output when programmed timer counter expired four programmable general-purpose pins (FLAG3-0) that function either single-bit input output. outputs, these pins signal peripheral devices; inputs, they provide test conditional branching.
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Reset Booting
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ADSP-TS101S
Low-Power Operation
ADSP-TS101S three levels reset: Power-up reset-After power-up system, strap options stable, RESET must asserted (low) minimum followed deasserted (high) pulse minimum SCLK cycles maximum SCLK cycles asserted (low) minimum SCLK cycles. TRST must also asserted (low) during power-up ensure proper operation device. Figure Normal reset-For resets following power-up reset sequence, RESET must asserted least SCLK cycles. Core reset-When setting SQRST SQCTL, core reset, external port I/O.
ADSP-TS101S enter low-power sleep mode, which core does execute instructions, reducing power consumption minimum. ADSP-TS101S exits sleep mode when senses falling edge IRQ3-0 interrupt inputs. interrupt, enabled, causes ADSP-TS101S execute corresponding interrupt service routine. This feature useful systems that require low-power standby mode.
Clock Domains
ADSP-TS101S clock inputs that drive major clock domains: SCLK (system clock). Provides clock input external interface defines specification reference external signals. external interface runs SCLK frequency. locks internal SCLK SCLK input. maximum SCLK frequency half internal clock (CCLK) frequency. SCLK must connected same clock source LCLK. LCLK (local clock). Provides clock input internal clock driver, CCLK, which internal clock core, internal buses, memory, link ports. instruction execution rate equal CCLK. from LCLK generates CCLK which phase-locked. LCLKRAT pins define clock multiplication LCLK CCLK (see Table page 13). link port clock generated from CCLK software programmable divisor. RESET must asserted until LCLK stable within specification least This applies power-up well dynamic modification LCLK after powerup. Dynamic modification include LCLK going specification long RESET asserted. Connecting SCLK LCLK same clock source requirement device. Using integer clock multiplication value provides predictable cycle-by-cycle operation, requirement fault-tolerant systems some multiprocessing systems.
Power Supplies
RESET
tSTART_LO
NOTES:
tPULSE1_HI
tPULSE2_LO
tSTART_LO MINIMUM AFTER POWER SUPPLIES STABLE tPULSE1_HI SCLK MINIMUM SCLK MAXIMUM tPULSE2_LO SCLK MINIMUM
Figure Power-up Reset Waveform
After reset, ADSP-TS101S four boot options beginning operation: Boot from EPROM. defaults EPROM booting when strap option low. more information, Strap Function Descriptions page Boot external master (host another ADSPTS101S). master cluster boot ADSP-TS101S through writes internal memory through auto DMA. Boot link port. four receive link channels initialized after reset transfer 256-word block internal memory address 255, issue interrupt block (similar DMA). corresponding interrupts address zero (0). boot-Start running from external memory. Using boot' option, ADSP-TS101S must start running from external memory, caused asserting IRQ3-0 interrupt signals. ADSP-TS101S core always exits from reset idle state waits interrupt. Some interrupts interrupt vector table initialized enabled after reset.
ADSP-TS101S separate power supply connections internal logic (VDD), analog circuits (VDD_A), buffer (VDD_IO) power supply. internal (VDD) analog (VDD_A) supplies must meet requirement. buffer (VDD_IO) supply must meet requirement. Note that analog (VDD_A) supply powers clock generator PLLs. produce stable clock, systems must provide clean power supply power input VDD_A. Designs must critical attention bypassing VDD_A supply. ideal power sequence provide power supplies simultaneously. there going some delay between power supplies, provide (and VDD_A) first, then VDD_IO.
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Filtering Reference Voltage Clocks
Debug source-level code Create custom debugger windows VisualDSP++ lets programmers define manage software development. dialog boxes property pages programmers configure manage TigerSHARC development tools, including syntax highlighting VisualDSP++ editor. This capability lets programmers: Control development tools process inputs generate outputs. Maintain one-to-one correspondence with tool's command line switches. Analog Devices' emulators IEEE 1149.1 JTAG test access port ADSP-TS101S processor monitor control target board processor during emulation. emulator provides full-speed emulation, allowing inspection modification memory, registers, processor stacks. Nonintrusive in-circuit emulation assured processor's JTAG interface-the emulator does affect target system loading timing. addition software hardware development tools available from Analog Devices, third parties provide wide range tools supporting TigerSHARC processor family. Hardware tools include TigerSHARC plug-in cards. Third Party software tools include libraries, real-time operating systems, block diagram design tools.
Designing Emulator-Compatible Board (Target)
Figure shows possible circuit filtering VREF, SCLK_N, LCLK_N. This circuit provides reference voltage switching voltage, system clock, local clock references.
VDD_IO VREF SCLK_N LCLK_N
SERIES RESISTOR 1.67 SERIES RESISTOR CAPACITOR (SMD) CAPACITOR SMD) PLACED CLOSE DSP'S PINS
Figure VREF, SCLK_N, LCLK_N filtering scheme Development Tools
ADSP-TS101S supported with complete software hardware development tools, including Analog Devices' emulators VisualDSP++2 development environment. same emulator hardware that supports other TigerSHARC DSPs also fully emulates ADSP-TS101S. VisualDSP++ project management environment lets programmers develop debug application. This environment includes easy-to-use assembler (which based algebraic syntax), archiver (librarian/library builder), linker, loader, cycle-accurate instruction-level simulator, C/C++ compiler, C/C++ run-time library that includes mathematical functions. points these tools are: Compiled TigerSHARC C/C++ code efficiency-the compiler been developed efficient translation C/C++ code TigerSHARC assembly. architectural features that improve efficiency compiled C/C++ code. TigerSHARC family code compatibility-The assembler legacy features ease conversion existing previous TigerSHARC applications ADSPTS101S. Debugging both C/C++ assembly programs with VisualDSP++ debugger, programmers can: View mixed C/C++ assembly code (interleaved source object information) Insert break points conditional breakpoints registers, memory, stacks Trace instruction execution Perform linear statistical profiling program execution Fill, dump, graphically plot contents memory
White Mountain (Product Line Analog Devices, Inc.) family emulators tools that every developer needs test debug hardware software systems. Analog Devices supplied IEEE 1149.1 JTAG Test Access Port (TAP) each JTAG DSP. emulator uses access internal features DSP, allowing developer load code, breakpoints, observe variables, observe memory, examine registers. must halted send data commands, once operation been completed emulator, system running full speed with impact system timing. these emulators, target's design must include interface between Analog Devices' JTAG emulation header custom target board.
Target Board Header
emulator interface Analog Devices' JTAG 14pin header, shown Figure customer must supply this header target board order communicate with emulator. interface consists standard dual 0.025" square post header, 0.1" 0.1" spacing, with minimum post length 0.235". position used prevent from being inserted backwards. This must clipped target board.
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Also, clearance (length, width, height) around header must considered. Leave clearance least 0.15" 0.10" around length width header, reserve height clearance attach detach connector.
When emulator connected this header, place jumpers across BTMS, BTCK, BTRST, BTDI shown Figure This holds JTAG signals correct state allow free. Remove jumpers when connecting emulator JTAG header.
PIN) BTMS BTCK BTRST BTDI
TRST
PIN) BTMS BTCK BTRST BTDI
TRST
VIEW
VIEW
Figure JTAG Target Board Connector JTAG Equipped Analog Devices (Jumpers Place)
Figure JTAG Target Board Connector with Local Boundary Scan JTAG Emulator Connector
seen Figure there sets signals header. There standard JTAG signals TMS, TCK, TDI, TDO, TRST, used emulation purposes (via emulator). There also secondary JTAG signals BTMS, BTCK, BTDI, BTRST that optionally used boardlevel (boundary scan) testing.
Figure details dimensions JTAG connector 14-pin target end. Figure displays keep-out area target board header. keep-out area allows connector properly seat onto target board header. This board area should contain components (chips, resistors, capacitors, etc.). dimensions referenced center 0.25" square post pin.
0.64"
0.88"
0.24"
Figure JTAG Connector Dimensions
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0.10"
set, TigerSHARC Hardware Specification TigerSHARC Instruction Specification. detailed information development tools this processor, VisualDSP++ User's Guide Reference ADSP-TS101S TigerSHARC DSP.
FUNCTION DESCRIPTIONS
0.15"
Figure JTAG Connector Keep-Out Area Design-for-Emulation Circuit Information
details target board design issues including: single processor connections, multiprocessor scan chains, signal buffering, signal termination, emulator logic, EE-68: Analog Devices JTAG Emulation Technical Reference Analog Devices website-use site search "EE-68" (www.analog.com). This document updated regularly keep pace with improvements emulator support.
Additional Information
While most ADSP-TS101S's input pins normally synchronous-tied specific clock-a asynchronous. these asynchronous signals, on-chip synchronization circuit prevents metastability problems. specification asynchronous signals used only when having predictable cycle-bycycle behavior required. output pins three-stated during normal operation. three-states outputs during reset, allowing these pins their internal pullup pulldown state. Some output pins (control signals) have pullup pulldown that maintain known value during transitions between different drivers.
This data sheet provides general overview ADSPTS101S's architecture functionality. detailed information ADSP-TS101S's core architecture instruction
Table Definitions-Clocks Reset Signal Type Description
LCLK_N LCLK_P
Local Clock Reference. Connect this VREF shown Figure Local Clock Input. clock input. instruction cycle rate LCLK, where user-programmable 2.5, 3.5, more information, Clock Domains page LCLK Ratio. DSP's core clock (instruction cycle rate) LCLK, where user-programmable 2.5, 3.5, shown Table These pins must have constant value while powered. System Clock Reference. Connect this VREF shown Figure System Clock Input. DSP's system input clock cluster bus. This must connected same clock source LCLK_P. more information, Clock Domains page SCLK Frequency. Indicates SCLK frequency range SCLK deskew PLL. When SCLKFREQ SCLK MHz. When SCLKFREQ SCLK (default). This must have constant value while powered. Reset. Sets known state causes program idle state. RESET must asserted specified time according type reset operation. details, Reset Booting page
LCLKRAT2-01
(pd)
SCLK_N SCLK_P
SCLKFREQ2
(pu)
RESET
asynchronous; ground; input; output; open drain output; power supply; internal pulldown internal pullup Three-State
internal internal pulldown sufficient depending system noise and/or leakage. stronger pulldown necessary. internal internal pullup sufficient depending system noise and/or leakage. stronger pullup necessary.
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Table LCLK Ratio LCLKRAT2-0 Ratio
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ADSP-TS101S
(default)
Reserved
Table Definitions-External Port Signal Type Description
ADDR31-01
I/O/T
Address Bus. issues addresses accessing memory peripherals these pins. multiprocessor system, master drives addresses accessing internal memory processor registers other ADSP-TS101Ss. inputs addresses when host another accesses internal memory processor registers. External Data Bus. drives receives data instructions these pins. Pull-up resistors unused DATA pins unnecessary.
DATA63-01
I/O/T
I/O/T (pu) Memory Read. asserted whenever reads from slave system, excluding SDRAM. When slave, input indicates read transactions that access internal memory universal registers. multiprocessor system, master drives changes concurrently with ADDR pins. I/O/T (pu) Write Low. asserted cases: When ADSP-TS101S writes even address word external memory another external agent; when ADSP-TS101S writes 32-bit zone (host, memory programmed 32-bit bus). external master (host DSP) asserts writing DSP's word internal memory. multiprocessor system, master drives WRL. changes concurrently with ADDR pins. When slave, input indicates write transactions that access internal memory universal registers. I/O/T (pu) Write High. asserted when ADSP-TS101S writes long word bits) writes address word external memory another external agent 64-bit data bus. external master (host another DSP) must assert writing DSP's high word 64-bit data bus. multiprocessing system, master drives WRH. changes concurrently with ADDR pins. When slave, input indicates write transactions that access internal memory universal registers. I/O/T Acknowledge. External slave devices de-assert wait states external memory accesses. used devices, memory controllers other peripherals data phase. de-assert wait states read accesses internal memory. ADSP-TS101S does drive during slave writes. Therefore, external (approximately pullup required.
WRL2
WRH2
asynchronous; ground; input; output; open drain output; power supply; internal pulldown internal pullup Three-State
REV.
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Table Definitions-External Port (continued) Description
BMS2,3
(pu/pd)
Boot Memory Select. chip select boot EPROM flash memory. During reset, uses strap (EBOOT) EPROM boot mode. When configured boot from EPROM, active during boot sequence. Pulldown enabled during RESET (asserted); pullup enabled after RESET (deasserted). multiprocessor system, master drives BMS.For details Reset Booting page EBOOT signal description Table page Memory Select. asserted whenever accesses memory banks respectively. MS1-0 decoded memory address pins that change concurrently with ADDR pins. When ADDR31:26 0b000010, asserted. When ADDR31:26 0b000011, asserted. multiprocessor systems, master drives MS1-0. Memory Select Host. asserted whenever accesses host address space (ADDR31:28 0b0000). decoded memory address that changes concurrently with ADDR pins. multiprocessor system, master drives MSH. Multiprocessing Request Pins. Used DSPs multiprocessor system arbitrate mastership. Each drives line (corresponding value ID2-0 inputs) monitors others. systems with fewer than eight DSPs, unused pins high. Multiprocessor Indicates DSP's from which determines order multiprocessor system. These pins also indicate which request (BR0-BR7) assert when requesting bus: BR0, BR1, BR2, BR3, BR4, BR5, BR6, BR7. ID2-0 must have constant value during system operation change during reset only. Master. current master asserts debugging only. reset this strap pin. more information, Table page Back Off. deadlock situation occur when host read from each other's same time. When deadlock occurs, host assert BOFF force relinquish before completing outstanding transaction. Lock Indication. Provides indication that current master locked bus.
MS1-02
(pu)
MSH2
(pu)
BR7-0
ID2-03
(pd)
BOFF
(pd)
BUSLOCK2 BRST2
(pu)
I/O/T (pu) Burst. current master (DSP host) asserts this indicate that reading writing data associated with consecutive addresses. slave device ignore addresses after first increment internal address counter after each transfer. host-to-DSP burst accesses, increments address automatically while BRST asserted. Host Request. host must assert request control DSP's external bus. When asserted multiprocessing system, master relinquishes asserts once outstanding transaction finished.
HBG2
I/O/T (pu) Host Grant. Acknowledges indicates that host take control external bus. When relinquishing bus, master three-states ADDR31-0, DATA63-0, MSH, MSSD, MS1-0, WRL, WRH, BMS, BRST, FLYBY, IOEN, RAS, CAS, SDWE, SDA10, SDCKE, LDQM HDQM pins, puts SDRAM self-refresh mode. asserts until host deasserts HBR. multiprocessor systems, current master drives HBG, slave DSPs monitor
asynchronous; ground; input; output; open drain output; power supply; internal pulldown internal pullup Three-State
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Table Definitions-External Port (continued) Description
(o/d)
Core Priority Access. Asserted while DSP's core accesses external memory. This enables slave interrupt master DSP's background transfers gain control external core-initiated transactions. open drain output, connected DSPs system. internal pullup resistor, which only enabled with ID=0. required system, leave unconnected (external pullups will required ID1-ID7). Priority Access. Asserted while high-priority channel accesses external memory. This enables high-priority channel slave interrupt transfers normal-priority channel master gain control external DMA-initiated transactions. open drain output, connected DSPs system. internal pullup resistor, which only enabled with ID=0. required system, leave unconnected (external pullups will required ID1-ID7). Request Pins. Enable external devices request services from DSP. response DMARx, performs transfers according channel's initialization. ignores requests from uninitialized channels. Flyby Mode. When channel initiated FLYBY mode, generates flyby transactions external bus. During flyby transactions, asserts FLYBY, which signals source destination device latch next data strobe current data, respectively, prepare next data next cycle. Device Output Enable. Enables output buffers external device fly-by transactions between device external memory. Active fly-by transactions.
(o/d)
DMAR3-0
FLYBY2
(pu)
IOEN2
(pu)
asynchronous; ground; input; output; open drain output; power supply; internal pulldown internal pullup Three-State
address data buses float several cycles during mastership transitions between TigerSHARC host. Floating this case means that these inputs driven source that DC-biased terminations present. necessary pullups there reliability issues worst-case power consumption these floating inputs negligible. Unconnected address pins require pullups pulldowns avoid erroneous slave accesses, depending system. Unconnected data pins left floating. internal internal pullup sufficient depending system noise and/or leakage. stronger pullup necessary. internal internal pulldown sufficient depending system noise and/or leakage. stronger pulldown necessary.
Table Definitions-SDRAM Controller Signal Type Description
MSSD1
I/O/T (pu) Memory Select SDRAM. MSSD asserted whenever accesses SDRAM memory space. MSSD decoded memory address that asserted whenever issues SDRAM command cycle (access ADDR31:26 0b000001). multiprocessor system, master drives MSSD. I/O/T (pu) Address Select. When sampled low, indicates that address valid read write SDRAM. other SDRAM accesses, defines type operation execute according SDRAM specification. I/O/T (pu) Column Address Select. When sampled low, indicates that column address valid read write SDRAM. other SDRAM accesses, defines type operation execute according SDRAM specification.
RAS1
CAS1
asynchronous; ground; input; output; open drain output; power supply; internal pulldown internal pullup Three-State
REV.
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Signal Type
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Table Definitions-SDRAM Controller (continued) Description
LDQM1
(pu)
Word SDRAM Data Mask. When sampled high, three-states SDRAM buffers. LDQM valid SDRAM transactions when asserted, inactive read transactions. write transactions, LDQM active when accessing address word 64-bit memory disable write word. High Word SDRAM Data Mask. When sampled high, three-states SDRAM buffers. HDQM valid SDRAM transactions when asserted, inactive read transactions. write transactions, HDQM active when accessing even address word accesses when memory configured 32-bit disable write high word. SDRAM Address pin. Separate signals enable SDRAM refresh operation while executes non-SDRAM transactions. SDRAM Clock Enable. Activates SDRAM clock SDRAM self-refresh suspend modes. slave multiprocessor system does have pullup pulldown. master ID=0 single processor system) pullup before granting host, except when SDRAM self refresh mode. self refresh mode, master pulldown before granting host.
HDQM1
(pu)
SDA101 SDCKE1,2
(pu) I/O/T (pu/pd)
SDWE1
I/O/T (pu) SDRAM Write Enable. When sampled while active, SDWE indicates SDRAM write access. When sampled high while active, SDWE indicates SDRAM read access. other SDRAM accesses, SDWE defines type operation execute according SDRAM specification.
asynchronous; ground; input; output; open drain output; power supply; internal pulldown internal pullup Three-State
internal internal pullup sufficient depending system noise and/or leakage. stronger pullup necessary. internal internal pulldown sufficient depending system noise and/or leakage. stronger pulldown necessary.
Table Definitions-JTAG Port Signal Type Description
(o/d) (pu) (pu) (pu)
Emulation. Connected DSP's JTAG emulator target board connector only. Test Clock (JTAG). Provides asynchronous clock JTAG scan. Test Data Input (JTAG). serial data input scan path. Test Data Output (JTAG). serial data output scan path. Test Mode Select (JTAG). Used control test state machine. Test Reset (JTAG). Resets test state machine. TRST must asserted pulsed after power proper device operation. more information, Reset Booting page
TRST1
asynchronous; ground; input; output; open drain output; power supply; internal pulldown internal pullup Three-State
internal internal pullup sufficient depending system noise and/or leakage. stronger pullup necessary.
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Table Definitions-Flags, Interrupts, Timer Description
FLAG3-0
I/O/A (pd) (pu)
IRQ3-02
TMR0E1
(pd)
FLAG pins. Bidirectional input/output pins used program conditions. Each configured individually input output. FLAG3-0 inputs after power-up reset. Interrupt Request. When asserted, generates interrupt. Each IRQ3-0 pins independently edge-triggered level-sensitive operation. After reset, these pins disabled unless IRQ3-0 strap option interrupt vectors initialized booting. Timer expires. This output pulses four SCLK cycles whenever timer expires. reset this strap pin. more information, Table page
asynchronous; ground; input; output; open drain output; power supply; internal pulldown internal pullup Three-State
internal internal pulldown sufficient depending system noise and/or leakage. stronger pulldown necessary. internal internal pullup sufficient depending system noise and/or leakage. stronger pullup necessary.
Table Definitions-Link Ports Signal Type Description
L0DAT7-01 L1DAT7-01 L2DAT7-0 L3DAT7-0
(pd) (pd)
Link0 Data Link1 Data Link2 Data Link3 Data Link0 Clock/Acknowledge Output Link1 Clock/Acknowledge Output Link2 Clock/Acknowledge Output Link3 Clock/Acknowledge Output Link0 Clock/Acknowledge Input Link1 Clock/Acknowledge Input Link2 Clock/Acknowledge Input Link3 Clock/Acknowledge Input Link0 Direction. input, output) Link1 Direction. input, output) Link2 Direction. input, output) reset this strap pin. more information, Table page Link3 Direction. input, output)
L0CLKOUT L1CLKOUT L2CLKOUT L3CLKOUT L0CLKIN L1CLKIN L2CLKIN L3CLKIN L0DIR L1DIR L2DIR
L3DIR
asynchronous; ground; input; output; open drain output; power supply; internal pulldown internal pullup Three-State
link port data pins, connected floated extended periods (i.e., token slave with token master), require pullups pulldowns there reliability issues worst-case power consumption these floating inputs negligible. Floating this case means that these inputs driven source that DC-biased terminations present. internal internal pulldown sufficient depending system noise and/or leakage. stronger pulldown necessary.
REV.
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Table definitions-Impedance Drive Strength Control Description
CONTROLIMP2-11 CONTROLIMP02
(pu) (pd)
Impedance Control. Every group outputs controls: dig_ctrl Disabled (maximum drive strength) Enabled (use drive strength selection) pulse Disabled (constant drive strength selected pins) Enabled pulse drive beginning transition; constant drive otherwise selected pins) (Address/Data/Controls) LINK (all link port outputs) signals, CONTROLIMP2-0 pins control impedance shown Table Digital Drive Strength Selection. Selected shown Table drive strength calculation, Output Drive Currents page
DS2-01
(pu)
asynchronous; ground; input; output; open drain output; power supply; internal pulldown internal pullup Three-State
internal internal pullup sufficient depending system noise and/or leakage. stronger pullup necessary. internal internal pulldown sufficient depending system noise and/or leakage. stronger pulldown necessary.
Table Control Impedance Selection CONTROLIMP2-0 dig_ctrl LINK pulse dig_ctrl pulse
(default)
Table Drive Strength Selection DS2-0 Drive Strength
(default)
100%
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Table Definitions-Power, Ground, Reference Description
VDD_A VDD_IO VREF
pins internal logic. pins analog circuits. critical attention bypassing this supply. pins buffers. Reference voltage defines trip point input buffers, except RESET, IRQ3-0, DMAR3-0, ID2-0, CONTROLIMP2-0, TCK, TDI, TMS, TRST. value (which trip point). VREF connected power supply voltage divider circuit. voltage divider should have decoupling capacitor SMD) connected VSS. decoupling capacitor between VREF input VSS, close DSP's pins possible. more information, Filtering Reference Voltage Clocks page Ground pins. Ground pins analog circuits.
VSS_A
asynchronous; ground; input; output; open drain output; power supply; internal pulldown internal pullup Three-State
STRAP FUNCTION DESCRIPTIONS
Some pins have alternate functions reset. Strap options operating modes. During reset, samples strap option pins. Strap pins have pull-down default value. strap connected external pull-up logic load, samples default value during reset. strap
Table Definitions-I/O Strap Pins Signal Pin. Description
pins connected logic inputs, stronger external pulldown required ensure default value depending leakage and/or level input current logic load. mode other than default mode, connect strap sufficiently stronger external pull-up. Table lists describes each DSP's strap pins.
EBOOT
EPROM boot. boot from EPROM immediately after reset (default) idle after reset wait external device boot through external port link port Interrupt Enable. disable IRQ3-0 interrupts level-sensitive after reset (default) enable IRQ3-0 interrupts edge-sensitive immediately after reset Test Mode required setting during reset. reserved. Test Mode required setting during reset. reserved.
IRQEN
L2DIR
TMR0E
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February 2002
Note that component specifications subject change without notice.
RECOMMENDED OPERATING CONDITIONS
Parameter Test Conditions Unit
VDD_A VDD_IO TCASE VREF
Internal Supply Voltage Analog Supply Voltage Supply Voltage Case Operating Temperature High-Level Input Voltage
1.14 1.14 3.15 VDD, VDD_IO VDD, VDD_IO -0.5
1.26 1.26 3.45 VDD_IO
Low-Level Input Voltage1 Voltage reference
Applies input bidirectional pins.
ELECTRICAL CHARACTERISTICS
Parameter Test Conditions Unit
IIHP IILP IOZH IOZHP IOZL IOZLP IOZLO
High-Level Output Voltage1 Low-Level Output Voltage1 High-Level Input Current
@VDD_IO min, @VDD_IO min, @VDD_IO max, VDD_IO @VDD_IO max, VDD_IO @VDD_IO max,
6,10
High-Level Input Current (pd) Low-Level Input Current4 Low-Level Input Current (pu)
@VDD_IO max, @VDD_IO max, VDD_IO
Three-State Leakage Current High
Three-State Leakage Current High (pd)7 @VDD_IO max, VDD_IO Three-State Leakage Current
@VDD_IO max, @VDD_IO max,
Three-State Leakage Current (pu)
Three-State Leakage Current (od)10 @VDD_IO max, Input Capacitance
11,12
@fIN 1MHz,TCASE 25C, 2.5V
Applies output bidirectional pins. Applies input pins without internal pulldowns (pd). Applies input pins with internal pulldowns (pd). Applies input pins without internal pullups (pu). Applies input pins with internal pullups (pu). Applies three-stateable pins without internal pulldowns (pd). Applies three-stateable pins with internal pulldowns (pd). Applies three-stateable pins without internal pullups (pu). Applies three-stateable pins with internal pullups (pu). Applies open drain (od) pins with pullups (pu). Applies signals. Guaranteed tested.
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ADSP-TS101S
ABSOLUTE MAXIMUM RATINGS
Internal (Core) Supply Voltage (VDD)1 -0.3 +1.40 Analog (PLL) Supply Voltage (VDD_A)1 -0.3 +1.40 External (I/O) Supply Voltage (VDD_IO)1 -0.3 +4.6 Input Voltage1 -0.5 VDD_IO +0.5 Output Voltage Swing1 -0.5 VDD_IO +0.5 Storage Temperature Range1
Stresses greater than those listed above cause permanent damage device. These stress ratings only. Functional operation device these other conditions greater than those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
SENSITIVITY
CAUTION (electrostatic discharge) sensitive device. Electrostatic charges high 4000V readily accumulate human body test equipment discharge without detection. Although ADSP-TS101S features proprietary protection circuitry, permanent damage occur devices subjected high-energy electrostatic discharges. Therefore, proper precautions recommended avoid performance degradation loss functionality.
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With exception Link port, DMAR3-0, IRQ3-0 pins, timing ADSP-TS101S relative reference clock edge. Because input setup/hold, output valid/hold, output enable/disable times relative clock edge, timing data ADSP-TS101S calculated (formula-based) values.For information timing, General Timing page information Link port transfer timing, Link Port Data Transfer Token Switch Timing page
described Figure page delays nanoseconds) measured between point that first signal reaches point that second signal reaches general timing data appears Table Table asynchronous timing data IRQ3-0 DMAR3-0 pins appears Table
Table Asynchronous Signal Specifications (all values this table nanoseconds) Name Description Pulsewidth (min) Pulsewidth High (min)
IRQ3-01 DMAR3-01
Interrupt Request Request
tCCLK tCCLK
tCCLK tCCLK
These input pins have Schmitt triggers therefore need synchronized clock reference.
Table Reference Clocks Speed Grade (MHz) Clock Cycle (ns) Clock Cycle (ns) Clock Clock Skew High LCLK (ns) (ns) (ps)
Signal
Type
Description
CCLK1 LCLK_P2,3 SCLK_P3,4
Core Clock Local Clock System Clock, SCLKFREQ System Clock, SCLKFREQ Test Clock (JTAG)
Greater Greater Greater
12.5
{40% Duty Cycle} {40% Duty Cycle}
CCLK internal clock instruction cycle time. period this clock equal Local Clock (LCLK_P) period divided Local Clock Ratio (LCLKRAT2-0). information available internal clock rates, Ordering Guide page Core clock Ratio (CR) 2.5, 3.5, LCLKRAT2-0 pins. more information, Table page more information, Clock Domains page more information, Table page
Table Signal Specifications (all values this table nanoseconds) Output Disable (max)1 Output Enable (max)1
Output Valid (max)
Output Hold (min)
Input Setup (min)
Input Hold (min)
Name
Description
ADDR31-0 DATA63-0 MSSD
External Address External Data Memory Select HOST Line Memory Select SDRAM Line
SCLK SCLK SCLK SCLK REV.
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Reference Clock
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Output Disable (max)1 Output Enable (max)1
Table Signal Specifications (all values this table nanoseconds) (continued)
Output Valid (max)
Output Hold (min)
Input Setup (min)
Input Hold (min)
Name
Description
MS1-0 SDCKE SDWE LDQM HDQM SDA10 BOFF BUSLOCK BRST BR7-0 FLYBY IOEN
Memory Select Static Blocks Memory Read Write Word Write High Word Acknowledge Data SDRAM Clock Enable Address Select Column Address Select SDRAM Write Enable Word SDRAM Data Mask High Word SDRAM Data Mask SDRAM ADDR10 Host Request Host Grant Back Request Lock Burst FLYBY FLYBY Core Priority Access Priority Access Boot Memory Select FLAG pins Timer Expired Global Reset Test Mode Select (JTAG) Test Data Input (JTAG) Test Data Output (JTAG)
SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK SCLK LCLK
Multiprocessing Request pins
FLAG3-04 TMR0E3 RESET TDI5 TRST
5,6,8
Test Reset (JTAG) Master Debug only Emulation Chip must constant
EMU7 ID2-08 CONTROLIMP2-0 REV.
Static pins must constant
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Reference Clock
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Output Disable (max)1 Output Enable (max)1
Table Signal Specifications (all values this table nanoseconds) (continued)
Output Valid (max)
Output Hold (min)
Input Setup (min)
Input Hold (min)
Name
Description
DS2-0
Static pins must constant Static pins must constant Static pins must constant
LCLKRAT2-0 SCLKFREQ8
external port protocols employ IDLE cycles mastership transitions well slave address boundary crossings avoid potential contention. apparent driver overlap, output disables being larger than output enables, actual. pins open drains have internal pullups. This strap option. During reset, internal resistor pulls low. These pins have asynchronous minimum pulse width tSCLK These input pins have Schmitt triggers therefore need synchronized clock reference. These synchronous specifications only apply recognition current clock reference cycle. additional requirement details, Reset Booting page Reference clock depends function. These pins change only during reset; recommend connecting VDD/VSS.
REFERENCE CLOCK 1.5V
INPUT SIGNAL 1.5V INPUT SETUP INPUT HOLD
OUTPUT SIGNAL OUTPUT VALID 1.5V OUTPUT HOLD
THREESTATE OUTPUT DISABLE OUTPUT ENABLE
Figure General parameters timing
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Reference Clock
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Link Port Data Transfer Token Switch Timing
Table Table Table Table with Figure Figure Figure Figure provide timing specifications link ports data transfer token switch.
Table Link Ports-Transmit Parameter Unit
Timing Requirements: tCONNS Connectivity Pulse Setup tCONNIW Connectivity Pulse Input Width tACKS Acknowledge Setup Switching Characteristics: tLXCLK_TX1 Transmit Link Clock Period tLXCLKH_TX Transmit Link Clock Width High tLXCLKL_TX Transmit Link Clock Width tDIRS LxDIR Transmit Setup tDIRH LxDIR Transmit Hold tDOS2 LxDAT7-0 Output Setup tDOH2 LxDAT7-0 Output Hold tDOS3 LxDAT7-0 Output Setup tDOH3 LxDAT7-0 Output Hold tLDOE LxDAT7-0 Output Enable tLDOD4 LxDAT7-0 Output Disable
0.25 tLXCLK_TX tLXCLK_TX tLXCLK_TX CCLK tLXCLK_TX tLXCLK_TX tLXCLK_TX tLXCLK_TX 0.25 tLXCLK_TX 0.25 tLXCLK_TX 0.17 tLXCLK_TX 0.17 tLXCLK_TX CCLK CCLK CCLK tLXCLK_TX tLXCLK_TX tLXCLK_TX tLXCLK_TX
Link clock Ratio (LR) bits LxCTL register. formula this parameter applies when formula this parameter applies when This specification applies last data byte "Dummy" byte that follows verification byte enabled. more information, TigerSHARC Hardware Specification.
tCONN tDIRS tLxCLK H_Tx
LxCLKOUT
tLxCLK_Tx tLxCLKL_Tx tDOS
tACKS tDOH tDOS
tDIRH
tCONNIW
LxCLKIN
tLDO
tLDOD
LxDAT7-0
LxDIR
Note: LxCLKIN shows connectivity pulse with each three possible transitions "Acknowledge". After connectivity pulse minimum, LxCLKIN return high remain high "Acknowledge", return high subsequently (meeting tACKS) "Not Acknowledge", remain "Not Acknowledge".
Figure Link Ports-Transmit
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Table Link Ports-Receive Parameter Unit
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Timing Requirements: tLXCLK_RX1 Receive Link Clock Period Receive Link Clock Width High tLXCLKH_RX Receive Link Clock Width tLXCLKL_RX tDIS LxDAT7-0 Input Setup tDIH LxDAT7-0 Input Hold Switching Characteristics: tCONNV Connectivity Pulse Valid tCONNOW Connectivity Pulse Output Width
CCLK tLXCLK_RX tLXCLK_RX tLXCLK_RX
CCLK tLXCLK_RX tLXCLK_RX
tLXCLK_RX
Link clock Ratio (LR) bits LxCTL register.
tLxCLK_Rx tCONNV
LxCLKIN
tLxCLKH_Rx tLxCLKL_Rx
tDIH tDIS
tDIH tDIS
tCONNOW
LxCLKOUT
LxDAT7-0
LxDIR
Figure Link Ports-Receive
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Unit
Table Link Ports-Token Switch, Token Master
Timing Requirements: tREQI Token Request Input Width tLXCLK_RX tTKRQ Token Request from Token Enable (for guaranteeing token switch during Token Enable) Switching Characteristics: tTKENO Token Switch Enable Output tLXCLK_TX tREQO Token Request Output Width tLXCLK_TX
tTKENO
LxCLKOUT
tLXCLK_TX
tREQO
tTKRQ
tREQI
LxCLKIN
Note: LxCLKOUT shows both possible responses token request: "Token Grant" (LxCLKOUT remains high), "Token Regret" (LxCLKOUT goes low).
Figure Link Ports-Token Switch, Token Master
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Parameter
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February 2002
Unit
Table Link Ports-Token Switch, Token Requester
Timing Requirements: tTKENI1 Token Switch Enable Input Switching Characteristics: tREQO Token Request Output Width
tLXCLK_RX tLXCLK_RX
Required whenever there break transmission.
tTKENI
LxCLKIN token regret
tREQO
tTKRQ tREQO
LxCLKOUT token regret
tTKENI
LxCLKIN token grant
tTKRQ tREQO
LxCLKOUT token grant
Note: LxCLKOUT shows both possible responses token request: "Token Grant" (LxCLKOUT remains high), "Token Regret" (LxCLKOUT goes low).
Figure Link Ports-Token Switch, Token Requester
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Output Drive Currents
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Unit
Table Power Vectors Parameter Test Conditions
Figure place holder typical characteristics output drivers ADSP-TS101S. curves this diagram will represent current drive capability output drivers function output voltage.
IDDINPEAK IDDINMAX IDDINTYP IDDINCTRL IDDINDMA IDDINIDLE IDDINIDLELP
following power vector definitions apply power consumption calculation power vector specifications Table IDDINPEAK-VDD supply current peak activity Peak activity SIMD quad 16-bit fixed-point multiply, add, subtract parallel with quad-word data fetches. data fetched operated worst case terms power consumption. This vector includes activity described below IDDINDMA definition. This represents worst-case processor operation sustainable under normal application conditions. IDDINMAX-VDD supply current maximum activity Maximum activity SIMD quad 16-bit fixed-point multiply parallel with quad-word data fetches. data fetched operated random. This vector includes activity described below IDDINDMA definition. IDDINTYP-VDD supply current typical activity Typical activity SIMD quad 16-bit fixed-point compute operation parallel with quad-word data fetches. data fetched operated random. This vector includes activity described below IDDINDMA definition. IDDINCTRL-VDD supply current control activity Control activity continuous decision making predicted branches. branch prediction deliberately incorrect time equal distribution. This vector includes activity described below IDDINDMA definition. IDDINDMA-VDD supply current activity activity single external port from external internal memory, quad-word transfers words total. chained itself does interrupts. After setup, core involved, executing IDLE instruction only.
Figure ADSP-TS101S Typical Drive Currents Power Dissipation
Total power dissipation components, internal circuitry switching external output drivers. These specifications apply internal power portion only (VDD).
Internal Power Calculation
Internal power dissipation dependent instruction execution sequence data operands involved. ADSPTS101S's power consumption specific application calculated according following formula, where amount time application spends that state:
Peak DDINPEAK Maximum IDDINMAX Typical DDINTYP Control DDINCTRL IDDINDMA Idle DDINIDLE Idle Power DDINIDLELP -Total Current DDIN
calculation Figure provides PINT.
DDIN Figure Internal Power PINT Calculation
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IDDINIDLE-VDD supply current idle activity Idle activity core executing IDLE instruction only with interrupts. IDDINIDLELP-VDD supply current idle power activity Idle Power activity core executing IDLE(LP) instruction only with interrupts.
External Power Calculation
load capacitance should include input capacitance each connected device well DPS's input capacitance (CIN) additional accuracy trace capacitance should included possible. switching frequency includes driving load high then back low. Address data pins drive high maximum rate SCLK. example, estimate PEXT external port pins with following assumptions: System consists ADSP-TS101S with bank external memory (64-bit). SDRAM chips used, each with load (trace capacitance neglected this example). Continuous burst quad-word (128-bit) writes occur every cycle rate SCLK, with data pins switching (represents random data). Address increments sequentially transaction boundary (every quad-word). sequential addressing, number address bits switching approaches 2-bits. Control switches refresh page boundaries. SCLK 100Mhz (bus cycle time). PEXT equation calculated each class pins that drive shown Table
external power VDD_IO consumed switching output pins system dependent. each unique group pins, magnitude power consumed depends number output pins that switch during each cycle, Their load capacitance, Their voltage swing, VDD_IO maximum frequency which they switch, calculated formula Figure
VDD_IO Figure External Power PEXT Calculation Table External Power PEXT Calculation Type Pins Switching
VDD_IO2
PEXT
Data Address Control
6.25
CIN) CIN) CIN)
10.9 10.9 10.9
PEXT =TBD
Test Conditions
test conditions timing parameters appearing ADSPTS101S-Specifications page include output disable time, output enable time, capacitive loading. timing specifications apply voltage reference levels Figure
REFERENCE SIGNAL
tMEASURED_DIS tDIS
(MEASURED) (MEASURED)
tMEASURED_ENA tENA
2.0V 1.0V
INPUT OUTPUT
(MEASU RED)
1.5V 1.5V
(MEASURED)
tDECAY
OUTPUT STOPS DRIVING
tRAMP
OUTPUT STARTS DRIVING
Figure Voltage reference levels measurements (except output enable/disable)
HIGH-IMPEDANCE STATE. TEST CONDITIONS CAUSE THIS VOLTAGE APPROXIMATELY 1.5V
Figure Output Enable/Disable
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Output Disable Time
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ADSP-TS101S
Output pins considered disabled when they stop driving, into high impedance state, start decay from their output high voltage. time voltage decay dependent capacitive load, load current, This decay time approximated following equation: tDECAY (CLV)/IL output disable time tDIS difference between tMEASURED_DIS tDECAY shown Figure time tMEASURED_DIS interval from when reference signal switches when output voltage decays from measured output high output voltage. tDECAY calculated with test loads with equal
Output Enable Time
Output pins considered enabled when they have made transition from high impedance state when they start driving. time voltage ramp dependent capacitive load, drive current, This ramp time approximated following equation: tRAMP (CLV)/ID output enable time tENA difference between tMEASURED_ENA tRAMP shown Figure time tMEASURED_ENA interval from when reference signal switches when output voltage ramps from measured three-stated output level. tRAMP calculated with test load drive current with equal
Capacitive Loading
Figure Typical Output Rise Time (10%-90%, VDD_IO Max) Load Capacitance Default Drive Strength Default Impedance Control)
Output valid holds based standard capacitive loads: pins (see Figure 20). delay hold specifications given should derated factor ns/TBD loads other than nominal value Figure Figure show output rise time varies with capacitance. Figure graphically shows output valid holds vary with load capacitance. (Note that this graph derating does apply output disable delays; Output Disable Time page 31.) graphs Figure Figure Figure linear outside ranges shown.
Figure Typical Output Rise Time (10%-90%, VDD_IO Min) Load Capacitance Default Drive Strength Default Impedance Control)
REV.
Figure Equivalent Device Loading Measurements (Includes Fixtures)
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Figure Typical Output Delay Hold Load Capacitance Case Temperature Default Drive Strength Default Impedance Control) Environmental Conditions
ADSP-TS101S rated performance over extended commercial temperature range, TCASE -40°C 85°C.
Thermal Characteristics
ADSP-TS101S packaged Plastic Ball Grid Array (PBGA). ADSPTS101S specified case temperature (TCASE). ensure that TCASE data sheet specification exceeded, heatsink and/or flow source used. TCASE TAMB TCASE Case temperature (measured surface package). Power dissipation PINT PEXT This value depends specific application; methods calculating PINT PEXT shown under Power Dissipation page 29). Value from Table Table
Table Values1
Airflow (Linear Ft./Min.) (oC/W)
10.0
Where: 6.7°C/W 5.8°C/W.
Table Values1
Airflow (Linear Ft./Min.) (oC/W)
10.8
Where: 3.2°C/W 5.9°C/W.
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ADSP-TS101S
484-BALL PBGA CONFIGURATIONS Table 484-Ball PBGA Assignments Pin# Signal Name Pin# Signal Name Pin# Signal Name Pin# Signal Name Pin# Signal Name
DATA14 DATA11 DATA8 DATA4 DATA1 L0DIR L0CLKIN L0DAT6 L0DAT3 L0DAT1 LCLK_N VSS_A SCLK_N SCLK_P CONTROLIMP2 CONTROLIMP1 RESET DMAR1 DATA29 DATA30 DATA26 VDD_IO VDD_IO VDD_IO VDD_IO LCLKRAT0 SCLKFREQ TMR0E
DATA21 DATA18 DATA12 DATA13 DATA7 DATA5 DATA2 L0DAT7 L0DAT4 L0DAT0 VDD_A VSS_A CONTROLIMP0 DMAR2 DMAR0 IRQ1 L3DAT1 DATA28 DATA27 VDD_IO FLAG3 BUSLOCK FLAG0
DATA23 DATA17 DATA15 DATA9 DATA10 DATA6 DATA3 DATA0 L0CLKOUT L0DAT5 L0DAT2 LCLK_P VDD_A VREF TRST DMAR3 IRQ3 IRQ0 L3DAT2 L3DAT0 DATA31 VDD_IO VDD_IO FLAG1 FLAG2
DATA24 DATA19 DATA16 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO IRQ2 LCLKRAT1 L3DAT5 L3DAT3 L3DAT4 VDD_IO VDD_IO VDD_IO
DATA25 DATA22 DATA20 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO LCLKRAT2 L3CLKOUT L3DAT7 L3DAT6 VDD_IO VDD_IO VDD_IO IOEN FLYBY
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Pin# Signal Name
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L1DAT6 DATA32 DATA33 VDD_IO VDD_IO ADDR28 ADDR29 DATA42 DATA45 L2DAT5 DATA48 DATA52 DATA58 DATA60 DATA63 L2DAT4 L2CLKOUT ADDR0 ADDR1 ADDR11 ADDR21 ADDR18 ADDR16
Table 484-Ball PBGA Assignments (continued) Pin# Signal Name Pin# Signal Name Pin# Signal Name Pin# Signal Name
L3CLKIN L3DIR VDD_IO VDD_IO VDD_IO BRST L1DIR DATA36 DATA37 VDD_IO VDD_IO ADDR23 ADDR25 ADDR27
L1DAT0 L1DAT2 L1DAT1 VDD_IO VDD_IO HDQM DATA38 DATA39 VDD_IO VDD_IO ADDR30 ADDR22 ADDR26
L1DAT3 L1DAT5 L1DAT7 VDD_IO VDD_IO VDD_IO SDWE MSSD LDQM DATA34 DATA41 DATA35 VDD_IO VDD_IO VDD_IO VDD_IO ADDR14 ADDR19 ADDR24
L1DAT4 L1CLKOUT L1CLKIN VDD_IO VDD_IO VDD_IO ADDR31 SDCKE DATA40 DATA43 DATA46 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO ADDR12 ADDR17 ADDR20
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Pin# Signal Name
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ADSP-TS101S
Table 484-Ball PBGA Assignments (continued) Pin# Signal Name Pin# Signal Name Pin# Signal Name Pin# Signal Name
AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22
DATA44 DATA50 DATA47 DATA49 DATA51 DATA54 DATA57 DATA61 L2DAT0 L2DAT3 L2DAT7 ADDR2 ADDR5 ADDR8 SDA10 ADDR10 ADDR13 ADDR15
AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22
DATA53 DATA55 DATA56 DATA59 DATA62 L2DAT1 L2DAT2 L2DAT6 L2CLKIN L2DIR BOFF ADDR3 ADDR4 ADDR6 ADDR7 ADDR9
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484-BALL METRIC PBGA CONFIGURATIONS (TOP VIEW, SUMMARY)
VDD_A VSS_A KEY: VDD_IO SIGNAL
VIEW
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625-BALL PBGA CONFIGURATIONS Table 625-Ball PBGA Assignments Pin# Signal Name Pin# Signal Name Pin# Signal Name Pin# Signal Name Pin# Signal Name
DATA17 DATA14 DATA11 DATA9 DATA7 DATA4 DATA1 L0DIR L0DAT7 L0DAT4 L0DAT1 LCLK_N LCLK_P VDD_A SCLK_N VREF CONTROLIMP2 RESET DMAR2 TRST DATA26 DATA25 DATA24 VDD_IO VDD_IO VDD_IO BUSLOCK TMR0E
DATA16 DATA13 DATA12 DATA10 DATA5 DATA2 L0CLKOUT L0DAT5 L0DAT2 VSS_A SCLK_P CONTROLIMP1 DMAR3 DMAR0 IRQ3 IRQ1 DATA29 DATA28 DATA27 VDD_IO VDD_IO FLAG3 FLAG2 FLAG1
DATA20 DATA21 DATA18 DATA15 DATA8 DATA6 DATA3 DATA0 L0CLKIN L0DAT6 L0DAT3 L0DAT0 VSS_A VDD_A CONTROLIMP0 DMAR1 IRQ2 LCLKRAT0 LCLKRAT1 IRQ0 L3DAT0 DATA31 DATA30 VDD_IO VDD_IO VDD_IO FLAG0
DATA19 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO L3DAT3 L3DAT2 L3DAT1 VDD_IO VDD_IO VDD_IO VDD_IO
DATA23 DATA22 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO SCLKFREQ LCLKRAT2 L3DAT6 L3DAT5 L3DAT4 VDD_IO VDD_IO VDD_IO
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Pin# Signal Name Pin#
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Signal Name Pin# Signal Name
Table 625-Ball PBGA Assignments (continued) Signal Name Pin# Signal Name Pin#
L3CLKIN L3CLKOUT L3DAT7 VDD_IO VDD_IO FLYBY L1DIR L1CLKIN VDD_IO VDD_IO VDD_IO SDCKE SDWE
L1DAT0 L3DIR VDD_IO VDD_IO VDD_IO IOEN BRST DATA34 DATA33 DATA32 VDD_IO VDD_IO VDD_IO VDD_IO
L1DAT2 L1DAT1 VDD_IO VDD_IO VDD_IO VDD_IO DATA37 DATA36 DATA35 VDD_IO VDD_IO VDD_IO ADDR31 ADDR30 ADDR29
L1DAT5 L1DAT4 L1DAT3 VDD_IO VDD_IO VDD_IO HDQM DATA40 DATA39 DATA38 VDD_IO VDD_IO ADDR28 ADDR27
L1CLKOUT L1DAT7 L1DAT6 VDD_IO VDD_IO LDQM MSSD DATA43 DATA42 DATA41 VDD_IO VDD_IO VDD_IO ADDR26 ADDR25 ADDR24
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Pin# Signal Name Pin#
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Signal Name Pin# Signal Name
Table 625-Ball PBGA Assignments (continued) Signal Name Pin# Signal Name Pin#
AA10 AA11 AA12 AA13 AA14 AA15 AA16 AA17 AA18 AA19 AA20 AA21 AA22 AA23 AA24 AA25
DATA46 DATA45 DATA44 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO ADDR23 ADDR22 ADDR21
AB10 AB11 AB12 AB13 AB14 AB15 AB16 AB17 AB18 AB19 AB20 AB21 AB22 AB23 AB24 AB25
DATA49 DATA48 DATA47 VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO VDD_IO ADDR20 ADDR19 ADDR18
AC10 AC11 AC12 AC13 AC14 AC15 AC16 AC17 AC18 AC19 AC20 AC21 AC22 AC23 AC24 AC25
DATA50 DATA51 DATA54 DATA57 DATA60 DATA63 L2DAT2 L2DAT5 L2CLKOUT ADDR0 ADDR3 ADDR6 ADDR9 ADDR11 ADDR14 ADDR17 ADDR16
AD10 AD11 AD12 AD13 AD14 AD15 AD16 AD17 AD18 AD19 AD20 AD21 AD22 AD23 AD24 AD25
DATA52 DATA55 DATA58 DATA61 L2DAT0 L2DAT3 L2DAT6 L2CLKIN ADDR1 ADDR4 ADDR7 SDA10 ADDR12 ADDR15
AE10 AE11 AE12 AE13 AE14 AE15 AE16 AE17 AE18 AE19 AE20 AE21 AE22 AE23 AE24 AE25
DATA53 DATA56 DATA59 DATA62 L2DAT1 L2DAT4 L2DAT7 L2DIR BOFF ADDR2 ADDR5 ADDR8 ADDR10 ADDR13
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625-BALL METRIC PBGA CONFIGURATIONS (TOP VIEW, SUMMARY)
KEY: VDD_IO SIGNAL VDD_A VSS_A
VIEW
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OUTLINE DIMENSIONS
ADSP-TS101S comes 484-ball Metric PBGA package with rows balls (B-484) comes 625-ball Metric PBGA package with rows balls (B-625).
484-BALL METRIC PBGA (B-484)
19.10 19.00 18.90 1.10 19.10 19.00 18.90 BOTTOM VIEW DETAIL 2.50 0.65 0.55 0.45 SEATING PLANE BALL DIAMETER 0.55 0.50 0.45 DETAIL 1.30
17.05 16.95 16.85
19.10 19.00 18.90
16.80
0.80 BALL PITCH 1.10
17.05 16.95 16.85 VIEW
NOTES: DIMENSIONS MILLIMETERS. ACTUAL POSITION BALL GRID WITHIN 0.25mm IDEAL POSITION RELATIVE PACKAGE EDGES. ACTUAL POSITION EACH BALL WITHIN 0.10mm IDEAL POSITION RELATIVE BALL GRID. CENTER DIMENSIONS NOMINAL.
0.40 0.20
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625-BALL METRIC PBGA (B-625)
27.20 27.00 26.80
27.20 27.00 26.80 BOTTOM VIEW DETAIL 1.25
1.50 24.00
24.20 24.00 23.80
27.20 27.00 26.80
1.00 BALL PITCH 24.20 24.00 23.80 VIEW 1.50
2.50
0.65 0.55 0.45 SEATING PLANE BALL DIAMETER 0.70 0.60 0.50
NOTES: DIMENSIONS MILLIMETERS. ACTUAL POSITION BALL GRID WITHIN 0.25mm IDEAL POSITION RELATIVE PACKAGE EDGES. ACTUAL POSITION EACH BALL WITHIN 0.10mm IDEAL POSITION RELATIVE BALL GRID. CENTER DIMENSIONS NOMINAL.
0.40 0.20
DETAIL
ORDERING GUIDE Case Temperature Range
Part Number1,
Instruction Rate3
On-chip SRAM
Operating Voltage
Package
ADSP-TS101SKB1250X ADSP-TS101SKB2250X
-40°C 85°C -40°C 85°C
6Mbit 6Mbit
VDD_IO VDD_IO
(B-625)4 (B-484)5
indicates 1.2/3.3 supplies. indicates -40°C 85°C temperature. indicates instruction rate. Plastic Ball Grid Array (PBGA) package. instruction rate runs internal clock (CCLK) rate. B-625 package measures 27mm 27mm. B-484 package measures 19mm 19mm.
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