with Triple-level Metal 5.0V, 3.3V 2.0V Operation including Mixed
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Drawn Gate Length (0.5 Leff) Sea-of-Gates Architecture
with Triple-level Metal
5.0V, 3.3V 2.0V Operation including Mixed Voltages On-chip Phase Locked Loop Available Synthesize Frequencies
Manage Chip-to-Chip Clock Skew Compiled (Gate Level) Embedded (Custom) SRAMs, ROM, CAMs Available PCI, SCSI High Speed (250 MHz) Buffers Available Easy Alternative Sourcing Existing ASIC, FPGA Designs Design-for-Test Methods, Including JTAG, Serial Boundary Scan ATPG High Output Drive Capability: with Slew Rate Control
ASIC ATLS60 Series
Description
Atmel's next generation ATL60 Series CMOS ASICs fabricated using 0.6µm drawn gate, oxide isolated, triple-level metal process. Extensive cell libraries available support major software tools. with Atmel ASIC families, customer involvement satisfaction integral steps design flow. variety Design Testability techniques supported libraries, wide range packaging options available. ATLS version utilizes fine pitch staggered bond pads achieve smallest size possible given count. ATLS60 only available limited number PQFP packages. Table ATL60 Array Organization
Device Number ATL60/4 ATL60/15 ATL60/25 ATL60/40 ATL60/60 ATL60/85 ATL60/110 ATL60/150 ATL60/200 ATL60/235 ATL60/300 ATL60/435 ATL60/550 ATL60/700 ATL60/870 ATL60/1100 Note: Gates 4,000 15,000 25,000 38,000 58,000 86,000 110,000 149,000 195,000 232,000 301,000 430,000 545,000 693,000 870,000 1,119,000 Routable Gates 3,000 10,000 16,900 25,400 34,600 51,900 65,900 89,300 116,900 139,500 181,000 260,000 288,000 363,000 456,000 590,000 Count Pins Gate(1) Speed
Nominal input NAND gate with fanout volts
Rev. 0388D-ASIC-07/02
ATLS60 Array Organization
Device Number ATLS60/80 ATLS60/100 ATLS60/120 ATLS60/144 ATLS60/160 ATLS60/208 ATLS60/225 ATLS60/256 Note: Gates 12,500 20,400 30,200 44,600 55,300 96,500 113,500 148,200 Routable Gates 8,000 13,000 17,500 26,000 32,500 57,000 67,500 88,000 Count Pins Gate(1) Speed
Nominal two-input NAND gate with fanout volts
Design
Design Systems Supported
Atmel supports major software systems design with complete macro cell libraries, well utilities checking netlist accurate pre-route delay simulations. Table Design Systems Supported
System Cadence® Design Systems, Inc. Tools Opus- Schematic Layout Verilog- Verilog Simulator Pearl- Static Path Verilog-XL- Verilog Simulator BuildGates- Synthesis (Ambit) ModelSim® Verilog VHDL (VITAL) Simulator Leonardo Spectrum- Logic Synthesis Design Compiler- Synthesis Compiler 1-Pass Test Synthesis Compiler Boundary Scan Synthesis TetraMax® Automatic Test Pattern Generation PrimeTime- Static Path VCS- Verilog Simulator Floorplan ManagerDebussy® First Encounter® Version 4.46 3.3-s008 4.3-s095 3.3-s006 4.0-p003 5.5e 2001.1d 01.01-SP1 01.08-SP1 01.08-SP1 01.08 01.08-SP1 01.08-SP1 v2001.2.3
Mentor Graphics® Synopsys
Novas Software, Inc. Silicon Perspective
ATL60 ATLS60 Series
0388D-ASIC-07/02
ATL60 ATLS60 Series
Design Flow
Atmel provides three methods implementing ASIC design while maintaining same basic design flow each method. This flow involves both customer Atmel critical review acceptance steps, shown following page. Database Acceptance occurs when Atmel receives accepts complete design database. Upon completion this critical step, Atmel performs physical place-and-route. Functional timing simulations performed, based physical design, including generation back annotation report provide customer with most accurate timing information available. Final Design Review last step design flow prior generation masks. After this acceptance step completed, masks generated released, prototype parts ceramic packages delivered.
0388D-ASIC-07/02
ASIC Design Flow
Customer Kickoff Meeting
Atmel
Customer
Synthesis, Translation Conversion
Atmel
Customer
Database Submission Underlayer
Atmel
Customer
Underlayer Acceptance Tapeout
Atmel
Customer
Final Database Submission
Atmel
Customer
Database Acceptance
Atmel
Physical Design Verification
Atmel
Customer
Final Design Review
Atmel
Customer
Prototype Delivery
Notes:
Performed customer optionally Atmel 9001/QS9000 Milestone
Rev.2.3-04/02
ATL60 ATLS60 Series
0388D-ASIC-07/02
ATL60 ATLS60 Series
Definition Requirements
Within Physical Design step (i.e., layout), certain restrictions apply during definition. corner pins each reserved programmable power ground only. other buffer pins fully programmable input, output, bidirectional, clockinto-array, power, ground.
Design Options
Logic Synthesis
Atmel accept Register Transfer Level (RTL) designs VHDL (MIL-STD-454, IEEE 1076) Verilog-HDL format. Atmel fully supports Synopsys VHDL simulation well synthesis. VHDL Verilog-HDL Atmel's preferred method performing ASIC design. Atmel successfully translated dozens existing designs from most major ASIC vendors into ASICs. These designs have been optimized speed gate count modified logic memory, replicated pin-for-pin compatible, drop-in replacement. Atmel successfully translated existing FPGA/PLD designs from most major vendors into ASICs. There four primary reasons convert from FPGA/PLD ASIC. Conversion high-volume devices (over 10,000 units) single combined design cost effective. Performance often optimized speed power consumption. Several FPGA/PLDs combined onto single chip minimize cost while reducing on-board space requirements. Finally, situations where FPGA/PLD used fast cycle time prototyping, ASIC provide lower cost answer long-term volume production.
ASIC Design Translation
FPGA Conversions
0388D-ASIC-07/02
ATL60 Series Cell Library
Atmel's ATL60 Series ASICs make extensive library cell structures, including logic cells, buffers inverters, multiplexers, decoders options. Soft macros also available. ATL60 Series operates frequencies with minimal phase error jitter, making ideal frequency synthesis high-speed on-chip clocks chip-to-chip synchronization. Output buffers programmable meet voltage current requirements both SCSI. These cells characterized SPICE modeling transistor level, with performance verified manufactured test arrays. Characterization performed over military temperature voltage ranges ensure that simulation accurately predicts performance finished product.
Table Cell Index
Signal Name ADD3X AND2 AND2H AND3 AND3H AND4 AND4H AND5 AOI22 AOI22H AOI222 AOI222H AOI2223 AOI2223H AOI23 BUF1 BUF2 BUF2T BUF2Z BUF3 BUF4 BUF8 BUF12 BUF16 CLA7X DEC4 DEC4N Description One-bit full adder with buffered outputs 2-input 2-input High-drive 3-input 3-input High-drive 4-input 4-input High-drive 5-input 2-input into 2-input 2-input into 2-input High-drive 2-input ANDs into 2-input 2-input ANDs into 2-input High-drive Three 2-input ANDs into 3-input Three 2-input ANDs into 3-input High-drive 2-input into 3-input Buffer Buffer Tristate Driver with Active-high Enable Tristate Driver with Active-low Enable Buffer Buffer Buffer Buffer Buffer 7-input Carry Lookahead Decoder Decoder with Active-low Enable Site Count(1)
ATL60 ATLS60 Series
0388D-ASIC-07/02
ATL60 ATLS60 Series
Table Cell Index (Continued)
Signal Name DEC8N DFFBCPX DFFBSRX DFFC DFFR DFFS DFFSR DLY1500 DLY2000 DLY6000 DSSBCPY DSSBR DSSBS DSSR DSSS DSSSR INV1 INV1D INV1Q INV1TQ INV2 INV2T INv3h INV4 INV8 INV10 JKFBCPX JKFC LATBG LATBH Description Decoder with Active-low Enable Flip-flop Flip-flop with Asynchronous Clear Preset with Complementary Outputs Flip-flop with Asynchronous Reset with Complementary Outputs Flip-flop with Asynchronous Clear Flip-flop with Asynchronous Reset Flip-flop with Asynchronous Flip-flop with Asynchronous Reset Delay Buffer Delay Buffer Delay Buffer Scan Flip-flop Scan Flip-flop with Clear Preset Scan Flip-flop with Reset Scan Flip-flop with Scan Flip-flop with Reset Scan Flip-flop with Scan Flip-flop with Reset Inverter Dual Inverters Quad Inverters Quad Tristate Inverter Inverter Tristate Inverter with Active-high Enable Inverter Inverter Inverter Inverter Flip-flop Clear Preset Flip-flop with Asynchronous Clear Preset Complementary Outputs Flip-flop with Asynchronous Clear LATCH LATCH with Complementary Outputs Inverted Gate Signal LATCH with High-drive Complementary Outputs Site Count(1)
0388D-ASIC-07/02
Table Cell Index (Continued)
Signal Name LATR LATS LATSR LSCC LSISO MUX2 MUX2H MUX2I MUX2IH MUX2N MUX2NQ MUX2Q MUX3I MUX3IH MUX4 MUX4X MUX4XH MUX5H MUX8 MUX8N MUX8XH NAN2 NAN2D NAN2H NAN3 NAN3H NAN4 NAN4H NAN5 NAN5H NAN6 NAN6H NAN8 NAN8H NOR2 NOR2D Description LATCH with Reset LATCH with LATCH with Reset Voltage Level Shifter Voltage Level Shifter with Power Supply Isolation Function High-drive with Inverted Output with Inverted Output High-drive with Active-low Enable Quad with Active-low Enable Quad with Inverted Output with Inverted Output High-drive with Transmission Gate Data Inputs with Transmission Gate Data Inputs High-drive High-drive with Active-low Enable with Transmission Gate Data Inputs High-drive 2-input NAND Dual 2-input NAND 2-input NAND High-drive 3-input NAND 3-input NAND High-drive 4-input NAND 4-input NAND High-drive 5-input NAND 5-input NAND High-drive 6-input NAND 6-input NAND High-drive 8-input NAND 8-input NAND High-drive 2-input Dual 2-input Site Count(1)
ATL60 ATLS60 Series
0388D-ASIC-07/02
ATL60 ATLS60 Series
Table Cell Index (Continued)
Signal Name NOR2H NOR3 NOR3H NOR4 NOR4H NOR5 NOR8 OAI22 OIA22H OAI222 OAI222H OAI22224 OAI23 ORR2 ORR2H ORR3 ORR3H ORR4 ORR4H ORR5 XNR2 XNR2H XOR2 XOR2H Note: Description 2-input High-drive 3-input 3-input High-drive 4-input 4-input High-drive 5-input 8-input 2-input into 2-input NAND 2-input into 3-input NAND High-drive 2-input into 2-input NAND 2-input into 2-input NAND High-drive Four 2-input into 4-input NAND 2-input into 3-input NAND 2-input 2-input High-drive 3-input 3-input High-drive 4-input 4-input High-drive 5-input 2-input Exclusive 2-input Exclusive High-drive 2-input Exclusive 2-input Exclusive High-drive Site Count(1)
single ATL60 routing site contains four transistors, N-channel P-channel, aligned columns. number sites used gate varies according specific isolation power requirements. Percent utilization varies from 70%, with more accurate utilization figures generated DoubleCheckTM, netlist checker.
0388D-ASIC-07/02
Table CMOS Input Interface Characteristics
Interface CMOS Logic High 3.5V Minimum 2.0V Minimum Logic 1.5V Maximum 0.8V Maximum Switchpoint Typical 1.4V Typical
Table Absolute Maximum Ratings(1)
Operating Temperature Storage Temperature Voltage with Respect Ground Maximum Operating Voltage Notes: -55°C +125°C -65°C +150°C -2.0V +7.0V(2) 6.0V
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. This stress rating only; functional operation device these other conditions beyond those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect device reliability. Minimum voltage -0.6V which undershoot -2.0V pulses less than Maximum output voltage 0.75V which overshoot +7.0V pulses less than
Table 5.0-volt Characteristics Applicable over recommended operating range from -55°C +125°C, 4.5V 5.5V (unless otherwise noted)
Symbol Parameter Input Leakage High Input Leakage pull-up) pull-up Output Leakage pull-up) Output Short Circuit Current buffer)(1) Input Voltage CMOS Input Voltage Input High Voltage CMOS Input High Voltage Switching Threshold CMOS Switching Threshold Output Voltage Output buffer stages drive capability with stage Output High Voltage Output buffer stages drive capability with stage 5.0V, 25°C 5.0V, 25°C rated 4.5V rated 4.5V Test Condition VDD, 5.5V VSS, 5.5V VSS, 5.5V VSS, 5.5V 5.5V, VOUT 5.5V, VOUT Units
-100
Note:
This specification buffer. Output short circuit current other outputs will scale accordingly. more than output shorted time, maximum second, allowed.
ATL60 ATLS60 Series
0388D-ASIC-07/02
ATL60 ATLS60 Series
Table 3.3-volt Characteristics Applicable over recommended operating range from -55°C +125°C, 2.7V 3.6V (unless otherwise noted)
Symbol Parameter Input Leakage High Input Leakage pull-up) pull-up (U31) Output Leakage pull-up) Output Short Circuit Current buffer)(1) CMOS Input Voltage CMOS Input High Voltage CMOS Switching Threshold Output Voltage Output buffer stages drive capability with stage. Output High Voltage Output buffer stages drive capability with stage. 3.0V, 25°C rated 2.7V rated 2.7V Test Condition VDD, 3.6V VSS, 3.6V VSS, 3.6V VSS, VOUT VOUT Units
Table 2.0-volt Characteristics Applicable over recommended operating range from +70°C, 1.8V 2.2V (unless otherwise noted)
Symbol Parameter Input Leakage High Input Leakage pull-up) pull-up (U31) Output Leakage pull-up) Output Short Circuit Current buffer)(1) CMOS Input Voltage CMOS Input High Voltage CMOS Switching Threshold Output Voltage Output buffer stages drive capability with stage. Output High Voltage Output buffer stages drive capability with -0.5 stage. 0.5xVDD Test Condition VDD, 2.2V VSS, 2.2V VSS, 2.2V VSS, 2.2V 2.2V, VOUT 2.2V, VOUT Units
rated 1.8V
Note:
rated 1.8V
This specification buffer. Output short circuit current other outputs will scale accordingly. more than output shorted time, maximum second, allowed.
0388D-ASIC-07/02
Table Buffer Characteristics
Symbol COUT CI/O Parameter Capacitance, Input Buffer (die) Capacitance, Output Buffer (die) Capacitance, Bidirectional Test Condition 5.0V, 3.3V, 2.0V 5.0V, 3.3V, 2.0V 5.0V, 3.3V, 2.0V Units
Schmitt Trigger Positive Threshold CMOS Positive Threshold Negative Threshold CMOS Negative Threshold Hysteresis CMOS Hysteresis CMOS Positive Threshold CMOS Negative Threshold CMOS Hysteresis 25°C, 5.0V 25°C, 5.0V 25°C, 5.0V 25°C, 5.0V 25°C, 5.0V 25°C, 5.0V 25°C, 3.3V 25°C, 3.3V 25°C, 3.3V
Buffers
Programmable output drive IOL; volts IOL; volts Programmable slew rate control Built-in configurable test logic
Design Testability
Atmel supports wide range Design Testability techniques improve percentage design that fully tested. achieving high degree testability, designer reduce design prototype debug time, minimize production test time, improve board- system-level test diagnostic capability. Synopsys Test Compiler software fully supported Atmel. using this system during design, computer will create scan chains design, test vectors will generated provide greater than fault coverage. This method requires only added pins Test Enable Test Mode. This easiest least expensive method designing testability into ASIC design. means increasing testability ASIC also available. Partitioning, memory array isolation, test point insertion encouraged supported ATL60 Series ASICs. Atmel also encourages inclusion Built-In Self-Test (BIST) techniques whenever possible. Each these methods discussed detail Atmel CMOS ASIC Design Manual. addition above, ATL60 Series ASICs also support Joint Test Action Group (JTAG) boundary scan architecture Test Access Port (TAP) requirements. required soft hard macros implement IEEE 1149.1-compliant architecture available Atmel's cell library. JTAG architecture requires additional four five pins test mode, data, clock signals.
ATL60 ATLS60 Series
0388D-ASIC-07/02
ATL60 ATLS60 Series
Advanced Packaging
ATL60 Series ASICs offered wide variety standard packages, including plastic ceramic quad flatpacks, thin quad flatpacks, ceramic grid arrays ball grid arrays. High-volume on-shore off-shore contractors provide assembly test commercial product, with prototype capability Colorado Springs. Custom package designs also available required meet customer's specific needs supported through Atmel's package design center. When standard package cannot meet customer's need, package designed precisely application maintain performance obtained silicon. Atmel delivered custom-designed packages wide variety configurations. Table Package Options (Partial List)
Package Type PQFP Power Quad L/TQFP PLCC CPGA CQFP PBGA Super Low-profile Mini Chip-scale Flex-tape FCBGA* Note: Count 100, 120, 128, 132, 144, 160, 184, 208, 240, 144, 160, 208, 240, 100, 120, 128, 144, 160, 176, 100, 124, 144, 155, 180, 223, 224, 299, 100, 120, 132, 144, 160, 224, 121, 169, 208, 217, 225, 240, 256, 272, 300, 304, 313, 316, 329, 352, 388, 420, 168, 204, 240, 256, 304, 352, 432, 560, 100, 108, 128, 132, 144, 160, 176, 192, 208, 224, 100, 108, 121, 128, 144, 160, 169, 176, 192, 208, 224, 256, 288, 100, 112, 132, 144, 156, 160, 180, 192, 196, 204, 208, 220, 225, 228, 256, 416, 480, 564, 672, 788, 896, 960, 1032, 1152, 1157, 1292, 1357, 1413, 1500, 1517, 1557, 1677, 1728, 1932
These packages require custom design substrate.
0388D-ASIC-07/02
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Atmel Corporation 2002. Atmel Corporation makes warranty products, other than those expressly contained Company's standard warranty which detailed Atmel's Terms Conditions located Company's site. Company assumes responsibility errors which appear this document, reserves right change devices specifications detailed herein time without notice, does make commitment update information contained herein. licenses patents other intellectual property Atmel granted Company connection with sale Atmel products, expressly implication. Atmel's products authorized critical components life support devices systems. Atmel® registered trademark DoubleCheck trademark Atmel. Cadence® registered trademark Opus Verilog Pearl, Verilog-XL BuildGatesare trademarks Cadence Design Systems, Inc.; Mentor Graphics ModelSim registered trademarks Leonardo Spectrum trademark Mentor Graphics; Design Compiler PrimeTime, Floorplan Manager trademarks Synopsys TetraMax registered trademarks Synopsys; Debussy registered trademark Novas Software, Inc.; Silicon Perspective First Encounter registered trademarks Silicon Perspective. Other terms product names trademarks others.
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0388D-ASIC-07/02
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