MIL-STD-1553A/B NOTICE BC/RT/MT, ADVANCED COMMUNICATION ENGINE (ACE)
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BU-65170/61580 BU-61585
MIL-STD-1553A/B NOTICE BC/RT/MT, ADVANCED COMMUNICATION ENGINE (ACE)
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FEATURES
Fully Integrated MIL-STD-1553 Interface Terminal Flexible Processor/Memory Interface Standard Optional Available Optional Parity Generation/ Checking Automatic Retries Programmable Times Frame Auto-Repeat Flexible Data Buffering Programmable llegalization
DESCRIPTION
DDC's BU-65170, BU-61580 BU-61585 Controller Remote Terminal Monitor Terminal (BC/RT/MT) Advanced Communication Engine (ACE) terminals comprise complete integrated interface between host processor MIL-STD-1553 STANAG 3838 bus. series packaged -square-inch, 70-pin, low-profile, cofired MultiChip Module (MCM) ceramic package that well suited applications with stringent height requirements. BU-61585 integrates dual transceiver, protocol, memory management, processor interface logic, total words choice flat pack packages. BU-61585 requires power either power. BU-61585 internal configured feature provides capability memory integrity checking implementing parity generation verification accesses. minimize board space "glue" logic, provides ultimate flexibility interfacing host processor internal/external RAM. advanced functional architecture terminals provides software compatibility DDC's Advanced Integrated Multiplexer (AIM) series hybrids, while incorporating multiplicity architectural enhancements. allows flexible operation while off-loading host processor, ensuring data sample consistency, supports bulk data transfers.The hybrids operated either MHz. Wire bond options allow programmable address (hardwired standard) external transmitter inhibit inputs.
Selective Message Monitor Simultaneous RT/Monitor Mode
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SHARED TRANSCEIVER
TX/RX_A
TX/RX_A DUAL ENCODER/DECODER, MULTIPROTOCOL MEMORY MANAGEMENT ADDRESS ADDRESS BUFFERS
DATA
DATA BUFFERS
D15-D0
PROCESSOR DATA
TX/RX_B
A15-A0
PROCESSOR ADDRESS
TRANSCEIVER TRANSPARENT/BUFFERED, STRBD, SELECT, RD/WR, MEM/REG, TRIGGER_SEL/MEMENA-IN, MSB/LSB/DTGRT PROCESSOR MEMORY INTERFACE LOGIC IOEN, MEMENA-OUT, READYD ADDR_LAT/MEMOE, ZERO_WAIT/MEMWR, 8/16-BIT/DTREQ, POLARITY_SEL/DTACK PROCESSOR MEMORY CONTROL RTAD4-RTAD0, RTADP INCMD CLK_IN, TAG_CLK, MSTCLR,SSFLAG/EXT_TRG INTERRUPT REQUEST ORDERING INFORMATION AVAILABLE MEMORY
TX/RX_B
ADDRESS
MISCELLANEOUS
BU-65170/61580/61585 L-03/06-0
FIGURE BLOCK DIAGRAM
TABLE "ACE" SERIES SPECIFICATIONS PARAMETER ABSOLUTE MAXIMUM RATING Supply Voltage Logic Transceiver -15V -12V Logic Voltage Input Range RECEIVER Differential Input Resistance (BU-65170/61580/61585X1, BU-65170/61580/61585X2) (Notes 1-7) (BU-65170/61580/61585X3, BU-65170/61580/61585X6) (Notes 1-7) Differential Input Capacitance (BU-65170/61580/61585X1, BU-65170/61580/61585X2) (Notes 1-7) (BU-65170/61580/61585X3, BU-65170/61580/61585X6) (Notes 1-7) Threshold Voltage, Transformer Coupled, Measured Stub Common Mode Voltage (Note TRANSMITTER Differential Output Voltage Direct Coupled Across Measured Transformer Coupled Across Measured Output Noise, Differential (Direct Coupled) Output Offset Voltage, Transformer Coupled Across ohms Rise/Fall Time LOGIC (Vcc=5.5V, VIN=Vcc) (Vcc=5.5V, VIN=2.7V) SSFLAG/EXT_TRIG Other Inputs (Vcc=5.5V, VIN=0.4V) SSFLAG/EXT_TRIG Other Inputs (Vcc=4.5V, VIH=2.7V, VIL=0.2V, IOH=max) (Vcc=4.5V, VIH=2.7V, VIL=0.2V, IOL=max) DB15-DB0, A15-A0, MEMOE/ ADDR_LAT, MEMWR/ ZEROWAIT, DTREQ/16/8, DTACK/POLARITY_SEL UNITS
TABLE "ACE" SERIES SPECIFICATIONS (CONTD) PARAMETER LOGIC (cont'd) INCMD, MEMENA_OUT, READYD, IOEN, TXA, TXA, TXB, TXB, TX_INH_OUT_A, TX_INH_OUT_B, DB15-DB0, A15-A0, MEMOE/ ADDR_LAT, MEMWR/ ZEROWAIT, DTREQ/16/8, DTACK/POLARITY_SEL INCMD, INT, MEMENA_OUT, READYD, IOEN, TXA, TXA, TXB, TXB, TX_INH_OUT_A, TX_INH_OUT_B, (Input Capacitance) (Bi-directional signal input capacitance) POWER SUPPLY REQUIREMENTS Voltages/Tolerances BU-65170/61580/61585X1 (Logic) (Ch. -15V (Ch. BU-65170/61580/61585X2 (Logic) (Ch. -12V (Ch. BU-65170/61580/61585X3, BU-65170/61580/61585X6 (Logic) (Ch. Current Drain (Total Hybrid) BU-65170/61580X1 (Logic, -15V (Ch. Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-65170/61580X2 (Logic, -12V (Ch. Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-65170/61580X3, BU-65170/61580X6 (Logic, Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-61585X1 (Logic, -15V (Ch. Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle UNITS
-0.3 -0.3 -18.0 -18.0 -0.3
Vcc+0.
-6.4
-3.2
0.200
0.860
Vp-p Vpeak
-15.75 -15.0 -14.25 -12.6 -12.0 -11.4
Vp-p
4.75
5.25
-250
Vp-p Vp-p mVp-p, diff nsec
-692 -346 -794 -397
-100
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BU-65170/61580/61585 L-03/06-0
TABLE "ACE" SERIES SPECIFICATIONS (CONTD) PARAMETER BU-61585X2 (Logic, -12V (Ch. Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-61585X3, BU-61585X6 (Logic, Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle POWER DISSIPATION Total Hybrid BU-65170/61580X1 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-65170/61580X2 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-65170/61580X3, BU-65170/61580X6 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-61585X1 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-61585X2 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-61585X3, BU-61585X6 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle Hottest BU-65170/61580X1 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-65170/61580X2 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-65170/61580X3, BU-65170/61580X6 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle UNITS
TABLE "ACE" SERIES SPECIFICATIONS (CONTD) PARAMETER BU-61585X1 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-61585X2 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle BU-61585X3, BU-61585X6 Idle Transmitter Duty Cycle Transmitter Duty Cycle 100% Transmitter Duty Cycle CLOCK INPUT Frequency Nominal Value (programmable) Default Mode Software Programmable Option Long Term Tolerance 1553A Mode 1553B Mode Short Term Tolerance, second 1553A Mode 1553B Mode Duty Cycle 1553 MESSAGE TIMING Completion Write Start)to-Start Next Message Intermessage (Note BC/RT/MT Response Timeout (Note 18.5 nominal 22.5 nominal 50.5 nominal 128.0 nominal Response Timeout (Note Transmitter Watchdog Timeout THERMAL Thermal Resistance, Junction-to-Case, Hottest (JC) BU-65170/61580/61585X1, BU-65170/61580/61585X2, BU-65170/61580/61585X3, BU-65170/61580/61585X6 Operating Junction Temperature Storage Temperature Lead Temperature (soldering, sec.) PHYSICAL CHARACTERISTICS Size BU-65170/61580/61585 BU-65170/61580/61585 Weight BU-65170/61580/61585 0.335 0.600 0.860 1.385 0.290 0.590 0.890 1.490 UNITS 0.68 1.06 1.45 2.23 0.59 0.92 1.36 2.16
0.18 0.42 0.66 1.14
0.28 0.51 0.75 1.22
0.850 1.195 1.450 1.975 0.835 1.135 1.435 2.035
1.85 2.25 2.72 3.52 1.67 2.10 2.59 3.46
16.0 12.0 0.01 0.001 0.01 17.5 18.5 21.5 22.5 49.5 50.5 129.5 19.5 23.5 51.5
0.64 0.93 1.22 1.81 0.900 1.245 1.500 2.025 0.885 1.185 1.485 2.085
0.88 1.11 1.33 1.97 2.10 2.50 2.97 3.77 1.92 2.35 2.84 3.71
0.69 0.98 1.27 1.86
0.93 1.16 1.38 2.02
6.99 +300
°C/W °C/W
0.335 0.600 0.860 1.385 0.290 0.590 0.890 1.490
0.68 1.06 1.45 2.23 0.59 0.92 1.36 2.16
0.165 (48.3 25.4 4.19) 0.150 (48.3 25.4 3.81) (17)
(mm) (mm)
0.18 0.42 0.66 1.14
0.28 0.51 0.75 1.22
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BU-65170/61580/61585 L-03/06-0
Notes Table Notes through applicable Receiver Differential Resistance Differential Capacitance specifications: Specifications include both transmitter receiver (tied together internally). Measurement impedance directly between pins TX/RX A(B) TX/RX A(B) BU-65170/61580XX hybrid. Assuming connection power ground inputs hybrid. specifications applicable both unpowered powered conditions. specifications assume volt balanced, differential, sinusoidal input. applicable frequency range MHz. Minimum resistance maximum capacitance parameters guaranteed,but tested, over operating range. Assumes common mode voltage within frequency range 2MHz, applied pins isolation transformer stub side (either direct transformer coupled), referenced hybrid ground. recommended transformer other transformer that provides equivalent minimum CMRR. Typical value minimum intermessage time. Under software control, lengthened (65,535µs minus message time), increments 1µs. Software programmable options). Includes RT-to-RT Timeout (Mid-Parity Transmit Command Mid-Sync Transmitting Status). (10) both logic transceiver. channels (11) Measured from mid-parity crossing Command Word mid-sync crossing RT's Status Word. (12) Specifications BU-65171, BU-61581, BU-61586 identical specifications BU-65170, BU-61580, BU61585 respectively.
memory management scheme mode provides option separation broadcast data, compliance with 1553B Notice Both double buffer circular buffer options programmable subaddress. These features serve ensure data consistency off-load host processor bulk data transfer applications. series implements three monitor modes: word monitor, selective message monitor, combined RT/selective monitor. Other features include options automatic retries programmable intermessage mode, internal Time Register, Interrupt Status Register internal command illegalization mode.
FUNCTIONAL OVERVIEW
TRANSCEIVERS
transceivers BU-65170/61580X3(X6) fully monolithic, requiring only volt power input. Besides eliminating need additional power supply, volt (only) transceiver requires step-up, rather than step-down, isolation transformers. This provides advantage higher terminal input impedance than possible volt volt transmitter. result, there greater margin input impedance test, mandated 1553 validation testing. This allows longer cable lengths between LRU's system connector isolation transformers embedded 1553 terminal. V/-12 front end, BU-65170/ 61580X1(X2) uses low-power bipolar analog monolithic thick-film hybrid technology. transceiver requires (-12 only (requiring V/+12 includes voltage source transmitters. voltage source transmitters provide superior line driving capability long cables heavy amounts loading. addition, monolithic transceivers BU-65170/61580X1 provide minimum stub voltage level volts peak-to-peak transformer coupled, making them suitable MIL-STD-1760 applications. receiver sections BU-65170/61580 fully compliant with MIL-STD-1553B terms front overvoltage protection, threshold, common mode rejection, word error rate. addition, receiver filters have been designed optimal operation with chip's Manchester decoders.
INTRODUCTION
DDC's series Integrated BC/RT/MT hybrids provide complete, flexible interface between microprocessor MIL-STD-1553A, Notice McAir, STANAG 3838 bus, implementing Controller, Remote Terminal (RT) Monitor Terminal (MT) modes. Packaged single 1.9-square-inch, 70-pin surface mountable flatpack J-lead package, series contains dual low-power transceivers encoder/decoders, complete BC/RT/MT multi-protocol logic, memory management interrupt logic, shared static direct, buffered interface host processor bus. BU-65170/61580 contains internal address latches bidirectional data buffers provide direct interface host processor bus. BU-65170/61580 interfaced directly both 16-bit 8-bit microprocessors buffered shared configuration. addition, connect 16-bit processor Direct Memory Access (DMA) interface. BU-65170/61580 includes words buffered RAM. Alternatively, interfaced much words external either shared configurations. mode multiprotocol, supporting MIL-STD-1553A, MIL-STD-1553B Notice STANAG 3838 (including EFAbus), McAir A3818, A5232, A5690 protocols. Full compliance McAir specs, however, requires sinusoidal transceiver (transceiver option Refer BU-61590 data sheet additional information McAir terminals. Data Device Corporation www.ddc-web.com
DIGITAL MONOLITHIC digital monolithic represents cornerstone element family terminals. development chip represents fifth generation 1553 protocol interface design DDC. Over years, DDC's 1553 protocol interface design evolved from: discrete component sets, consisting multiple hybrids (with large numbers chips inside individual hybrids) programmable logic devices, multiple custom ASICs perform functions encoder/decoder
BU-65170/61580/61585 L-03/06-0
protocol within single hybrid, BUS-61553 Advanced Integrated Hybrid (AIM-HY) series, containing, addition dual monolithic/thick-film transceiver discrete chips, custom protocol chip separate custom memory management/processor interface chip, BUS-61559 Advanced Integrated Hybrids with Enhanced Features (AIM-HY'er AIM-HY'er series includes memory management processor interface functions beyond those AIMHY series) full integration chip. chip consists dual encoder/decoder, complete protocol Controller (BC), 1553A/B/McAir Remote Terminal (RT), Monitor (MT) modes; memory management interrupt logic; flexible, buffered interface host processor optional external RAM; words on-chip RAM. Reference region within dotted line FIGURE Besides realizing protocol, memory management, interface functions earlier AIM-HY'er series, chip includes large number enhancements facilitate hardware software design, further off-load 1553 terminal's host processor.
Interrupt Status Register when Time Register rolls over from 0000 FFFF. Assuming Time Register loaded reset, this will occur approximately 4-second time intervals, µs/LSB resolution, down intervals, µs/LSB resolution. Another programmable option mode automatic clearing Service Request Status Word following ACE's response Transmit Vector Word mode command.
INTERRUPTS
series components provide many programmable options interrupt generation handling. interrupt output (INT) three software programmable modes operation: pulse, level output cleared under software control, level output automatically cleared following read Interrupt Status Register. Individual interrupts enabled Interrupt Mask Register. host processor easily determine cause interrupt using Interrupt Status Register. Interrupt Status Register provides current state interrupt conditions. Interrupt Status Register updated ways. standard interrupt handling mode, particular Interrupt Status Register will updated only condition exists corresponding Interrupt Mask Register enabled. enhanced interrupt handling mode, particular Interrupt Status Register will updated condition exists regardless contents corresponding Interrupt Mask Register bit. case, respective Interrupt Mask Register enables interrupt particular condition.
DECODERS default mode operation BU-65170 BU61580 BC/RT/MT requires clock input. needed, software programmable option allows device operated from clock input. Most current 1553 decoders sample using clock. mode (default following hardware software reset), decoders sample 1553 serial data using clock. mode, decoders sample using both clock edges; this provides sampling rate MHz. faster sampling rate chip's Manchester decoders provides superior performance terms error rate zero-crossing distortion tolerance.
interfacing fiber optic transceivers MIL-STD-1773 applications, transceiverless version chip, BU-65620, used. These versions provide pin-programmable option direct interface single-ended outputs fiber optic receiver. external logic needed.
ADDRESSING, INTERNAL REGISTERS, MEMORY MANAGEMENT
software interface BU-65170/61580 host processor consists internal operational registers normal operation, additional test registers, plus shared memory address space. BU-65170/61580's internal resides this address space. Reference TABLE Definition address mapping accessibility ACE's non-test registers, test registers, follows: Interrupt Mask Register used enable disable interrupt requests various conditions. Configuration Registers used select BU61580's mode operation, software control Status Word bits, Active Memory Area, Stop-on-Error, Memory Management mode selection, control Time operation. Start/Reset Register used "command" type functions, such software reset, BC/MT Start, Interrupt Reset, Time Reset, Time Register Test. Start/Reset Register includes provisions stopping auto-repeat mode, either current message current frame.
TIME TAGGING includes internal read/writable Time Register. This register read/writable 16-bit counter with programmable resolution either LSB. Also, Time Register clocked from external oscillator. Another option allows software-controlled incrementing Time Register. This supports self-testing Time Register. each message processed, value Time register loaded into second location respective descriptor stack entry ("TIME WORD") both modes.
Additional provided options will: clear Time Register following Synchronize (without data) mode command load Time Register following Synchronize (with data) mode command; enable interrupt request setting Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
TABLE ADDRESS MAPPING ADDRESS LINES reserved applicable BU-65170/61571 Test Mode Register reserved Interrupt Mask Register (RD/WR) Configuration Register (RD/WR) Configuration Register (RD/WR) Start/Reset Register (WR) BC/RT Command Stack Pointer Register (RD) Control Word*/RT Subaddress Control Word Register (RD/WR) Time Register (RD/WR) Interrupt Status Register (RD) Configuration Register (RD/WR) Configuration Register (RD/WR) Configuration Register (RD/WR) Data Stack Address Register (RD)* Frame Time Remaining Register (RD)* Time Remaining Next Message Register (RD)* Frame Time*/RT Last Command/MT Trigger Word* Register (RD/WR) Status Word Register (RD) Word Register (RD) Test Mode Register REGISTER DESCRIPTION/ACCESSIBILITY
µs/LSB.The TAG_CLK input signal also cause external oscillator clock Time Register. Start-of-Message (SOM) End-ofMessage (EOM) sequences Message Monitor modes cause write current value Time Register stack area RAM. Interrupt Status Register mirrors Interrupt Mask Register contains Master Interrupt bit. allows host processor determine cause interrupt request means single READ operation. Configuration Registers used enable many BU-61580's advanced features. These include enhanced mode features; that functionality beyond that previous generation product, BUS-61559 Advanced Integrated Hybrid with Enhanced Features (AIM-HY'er).For three modes, Enhanced Mode enables various read-only bits Configuration Register mode, enhanced mode features include expanded Control Word Block Status Word, additional Stop-On-Error Stop-OnStatus functions, frame auto-repeat, programmable intermessage times, automatic retries, expanded Status Word Masking, capability generate interrupts following completion selected message. mode, enhanced mode features include expanded Block Status Word, combined RT/Selective Message Monitor mode, internal wrapping RTFAIL output signal (from chip) RTFLAG Status Word bit, double buffering scheme individual receive (broadcast) subaddresses, alternate (fully software programmable) Status Word. mode, enhanced mode enables Selective Message Monitor, combined RT/Selective Monitor modes, monitor triggering capability. Data Stack Address Register used point current address location shared used storing message words (second Command Words, Data Words, Status Words) Selective Word Monitor mode. Frame Time Remaining Register provides read only indication time remaining current frame. resolution this register µs/LSB. Message Time Remaining Register provides read only indication time remaining before start next message frame. resolution this register µs/LSB. Frame/RT Last Command/MT Trigger Word Register: mode, programs frame time, frame auto-repeat mode. resolution this register µs/LSB, with range 6.55 seconds; mode, this register stores current most previous) 1553 Command Word processed Word Monitor mode, this register specifies 16-bit Trigger (Command) Word. Trigger Word used start stop monitor, generate interrupts. Status Word Register Word Registers provide read-only indications BU-65170/61580's Status Words. Test Mode Registers 0-7: These registers used facilitate production maintenance testing BU-65170/61580 systems incorporating BU-65170/61580.
BC/RT Command Stack Pointer Register allows host determine pointer location current most recent message when BU-61580 modes. Control Word/RT Subaddress Control Word Register: mode, allows host access current, most recent Control Word. Control Word contains bits that select active message format, enable off-line self-test, masking Status Word bits, enable retries interrupts, specify MIL-STD-1553A -1553B error handling. mode, this register allows host access current most recent Subaddress Control Word. Subaddress Control Word used select memory management scheme enable interrupts current message. read/write accessibility used testing ACE. Time Register maintains value real-time clock. resolution this register programmable from among Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
TABLE INTERRUPT MASK REGISTER (READ/WRITE 00h) 0(LSB) DESCRIPTION PARITY ERROR BC/RT TRANSMITTER TIMEOUT BC/RT COMMAND STACK ROLLOVER COMMAND STACK ROLLOVER DATA STACK ROLLOVER FAIL RETRY ADDRESS PARITY ERROR TIME ROLLOVER CIRCULAR BUFFER ROLLOVER
CONTROL WORD/RT SUBADDRESS CONTROL WORD
TABLE CONFIGURATION REGISTER (READ/WRITE 02h) 15(MSB) DESCRIPTION ENHANCED INTERRUPTS
PARITY ENABLE (BU-61585/6 BU-65621 ONLY)
15(MSB) RESERVED
BUSY LOOKUP TABLE ENABLE DOUBLE BUFFER ENABLE OVERWRITE INVALID DATA 256-WORD BOUNDARY DISABLE TIME RESOLUTION 2(TTR2) TIME RESOLUTION (TTR1) TIME RESOLUTION (TTR0) CLEAR TIME SYNCHRONIZE LOAD TIME SYNCHRONIZE INTERRUPT STATUS AUTO CLEAR LEVEL/PULSE INTERRUPT REQUEST CLEAR SERVICE REQUEST ENHANCED MEMORY MANAGEMENT SEPARATE BROADCAST DATA
FRAME FORMAT ERROR
STATUS SET/RT MODE CODE/MT PATTERN TRIGGER
MESSAGE
0(LSB)
TABLE CONFIGURATION REGISTER (READ/WRITE 01H) (LSB) FUNCTION (Bits 11-0 Enhanced Mode Only) RT/BC-MT (logic MT/BC-RT (logic CURRENT AREA MESSAGE STOP-ON-ERROR FRAME STOP-ON-ERROR WITHOUT ALTERNATE STATUS (logic (logic CURRENT AREA WITH ALTERNATE STATUS (Enhanced Only) (logic (logic CURRENT AREA MONITOR FUNCTION (Enhanced mode only bits 12-0) (logic (logic CURRENT AREA MESSAGE MONITOR ENABLED (MMT) TRIGGER ENABLED WORD START-ON-TRIGGER STOP-ON-TRIGGER USED EXTERNAL TRIGGER ENABLED USED USED USED USED MONITOR ENABLED(Read Only) MONITOR TRIGGERED (Read Only)
MESSAGE MONITOR ENABLED MESSAGE MONITOR (MMT) ENABLED (MMT) DYNAMIC CONTROL ACCEPTANCE
STATUS STOP-ON-MESSAGE BUSY STATUS STOP-ON-FRAME FRAME AUTO-REPEAT EXTERNAL TRIGGER ENABLED INTERNAL TRIGGER ENABLED INTERMESSAGE TIMER ENABLED RETRY ENABLED DOUBLED/SINGLE RETRY ENABLED (Read Only) FRAME PROGRESS (Read Only) MESSAGE PROGRESS (Read Only) SERVICE REQUEST SUBSYSTEM FLAG RTFLAG (Enhanced Mode Only) USED USED USED USED USED USED
MESSAGE PROGRESS MESSAGE PROGRESS MONITOR ACTIVE (Enhanced mode only,Read Only) (Read Only) (Read Only)
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BU-65170/61580/61585 L-03/06-0
TABLE START/RESET REGISTER (WRITE 03H) 0(LSB) DESCRIPTION RESERVED BC/MT STOP-ON-MESSAGE STOP-ON-FRAME TIME TEST CLOCK TIME RESET INTERRUPT RESET BC/MT START RESET 15(MSB) RESERVED TABLE BC/RT COMMAND STACK POINTER REG. (READ 03H) DESCRIPTION 15(MSB) COMMAND STACK POINTER 0(LSB) COMMAND STACK POINTER TABLE CONTROL WORD REGISTER READ/WRITE 04H, (BU-61580 ONLY) 0(LSB) DESCRIPTION M.E. MASK SERVICE REQUEST MASK SUBSYS BUSY MASK SUBSYS FLAG MASK TERMINAL FLAG MASK RESERVED BITS MASK RETRY ENABLED CHANNEL LINE SELF TEST MASK BROADCAST INTERRUPT ENABLE 1553A/B SELECT MODE CODE FORMAT BROADCAST FORMAT RT-RT FORMAT 0(LSB) 15(MSB) RESERVED 0(LSB) 0(LSB)
TABLE SUBADDRESS CONTROL WORD (READ/WRITE 04H) DESCRIPTION CIRC MEMORY MANAGEMENT (MM2) MEMORY MANAGEMENT (MM1) MEMORY MANAGEMENT (MM0) CIRC MEMORY MANAGEMENT (MM2) MEMORY MANAGEMENT (MM1) MEMORY MANAGEMENT (MM0) BCST: BCST: CIRC BCST:MEMORY MANAGEMENT (MM2) BCST: MEMORY MANAGEMENT (MM1) BCST: MEMORY MANAGEMENT (MM0) TABLE TIME REGISTER (READ/WRITE 05H) DESCRIPTION TIME
15(MSB) DOUBLE BUFFER ENABLE
15(MSB) TIME
TABLE INTERRUPT STATUS REGISTER (READ 06H) DESCRIPTION PARITY ERROR BC/RT TRANSMITTER TIMEOUT BC/RT COMMAND STACK ROLLOVER COMMAND STACK ROLLOVER DATA STACK ROLLOVER FAIL RETRY ADDRESS PARITY ERROR TIME ROLLOVER CIRCULAR BUFFER ROLLOVER
CONTROL WORD/RT SUBADDRESS CONTROL WORD
15(MSB) MASTER INTERRUPT
FRAME FORMAT ERROR STATUS SET/RT MODE CODE/MT PATTERN TRIGGER MESSAGE
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BU-65170/61580/61585 L-03/06-0
TABLE CONFIGURATION REGISTER (READ/WRITE 07H) 0(LSB) DESCRIPTION BC/RT COMMAND STACK SIZE BC/RT COMMAND STACK SIZE COMMAND STACK SIZE COMMAND STACK SIZE DATA STACK SIZE DATA STACK SIZE DATA STACK SIZE ILLEGALIZATION DISABLED OVERRIDE MODE ERROR ALTERNATE STATUS WORD ENABLE ILLEGAL TRANSFER DISABLE BUSY TRANSFER DISABLE RTFAIL-FLAG WRAP ENABLE 1553A MODE CODES ENABLE ENHANCED MODE CODE HANDLING
TABLE CONFIGURATION REGISTER (READ/WRITE 09H) DESCRIPTION
15(MSB) ENHANCED MODE ENABLE
15(MSB) 12MHZ CLOCK SELECT 0(LSB) LOGIC EXTERNAL INHIBIT read only BU-65170/61580X6 EXTERNAL INHIBIT read only BU-65170/61580X6 EXPANDED CROSSING ENABLED RESPONSE TIMEOUT SELECT RESPONSE TIMEOUT SELECT CHECK ENABLED BROADCAST DISABLED ADDRESS LATCH/TRANSPARENT (see NOTE) ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS ADDRESS PARITY
TABLE CONFIGURATION REGISTER (READ/WRITE 08H) DESCRIPTION
Notes TABLE Read only, logic 65170/61580, logic 65171/61581/61586.
15(MSB) EXTERNAL WORD ENABLE 0(LSB) INHIBIT WORD BUSY MODE COMMAND OVERRIDE BUSY EXPANDED CONTROL WORD ENABLE BROADCAST MASK ENABLE/XOR RETRY M.E. RETRY STATUS RETRY ALT/SAME RETRY ALT/SAME VALID M.E./NO DATA VALID BUSY/NO DATA OPTION LATCH ADRRESS WITH CONFIG TEST MODE TEST MODE TEST MODE
TABLE MONITOR DATA STACK ADDRESS REGISTER (READ/WRITE 0AH) DESCRIPTION MONITOR DATA STACK ADDRESS TABLE FRAME TIME REMAINING REGISTER (READ/WRITE 0BH) DESCRIPTION 15(MSB) FRAME TIME REMAINING 0(LSB) FRAME TIME REMAINING 15(MSB) MONITOR DATA STACK ADDRESS
0(LSB)
Note: resolution TABLE MESSAGE TIME REMAINING REGISTER (READ/WRITE 0CH) 0(LSB) DESCRIPTION MESSAGE TIME REMAINING 15(MSB) MESSAGE TIME REMAINING
Note: resolution
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BU-65170/61580/61585 L-03/06-0
TABLE FRAME TIME/RT LAST COMMAND/T TRIGGER REGISTER (READ/WRITE 0DH) DESCRIPTION 15(MSB) 0(LSB) 15(MSB) TABLE STATUS WORD REGISTER (READ/WRITE 0EH) DESCRIPTION 0(LSB)
NOTE: TABLES REGISTERS, THEY WORDS STORED RAM. TABLE MODE BLOCK STATUS WORD DESCRIPTION CHANNEL ERROR FLAG STATUS FORMAT ERROR RESPONSE TIMEOUT LOOP TEST FAIL MASKED STATUS RETRY COUNT RETRY COUNT GOOD DATA BLOCK TRANSFER WRONG STATUS ADDRESS/NO WORD COUNT ERROR INCORRECT SYNC TYPE INVALID WORD TABLE MODE BLOCK STATUS WORD 15(MSB) DESCRIPTION CHANNEL ERROR FLAG RT-RT FORMAT FORMAT ERROR RESPONSE TIMEOUT LOOP TEST FAIL DATA STACK ROLLOVER ILLEGAL COMMAND WORD WORD COUNT ERROR INCORRECT SYNC INVALID WORD RT-RT GAP/SYNC/ADDRESS ERROR RT-RT COMMAND ERROR COMMAND WORD CONTENTS ERROR
15(MSB) LOGIC 0(LSB) LOGIC LOGIC LOGIC LOGIC MESSAGE ERROR INSTRUMENTATION SERVICE REQUEST RESERVED RESERVED RESERVED BROADCAST COMMAND RECEIVED BUSY SUBSYSTEM FLAG DYNAMIC CONTROL ACCEPT TERMINAL FLAG
TABLE WORD REGISTER (READ 0FH) 15(MSB) 0(LSB) DESCRIPTION TRANSMITTER TIMEOUT LOOP TEST FAILURE LOOP TEST FAILURE HANDSHAKE FAILURE TRANSMITTER SHUTDOWN TRANSMITTER SHUTDOWN TERMINAL FLAG INHIBITED CHANNEL HIGH WORD COUNT WORD COUNT INCORRECT SYNC RECEIVED PARITY/MANCHESTER ERROR RECEIVED RT-RT GAP/SYNCH/ADDRESS ERROR RT-RT RESPONSE ERROR RT-RT COMMAND WORD ERROR COMMAND WORD CONTENTS ERROR
0(LSB)
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BU-65170/61580/61585 L-03/06-0
TABLE WORD MONITOR IDENTIFICATION WORD 0(LSB) DESCRIPTION TIME WORD FLAG THIS BROADCAST ERROR COMMAND/DATA CHANNEL CONTIGUOUS DATA/GAP MODE CODE
15(MSB) TIME
program either single frame frame auto-repeat operation. auto-repeat mode, frame repetition rate controlled either internally, using programmable frame timer, from external trigger input. internal frame time programmable 6.55 seconds increments addition frame time, intermessage time, measured from start current message start subsequent message, programmable individual message basis. time between individual successive messages programmable 65.5 increments
TABLE TYPICAL MEMORY ORGANIZATION (SHOWN RAM) ADDRESS (HEX) 0000-00FF 0100 0101 0102 0103 0104 0105 0106 0107 0108-012D 012E-0153 0154-0179 0ED6-0EFB 0EFC-0EFF 0F00-0FFF DESCRIPTION Stack Stack Pointer (fixed location) Message Count (fixed location) Initial Stack Pointer (see note) (Auto-Frame Repeat Mode) Initial Message Count (see note) (Auto-Frame Repeat Mode) Stack Pointer Message Count Initail Stack Pointer (see note) (Auto-Frame Repeat Mode) Initial Message Count (see note) (Auto-Frame Repeat Mode) Message Block Message Block Message Block Message Block Used Stack
TABLE MESSAGE MONITOR MODE BLOCK STATUS WORD DESCRIPTION
15(MSB) CHANNEL ERROR FLAG RT-RT TRANSFER FORMAT ERROR RESPONSE TIMEOUT GOOD DATA BLOCK TRANSFER DATA STACK ROLLOVER RESERVED WORD COUNT ERROR INCORRECT SYNC INVALID WORD RT-RT GAP/SYNC/ADDRESS ERROR RT-RT COMMAND ERROR
CONTROLLER (BC) ARCHITECTURE
protocol BU-61580 implements MIL-STD1553B message formats. Message format programmable message-by-message basis means bits Control Word Command Word respective message. Control Word allows 1553 message format, 1553A/B type channel, self-test, Status Word masking specified individual message basis. addition, automatic retries and/or interrupt requests enabled disabled individual messages. performs error checking required MIL-STD-1553B. This includes validation response time, sync type sync encoding, Manchester encoding, parity, count, word count, Status Word Address field, various RT-to-RT transfer errors. BU-61580's response timeout value programmable with choices longer response timeout values enable operation over long buses and/or repeaters. FIGURE illustrates intermessage frame timing. BU-61580 programmed process frames messages with processor intervention. possible Data Device Corporation www.ddc-web.com
Note: Used only Enhanced mode with Frame Auto-Repeat enabled.
MEMORY ORGANIZATION
TABLE illustrates typical memory mode. important note that only fixed locations BU-61580 Standard mode Stack Pointers (address locations 0100 (hex) 0104) Message Count locations (0101 0105). Enabling Frame Auto-Repeat mode will reserve four more memory locations Enhanced mode; these locations Initial Stack Pointers (address locations (hex) 106) Initial Message Count locations (103 107). user free locate Stack Message Blocks anywhere else within internal) shared address space. simplicity illustration, assume allocation maximum length message each message block typBU-65170/61580/61585 L-03/06-0
ical memory TABLE maximum size message block words, RT-to-RT transfer Data Words (Control Commands Loopback Status Words Data Words). Note, however, that this example assumes disabling 256-word boundaries.
MEMORY MANAGEMENT
FIGURE illustrates BU-61580's memory management scheme. memory management features global double buffering mechanism. This provides sets various mode data structures: Stack Pointer Message Counter locations, Descriptor Stack areas, message blocks. Configuration Register selects current active area. point time, BU-61580's internal 1553 memory management logic access only various data structures within "active" area. FIGURE delineates "active" "inactive" areas nonshaded shaded areas, respectively; however, point time, both "active" "nonactive" areas accessible host processor. most applications, host processor will access "nonactive" area, while 1553 processes "active" area messages. programmed transmit multimessage frames messages. number messages processed programmable Active Area Message Count location shared RAM, initialized host processor. addition, host processor must initialize another location, Active Area Stack Pointer. Stack Pointer references four-word message block descriptor Stack area shared each message processed. Stack size programmable with choices 256, 512, 1024, 2048 words. Frame Auto-Repeat mode, Initial Stack Pointer Initial Message Counter locations must loaded host prior processing first frame. single frame mode does these locations. third fourth words block descriptor Intermessage Time Message Block Address respective message. These memory locations must written host processor prior start message processing. Intermessage Time optional. Block Address pointer specifies starting location each message block. first word each message block Control Word. start each message, Block Status Time Words write message block descriptor stack.
Block Status Word includes indications message process message completion, channel, status set, response timeout, retry count, status address mismatch, loop test (on-line self-test) failure, other error conditions. TABLE illustrates mapping Block Status word. 16-bit Time Word will reflect current contents internal Time Register. This read/writable register, which operates three modes, programmable resolution from µs/LSB. addition, Time register clocked from external source.
MESSAGE BLOCK FORMATS CONTROL WORD
mode, BU-61580 supports MIL-STD-1553 message formats. each 1553 message format, BU-61580 mandates specific sequence words within Message Block. This includes locations Control, Command (transmitted) Data Words that read from protocol logic. addition, subsequent contiguous locations must allocated storage received Loopback, Status Data Words. FIGURE illustrates organization message blocks various MIL-STD-1553 message formats. Note that message formats, Control Word located first location message block. each Message Block formats, first word block Control Word. Control Word transmitted 1553 bus. Instead, contains bits that select active message format; enable off-line self-test; masking Status Word bits; enable retries interrupts; specifies MIL-STD-1553A -1553B error handling. mapping definitions Control Word illustrated TABLE Control Word followed Command Word transmitted, subsequently second Command Word (for RT-to-RT transfer), followed Data Words transmitted (for Receive commands). location after last word transmitted reserved Loopback Word. Loopback Word on-line self-test feature. subsequent locations after Loopback Word reserved received Status Words Data Words (for Transmit commands).
MESSAGE TIME MESSAGE INTERMESSAGE TIME
MESSAGE
MESSAGE
MESSAGE
FRAME TIME
FIGURE MESSAGE FRAME TIMING
Data Device Corporation www.ddc-web.com BU-65170/61580/61585 L-03/06-0
INITIAL STACK POINTERS (NOTE) MESSAGE BLOCKS
CONFIGURATION REGISTER
STACK POINTERS
DESCRIPTOR STACKS
CURRENT AREA INITIAL MESSAGE COUNTERS (NOTE)
BLOCK STATUS WORD TIME WORD MESSAGE TIME WORD MESSAGE BLOCK ADDR MESSAGE BLOCK
MESSAGE COUNTERS
MESSAGE BLOCK
NOTE: INITIAL STACK POINTERS INITIAL MESSAGE COUNTERS USED ONLY FRAME AUTO-REPEAT MODE.
FIGURE MODE MEMORY MANAGEMENT
AUTOMATIC RETRIES
BU-61580 implements automatic message retries. When enabled, retries will occur, following response timeout format error conditions. additional options, retries enabled when Message Error Status Word 1553A following "Status Set" condition. failed message, either message retries will occur, channel (same alternate) independently programmable first second retry attempts. Retries enabled disabled individual message basis. codes. This design based largely previous generation products that have passed SEAFAC testing MIL-STD-1553B compliance. performs comprehensive error checking, word format validation, checks various RT-to-RT transfer errors. Other features BU-65170/61580 include interrupt conditions, internal command illegalization, programmable busy subaddress.
MEMORY ORGANIZATION
TABLE illustrates typical memory BU-61580 mode. mode, Stack Pointers reside fixed locations shared address space: address 0100 (hex) Area Stack Pointer address 0104 Area Stack Pointer. Besides Stack Pointer, mode there several other areas address space designated fixed locations. modes operation require Area Area Lookup Tables. Also allocated several fixed locations optional features: Command Illegalization Lookup Table, Mode Code Selective Interrupt Table, Mode Code Data Table, Busy Lookup Table. should noted that unenabled optional fixed locations used general purpose storage (data blocks). Lookup tables, which provide mechanism mapping data blocks individual Tx/Rx/Bcst-subaddresses areas RAM, occupy address range locations 0140 01BF Area 01C0 023F Area lookup tables include Subaddress Control Words individual Data Block Pointers. used, address range 0300-03FF will dedicated illegalizing section RAM. actual Stack area individual data blocks located nonfixed areas shared address space.
INTERRUPTS
interrupts enabled Interrupt Mask Register Stack Rollover, Retry, End-of-Message (global), End-ofMessage conjunction with Control Word individual messages), response timeout, message error, frame, Status conditions. definition "Status Set" programmable individual message basis, means Control Word. This allows masking ("care/don't care") individual Status Word bits.
REMOTE TERMINAL (RT) ARCHITECTURE
protocol design BU-65170/61580 represents DDC's fifth generation implementation 1553 salient features ACE's architecture true multiprotocol functionality. This includes programmable options support MIL-STD-1553A, various McAir protocols, MILSTD-1553B Notice BU-65170/61580 response time dead time 1553B), providing compliance 1553 protocols. Additional multiprotocol features BU-65170/61580 include options full software control Status Built-in-Test (BIT) words. Alternatively, 1553B applications, these words formulated real time BU-65170/61580 protocol logic. BU-65170/61580 protocol design implements MIL-STD-1553B message formats dual redundant mode Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
BC-to-RT Transfer Control Word Receive Command Word Data Word Data Word Last Data Word Last Data Word Looped Back Status Received RT-to-RT Transfer Control Word Receive Command Transmit Command Transmit Command Looped Back Status Word Data Data Last Data Status Word Mode Code; With Data Control Word Mode Command Data Word Data Word Looped Back Status Received Broadcast Control Word Broadcast Command Data Data Last Data Last Data Status Word Mode Code; Data Control Word Mode Command Mode Command Looped Back Status Received
RT-to-BC Transfer Control Word Transmit Command Word Transmit Command Looped Back Status Received Data Word Data Word Last Data Word Mode Code; With Data Control Word Mode Command Mode Command Looped Back Status Received Data Word
data received from broadcast messages from nonbroadcast received data. Besides supporting global double buffering scheme mode), provides pair 128-word Lookup Tables memory management control. They programmable subaddress basis (refer TABLE 27). These 128-word tables include 32-word tables transmit message pointers receive message pointers. There also third, optional Lookup Table broadcast message pointers, providing Notice compliance, necessary. fourth section each Lookup Tables stores Subaddress Control Words (refer TABLE 28). individual Subaddress Control Words used select memory management option interrupt scheme each transmit, receive, (optionally) broadcast subaddress. each transmit subaddress, there possible memory management schemes: single message; circular buffer. each receive (and optionally broadcast) subaddress, there three possible memory management schemes: single message; double buffered; circular buffer. each transmit, receive broadcast subaddress, there interrupt conditions that programmable respective Subaddress Control Word: after every message subaddress; after circular buffer rollover. additional table used enable interrupts following selected mode code messages. When using circular buffer scheme given subaddress, size circular buffer programmable three bits Subaddress Control Word (see TABLE 28). options circular buffer size 128, 256, 512, 1024, 2048, 4096, 8192 Data Words.
RT-to-RTs (Broadcast) Transfer Control Word Broadcast Command Command Command Looped Back Status Word Data Data Last Data
SINGLE MESSAGE MODE
FIGURE illustrates Single Message memory management scheme. When operating BU-65170/61580 "AIMHY" (default) mode, Single Message scheme implemented transmit, receive, broadcast subaddresses. Single Message mode (also Double Buffer Circular Buffer modes), there global double buffering scheme, controlled Configuration Register This selects from between sets various data structures shown figure: Stack Pointers (fixed addresses), Descriptor Stacks (user defined addresses), Lookup Tables (fixed addresses), Data Word blocks (user defined addresses). FIGURES delineate "active" "nonactive" areas nonshaded shaded areas, respectively. shown, stores Command Word from each message received, fourth location within message descriptor stack) respective message. bit, subaddress field, (optionally) broadcast/own address, index into active area Lookup Table, locate data block pointer current message. BU-65170/61580 memory management logic then accesses data block pointer locate starting address Data Word block current message. maximum size Data Word block words.
Broadcast Mode Code; Data Control Word Broadcast Mode Command Broadcast Mode Command Looped Back
Broadcast Mode Code; With Data Control Word Broadcast Mode Command Data Word Data Word Looped Back
FIGURE MESSAGE BLOCK FORMATS
MEMORY MANAGEMENT
salient features series products flexibility memory management architecture. architecture allows memory management scheme each transmit, receive, broadcast subaddress programmable subaddress basis. Also, compliance with MIL-STD-1553B Notice BU-65170/61580 provides option separate Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
particular subaddress Single Message mode, there overwriting contents data blocks receive/broadcast subaddresses overreading, transmit subaddresses. single message mode, possible access multiple data blocks same subaddress. This, however, requires intervention host processor update respective Lookup Table pointer. implement data wraparound subaddress, required Notice MIL-STD-1553B, Single Message scheme should used wraparound subaddress. Notice recommends subaddress wraparound subaddress.
TABLE LOOK-UP TABLES AREA 0140 015F 0160 017F 0180 019F 01A0 01BF AREA 01C0 01DF 01E0 01FF 0200 021F 0220 023F DESCRIPTION Rx(/Bcst)_SA0 Rx(/Bcst)_SA31 Tx_SA0 Tx_SA31 Bcst_SA0 Bcst_SA31 SACW_SA0 SACW_SA31 COMMENT Receive (/Broadcast) Lookup Table
Transmit Lookup Table
TABLE TYPICAL MEMORY (SHOWN RAM) ADDRESS (HEX) 0000-00FF 0100 0101-0103 0104 0105-0107 0108-010F 0110-013F 0140-01BF 01C0-023F 0240-0247 0248-025F 0260-027F 0280-02FF 0300-03FF 0400-041F 0420-043F 0FE0-0FFF DESCRIPTION Stack Stack Pointer (fixed location) RESERVED Stack Pointer (fixed location) RESERVED Mode Code Selective Interrupt Table (fixed area) Mode Code Data (fixed area) Lookup Table (fixed area) Lookup Table (fixed area) Busy Lookup Table (fixed area) (not used) Data Block Data Block Command Illegalizing Table (fixed area) Data Block Data Block Data Block
Broadcast Lookup Table Optional
Subaddress Control Word Lookup Table (Optional)
TABLE SUBADDRESS CONTROL WORD Memory Management Subaddress Buffer Scheme DESCRIPTION 128-Word 256-Word 512-Word 1024-Word 2048-Word 4096-Word 8192-Word COMMENT Circular Buffer Specified Size
Single Message Double Buffered
CIRCULAR BUFFER MODE
FIGURE illustrates circular buffer memory management scheme. circular buffer mode facilitates bulk data transfers. size circular buffer, shown right side figure, programmable from 8192 words even powers respective Subaddress Control Word. single message mode, host processor initially loads individual Lookup Table entries. start each message, stores Lookup Table entry third position respective message block descriptor stack area RAM, Single Message mode. transfers Receive Transmit Data Words (from) circular buffer, starting location referenced Lookup Table pointer. valid optionally invalid) message, value Lookup Table entry updates next location after last address accessed current message. result, Data Words next message directed same Tx/RX(/Bcst) subaddress will accessed from next contiguous block address locations within circular buffer. recommended Data Device Corporation www.ddc-web.com
option, Lookup Table pointers programmed update following invalid receive broadcast) message. This allows 1553 controller retry failed message, resulting valid (retried) data overwriting invalid data. This eliminates overhead RT's host processor. When pointer reaches lower boundary circular buffer (located 128, 256, 8192-word boundaries BU-65170/61580 address space), pointer moves boundary circular buffer, FIGURE shows. Implementing Bulk Data Transfers Circular Buffer scheme ideal bulk data transfers; that multiple messages to/from same subaddress. recommendation such applications enable circular buffer interrupt request. doing, routine transfer multiple messages selected subaddress, including errors retries, transparent RT's host processor. strategically initializing subaddresses' Lookup Table pointer prior start bulk transfer, BU-65170/61580 configured issue interrupt request only after received anticipated number valid Data Words designated subaddress.
BU-65170/61580/61585 L-03/06-0
SUBADDRESS DOUBLE BUFFERING MODE receive (and broadcast) subaddresses, BU-65170/61580 offers third memory management option, Subaddress Double Buffering. Subaddress Double Buffering provides means ensuring data consistency. FIGURE illustrates Subaddress Double Buffering scheme. Like Single Message Circular Buffer modes, Double Buffering mode selected subaddress basis means Subaddress Control Word. purpose Double Buffering mode provide host processor convenient means accessing most recent, valid data received given subaddress. This serves ensure highest possible degree data consistency allocating 32-bit Data Word blocks each individual receive (and/or broadcast) subaddress.
given point time, blocks will designated "active" 1553 data block while other will designat-
"inactive" block. Data Words from next receive message that subaddress will stored "active" block. Upon completion message, provided that message valid Subaddress Double Buffering enabled, BU65170/61580 will automatically switch "active" "inactive" blocks respective subaddress. accomplishes this toggling subaddress's Lookup Table Pointer rewriting pointer. result, most recent valid block received Data Words will always readily accessible host processor. means ensuring data consistency, host processor able reliably access most recent valid, received Data Word block performing following sequence:
INITIAL STACK POINTERS (NOTE) MESSAGE BLOCKS
CONFIGURATION REGISTER
STACK POINTERS
DESCRIPTOR STACKS
CURRENT AREA INITIAL MESSAGE COUNTERS (NOTE)
BLOCK STATUS WORD TIME WORD MESSAGE TIME WORD MESSAGE BLOCK ADDR MESSAGE BLOCK
MESSAGE COUNTERS
MESSAGE BLOCK
NOTE: INITIAL STACK POINTERS INITIAL MESSAGE COUNTERS USED ONLY FRAME AUTO-REPEAT MODE.
FIGURE MEMORY MANAGEMENT: SINGLE MESSAGE MODE
CONFIGURATION REGISTER STACK POINTERS DESCRIPTOR STACK CIRCULAR DATA BUFFER
LOOK-UP TABLES
CURRENT AREA BLOCK STATUS WORD TIME WORD DATA BLOCK POINTER RECEIVED COMMAND WORD LOOK-UP TABLE ADDRESS POINTER CURRENT DATA BLOCK LOOK-UP TABLE ENTRY POINTER NEXT DATA BLOCK RECEIVED (TRANSMITTED) MESSAGE DATA (NEXT LOCATION)
128,
8192 WORDS
TX/RS/BCST_SA LOOK-UP TABLE ENTRY UPDATED
FOLLOWING VALID RECEIVE (BROADCAST) MESSAGE FOLLOWING COMPLETION TRANSIT MESSAGE.
CIRCULAR BUFFER ROLLOVER
FIGURE MEMORY MANAGEMENT: CIRCULAR BUFFER MODE
Data Device Corporation www.ddc-web.com BU-65170/61580/61585 L-03/06-0
CONFIGURATION REGISTER
STACK POINTERS
DESCRIPTOR STACK
LOOK-UP TABLES
DATA BLOCKS
CURRENT AREA BLOCK STATUS WORD YYYYY TIME WORD DATA BLOCK POINTER RECEIVED COMMAND WORD DATA BLOCK POINTER YYYYY DATA BLOCK DATA BLOCK
RECEIVE DOUBLE BUFFER ENABLE SUBADDRESS CONTROL WORD
FIGURE MEMORY MANAGEMENT: SUBADDRESS DOUBLE BUFFERING MODE
Disable double buffering respective subaddress Subaddress Control Word. That temporarily switch subaddress' memory management scheme Single Message mode. Read current value receive broadcast) subaddress's Lookup Table pointer. This points current "active" Data Word block. inverting this pointer value, possible locate start "inactive" Data Word block. This block will contain Data Words received during most recent valid message subaddress. Read words from "inactive" (most recent) Data Word Block. Re-enable Double Buffering mode respective subaddress Subaddress Control Word. resolution Time Register programmable from among µs/LSB. Also, incrementing Time counter from external clock source software command. stores contents accessed Lookup Table location current message, indicating starting location Data Word block, Data Block Pointer. This serves convenience locating stored message data blocks. stores full 16-bit 1553 Command Word fourth location message descriptor.
INTERRUPTS mode, BU-65170/61580 provides many maskable interrupts. interrupt conditions include (every) Message, Message Error, Selected Subaddress (Subaddress Control Word) Interrupt, Circular Buffer Rollover, Selected Mode Code Interrupt, Stack Rollover. DESCRIPTOR STACK beginning each message, BU65170/61580 stores four-word message descriptor active area stack. stack size programmable, with choices 256, 512, 1024, 2048 words. FIGURES show four words: Block Status Word, Time Word, Data Block Pointer, 1553 received Command Word. Block Status Word includes indications message in-progress message complete, channel, RT-to-RT transfer RT-toRT transfer errors, message format error, loop test (self-test) failure, circular buffer rollover, illegal command, other error conditions. TABLE shows mapping Block Status Word.
mode, Time Word stores current contents BU-65170/61580's read/writable Time Register. Data Device Corporation www.ddc-web.com
COMMAND ILLEGALIZATION BU-65170/61580 provides internal mechanism command illegalization. addition, Busy Status Word that only programmed subset transmit/receive/broadcast subaddresses.
illegalization scheme uses 256-word area BU65170/61580's address space. benefit this feature reduction printed circuit board requirements, eliminating need external PROM, PLD, device that does illegalizing function. BU-J1165170/61580's illegalization scheme provides maximum flexibility, allowing subset 4096 possible combinations broadcast/own address, bit, subaddress, word count/mode code illegalized. Another advantage RAM-based illegalization technique that provides high degree self-testability.
Addressing Illegalization Table TABLE illustrates addressing scheme illegalization RAM. shown, base address illegalizing 0300 (hex). formulates index into Illegalizing Table based values BROADCAST/OWN ADDRESS, bit, Subaddress, Word Count/Mode Code field (WC/MC4) current Command Word.
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internal words reserved command illegalization. Broadcast commands illegalized separately from nonbroadcast receive commands mode commands. Commands illegalized down word count level. example, one-word receive command subaddress legal, while two-word receive command subaddress illegalized. first words Illegalization Table refer broadcast receive commands (two words subaddress). next words refer broadcast transmit commands. Since nonmode code broadcast transmit commands definition invalid, this section table (except subaddresses does need initialized user. next words correspond nonbroadcast receive commands. final words refer nonbroadcast transmit commands. Messages with Word Count/ Mode Code (WC/MC) fields between illegalized setting corresponding data bits respective evennumbered address locations illegalization table. Likewise, messages with WC/MC fields between illegalized setting corresponding data bits respective odd-numbered address locations illegalization table. following should noted with regards command illegalization: illegalize particular word count given broadcast/own address-T/R subaddress, appropriate position respective illegalization word should logic value logic designates respective Command Word legal command. will respond illegalized nonbroadcast command with Message Error Status Word. subaddresses 00001 through 11110, "WC/MC" field specifies Word Count field respective Command Word. subaddresses 00000 11111, "WC/MC" field specifies Mode Code field respective Command Word. Since nonmode code broadcast transmit messages defined MIL-STD-1553B, sixty (60) words illegalization RAM, addresses 0342 through 037D, corresponding these commands need initialized. will respond nonmode code broadcast transmit command, will automatically Message Error internal Status Register, regardless whether corresponding illegalization been set. next message Transmit Status Transmit Last Command mode code, will respond with Message Error set.
TABLE ILLEGALIZATION ADDRESS DEFINITION 0(LSB) DESCRIPTION BROADCAST/OWN_ADDRESS WC4/MC4
15(MSB)
PROGRAMMABLE BUSY means providing compliance with Notice MIL-STD1553B, BU-65170/61580 provides software controllable means setting Busy Status Word function subaddress. Busy Lookup Table BU-65170/61580 address space, possible Busy based command broadcast/own address, bit, subaddress. Another programmable option, allows received Data Words either stored stored messages, when Busy set. OTHER FUNCTIONS BU-65170/61580 allows hardwired Address read host processor. Also, there options FLAG Status Word under software control and/or automatically following failure loopback self-test. Other software controllable options include software programmable Status words, automatic clearing Service Request Status Word following Transmit Vector Word mode command, capabilities clear and/or load Time Register following receipt Synchronize mode commands, options regarding Data Word transfers Busy and/or Message Error (Illegal) Status Word bits, handling 1553A reserved mode codes.
MONITOR (MT) ARCHITECTURE
BU-61580 provides three monitor (MT) modes: "AIM-HY" (default) "AIM-HY'er" Word Monitor mode. Selective Message Monitor mode. Simultaneous Remote Terminal/Selective Message Monitor mode.
Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
strong recommendation applications Selective Message Monitor, rather than Word Monitor. Besides providing monitor filtering based Address, bit, Subaddress, Message Monitor eliminates need determine start messages software. development such software tends tedious task. Moreover, time, tends entail high degree overhead.
various stacks have fixed locations BU-61580 address space.
WORD MONITOR Word Monitor mode, BU-61580 monitors both 1553 buses. After initializing Word Monitor putting on-line BU-61580 stores Command, Status, Data Words received from both buses. each word received from either bus, BU-61580 stores pair words RAM. first word bits data from received word. second word Monitor Identification (ID), "Tag" word. Word contains information relating channel, sync type, word validity, interword time gaps. BU-61580 stores data words circular buffer shared address space. TABLE shows mapping Monitor word. MONITOR TRIGGER WORD There Trigger Word Register that provides additional flexibility Word Monitor mode. BU-61580 stores value 16-bit Trigger Word Trigger Word Register. contents this register represent value Trigger Command Word. BU-61580 programmable options start stop Word Monitor, and/or issue interrupt request following receipt Trigger Command Word from 1553 bus. SELECTIVE MESSAGE MONITOR MODE BU-61580 Selective Message Monitor provides features greatly reduce software processing burden host CPU. Selective Message Monitor implements selective monitoring messages from dual 1553 bus, with monitor filtering based Address, bit, Subaddress fields received 1553 Command Words. Selective Message Monitor mode greatly simplifies host processor software distinguishing between Command Status Words. Selective Message Monitor maintains stacks BU61580 RAM: Command Stack Data Stack. Simultaneous RT/Message Monitor Mode Selective Message Monitor function purely passive monitor programmed function simultaneous RT/Monitor. RT/Monitor mode provides complete Remote Terminal (RT) operation BU-61580's strapped address monitor capability other nonbroadcast addresses. This allows BU-61580 simultaneously operate full function "snoop" subset activity involving other bus. This type operation sometimes needed implement backup controller. combined RT/Selective Monitor maintains three stack areas BU-61580 address space: Command Stack, Monitor Command Stack, Monitor Data Stack. pointers
Data Device Corporation www.ddc-web.com
Selective Message Monitor Memory Organization TABLE illustrates typical memory Selective Message Monitor mode. This mode operation defines several fixed locations RAM. These locations allocate manner that compatible with combined RT/Selective Message Monitor mode. Refer TABLE example typical Selective Message Monitor Memory Map. fixed memory consists Monitor Command Stack Pointers (location 102h 106h), Monitor Data Stack Pointers (locations 103h 107h), Selective Message Monitor Lookup Table (0280-02FFh) based Address, T/R, subaddress. Assume Monitor Command Stack size words, Monitor Data Stack size words.
Refer FIGURE illustration Selective Message Monitor operation. Upon receipt valid Command Word, BU-61580 will reference Selective Monitor Lookup Table fixed block addresses) check condition (disabled/enabled) current command. disabled, BU61580 will ignore (and store) current message; enabled, BU-61580 will create entry Monitor Command Stack address location referenced Monitor Command Stack Pointer. Similar mode, stores Block Status Word, 16-bit Time Word, Data Block Pointer Message Descriptor, along with received 1553 Command Word following reception Command Word. writes Block Status Time Words both start message. Monitor Block Status Word contains indications message in-progress message complete, channel, Monitor Data Stack Rollover, RT-to-RT transfer RT-to-RT transfer errors, message format error, other error conditions. TABLE shows Message Monitor Block Status Word. Data Block Pointer references first word stored Monitor Data Stack (the first word following Command Word) current message. BU-61580 will then proceed store subsequent words from message (possible second Command Word, Data Word(s), Status Word(s)) into consecutive locations Monitor Data Stack. size Monitor Command Stack programmable 256, words. Monitor Data Stack size programmable 512, 16K, 32K, words. Monitor interrupts enabled Monitor Command Stack Rollover, Monitor Data Stack Rollover, and/or End-of-Message conditions. addition, Word Monitor mode there interrupt enabled Monitor Trigger condition.
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TABLE TYPICAL SELECTIVE MESSAGE MONITOR MEMORY (SHOWN RAM) ADDRESS (HEX) 0000-0101 0102 0103 0104-0105 0106 0107 0108-027F 0280-02FF 0300-03FF 0400-07FF 0800-0FFF DESCRIPTION Used Monitor Command Stack Pointer (fixed location) Monitor Data Stack Pointer (fixed location) Used Monitor Command Stack Pointer (fixed location) Monitor Data Stack Pointer (fixed location) Used Selective Monitor Lookup Table (fixed area) Used Monitor Command Stack Monitor Data Stack
BU-65170 BU-61580 host processor bus. various possible configurations serve reduce absolute minimum amount glue logic required interface 16-, 32bit processor buses. Also included features facilitate interfacing processors that have "wait state" type handshake acknowledgement. Finally, supports reliable interface external dual port RAM. This type interface minimizes portion available processor bandwidth required access 1553 RAM. 16-bit buffered mode (FIGURE most common configuration used. provides direct, shared interface 16-bit 32-bit microprocessor. this mode, ACE's internal address data buffers provide necessary isolation between host processor's address data buses corresponding internal memory buses. buffered mode, 1553 shared address space limit BU-65170/61580's words internal RAM. 16-bit buffered mode provides pair pin-programmable options:
PROCESSOR MEMORY INTERFACE
terminals provide much flexibility interfacing host processor optional external memory. FIGURE shows that there control signals, which dual purpose, processor/memory interface. FIGURES through illustrate configurations that used interfacing
CONFIGURATION REGISTER
MONITOR COMMAND STACK POINTERS
MONITOR COMMAND STACKS
MONITOR DATA STACKS
CURRENT AREA
BLOCK STATUS WORD TIME WORD
CURRENT COMMAND WORD MONITOR DATA BLOCK MONITOR DATA BLOCK
DATA BLOCK POINTER RECEIVED COMMAND WORD
NOTE
THIS (NOT SELECTED) WORDS STORED EITHER COMMAND STACK DATA STACK. ADDITION, COMMAND DATA STACK POINTERS WILL UPDATED.
MONITOR DATA STACK POINTERS
SELECTIVE MONITOR LOOKUP TABLES OFFSET BASED RTA4-RTA0, T/R, SELECTIVE MONITOR ENABLE (SEE NOTE)
FIGURE SELECTIVE MESSAGE MONITOR MEMORY MANAGEMENT
Data Device Corporation www.ddc-web.com BU-65170/61580/61585 L-03/06-0
logic sense RD/WR control input selectable POLARITY_SEL input: example, write when RD/WR Motorola 680X0 processors; write when RD/WR high Intel i960 series microprocessors. strapping input signal ZERO_WAIT logic "1," terminals interface processors that have acknowedge type handshake input accommodate hardware controlled wait states; most current processor chips have such input. this case, BU-65170/61580 will assert READYD output only after latched WRITE data internally presented READ data D15D0. strapping ZERO_WAIT logic "0," possible easily interface BU-65170/61580 processors that have acknowledge type handshake input. example such processor Analog Device's ADSP2101 chip. this configuration, processor clear strobe output before completion access BU-65170/61580 internal register. this case, READYD will high following rising edge STRBD will stay high until completion transfer. READYD will normally when ZERO_WAIT low. Similar 16-bit buffered mode, 16-bit transparent mode (FIGURE supports shared interface host CPU. transparent mode offers advantage allowing buffer size expanded words, using external RAM. disadvantage transparent mode that requires external address data buffers isolate processor buses from memory/BU-65170/61580 buses. modified version transparent mode involves dual port RAM, rather than conventional static RAM. Refer FIGURE This allows host access very quickly, only limitation being access time dual port RAM. This configuration eliminates BU-65170/61580 arbitration delays memory accesses. worst case delay time occurs only during simultaneous access host BU65170/61580 1553 logic same memory address. general, this will occur very rarely limits delay approximately FIGURE illustrates connections 16-bit Direct Memory Access (DMA) mode. this configuration host processor, rather than terminal, arbitrates address data buses. arbitration involves output signals Request (DTREQ) Acknowledge (DTACK), input signal Grant (DTGRT). interface allows components interface large amounts system while eliminating need external buffers. system address spaces larger than words, necessary host processor provide page register upper address bits (above A15) when BU-65170/61580 accesses (while asserting DTACK low). internal accessible through standard interface (SELECT, STRBD, READYD, etc). host Data Device Corporation www.ddc-web.com
access external ACE's arbitration logic output control signals, illustrated FIGURE Alternatively, control shared both host processor ACE, illustrated FIGURE latter requires external logic, allows processor access directly full access speed RAM, rather than waiting handshake acknowledge output (READYD). FIGURE illustrates 8-bit buffered mode. This interface allows direct connection 8-bit microprocessors 8-bit microcontrollers. 16-bit buffered configuration, buffer limit BU-65170/61580's words internal RAM. 8-bit mode, host accesses BU65170/61580's internal registers pair 8-bit registers embedded interface. 8-bit interface further configured three strappable inputs: ZERO_WAIT, POLARITY_SEL, TRIGGER_SEL. connecting ZERO_WAIT logic "0," BU-65170/61580 interfaced with minimal "glue" logic 8-bit microcontrollers, such Intel 8051 series, that have Acknowledge type handshake input. programmable inputs POLARITY_SEL TRIGGER_SEL allow BU-65170/61580 accommodate different byte ordering conventions "A0" logic sense utilized different 8-bit processor families.
PROCESSOR INTERFACE TIMING FIGURES illustrate timing host processor access ACE's internal registers 16-bit, buffered, non-zero, wait-mode. FIGURE illustrates 16-bit buffered, nonzero wait mode read cycle timing while FIGURE shows 16-bit, buffered, nonzero wait mode write cycle timing.
During transfer cycle, signals STRBD SELECT must sampled rising edge system clock request access BU-65170/61580's internal shared RAM. transfer will begin first rising system clock edge when (SELECT STRBD) 1553 protocol/memory management unit accessing internal RAM. falling edge output signal IOEN indicates start transfer. latches signals MEM/REG RD/WR internally first falling clock edge after start transfer cycle. address inputs latch internally first rising clock edge after signal IOEN goes low. Note that address lines latched time using ADDR_LAT input signal.
BU-65170/61580/61585 L-03/06-0
output signal READYD will asserted third rising system clock edge after IOEN goes low. assertion READYD indicates host processor that read data available parallel data bus, that write data been stored. this time, should bring signal STRBD high, completing transfer cycle.
register test, protocol test, test fail-safe (transmitter timeout) timer. There also test mode. test mode, host processor emulate arbitrary activity 1553 buses writing pair test registers. test mode operated conjunction with Word Monitor mode facilitate end-to-end selftests.
Address Latch Timing FIGURE illustrates operation timing address input latches buffered interface mode. transparent mode, address buffers always transparent. Since transparent mode requires external buffers, external address latches would required demultiplex multiplexed address bus. buffered mode, however, ACE's internal address latches used perform demultiplexing function.
ADDR_LAT input signal controls address latch operation. When ADDR_LAT high, outputs latch (which drive ACE's internal memory bus) track state address inputs A00. When low, internal memory remains latched state just prior falling edge ADDR_LAT.
PARITY GENERATION CHECKING architecture monolithic such that amount buffered extended beyond words on-chip RAM. this off-chip buffered RAM, chip includes provisions implement parity generation checking. Parity generation checking provides mechanism checking data integrity internal, buffered memory. Furthermore, 17bit, rather than 16-bit, wide buffered would used. this RAM, chip will generate 17th (parity bit) (host 1553) write accesses check parity read accesses. parity error occurs, interrupt request issued, corresponding Interrupt Status Register would set. BU-61585 incorporates additional chip.
MISCELLANEOUS
SELF-TEST
BU-65170/61580 products incorporate several self-test features. These features include on-line wraparound self-test messages modes, off-line wraparound selftest mode, several other internal self-test features. BC/RT on-line loop test involves wraparound test encoder/decoder transceiver. off-line self-test involves encoder/decoder, transceiver. These tests entail checking received version every transmitted word validity (sync, encoding, count, parity) checking received version last transmitted word bit-by-bit comparison with encoded word. loopback test also fails there timeout internal transmitter watchdog timer. Note that timeout value watchdog timer depends mode operation selected (1553A 1553B). failure loop test results setting message's Block Status Word and, enabled, will result interrupt request. With appropriate host processor software, off-line test able exercise parallel serial data paths, encoder, decoder, substantial portion protocol memory management logic. There additional built-in self-test features, that involve three configuration register bits eight test registers. This allows test approximately chip's internal logic. These tests include encoder test, decoder test,
Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
+15V CLOCK OSCILLATOR
D15-D0 TX/RXA A15-A12 A11-A0 TX/RXA
ADDRESS LATCH (NOTE ADDR_LAT
TRANSPARENT/BUFFERED 16/8_BIT TRIGGER_SEL
(NOTE
TX/RXB
MSB/LSB POLARITY_SEL
HOST
(NOTE
ZERO_WAIT
TX/RXB
SELECT ADDRESS DECODER MEM/REG
RD/WR STROBE ACKNOWLEDGE
(NOTE
RD/WR STRBD READYD TAG_CLK RTAD4-RTAD0 RTADP ADDRESS, PARITY
RESET
MSTCLR
SSFLAG/EXT_TRIG
INTERRUPT REQUEST
NOTES:
ADDRESS LATCH SIGNAL PROVIDED PROCESSORS WITH MULTIPLEXED ADDRESS/DATA BUSES. POLARITY_SEL "1", RD/WR HIGH READ, WRITE. POLARITY_SEL "0", RD/WR READ, HIGH WRITE. ZERO_WAIT SHOULD STRAPPED LOGIC NON-ZERO WAIT INTERFACE LOGIC ZERO WAIT INTERFACE. ACKNOWLEDGE PROCESSOR INPUT ONLY NON-ZERO WAIT TYPE INTERFACE.
FIGURE 16-BIT BUFFERED MODE
Data Device Corporation www.ddc-web.com BU-65170/61580/61585 L-03/06-0
+15V CLOCK OSCILLATOR
D15-D0
'245
D15-D0 TX/RXA TX/RXA IOEN DTREQ DTGRT MEMWR MEMOE
A15-A0 '244 ADDRESS DECODER A15-A0 TX/RXB MEMENA-IN
HOST
MEMENA-OUT TRANSPARENT/BUFFERED
TX/RXB
SELECT ADDRESS DECODER MEM/REG
RD/WR STROBE ACKNOWLEDGE STRBD READYD TAG_CLK RESET MSTCLR RTAD4-RTAD0 RTADP ADDRESS, PARITY
SSFLAG/EXT_TRIG
INTERRUPT REQUEST
FIGURE 16-BIT TRANSPARENT MODE
Data Device Corporation www.ddc-web.com BU-65170/61580/61585 L-03/06-0
CS-L
CS-R
MEMENA-OUT
WR-L DUAL PORT
WR-R
MEMWR
OE-L BUSY-L
OE-R BUSY-R
MEMOE
D15-D0
D15-D0
ADDRESS
A15-A0
RD/WR
RD/WR
MEMENA-IN MEM/REG
HOST
1553 SELECT ADDRESS DECODER 1553 SELECT A4-A0
'245
IOEN
A4-A0 '244
DTREQ DTGRT
DTACK SELECT
DATA STROBE
STRBD
TRANSPARENT/BUFFERED READY READYD RESET MSTCLR
INTERRUPT REQUEST
FIGURE 16-BIT TRANSPARENT MODE USING DUAL PORT
Data Device Corporation www.ddc-web.com BU-65170/61580/61585 L-03/06-0
+15V CLOCK OSCILLATOR
D15-D0 RD/WR
D15-D0 TX/RXA RD/WR DTREQ DTGRT DTACK MEMWR MEMOE TX/RXA
A15-A0
A15-A0
TX/RXB
HOST
ADDRESS DECODER
MEMENA-IN
TX/RXB
MEMENA-OUT
SELECT ADDRESS DECODER TRANSPARENT/BUFFERED MEM/REG
STROBE ACKNOWLEDGE
STRBD RTAD4-RTAD0 READYD TAG_CLK RTADP ADDRESS, PARITY
RESET
MSTCLR SSFLAG/EXT_TRIG
INTERRUPT REQUEST
FIGURE 16-BIT DIRECT MEMORY ACCESS (DMA) MODE
Data Device Corporation www.ddc-web.com BU-65170/61580/61585 L-03/06-0
+15V CLOCK OSCILLATOR D15-D0 RD/WR
D15-D0 RD/WR TX/RXA MEMWR MEMOE TX/RXA
DTREQ DTGRT DTACK TX/RXB A15-A0 A15-A0 MEMENA-IN MEMENA-OUT MEM/REG 1553 SELECT ADDRESS DECODER 1553 SELECT TRANSPARENT/BUFFERED SELECT
HOST
TX/RXB
STROBE ACKNOWLEDGE
STRBD RTAD4-RTAD0 READYD TAG_CLK RTADP ADDRESS, PARITY
RESET
MSTCLR SSFLAG/EXT_TRIG
INTERRUPT REQUEST
FIGURE 16-BIT MODE WITH EXTERNAL LOGIC REDUCE PROCESSOR ACCESS TIME EXTERNAL
Data Device Corporation www.ddc-web.com BU-65170/61580/61585 L-03/06-0
CLOCK OSCILLATOR D7-D0
(NOTE
+15V
D15-D8
D7-D0 TX/RXA A15-A12 A12-A0 A12-A1 ADDRESS LATCH (NOTE A11-A0 ADDR_LAT MSB/LSB 16/8_BIT TRANSPARENT/BUFFERED TX/RXA
(NOTE
POLARITY_SEL
TX/RXB
(NOTE
ZERO_WAIT
HOST
(NOTE
TRIGGER_SEL
TX/RXB
SELECT ADDRESS DECODER MEM/REG
RD/WR STROBE ACKNOWLEDGE
(NOTE
RD/WR STRBD READYD TAG_CLK RTAD4-RTAD0 RTADP ADDRESS, PARITY
RESET
MSTCLR
SSFLAG/EXT_TRIG
INTERRUPT REQUEST
NOTES:
D7-D0 CONNECTS BOTH D15-D8 D7-D0. ADDRESS LATCH SIGNAL PROVIDED PROCESSORS WITH MULTIPLEXED ADDRESS/DATA BUFFERS. POLARITY_SEL "1", THEN MSB/LSB SELECTS MOST SIGNIFICANT BYTE WHEN LOW, LEAST SIGNIFICANT BYTE WHEN HIGH. POLARITY_SEL "0", THEN MSB/LSB SELECTS LEAST SIGNIFICANT BYTE WHEN LOW, MOST SIGNIFICANT BYTE WHEN HIGH. ZERO WAIT SHOULD STRAPPED LOGIC NON-ZERO WAIT INTERFACE LOGIC ZERO WAIT INTERFACE. OPERATION TRIGGER_SELECT INPUT FOLLOWS: NON-ZERO WAIT INTERFACE (ZERO WAIT "1"): TRIGGER_SEL "1", THEN INTERNAL 16-BIT TRANSFERS TRIGGERED MOST SIGNIFICANT BYTE TRANSFER READ ACCESSES LEAST SIGNIFICANT BYTE TRANSFER WRITE ACCESSES. TRIGGER_SEL "0", THEN INTERNAL 16-BIT TRANSFERS TRIGGERED LEAST SIGNIFICANT BYTE TRANSFER READ ACESSES MOST SIGNIFICANT BYTE TRANSFER WRITE ACCESSES. ZERO WAIT INTERFACE (ZERO WAIT "0"): TRIGGER_SEL "1", THEN INTERNAL 16-BIT TRANSFERS TRIGGERED LEAST SIGNIFICANT BYTE TRANSFER, BOTH READ WRITE ACCESSES. TRIGGER_SEL "0", THEN INTERNAL 16-BIT TRANSFERS TRIGGERED MOST SIGNIFICANT BYTE TRANSFER, BOTH READ WRITE ACCESSES. ACKNOWLEDGE PROCESSOR INPUT ONLY NON-ZERO WAIT TYPE INTERFACE.
Additional address lines required with BU-61585.
FIGURE 8-BIT BUFFERED MODE
Data Device Corporation www.ddc-web.com BU-65170/61580/61585 L-03/06-0
CLOCK
SELECT
(Note 2,7)
STRBD
(Note
MEM/REG
(Note 3,4,7)
VALID
RD/WR
(Note 4,5)
IOEN
(Note 2,6)
READYD
(Note
A15-A0
(Note 7,8,9)
D15-D0
(Note
FIGURE READING (SHOWN 16-BIT, BUFFERED, NON-ZERO WAIT MODE)
Data Device Corporation www.ddc-web.com
VALID VALID
BU-65170/61580/61585 L-03/06-0
TABLE FIGURE READING REGISTERS (SHOWN 16-BIT, BUFFERED, NONZERO WAIT MODE) DESCRIPTION SELECT STRBD setup time prior clock rising edge SELECT STRBD delay IOEN (uncontended access MHz) SELECT STRBD delay IOEN (contended access MHz) SELECT STRBD delay IOEN (uncontended access MHz) SELECT STRBD delay IOEN (contended access MHz) MEM/REG, RD/WR setup time following SELECT STRBD low(@ MHz) MEM/REG, RD/WR setup time following SELECT STRBD low(@ MHz) Address valid setup time following SELECT STRBD MHz) Address valid setup time following SELECT STRBD MHz) CLOCK rising edge delay IOEN falling edge SELECT hold time following IOEN falling MEM/REG, RD/WR setup time prior CLOCK falling edge MEM/REG, RD/WR hold time prior CLOCK falling edge Address valid setup time prior CLOCK rising edge Address hold time following CLOCK rising edge IOEN falling delay READYD falling (reading MHz) IOEN falling delay READYD falling (reading MHz) IOEN falling delay READYD falling (reading registers MHz) IOEN falling delay READYD falling (reading registers MHz) Output Data valid prior READYD falling MHz) Output Data valid prior READYD falling MHz) CLOCK rising edge delay READYD falling READYD falling STRBD rising release time STRBD rising edge delay IOEN rising edge READYD rising edge Output Data hold time following STRBD rising edge STRBD rising delay output Data tri-state STRBD high hold time from READYD rising CLOCK rising edge delay Output Data valid 187.5 187.5 107.5 128.3 UNITS note note note note notes notes notes notes notes notes notes notes note note note
NOTE REFERENCE
notes notes notes notes notes notes notes
Notes FIGURE associated table. 16-bit buffered nonzero wait configuration, TRANSPARENT/BUFFERED must connected logic "0". ZERO_WAIT DTREQ/16/8 must connected logic "1". inputs TRIGGER_SEL MSB/LSB connected either ground. SELECT STRBD tied together. IOEN goes first rising edge when STRBD sampled (satisfying BU-65170/61580's protocol/memory management logic accessing internal RAM. When this occurs, IOEN goes low, starting transfer cycle. After IOEN goes low, SELECT released high. MEM/REG must presented high memory access, register access. MEM/REG RD/WR buffered transparently until first falling edge after IOEN goes low. After this edge, MEM/REG RD/WR become latched internally. logic sense RD/WR diagram assumes that POLARITY_SEL connected logic "1." POLARITY_SEL connected logic "0," RD/WR must asserted read. timing IOEN, READYD D15-D0 assumes load. loading above validity IOEN, READYD, D15-D0 delayed additional 0.14 ns/pf typ, 0.28 ns/pf max. Timing A15-A0, MEM/REG SELECT assumes ADDR-LAT connected logic "1." Refer Address Latch timing addition-
details. Internal accessed through (A13 through 61585 61586). Registers accessed through address A15-A0 internally buffered transparently until first rising edge after IOEN goes low. After this edge, A15-A0 become latched internally. Setup time given worst case timing calculations. None input signals required synchronized system clock. applications only, where SELECT STRBD meet setup time occur during setup window internal flip-flop, additional clock cycle will inserted between falling clock edge that latches MEM/REG RD/WR rising clock edge that latches Address (A15A0). When this occurs, pulse width IOEN falling READYD falling (t11) increases clock cycle address hold time (t10) must increased clock cycle.
Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
CLOCK
SELECT
(Note 2,7)
STRBD
(Note
MEM/REG
(Note 3,4,7)
VALID
RD/WR
(Note 4,5)
IOEN
(Note 2,6)
READYD A15-A0
(Note
VALID
(Note 7,8,9,10)
VALID
(Note 9,10)
D15-D0
FIGURE WRITING (SHOWN 16-BIT, BUFFERED, NON-ZERO WAIT MODE)
Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
TABLE FIGURE WRITING REGISTERS (SHOWN 16-BIT, BUFFERED, NONZERO WAIT MODE) DESCRIPTION SELECT STRBD setup time prior CLOCK rising edge SELECT STRBD delay IOEN (uncontended access MHz) SELECT STRBD delay IOEN (contended access MHz) SELECT STRBD delay IOEN (uncontended access MHz) SELECT STRBD delay IOEN (contended access MHz) MEM/REG, RD/WR setup time following SELECT STRBD low(@ MHz) MEM/REG, RD/WR setup time following SELECT STRBD low(@ MHz) Address valid setup time following SELECT STRBD MHz) Address valid setup time following SELECT STRBD MHz) Input Data valid setup time following SELECT STRBD MHz) Input Data valid setup time following SELECT STRBD MHz) CLOCK rising edge delay IOEN falling edge SELECT hold time following IOEN falling MEM/REG, RD/WR setup time prior CLOCK falling edge MEM/REG, RD/WR hold time prior CLOCK falling edge Address valid setup time prior CLOCK rising edge Input Data valid setup time prior CLOCK rising edge Address valid hold time following CLOCK rising edge Input Data valid hold time following CLOCK rising edge IOEN falling delay READYD falling MHz) IOEN falling delay READYD falling MHz) CLOCK rising edge delay READYD falling READYD falling STRBD rising edge release time STRBD rising edge delay IOEN rising edge READYD rising edge STRBD valid high hold time from READYD rising edge 187.5 107.5 128.3 UNITS note notes notes notes notes note note note notes notes notes NOTE REFERENCE notes notes notes notes notes notes notes
Notes FIGURE associated table. 16-bit buffered nonzero wait configuration, TRANSPARENT/BUFFERED must connected logic "0". ZERO_WAIT DTREQ/16/8 must connected logic "1". inputs TRIGGER_SEL MSB/LSB connected either ground. SELECT STRBD tied together. IOEN goes first rising edge when sampled (satisfying BU-65170/61580's protocol/memory management logic accessing internal RAM. When this occurs, IOEN goes low, starting transfer cycle. After IOEN goes low, SELECT released high. MEM/REG must presented high memory access, register access. MEM/REG RD/WR buffered transparently until first falling edge after IOEN goes low. After this edge, MEM/REG RD/WR become latched internally. logic sense RD/WR diagram assumes that POLARITY_SEL connected logic "1." POLARITY_SEL connected logic "0," RD/WR must asserted high write. timing IOEN, READYD D15-D0 assumes
load. loading above validity IOEN, READYD, D15-D0 delayed additional 0.14 ns/pf typ, 0.28 ns/pf max. Timing A15-A0, MEM/REG SELECT assumes ADDR-LAT connected logic "1." Refer Address Latch timing additional details. Internal accessed through (A13 through 61585 61586). Registers accessed through address A15-A0 internally buffered transparently until first rising edge after IOEN goes low. After this edge, A15-A0 become latched internally. Setup time given worst case timing calculations. None input signals required synchronized system clock. applications only, where SELECT STRBD meet setup time occur during setup window internal flip-flop, additional clock cycle will inserted between falling clock edge that latches MEM/REG RD/WR rising clock edge that latches Address (A15-A0) data (D15-D0). When this occurs, pulse width IOEN falling READYD falling (t14) increases clock cycle address hold time (t12 t13) must increased clock cycle.
Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
SELECT MSB/LSB INPUT SIGNALS MEM/REG A15-A0 ADDR_LAT SELECT MSB/LSB INTERNAL VALUES MEM/REG A15-A0
FIGURE ADDRESS LATCH TIMING
Notes FIGURE associated table. Applicable buffered mode only. Address SELECT MEM/REG latches always transparent transparent mode operation. Latches transparent when ADDR_LAT high. Internal values update when ADDR_LAT low. MSB/LSB input signal applicable 8-bit mode only (16/8 input logic "0"). MSB/LSB input "don't care" 16-bit operation.
TABLE FIGURE ADDRESS LATCH TIMING ADDR_LAT pulse width ADDR_LAT high delay internal signals valid Propagation delay from external input signals internal signals valid Input setup time prior falling edge ADDR_LAT Input hold time following falling edge ADDR_LAT DESCRIPTION UNITS
Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
INTERFACE MIL-STD-1553
FIGURE illustrates interface from various versions series terminals 1553 bus. figure also indicates connections both direct (short stub) transformer (long stub) coupling, plus peak-to-peak voltage levels that appear various points (when transmitting). TABLE lists characteristics required isolation transformers various terminals, Beta Transformer Technology Corporation corresponding part number, (DESC) drawing number applicable). Beta Transformer Technology direct subsidiary DDC. both coupling configurations, isolation transformer transformer that interfaces directly component. transformer (long stub) coupling configuration, transformer that interfaces stub coupling transformer. turns ratio isolation transformer varies, depending upon peak-to-peak output voltage specific terminal. transmitter voltage each model BU-65170/61580 varies directly function power supply voltage. turns ratios respective transformers will yield secondary voltage approximately volts peak-to-peak outer taps (used direct coupling) volts peak-to-peak inner taps (used stub coupling). accordance with MIL-STD-1553B, turns ratio coupling transformer 1.4. Both coupling configurations require isolation resistor series with each connecting 1553 bus; this protects against short circuit conditions transformers, stubs, terminal components.
TABLE ISOLATION TRANSFORMER GUIDE TURNS RATIO PART NUMBER BU-65170X1 BU-65171X1 BU-61580X1 BU-61581X1 BU-61585X1 BU-61586X1 DIRECT XFORMER COUPLED COUPLED 1.41:1 RECOMMENDED XFORMER PLUG-IN BUS-25679, B-2203, M21038/27 SURFACE MOUNT B-2387 M21038/27 -12, M21038/27 LPB-5002 LPB-5009 LPB-6002 LPB-6009 LPB-5001 LPB-5008 LPB-6001 LPB-6008 B-2388 M21038/27 -13, B-2334, M21038/27
BU-65170X2 BU-65171X2 BU-61580X2 BU-61581X2 BU-61585X2 BU-61586X2
1.20:1
1:0.6
BUS-29854
1.25:1 (Note
B-2204, M21038/27
BU-65170X3 BU-65171X3 BU-61580X3 BU-61581X3 BU-61585X3 BU-61586X3 BU-65170X6 BU-65171X6 BU-61580X6 BU-61581X6 BU-61585X6 BU-61586X6
1:2.5
1:1.79
Table
Notes TABLE FIGURE Shown redundant buses that interface BU-65170 BU61580. Transmitted voltage level 1553 Vp-p min, Vp-p nominal, Vp-p max. Required tolerance isolation resistors Instantaneous power dissipation (when transmitting) approximately (typ), (max). Transformer numbering correct (e.g., BUS-25679) transformers. Beta transformers (e.g., B-2203) QPL-21038-31 transformers (e.g., M21038/27-02), winding sense turns ratio mechanically same, with reversed numbering; therefore, necessary reverse pins pins Beta transformers (Note: transformer part numbers begin with BUS- prefix, while Beta transformer part numbers begin with prefix). (5)The B-2204, B-2388, B-2344 transformers have slightly different turns ratio direct coupled taps then turns ratio BUS-29854 direct coupled taps. They however, have same transformer coupled ratio. transformer coupled applications, either transformer used. transcevier BU-65170X2 BU-61580X2 designed work with 1:0.83 ratio direct coupled applictions. direct coupled applications, 1.20:1 turns ration recommended, 1.25:1 used. 1.25:1 turns ratio will result slightly lower transmitter amplitude. (Approximateley 3.6% lower) slight shift ACE's receiver threshold.
Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
TRANSFORMERS
selecting isolation transformers used with ACE, there limitation maximum amount leakage inductance. this limit exceeded, transmitter rise fall times increase, possibly causing amplitude fall below minimum level required MIL-STD-1553. addition, excessive leakage imbalance result transformer dynamic offset that exceeds 1553 specifications. maximum allowable leakage inductance measured follows: side transformer that connects defined "primary" winding. side primary shorted primary center-tap, inductance should measured across "secondary" (stub side) winding. This inductance
must less than Similarly, other side primary shorted primary center-tap, inductance measured across "secondary" (stub side) winding must also less than difference between these measurements "differential" leakage inductance. This value must less than Beta Transformer Technology Corporation (BTTC), subsidiary DDC, manufactures transformers variety mechanical configurations with required turns ratios 1:2.5 direct coupled, 1:1.79 transformer coupled. Table provides listing many these transformers.For further information, contact BTTC 631-244-7393 www.bttc-beta.com.
TABLE BTTC TRANSFORMERS WITH
TRANSFORMER CONFIGURATION Single epoxy transformer, through-hole, 0.625" 0.625", 0.250" height Single epoxy transformer, through-hole, 0.625" 0.625", 0.220" height. used with BU-6XXXXX4 versions Enhanced Mini-ACE. Single epoxy transformer, flat pack, 0.625" 0.625", 0.275" height Single epoxy transformer, surface mount, 0.625" 0.625", 0.275" height Single epoxy transformer, surface mount, hi-temp solder, 0.625" 0.625", 0.220" height. used with BU-6XXXXX4 versions Enhanced Mini-ACE.B-3819 Single epoxy transformer, flat pack, 0.625" 0.625", 0.150" height Single epoxy transformer, surface mount, 0.625" 0.625", 0.150" height Single epoxy transformer, through hole, transformer coupled only, 0.500" 0.350", 0.250" height Dual epoxy transformer, twin stacked, 0.625" 0.625", 0.280" height Dual epoxy transformer, twin stacked, surface mount, 0.625" 0.625", 0.280" height Dual epoxy transformer, twin stacked, flat pack, 0.625" 0.625", 0.280" height Dual epoxy transformer, side side, through-hole, 0.930" 0.630", 0.155" height Dual epoxy transformer, side side, flat pack, 0.930" 0.630", 0.155" height Dual epoxy transformer, side side, surface mount, 0.930" 0.630", 0.155" height Dual epoxy transformer, side side, surface mount, 1.410" 0.750", 0.130" height Single metal transformer, hermetically sealed, flat pack, 0.630" 0.630", 0.175" height Single metal transformer, hermetically sealed, surface mount, 0.630" 0.630", 0.175" height RECOMMENDED
Notes: BU-6XXXXX3/6 versions with -1553B transceivers, transformers listed table used. DLP-7115 operates +105°C max. other transformers listed operate +130°C max.
BTTC PART B-3067 B-3226 B-3818 B-3231 B-3227 B-3819 LPB-5014 LPB-5015 B-3229 TST-9007 TST-9017 TST-9027 TLP-1205 TLP-1105 TLP-1005 DLP-7115 (see note HLP-6014 HLP-6015 DLP-7014 SLP-8007 SLP-8024
Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
DIRECT COUPLED (SHORT STUB) 1.4:1
BU-61580X1
ISOLATION TRANSFORMER
TRANSFORMER COUPLED (LONG STUB) 1:1.4
0.75 0.75
ISOLATION TRANSFORMER
COUPLING TRANSFORMER
DIRECT COUPLED (SHORT STUB) 1:0.83
BU-61580X2
ISOLATION TRANSFORMER
TRANSFORMER COUPLED (LONG STUB) 1:0.6 1:1.4
0.75 0.75
ISOLATION TRANSFORMER
COUPLING TRANSFORMER
DIRECT COUPLED (SHORT STUB)
1:2.5 11.6
ISOLATION TRANSFORMER
BU-61580X3 BU-61580X6
TRANSFORMER COUPLED (LONG STUB)
1:1.79 11.6
1:1.4
0.75 0.75
ISOLATION TRANSFORMER
COUPLING TRANSFORMER
Note: BU-65170XX, BU-65171XX, BU-61581XX, BU-61585XX BU-61586XX models interfaced same corresponding BU-61580XX model shown (i.e. BU-65170X1 interfaced same BU-61580X1).
FIGURE BU-65170/61580 INTERFACE 1553
Data Device Corporation www.ddc-web.com BU-65170/61580/61585 L-03/06-0
TABLE SIGNAL DESCRIPTIONS BU-65170/61571, BU-61580/61585, BU-61586 PACKAGE) PROCESSOR/MEMORY INTERFACE CONTROL (15) SIGNAL NAME TRANSPARENT/ BUFFERED STRBD SELECT MEM/REG DESCRIPTION
Used select between Transparent/ mode (when strapped logic Buffered mode (when strapped logic host processor interface. Strobe Data. Used with SELECT initiate control data transfer cycle between host processor BU65170/61580. Generally connected address decoder output select BU-65170/61580 transfer to/from either register. tied STRBD. Memory/Register. Generally connected either address line address decoder output. Selects between memory access (MEM/REG register access (MEM/REG Read/Write. host processor access, selects either reading writing. 16-bit buffered mode, polarity select logic then RD/WR (logic read accesses high (logic write accesses. polarity select logic configuration interface mode other than 16-bit buffered mode, then RD/WR high (logic read accesses (logic write accesses.
RD/WR
IOEN
Tri-state control external address data buffers. Generally needed buffered mode. When low, external buffers should allow host processor access BU-65170/61580's registers. Handshake output host processor. nonzero wait state read access, signals that data available read through nonzero wait state write cycle, signals completion data transfer register location buffered zero wait state mode, active high output signal (following rising edge STRBD used indicate latching address data (write only) that internal transfer between address/data latches RAM/registers on-going. Interrupt request output. LEVEL/PULSE interrupt (bit Configuration Register low, negative pulse approximately width output INT. high, level interrupt request output will asserted INT. Data Transfer Request 16-bit/8-bit Transfer Mode Select. transparent mode, active output signal used request access processor interface (address,data, control buses). buffered mode, input signal used select between 16-bit data transfer mode (16/8 logic data transfer mode (16/8 logic Data Transfer Grant Most Significant Byte/Least Significant Byte. transparent mode, active input signal asserted, response DTREQ output, indicate that access processor buses been granted BU65170/61580. 8-bit buffered mode, input signal used indicate which byte being transferred (MSB LSB). POLARITY_SEL input controls logic sense MSB/LSB. (Note: only 8-bit buffered mode uses MSB/LSB.) description POLARITY_SEL signal. 16-bit buffered mode. Data Transfer Acknowledge Polarity Select. transparent mode, active output signal used indicate acceptance processor interface response data transfer grant (DTGRT).In 16-bit buffered mode (TRANSPARENT/ BUFFERED logic 16/8 logic input signal used control logic sense RD/WR signal. When POLARITY_SEL logic RD/WR must asserted high (logic read operation (logic write operation. When POLARITY_SEL logic RD/WR must asserted (logic read operation high (logic write operation.In 8-bit buffered mode (TRANSPARENT/BUFFERED logic 16/8 logic input signal used control logic sense MSB/LSB signal. When POLARITY_SEL logic MSB/LSB must asserted (logic indicate transfer least significant byte high (logic indicate transfer most significant byte. When POLARITY_SEL logic MSB/LSB must asserted high (logic indicate transfer least significant byte (logic indicate transfer most significant byte. Memory Enable Output. Asserted during both host processor 1553 protocol/memory management memory transfer cycles. Used memory chip select (CS) signal external transparent mode. Memory Enable Input Trigger Select. transparent mode, MEMENA-IN active Chip Select (CS) input internal shared RAM. When only using internal RAM, connect directly MEMENA-OUT. 8-bit buffered mode, input signal (TRIGGER_SEL) indicates order byte pairs transfer from BU-65170/61580 host processor. This signal operation (can N/C) 16-bit buffered mode.In 8-bit buffered mode, TRIGGER_SEL should asserted high (logic byte order both read operations write operations followed LSB. TRIGGER_SEL should asserted (logic byte order both read operations write operations followed MSB. Memory Output Enable Address Latch. transparent mode, MEMOE output will used enable data outputs external read cycles (normally connected signal external chips). buffered mode, ADDR_LAT input will used configure internal address latches latched mode (when low) transparent mode (when high). Memory Write Zero Wait State. transparent mode, active output signal (MEMWR will asserted during memory write transfers strobe data into internal external (normally connected signal external chips). buffered mode, input signal (ZERO_WAIT) will used select between zero wait mode (ZERO_WAIT logic nonzero wait mode (ZERO_WAIT logic
READYD
DTREQ /16/8
DTGRT /MSB/LSB
DTACK (O)/ POLARITY_SEL
MEMENA-OUT
MEMENA-IN /TRIGGER_SEL
MEMOE (O)/ ADDR_LAT
MEMWR /ZERO_WAIT
Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
TABLE SIGNAL DESCRIPTIONS BU-65170/61571, BU-61580/61585, BU-61586 PACKAGE) (CONTINUED) MISCELLANEOUS SIGNAL NAME CLOCK MSTCLR INCMD 16MHz 12MHz) clock input. Master Clear. Negative true Reset input, normally asserted following power turn-on. Requires minimum 100ns negative pulse reset internal logic "power turn-on" state. Command. mode, asserted throughout processing cycle each message. mode Message Monitor mode, asserted following receipt Command Word kept until completion current message sequence. Word Monitor mode, goes following MONITOR START command, kept while monitor on-line, goes high following RESET command. Subsystem Flag External Trigger input. Remote Terminal mode, asserting this input will Subsystem Flag BU-65170/61580's Status Word. SSFLAG input overrides logic respective (bit Configuration Register Controller mode, enabled external Start option (bit Configuration Register low-to-high transition this input will issue Start command, starting execution current frame. Word Monitor mode, enabled external trigger (bit Configuration Register low-to-high transition this input will issue monitor trigger. External Time Clock input. designated bits Configuration Register When used increments internal Time Register/Counter. used, should connected ground. Option BU-65170/61580X6 BU-61585X6. Inhibits (disables) respective (A/B) MIL-STD-1553 transmitter when asserted logic "1." DESCRIPTION
SSFLAG (I)/ EXT_TRIG
TAG_CLK TX_INH_A TX_INH_B
POWER GROUND SIGNAL NAME LOGIC LOGIC -15(-12)VA +5VA GNDA -15(-12)VB +5VB GNDB Logic Supply Logic Ground -15V(-12V) Supply* Supply Transceiver Ground -15V(-12V) Supply* Supply Transceiver Ground DESCRIPTION
NOTE: Connects (N/Cs) BU-65170/61580 TX_INH input BU-65170/61580X6.
ADDRESS SIGNAL NAME RTAD4 (MSB) RTAD3 RTAD2 RTAD1 RTAD0 (LSB) RTADP Remote Terminal Address Parity. Must provide parity with RTAD4-RTAD0 order respond nonRemote Terminal Address Inputs DESCRIPTION
1553 ISOLATION TRANSFORMER INTERFACE SIGNAL NAME TX/RX-A (I/O) TX/RX-A (I/O) TX/RX-B (I/O) TX/RX-B (I/O) DESCRIPTION Analog Transmit/Receive Input/Outputs. Connect directly 1553 isolation transformers.
Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
TABLE SIGNAL DESCRIPTIONS BU-65170/61571, BU-61580/61585, BU-61586 PACKAGE) (CONTINUED) ADDRESS (16) SIGNAL NAME (MSB) DESCRIPTION 16-bit bidirectional address bus. both buffered transparent modes, host accesses BU-65170/61580 registers words internal through (BU-61585 uses through A0). host performs register selection through A0.In buffered mode, A15-A0 inputs only. transparent mode, A15-A0 inputs during accesses drive outward (towards CPU) when 1553 protocol/memory management logic accesses external RAM. address drives outward only transparent when signal DTACK (indicating that 61580 control processor interface bus) IOEN high (indicating that this access). Most time, including immediately after power turn-on RESET, A15-A0 outputs will their disabled (high impedance) state.
DATA (16) SIGNAL NAME (MSB) DESCRIPTION
16-bit bidirectional data bus. This interfaces host processor internal registers words RAM(12K BU-61585). addition, transparent mode, this allows data transfers take place between internal protocol/memory management logic external RAM. Most time, outputs through their high impedance state. They drive outward buffered transparent mode when host reads internal registers. trasparent mode, when protocol/memory management logic access59 (either reading writing) internal writing external RAM.
Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
TABLE BU-65170/65171, BU-61580/61581/61585/61586 LISTINGS PACKAGE) TX/RX-A TX/RX-A SELECT STRBD MEM/REG RD/WR MSTCLR DTGRT/MSB/LSB SSFLAG/EXT_TRIG MEMENA_OUT MEMOE/ADDR_LAT MEMWR/ZERO_WAIT DTREQ/16/8 DTACK/POLARITY_SEL MEMENA_IN/TRIGGER_SEL TX/RX-B TX/RX-B NAME NAME (see note) GNDB +5VB RTAD0 RTAD1 RTAD2 RTAD3 RTAD4 RTADP INCMD Logic TAG_CLK TRANSPARENT/BUFFERED READYD IOEN +5VA GNDA (see note)
Notes: -15V BU-65170/61580X1. -12V BU-65170/61580X2. BU-65170/61580X3. BU-65170/61580X6. TX_INH_B TX_INH_A
Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
0.215 (5.46) PACKAGE 0.165 (4.19) PACKAGE 0.180 ±0.010 (4.57 ±0.25) 0.100 (2.54)
1.900 (48.26)
0.400 (10.16)
0.600 (15.24)
BOTTOM VIEW
0.018 ±0.002 (0.46 ±0.05)
SIDE VIEW
0.100 (2.54) 0.050 (1.27) 1.700 (43.18) 1.900 (48.26)
INDEX DENOTES
1.000 (25.4)
VIEW
INDEX DENOTES
NOTES: DIMENSIONS INCHES (MILLIMETERS). PACKAGE MATERIAL: ALUMINA (AL2O3). LEAD MATERIAL: KOVAR, PLATED 150µ MINIMUM NICKEL, PLATED MINIMUM GOLD.
FIGURE MECHANICAL OUTLINE
Data Device Corporation www.ddc-web.com BU-65170/61580/61585 L-03/06-0
1.900 (48.26) 0.018 0.002 (0.46 0.05) 0.215 (5.46) Package 0.150 (3.81) Package
INDEX DENOTES
1.000 (25.4)
0.400 (10.18) 0.050 (1.27)
0.010 0.002 (0.254 0.051) 0.050 1.700 (43.18) (1.27) NONCUM 0.070 0.010 (1.78) NUMBERS ONLY
VIEW
SIDE VIEW
NOTES: DIMENSIONS INCHES (MILLIMETERS). PACKAGE MATERIAL: ALUMINA (AL2O3). LEAD MATERIAL: KOVAR, PLATED 150µ MINIMUM NICKEL, PLATED MINIMUM GOLD.
FIGURE MECHANICAL OUTLINE
Data Device Corporation www.ddc-web.com BU-65170/61580/61585 L-03/06-0
DENOTED INDEX MARK
1.000 (MAX)
0.018 ±0.002
0.050 1.700 (TOL. NONCUM) 1.900 0.050
NUMBERS REF. ONLY 0.150 0.190 ±0.010 0.065 (REF) 0.080
0.010 ±0.002
0.040 0.012 1.024 1.38 ±0.02 0.050
VIEW
0.006 -0.004,+0.010 (0.152 +0.10,-0.254) VIEW
FIGURE MECHANICAL OUTLINE
Data Device Corporation www.ddc-web.com BU-65170/61580/61585 L-03/06-0
ORDERING INFORMATION
BU-XXXXXXX-XXXX Supplemental Process Requirements: Pre-Cap Source Inspection 100% Pull Test 100% Pull Test Pre-Cap Source Inspection Date Code Date Code Pre-Cap Source Inspection Date Code 100% Pull Test Date Code, Pre-Cap Source Inspection 100% Pull Test Blank None Above Test Criteria: Standard Testing MIL-STD-1760 Amplitude Compliant Applies Volt Transceiver Option Only Process Requirements: Standard practices, Burn-In (See following page.) MIL-PRF-38534 Compliant (See Note (See Note MIL-PRF-38534 Compliant (See Note with PIND Testing MIL-PRF-38534 Compliant (See Note with Solder MIL-PRF-38534 Compliant (See Note with PIND Testing Solder (See Note with PIND Testing (See Note with Solder (See Note with PIND Testing Solder Standard Processing with Solder Dip, Burn-In (See following page.) Temperature Range/Data Requirements: -55°C +125°C -40°C +85°C +70°C -55°C +125°C with Variables Test Data -40°C +85°C with Variables Test Data +70°C with Variables Test Data Voltage/Transceiver Option: Transceiverless Volts Volts (1760 Compliant Standard Configuration) Volts Volts Volts only Test Criteria 1760 Compliant with option -XX2) Volts only with Inhibit inputs brought negative supply pins Package Type: "Gull Wing" (Formed Lead) Lead Small Very Small Flat Pack Product Type: 65170 70-pin 65171 70-pin with Latchable Address Option 61580 70-pin BC/RT/MT 61581 70-pin BC/RT/MT with Latchable address Option 61585 70-pin BC/RT/MT with 61586 70-pin BC/RT/MT with Address Option Notes: series also available DESC drawing number 5962-93065. Standard Processing with burn-in full temperature test, table following page. above products contain tin-lead solder finish applicable solder requirements. MIL-PRF-38534 product grading designated with following dash numbers: Class -11X, 13X, 14X, 15X, 41X, 43X, 44X, Class -21X, 23X, 24X, 25X, 51X, 53X, 54X, Class -31X, 33X, 34X, 35X, 81X, 83X, 84X,
Data Device Corporation www.ddc-web.com
BU-65170/61580/61585 L-03/06-0
STANDARD PROCESSING HYBRID MONOLITHIC HERMETIC PRODUCTS
TEST INSPECTION SEAL TEMPERATURE CYCLE CONSTANT ACCELERATION BURN-IN MIL-STD-883 METHOD(S) 2009, 2010, 2017, 2032 1014 1010 2001 1015 (note 1030 (note CONDITION(S) 3000g TABLE
Notes: Process Requirement "B*" (refer ordering information), devices non-compliant with MILSTD-883, Test Method 1015, Paragraph 3.2. Contact factory details. When applicable.
information this data sheet believed accurate; however, responsibility assumed Data Device Corporation use, license rights granted implication otherwise connection therewith. Specifications subject change without notice. Please visit site www.ddc-web.com latest information.
Wilbur Place, Bohemia, York, U.S.A. 11716-2482 Technical Support 1-800-DDC-5757 ext. 7771 Headquarters, N.Y., U.S.A. Tel: (631) 567-5600, Fax: (631) 567-7358 Southeast, U.S.A. Tel: (703) 450-7900, Fax: (703) 450-6610 West Coast, U.S.A. Tel: (714) 895-9777, Fax: (714) 895-4988 United Kingdom Tel: +44-(0)1635-811140, Fax: +44-(0)1635-32264 Ireland Tel: +353-21-341065, Fax: +353-21-341568 France Tel: +33-(0)1-41-16-3424, Fax: +33-(0)1-41-16-3425 Germany Tel: +49-(0)89-15 12-11, Fax: +49-(0)89-15 12-22 Japan Tel: +81-(0)3-3814-7688, Fax: +81-(0)3-3814-7689 World Wide http://www.ddc-web.com
ERED
DATA DEVICE CORPORATION REGISTERED 9001:2000 FILE A5976
L-03/06-0
PRINTED U.S.A.
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