Description: NTE849 integrated circuit 14-Lead type package designed h

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Description: NTE849 integrated circuit 14-Lead type package designed h

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NTE849 Integrated Circuit Horizontal/Vertical Countdown Digital Sync System
Description: NTE849 integrated circuit 14-Lead type package designed horizontal/ vetical countdown digital sync systems. some video playback units, there incorrect frequency relationships between horizontal field frequencies. Automatic forced asynchronous mode eliminates jitter when equalizer pulses correct, these incorrect frequency relationships exist. Automatic standard mode occurs upon detection nine more equalizing pulses during six-line- width vertical driving period after seven fields coincidence between integrated vertical (IV) sync internal counter output. Standard mode retained seven fields missing mutilated vertical sync pulses. more noise pulses detected Pin12 during 384-line active scan time, noise detector reverts system standard mode next field coincidence (without seven fields coincidene delay). Thus, unit stays standard mode during tuner channel changes. automatic mode-recognition system places unit standard mode NTSC signals into non-synchronous mode non-standard sync signals. external oscillator (NTE701) supplies input Pin9 that times horizontal rate. internal divide-by-16 counter converts this input (32fH) elsewhere. This 32fH signal further divided which available Pin11 drive horizontal deflection circuits. divide-by-525 counter further divides signal generate vertical ramp generator timing pulses vertical blanking pulse. phasing circuit (part mode recognition vertical regeneration circuits) insures that counter reset coincidence with vertical sync. does this comparing internally generated vertical pulse with extrnal integrated vertical sync signal applied Pin12. automatic mode recognition circuit forces NTE849 into standard mode NTSC signals into non- synchronous mode non-standard sync signals such video games. input control signal connection) Pin8 places NTE849 into non-synchronous operation. phasing timing logic circuit checks line counter sync with signal Pin12. Seven consecutive fields in-phase coincidence with signal needed achieve standard mode unless more noise pulses de-detected input Pin12 during active scan time. this case, normal mode will acquired field.
Description (Cont'd): standard divide-by-525 mode, integrated vertical pulse used only provide coincidence with count (counter preset 525) phase detector circuit. vertical ramp timed output counter. standard mode, NTE849 will maintain divide- by-525 count fields lost mutilated sync. seventh field does have correct coincidence, unit will switch non-standard mode. this mode, vertical sync derived from integrated vertical pulse field-to-field basis. noise immunity lines provided. absence sync pulses, count will instead that rapid vertical capture achieved when sync restored. Non-satndard mode still selected removing from Pin8. vertical retrace signal converted ramp signal capacitor connected between Pin3 GND. ramp's slope corresponds vertical size controlled changing input current Pin2. ramp connected inverting input diffrence amplifier. output this amplifier, connectd Pin6, used drive vertical output stage. non-inverting input difference amplifier Pin5. voltage derived from yoke current applied this linearity improvement. pulse width vertical blanking signal Pin7 clocks wide synchronous mode, adjustable width changing monostable network Pin10 non-synchronous mode. proportional voltage regulator output Pin4 about supply voltage Pin12. maximum external load current 20mA (Peak).
Features: Automatic Forced Asynchronous Mode Remove Jitter Improved Voltage Start-Up Operation Lower Zero-State Horizontal-Drive Pulse Output Improved Symmetry Horizontal-Drive Output Improved Automatic Standard Operation Noise Detector Handles Standard NTSC Non-Standard Signals Automatic Mode Recognition
Clock Input Vertical Ramp (Sawtooth) Generator Vertical Amplifier Vertical Blanking Generator Horizontal Drive Pulse Output Ratio-Voltage Regulator Inherent Interlace NTSC Signals Vertical-Hold Control Eliminated Supply Voltage Range: 10.8V 13.2V Rapid Pull-In Co-Channel Sync Lockout NTSC Signals Logic
Absolute Maximum Ratings: Supply Voltage Device Dissipation +70°C) 530mW Derate Linearily Above 70°C 6.7mW/°C Operating Ambient Temperature Range +70°C Storage Temperature Range -55° +150°C Lead Temperature (During Soldering, 1/16" from case, 10sec max) +265°C
Electrical Characteristics: +25°C, switches open, test unless otherwise specified)
Parameter Amplifier Gain, Horizontal Frequency Divider Ratio, Horizontal Pulse Width, Pin11 Test Conditions Colsed, Note Test 12V, 1VRMS 1kHz Closed, Note Test 14.4V Closed, Notes Test 8.4V Closed, Notes Test pin1 14.4V Asynchronous Non-Coincident Frequency Divide Ratio, Ramp Charge Pulse Width, Pin3 Closed, Notes Test 14.4V, 0.2V, 1.5V Closed, Notes Test 14.4V, 0.2V, 1.5V 0.178 3.16 Unit VRMS Ratio Ratio Ratio Ratio Clocks Clocks
10944 10944 7872 8400 7872 8400
Asynchronous Coincident Noise Immunity, Notes Test 14.4V, Hold-Off Frequency Divide Ratio, 0.2V Synchronous Divider Ratio, Ramp Charge Pulse Width, Pin3 Vertical Blanking Pulse Width, Pin7 Mode Recognition Field Count Frequency Divide Ratio, Synchronous Non-Synchronous Closed, Notes Test 14.4V, 0.2V, 1.5V Closed, Notes Test 14.4V, 0.2V, 1.5V Closed, Notes Test 14.4V, 0.2V, 1.5V Closed, Notes Test 12.0V, 0.2V, 1.5V Initial Fields Serrations First Field, Serrations Second Field, Serrations Third Field, Serrations Fourth Field, Serrations Fifth Field, Serrations Sixth Field, Serrations Seventh Field, Serrations Mode Recognition Field Count Frequency Divide Ratio, Non-Synchronous Synchronous Closed, Notes Test 12.0V, 0.2V First Field Second Field Third Field Fourth Field Fifth Field Sixth Field Seventh Field Eight Field Ninth Field Fast Standard-Mode Resynchronization Closed, Notes Test 12.0V, 0.2V
8400 8400 8400 8400 8400 8400 8400
8400 8400 8400 8400 8400 8400 8400
Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio
10944 10944
8384 8384 8384 8384 8384 8384 8384 8400 8400
8384 8384 8384 8384 8384 8384 8384 8400 8400
Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio Ratio
Static Characteristics:
+25°C 12V, switches open, test unless otherwise specified)
Connect Test Pins Shown Below Test Conditions Closed, Note 14.4V -20mA Closed Notes Test Closed Notes Closed, Note Closed, Note Closed, Note Closed, Note Test GND, Closed, Note Closed, Note 14.4 14.4V 14.4V 14.4V 14.4V Closed, Note Test 4.5V Closed, Note Test 50µA Closed, Note Closed, Note Test 2.3V Closed, Note Test 3.0V 4.5V 1.5V 3.0V 4.5V -20mA -20mA 20mA 0.09 -0.15 -180 -0.1 0.12 0.15 0.75 -20mA Unit
Parameter Ratio Regulator Voltage, Load Load Vertical Blanking Output, Unblanked Blanked Horizontal Output Voltage, High Vertical Output Voltage, Difference Voltage, Supply Current, Clock Current, Voltage,
Composite Sync Input Current, Sync High Closed, Note Sync Forced Asynchronous Current, Ramp Current, Ramp Current, Async Time Constant Current, Charge Discharge Vert Sync Input Current, Normal Overdrive
Notes: Note Note Note Note Note Note Note Note Note Note10. Note Note12. Note13. Stop clock when Pin7 high. Stop clock when Pin9 low. Stop clock when Pin9 high. Stop clock when Pin7 low. Stop clock when Pin11 high. Stop clock when Pin11 low. Clock frequency 600kHz, clock amplitude: 0.45V, high 0.95V max). Frequency Pin9 (clock) divided frequency Pin11 (horizontal out). Clock frequency 500kHz, clock amplitude same Note Pulse width measured point output waveform. Total capacity 50pF when measuring pulse width. Sync serrations Sync amplitude: state 1.2V, high state with positive sync tips).
Notes (Cont'd): Note14. Frequency Pin9 (clock) divided frequency Pin3 (ramp control). Note15. Initilize repeat initilization procedure before doing this test. Note16. Apply pulse clock wide, 7808 clocks after first positive transition Pin3. Note17. Default count determined 16(H) 10944. Note18. Sync serrations Note19. Hold-off count determined 16(H) 7872. Note20. Number clocks occurring within ramp gate period. Note21. Number clocks occurring during blanking gate period. Note22. This series tests checks mode recognition circuits. first test after initialization applies serrations sync input pin. should synchronous count ratio 8400. During next seven fields only serrations applied. NTE849 should maintain synchronous count ratio 8400 first fields. seventh field NTE849 should default count 10944. test concludes with 9-serration input. NTE849 should revert synchronous count 8400. Note23. This test checks operation out-of-sync detector applying out-of-phase sync pulses Pin12. NTE849 will count eight fields before resetting sync pulse. Note24. Initialize 8364 sync eight fields before test. Note25. This test verifies operation fast resync performance simulating noise pulse clocks wide) applied 4000 6000 clocks (8ms 12ms) after sync. Initialize non-sync mode before performing this test. should resync next field maintained standard confidence count seven fields.
Connection Diagram Vertical Height Ramp Charge External Bias Load Comp Sync Input Vertical Sync Input Horizontal Deflection Circuit Async Time Constant Horizontal Mode Select
Yoke Feedback Vertical Driver Vertical Blank Output
.785 (19.95) .200 (5.08)
.300 (7.62)
.100 (2.45) .600 (15.24)
.099 (2.5)

Description: NTE849 integrated circuit 14-Lead type package designed h

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