PM7325 S/UNI-ATLAS-3200 3200 Mb/s ALayer Solution FEATURES
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PM7325 S/UNI-ATLAS-3200
3200 Mb/s ALayer Solution
FEATURES
Monolithic single chip device which handles bi-directional ALayer functions including VPI/VCI address translation, cell appending, policing, cell counting requirements 128k (virtual connections). Instantaneous bi-directional transfer rate 3200 Mb/s supports bidirectional cell transfer rate 5.68x106 cells/s. UTOPIA Level interface supports 32-bit interface 8-bit interface. Extended cell format supported byte cell). Handles logical ports. UTOPIA Level Switch interface supports 32-bit interface. Extended cell format supported byte cell). Handles logical ports. Includes FIFO buffered 32-bit microprocessor interface cell insertion extraction, deterministic Table access, status monitoring configuration device. Per-PHY output buffering scheme resolves head-of-line blocking issue. UTOPIA interfaces max. External SRAM interfaces max. Ingress Egress functions include flexible search engines that cover entire PHYID/VPI/VCI address range, dual leaky-bucket policing, per-VC cell counts, OAM-FM OAM-PM processing. Complete Fault Management (AIS, RDI, processing, VP/VC, Segment/End-to-end flows VCs. Complete Performance Monitoring processing, VP/VC, Segment/Endto-end, Forward/Backward flows, Bi-directional VCs. Per-PHY AIS/RDI generation.
CELL COUNTING
Per-VC counts include CLP0 cells, CLP1 cells, policing violations. Per-PHY counts include CLP0 cells, CLP1 cells, cells, errored cells, unassigned/invalid cells policing violations. Per-device counts include total cells received/transmitted, physical layer cells.
POLICING
ITU-I.371, AForum TM4.1 compliant, per-VC programmable dual leaky-bucket policing with programmable action (tag, discard, count only) each bucket, each with programmable non-compliant cell counts. Per-PHY single leaky-bucket policing with programmable action (tag, discard, count only) Guaranteed Frame Rate (GFR) Policing with Minimum Cell Rate Frame Tagging.
PACKAGING
Provides standard signal P1149.1 JTAG test port boundary scan board test purposes. Implemented power, 0.18 micron CMOS (1.8 Volt core) technology 3.3V UTOPIA external synchronous SRAM interfaces. Packaged ball grid array (BGA) package.
ITU-I.610 (1999) compliant both Ingress Egress directions.
BLOCK DIAGRAM
128-bit Synchronous SRAM Interface
Ingress Input Cell Interface UTOPIA Level Interface (Master)
Ingress Cell Processor
Ingress Output Cell Interface UTOPIA Level Interface (Slave) Egress Input Cell Interface UTOPIA Level Interface (Slave) JTAG Interface JTAG Interface
Ingress Backward Cell Interface
Per-PHY Statistics Collection
Egress Backward Cell Interface
Egress Output Cell Interface UTOPIA Level Interface (Master)
Egress Cell Processor
Microprocessor Interface
32-bit Microprocessor Interface
128-bit Synchronous SRAM Interface
PMC-990444 (P1)
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
1999 PMC-Sierra, Inc.
PM7325 S/UNI-ATLAS-3200 3200 Mb/s ALayer Solution
APPLICATIONS
ACore Edge Switches AEnterprise Workgroup Switches Access Switches/Multiplexers native ATM, wireless access applications
TYPICAL APPLICATIONS
OC-48C/STM-16C (2.488 Gb/s) SWITCH PORT
OC-48/ STM-16 Optics
OC-48C/ STM-16C
PM7325 S/UNI-ATLAS3200
Physical Layer
ALayer
Traffic Mgmt Switch Fabric
QUAD OC-12C/STM-4C (622 Mb/s) SWITCH PORT
OC-12/ STM-4 Optics OC-12/ STM-4 Optics OC-12/ STM-4 Optics OC-12/ STM-4 Optics Physical Layer ALayer Traffic Mgmt Switch Fabric
QUAD OC-12C/ STM-4C
PM7325 S/UNI-ATLAS3200
Head Office: PMC-Sierra, Inc. #105 8555 Baxter Place Burnaby, B.C. Canada Tel: 604.415.6000 Fax: 604.415.6200
order documentation, send email document@pmc-sierra.com contact head office, Attn: Document Coordinator
product documentation available site http://www.pmc-sierra.com corporate information, send email info@pmc-sierra.com
PMC-990444 (P1) 1999 PMC-Sierra, Inc. SATURN trademark PMC-Sierra, Inc.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
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