-55°C 125°C Operating Temperature Range, Processing Processed MIL

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-55°C 125°C Operating Temperature Range, Processing Processed MIL

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SMJ320C30 DIGITAL SIGNAL PROCESSOR
-55°C 125°C Operating Temperature
Range, Processing Processed MIL-PRF-38535 (QML) Performance SMJ320C30-40 (50-ns Cycle) MFLOPS MIPS SMJ320C30-50 (40-ns Cycle) MFLOPS MIPS 1K-Word 32-Bit Single-Cycle Dual-Access On-Chip Blocks Validated Compiler 64-Word 32-Bit Instruction Cache 32-Bit Instruction Data Words, 24-Bit Addresses 32-Bit Floating-Point Integer Multiplier Arithmetic Logic Unit (ALU) Parallel Multiplier Execution Single Cycle On-Chip Direct Memory Access (DMA) Controller Concurrent Operation Integer, Floating-Point, Logical Operations 4K-Word 32-Bit Single-Cycle Dual-Access On-Chip Block
32-Bit External Ports
(24- 13-Bit Address) Serial Ports With Support 32-Bit Transfers Packaging 181-Pin Grid Array Ceramic Package Suffix) 196-Pin Ceramic Quad Flatpack With Nonconductive Tie-Bar (HFG Suffix) Approval 50-MHz Versions Address Generators With Eight Auxiliary Registers Auxiliary Register Arithmetic Units (ARAUs) Zero-Overhead Loops With Single-Cycle Branches Interlocked Instructions Multiprocessing Support 32-Bit Barrel Shifter Eight Extended-Precision Registers (Accumulators) Two- Three-Operand Instructions Conditional Calls Returns Block Repeat Capability Fabricated Using Enhanced Performance Implanted CMOS (EPICt) Texas Instruments 32-Bit Timers
description
SMJ320C30 internal busing special digital signal processor (DSP) instruction speed flexibility execute MFLOPS. SMJ320C30 device optimizes speed implementing functions hardware that other processors implement through software microcode. This hardware-intensive approach provides performance previously unavailable single chip. emphasis total system cost resulted less expensive processor that designed into systems currently using costly bit-slice processors.
SMJ320C30-40: 50-ns single-cycle execution time, supply SMJ320C30-50: 40-ns single-cycle execution time, supply
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet.
EPIC trademark Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters. products compliant 38535, parameters tested unless otherwise noted. other products, production processing does necessarily include testing parameters.
Copyright 2004, Texas Instruments Incorporated
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
description (continued)
181-Pin Grid Array Package BOTTOM VIEW
196-Pin Quad Flatpack VIEW
DVDD DVSS
DVSS
DVDD
SMJ320C30 perform parallel multiply operations integer floating-point data single cycle. Each processor also possesses general-purpose register file, program cache, dedicated ARAUs, internal dual-access memories, channel supporting concurrent short machine-cycle time. High performance ease results these features. General-purpose applications enhanced large address space, multiprocessor interface, internally externally generated wait states, external interface ports, timers, serial ports, multiple interrupt structure. SMJ320C30 supports wide variety system applications from host processor dedicated coprocessor. High-level language support implemented easily through register-based architecture, large address space, powerful addressing modes, flexible instruction set, well-supported floating-point arithmetic. additional information when designing cold temperature operation, please Texas Instruments application report 320C3x, 320C4x 320MCM42x Power-up Sensitivity Cold Temperature, literature number SGUA001.
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
functional block diagram
Cache Block Block
PDATA PADDR HOLD HOLDA STRB D31- DDATA DADDR1 DADDR2 DMADATA DMAADDR
Controller Serial Port Global-Control Register Serial-Port-Control Register Receive/Transmit (R/X) Timer Register Data-Transmit Register Data-Receive Register Serial Port Serial-Port-Control Register Receive/Transmit (R/X) Timer Register FSX1 CLKX1 FSR1 CLKR1 FSX0 CLKX0 FSR0 CLKR0
RESET INT(3 IACK XF(1,0) IODVDD ADVDD PDVDD DDVDD MDVDD DVSS CVSS IVSS VBBP VSUBS CLKIN EMU(6 RSV(10 CPU1 CPU2 REG1 REG2 CPU1 REG1 REG2 Multiplier 32-Bit Barrel Shifter ExtendedPrecision Registers (R7-R0) Source-Address Register DestinationAddress Register TransferCounter Register Peripheral Address
Controller
Peripheral Data
DISP0, IR0,
ARAU0
ARAU1
Other Registers (12) Auxiliary Registers (AR0 AR7)
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Data-Transmit Register Data-Receive Register Timer
Global-Control Register Timer-Period Register Timer-Counter Register Timer Global-Control Register Timer-Period Register Timer-Counter Register Port Control Primary-Control Register Expansion-Control Register TCLK1 TCLK0
Block XRDY MSTRB IOSTRB XD31-XD0 XA12 -XA0
SMJ320C30 DIGITAL SIGNAL PROCESSOR
memory
Figure shows memory SMJ320C30. TMS320C3x User's Guide (literature number SPRU031) detailed description this memory mapping. Figure shows reset, interrupt, trap vector/branches memory-map locations. Figure shows peripheral memory-mapped registers.
Reset, Interrupt, Trap Vectors, Reserved Locations (64) (External STRB Active) Reset, Interrupt, Trap Vectors, Reserved Locations (192) (Internal) External STRB Active Words Words) 7FFFFFh 800000h 801FFFh 802000h 803FFFh 804000h 805FFFh 806000h 807FFFh 808000h 0FFFh 1000h External STRB Active Words Words) 7FFFFFh 800000h 801FFFh 802000h 803FFFh 804000h 805FFFh 806000h 807FFFh 808000h Expansion-Bus MSTRB Active Words) Reserved Words) Expansion-Bus IOSTRB Active Words) Reserved Words) Peripheral-Bus Memory-Mapped Registers Words Internal) Block Word Internal) Block Word Internal)
03Fh 040h
0BFh 0C0h
Expansion-Bus MSTRB Active Words) Reserved Words) Expansion-Bus IOSTRB Active Words) Reserved Words) Peripheral-Bus Memory-Mapped Registers Words Internal) Block Word Internal) Block Word Internal)
8097FFh 809800h 809BFFh 809C00h 809FFFh 80A000h
8097FFh 809800h 809BFFh 809C00h 809FFFh 80A000h
External STRB Active Words Words) 0FFFFFFh Microprocessor Mode 0FFFFFFh
External STRB Active Words Words)
Microcomputer Mode
Figure Memory
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
memory (continued)
TRAP Reset INT0 INT1 INT2 INT3 XINT0 RINT0 XINT1 RINT1 TINT0 TINT1 DINT Reserved TRAP Reset INT0 INT1 INT2 INT3 XINT0 RINT0 XINT1 RINT1 TINT0 TINT1 DINT Reserved
TRAP Reserved
TRAP Reserved
Microprocessor Mode
Microcomputer Mode
Figure Reset, Interrupt, Trap Vector/Branches Memory-Map Locations
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
memory (continued)
808000h 808004h 808006h 808008h 808020h 808024h 808028h 808030h 808034h 808038h 808040h 808042h 808043h 808044h 808045h 808046h 808048h 80804Ch 808050h 808052h 808053h 808054h 808055h 808056h 808058h 80805Ch 808060h 808064h Global Control Source Address Destination Address Transfer Counter Timer Global Control Timer Counter Timer Period Timer Global Control Timer Counter Timer Period Register Serial Port Global Control FSX/DX/CLKX Serial Port Control FSR/DR/CLKR Serial Port Control Serial Port Timer Control Serial Port Timer Counter Serial Port Timer Period Serial Port Data Transmit Serial Port Data Receive Serial Port Global Control FSX/DX/CLKX Serial Port Control FSR/DR/CLKR Serial Port Control Serial Port Timer Control Serial Port Timer Counter Serial Port Timer Period Serial Port Data Transmit Serial Port Data Receive Expansion-Bus Control Primary-Bus Control
Shading denotes reserved address locations
Figure Peripheral Memory-Mapped Registers
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
functions
This section gives signal descriptions SMJ320C30 devices microprocessor mode. following tables list each signal, number pins, type operating mode(s) (that input, output, high-impedance state indicated respectively), brief function description. pins labeled have special functions should connected user. line over signal name (for example, RESET) indicates that signal active (true logic-0 level). signals grouped according functions. Functions
NAME TYPE DESCRIPTION PRIMARY INTERFACE STRB I/O/Z 32-bit data port primary interface 24-bit address port primary interface Read write primary interface. high when read performed when write performed over parallel interface. External access strobe primary interface Ready. indicates that external device prepared primary interface transaction complete. Hold primary interface. When HOLD logic low, ongoing transaction completed. -A0, -D0, STRB, high-impedance state transactions over primary interface held until HOLD becomes logic high NOHOLD primary control register set. Hold acknowledge primary interface. HOLDA generated response logic HOLD. HOLDA indicates that -A0, -D0, STRB, high-impedance state that transactions over held. HOLDA high response logic high HOLD when NOHOLD primary control register set. EXPANSION INTERFACE XD31 -XD0 XA12 -XA0 MSTRB IOSTRB XRDY I/O/Z 32-bit data port expansion interface 13-bit address port expansion interface Read write signal expansion interface. When read performed, held high; when write performed, low. External memory access strobe expansion interface External access strobe expansion interface Ready signal. XRDY indicates that external device prepared expansion interface transaction complete. CONTROL SIGNALS RESET INT3 -INT0 IACK XF1, I/O/Z Reset. When RESET logic low, device reset condition. When RESET becomes logic high, execution begins from location specified reset vector. External interrupts Interrupt acknowledge. IACK logic high IACK instruction. IACK used indicate beginning interrupt-service routine. Microcomputer microprocessor mode External flags. used general-purpose support interlocked processor instructions. CONDITIONS WHEN SIGNAL
HOLD
HOLDA
input, output, high-impedance state, connect package active, HOLD active, RESET active
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
Functions (Continued)
NAME TYPE DESCRIPTION SERIAL PORT SIGNALS CLKX0 FSX0 CLKR0 FSR0 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Serial port transmit clock. CLKX0 serial-shift clock serial port transmitter. Data transmit output. Serial port transmits serial data DX0. Frame synchronization pulse transmit. FSX0 pulse initiates transmit-data process over DX0. Serial port receive clock. CLKR0 serial-shift clock serial port receiver. Data receive. Serial port receives serial data DR0. Frame synchronization pulse receive. FSR0 pulse initiates receive-data process over DR0. SERIAL PORT SIGNALS CLKX1 FSX1 CLKR1 FSR1 I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z I/O/Z Serial port transmit clock. CLKX1 serial-shift clock serial port transmitter. Data transmit output. Serial port transmits serial data DX1. Frame synchronization pulse transmit. FSX1 pulse initiates transmit-data process over DX1. Serial port receive clock. CLKR1 serial-shift clock serial port receiver. Data receive. Serial port receives serial data DR1. Frame synchronization pulse receive. FSR1 pulse initiates receive-data process over DR1. TIMER SIGNALS TCLK0 I/O/Z Timer clock input, TCLK0 used timer count external pulses. output, TCLK0 outputs pulses generated timer TIMER SIGNALS TCLK1 I/O/Z Timer clock input, TCLK1 used timer count external pulses. output, TCLK1 outputs pulses generated timer SUPPLY OSCILLATOR SIGNALS (see Note Ground Ground CONDITIONS WHEN SIGNAL
IODVDD ADVDD PDVDD DDVDD MDVDD DVSS
CVSS Ground input, output, high-impedance state, connect package active, HOLD active, RESET active Recommended decoupling capacitor NOTE CVSS, VSS, IVSS same plane.
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
Functions (Continued)
NAME TYPE DESCRIPTION SUPPLY OSCILLATOR SIGNALS (see Note (CONTINUED) IVSS VBBP VSUBS CLKIN EMU0 -EMU2 EMU3 Ground pump oscillator output Substrate pin. ground Output from internal oscillator crystal. crystal used, must left unconnected. Input internal oscillator from crystal clock External clock. period equal twice CLKIN. External clock. period equal twice CLKIN. RESERVED (see Note Reserved. pullup resistors Reserved Shutdown high impedance. When active, EMU4 shuts down SMJ320C30 places pins high-impedance state. EMU4 used board-level testing ensure that dual-drive conditions occur. CAUTION: corrupts SMJ320C30 memory register contents. Reset device with high restore known operating condition. Reserved Reserved. pins directly Reserved. pullups each CONDITIONS WHEN SIGNAL
EMU4
EMU5, EMU6 RSV0 -RSV4 RSV5 -RSV10
Locator Reserved input, output, high-impedance state, Connect package active, HOLD active, RESET active NOTES: CVSS, VSS, IVSS same plane. connections specified reserved pins must followed. best results, 18-k -22-k pullup resistors recommended. supply pins must connected common supply plane, ground pins must connected common ground plane.
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Assignments
NUMBER LOCATOR/NC IACK INT0 INT1 INT2 INT3 MSTRB RESET STRB IOSTRB NAME NUMBER NUMBER NUMBER NUMBER
NAME HOLD HOLDA XRDY FSR0 FSX0 CLKR0 CLKX0 FSR1 FSX1 CLKR1 CLKX1
NAME
NAME RSV6 RSV7 RSV8 RSV9 RSV10 ADVDD{ ADVDD{ DDVDD{ DDVDD{ IODVDD{ IODVDD{ IODVDD{ MDVDD{ MDVDD{ PDVDD{ CVSSw CVSSw VDD} VDD} VDD} VDD} VSSw VSSw VSSw VSSw VSSw VSSw VSSw VSSw VSSw VSUBS XD10
NAME XD11 XD12 XD13 XD14 XD15 XD16 XD17 XD18 XD19 XD20 XD21 XD22 XD23 XD24 XD25 XD26 XD27 XD28 XD29 XD30 XD31 DVDD DVDD DVSSW DVSSW DVSSW DVSSW IVSSw IVSSw
EMU0 EMU1 EMU2 EMU3 EMU4 EMU5 EMU6 CLKIN TCLK0 TCLK1 VBBP VSUBS VDD} VDD} VDD} VDD} VSSw XA10 XA11 XA12 RSV0 RSV1 RSV2 RSV3 RSV4 RSV5
ADVDD, DDVDD, IODVDD, MDVDD, PDVDD common plane internal device. common plane internal device. VSS, CVSS, IVSS common plane internal device. DVSS common plane internal device.
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
absolute maximum ratings over operating case temperature range (unless otherwise noted)
Supply voltage range, (see Note -0.3 Input voltage range, Output voltage range, -0.3 Continuous power dissipation (see Note 3.15 Operating case temperature range, 55°C 125°C Storage temperature range, Tstg 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: voltage values with respect VSS. Actual operating power less. This value obtained under specially produced worst-case test conditions, which sustained during normal device operation. These conditions consist continuous parallel writes checkerboard pattern both primary extension buses maximum rate possible. normal (ICC) current specification electrical characteristics table also read Calculation TMS320C30 Power Dissipation Application Report (literature number SPRA020).
recommended operating conditions (see Note
Supply voltage (AVDD, etc.) Supply voltage (CVSS, etc.) High-level input voltage High-level input voltage CLKIN Low-level input voltage High-level output current 0.3* 4.75 0.3* 0.3* 5.25 UNIT
Low-level output current Operating case temperature (see Note nominal values (ambient-air temperature)= 25°C. This parameter production tested. NOTE input output voltage levels compatible. NOTE maximum rated operating conditions point case, initial (time zero) power
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electrical characteristics over recommended ranges supply voltage (unless otherwise noted) (see Note
PARAMETER High-level output voltage XA12 -XA0 Low-level output voltage High-impedance current Input current Input current Input current CLKIN) Supply current Supply current, standby; IDLE2, clock shut Input capacitance Output capacitance others TEST CONDITIONS MIN, MIN, MIN, Inputs with internal pullups (see Note MAX, 25°C, tc(CI) MIN, Note 25°C 0.6* UNIT
CLKIN capacitance conditions shown MAX, appropriate value specified recommended operating conditions. typical values 25°C. This parameter production tested. NOTES: input output voltage levels compatible. Pins with internal pullup devices: INT0 -INT3, RSV0 -RSV10. Although RSV0 -RSV10 have internal pullup devices, external pullups should used each identified function tables. Actual operating current less than this maximum value. This value obtained under specially produced worst-case test conditions, which sustained during normal device operation. These conditions consist continuous parallel writes checkerboard pattern both primary expansion buses maximum rate possible. Calculation TMS320C30 Power Dissipation Application Report (literature number SPRA020).
PARAMETER MEASUREMENT INFORMATION
Tester Electronics
VLOAD
Output Under Test
Where:
VLOAD
(all outputs) (all outputs) Selected emulate termination (typical value 1.54 80-pF typical load-circuit capacitance
Figure Test Load Circuit
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
PARAMETER MEASUREMENT INFORMATION (CONTINUED) signal transition levels
TTL-level outputs driven minimum logic-high level maximum logic-low level Output transition times specified follows:
high-to-low transition TTL-compatible output signal, level which output said
longer high level which output said
low-to-high transition, level which output said longer level
which output said high
Figure TTL-Level Outputs Transition times TTL-compatible inputs specified follows:
high-to-low transition input signal, level which input said longer high
level which input said
low-to-high transition input signal, level which input said longer
level which input said high
Figure TTL-Level Inputs
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PARAMETER MEASUREMENT INFORMATION (CONTINUED) timing parameter symbology
Timing parameter symbols used herein were created accordance with JEDEC Standard 100-A. shorten symbols, some terminal names other related terminology have been abbreviated follows, unless otherwise noted:
ASYNCH Asynchronous reset signals include XF0, XF1, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, CLKX1, DX1, FSX1, CLKR1, DR1, FSR1, TCLK0, TCLK1 CLKX includes CLKX0 CLKX1 CLKIN Control signals include STRB, MSTRB, IOSTRB Includes DR0, Includes DX0, FSX/R includes FSX0, FSX1, FSR0, FSR1 Includes FSR0, FSR1 Includes FSX0, FSX1 General-purpose input/output; peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, TCLK0/1 Includes HOLD HOLDA IACK (M)S RESET TCLK (X)A (X)D (X)RDY (X)RW IACK INT3-INT0 IOSTRB (M)STRB includes MSTRB STRB RESET STRB CLKX/R includes CLKX0, CLKX1, CLKR0, CLKR1 TCLK0, TCLK1 Includes XA12 -XA0 Includes XD31 -XD0 includes Includes XRDY (X)R/W includes XR/W
CONTROL GPIO
HOLD HOLDA
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
X2/CLKIN, timing
following table defines timing parameters X2/CLKIN, interface signals. RESET timing Figure CLKIN delay specification.
timing parameters X2/CLKIN, (see Note Figure Figure Figure
tf(CI) tw(CIL) tw(CIH) tr(CI) tc(CI) tf(H) tw(HL) tw(HH) tr(H) td(HL-HH) Fall time, CLKIN Pulse duration, CLKIN low, tc(CI) (see Note Pulse duration, CLKIN high, tc(CI) (see Note Rise time, CLKIN Cycle time, CLKIN Fall time, Pulse duration, (see Note Pulse duration, high (see Note Rise time, Delay time, from high from high 320C30-40 320C30-50 UNIT
tc(H) Cycle time, Numbers this column match those used Figure Figure Figure This parameter production tested. NOTES: input output voltage levels compatible. Rise fall times, assuming duty cycle, incorporated within this specification (see Figure tc(CI) CLKIN (1.5
Figure CLKIN Timing
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timing parameters X2/CLKIN, (see Note Figure Figure Figure (continued)
Figure Timings
CLKIN H1/H3 Band
Band
Temperature Degrees
Figure CLKIN H1/H3 Function Temperature (Typical)
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
memory read/write timing
following table defines memory read/write timing parameters (M)STRB.
timing parameters memory [(M)STRB read/write (see Figure Figure
13.1 13.2 14.1 14.2 15.1 15.2 17.1 17.2 22.1 22.2 td[H1L-(M)SL] td[H1L-(M)SH] td(H1H-RWL) td[H1H-(X)RWL] td(H1L-A) td[H1L-(X)A] tsu(D-H1L)R tsu[(X)DR-H1L]R th[H1L-(X)D]R tsu(RDY-H1H) tsu[(X)RDY-H1H] th[H1H-(X)RDY] td[H1H-(X)RWH]W tv[H1L(X)D]W th[H1H-(X)D]W td(H1H-A) td[H1H-(X)A] td[A-(X)RDY] Delay time, (M)STRB Delay time, (M)STRB high Delay time, high Delay time, high (X)R Delay time, valid Delay time, (X)A valid Setup time, valid before (read) Setup time, (X)D before (read) Hold time, (X)D after (read) Setup time, before high Setup time, (X)RDY before high Hold time, (X)RDY after high Delay time, high (X)R high (write) Valid time, (X)D after (write) Hold time, (X)D after high (write) Delay time, high valid back-to-back write cycles (write) Delay time, high (X)A valid back-to-back write cycles (write) 320C30-40 320C30-50 UNIT
Delay time, (X)RDY from valid Numbers this column match those used Figure Figure This parameter production tested.
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memory read/write timing (continued)
(M)STRB (see Note
(X)R/W 14.1/14.2 (X)A 15.1/15.2 13.1/13.
(X)D 17.1/17.2 (X)RDY
NOTE (M)STRB remains during back-to-back read operations.
Figure Timing Memory [(M)STRB Read
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memory read/write timing (continued)
(M)STRB
13.1 13.2 (X)R 14.1 14.2 22.1 22.2 (X)A (X)D 17.1 17.2 (X)RDY
Figure Timing Memory [(M)STRB Write
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
memory read/write timing (continued)
following table defines memory read timing parameters IOSTRB.
timing parameters memory (IOSTRB read (see Figure
td(H1H-IOSL) td(H1H-IOSH) td[H1L-(X)RWH] td[H1L-(X)A] tsu[(X)D-H1H]R th[H1H-(X)D]R tsu[(X)RDY-H1H] th[H1H-(X)RDY] Delay time, high IOSTRB Delay time, high IOSTRB high Delay time, (X)R high Delay time, (X)A valid Setup time, (X)D before high Hold time, (X)D after high Setup time, (X)RDY before high 320C30-40 320C30-50 UNIT
Hold time, (X)RDY after high Numbers this column match those used Figure This parameter production tested.
IOSTRB (X)R (X)A (X)D (X)RDY
Figure Timing Memory (IOSTRB Read
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
memory read/write timing (continued)
following table defines memory write timing parameters IOSTRB.
timing parameters memory (IOSTRB write (see Figure
td(H1H-IOSL) td(H1H-IOSH) td[H1L-(X)RWH] td[H1L-(X)A] tsu[(X)RDY-H1H] th[H1H-(X)RDY] td(H1L-XRWL) tv[H1H(X)D]W Delay time, high IOSTRB Delay time, high IOSTRB high Delay time, (X)R high Delay time, (X)A valid Setup time, (X)RDY before high Hold time, (X)RDY after high Delay time, Valid time, (X)D after high 320C30-40 320C30-50 UNIT
th[H1L-(X)D]W Hold time, (X)D after Numbers this column match those used Figure This parameter production tested.
IOSTRB (X)R (X)A (X)D (X)RDY
Figure Timing Memory (IOSTRB Write
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
timing when executing LDFI LDII
following table defines timing parameters during execution LDFI LDII.
timing parameters when executing LDFI LDII (see Figure
td(H3H-XF0L) tsu(XF1-H1L) Delay time, high Setup time, valid before 320C30-40 320C30-50 UNIT
th(H1L-XF1) Hold time, after Numbers this column match those used Figure
Fetch LDFI LDII
Decode
Read
Execute
(M)STRB
(X)R
(X)A
(X)D
(X)RDY
Figure Timing When Executing LDFI LDII
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
timing when executing STFI STII
following table defines timing parameters during execution STFI STII.
timing parameters when executing STFI STII (see Figure
td(H3H-XF0H) Delay time, high high number this column matches that used Figure 320C30 320C30 UNIT
Fetch STFI STII
Decode
Read
Execute
(M)STRB
(X)R/W
(X)A
(X)D
(X)RDY
Figure Timing When Executing STFI STII
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
timing when executing SIGI
following table defines timing parameters pins during execution SIGI.
timing parameters when executing SIGI (see Figure
41.1 td(H3H-XF0L) td(H3H-XF0H) tsu(XF1-H1L) th(H1L-XF1) Delay time, high Delay time, high high Setup time, valid before Hold time, after 320C30 320C30 UNIT
Numbers this column match those used Figure Fetch SIGI
Decode
Read
Execute
41.1
Figure Timing When Executing SIGI
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
loading when configured output
following table defines timing parameter loading register when configured output.
timing parameters loading register when configured output (see Figure
tv(H3H-XF) Valid time, high valid number this column matches that used Figure 320C30 320C30 UNIT
Fetch Load Instruction
Decode
Read
Execute
OUTXF
NOTE OUTXFx represents either register.
Figure Timing Loading Register When Configured Output
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
changing from output input
following table defines timing parameters changing from output input pin.
timing parameters changing from output input mode (see Figure
td(H3H-XFx) tsu(XFx-H1L) Delay time, after high Setup time, before 320C30 320C30 UNIT
th(H1L-XFx) Hold time, after Numbers this column match those used Figure This parameter production tested.
Execute Load
Buffers From Output Input
Synchronizer Delay
Value Terminal Seen
I/OXFx (see Note Output
INXFx (see Note
Data Sampled
Data Seen
NOTE OXFx represents either register, INXFx represents either register depending whether XF1, respectively, being affected.
Figure Timing Change From Output Input Mode
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changing from input output
following table defines timing parameter changing from input output pin.
timing parameters changing from input output mode (see Figure
td(H3H-XFIO) Delay time, high switching from input output number this column matches that used Figure 320C30 320C30 UNIT
Execution Load
I/OXFx (see Note (see Note NOTE OXFx represents either register, INXFx represents either register depending whether XF1, respectively, being affected.
Figure Timing Change From Input Output Mode
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SMJ320C30 DIGITAL SIGNAL PROCESSOR
reset timing
RESET asynchronous input that asserted time during clock cycle. specified timings met, exact sequence shown Figure occurs; otherwise, additional delay clock cycle occur. high-impedance state during reset provided with resistive pullup, nominally prevent spurious writes from occurring. asynchronous reset signals include XF0/1, CLKX0/1, DX0/1, FSX0/1, CLKR0/1, DR0/1, FSR0/1, TCLK0/1. HOLD asynchronous input asserted during reset. Resetting device initializes primary- expansion-bus control registers seven software wait states and, therefore, results slow external accesses until these registers initialized.
timing parameters RESET tc(CI)] (see Figure Figure
320C30 tsu(RESET) td(CLKINH-H1H) td(CLKINH-H1L) tsu(RESETH-H1L) td(CLKINH-H3L) td(CLKINH-H3H) tdis(H1H-XD) tdis(H3H-XA) td(H3H-CONTROLH) td(H1H-IACKH) tdis(RESETL-ASYNCH) Setup time, RESET before CLKIN Delay time, CLKIN high high Delay time, CLKIN high Setup time, RESET high before after clock cycles Delay time, CLKIN high Delay time, CLKIN high high Disable time, high (X)D high-impedance state Disable time, high (X)A high-impedance state Delay time, high control signals high Delay time, high IACK high Disable time, RESET asynchronous reset signals high-impedance state 320C30 UNIT
Figure temperature dependence 40-MHz SMJ320C30. This parameter production tested.
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reset timing (continued)
CLKIN RESET Clock Cycles (X)D (see Note (X)A (see Note Control Signals (see Note IACK Asynchronous Reset Signals (see Note NOTES:
this diagram X(D) includes XD31 -XD0. this diagram, (X)A includes XA12 -XA0. Control signals include STRB, MSTRB, IOSTRB. Asynchronous reset signals include XF1, XF0, CLKX0, DX0, FSX0, CLKR0, DR0, FSR0, CLKX1, DX1, FSX1, CLKR1, DR1, FSR1, TCLK0, TCLK1. microprocessor mode, reset vector fetched twice, with seven software wait states each time. micromputer mode, reset vector fetched twice, with software wait states.
Figure Timing Reset tc(Cl)]
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interrupt-response timing
following table defines timing parameters signals.
timing parameters INT3-INT0 tc(H)] (see Figure
320C30 tsu(INT) tw(INT) Setup time, INT3 -INT0 before Pulse duration, INT3 -INT0, assure only interrupt seen 320C30 UNIT
This parameter production tested.
interrupt (INT) pins asynchronous inputs that asserted time during clock cycle. SMJ320C30 interrupts level-sensitive, edge-sensitive. Interrupts detected falling edge Therefore, interrupts must held falling edge proper detection. respond detected interrupts instruction-fetch boundaries only. processor recognize only interrupt given input, interrupt pulse must held
minimum falling edge more than falling edges
SMJ320C30 accept interrupt from same source every clock cycles. specified timings met, exact sequence shown Figure occurs; otherwise, additional delay clock cycle possible.
Reset Interrupt Vector Read Fetch First Instruction Service Routine
INT3 -INT0 Pins INT3 -INT0 Flag Vector Address Addr First Instruction Address
Data
Figure Timing INT3 -INT0 Response tc(H)]
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interrupt-acknowledge timing
IACK output goes active first half-cycle rising) decode phase IACK instruction goes inactive first half-cycle rising) read phase IACK instruction. following table defines timing parameters IACK signal.
timing parameters IACK (see Figure
td(H1H-IACKL) td(H1H-IACKH) Delay time, high IACK Delay time, high IACK high 320C30 320C30 UNIT
Numbers this column match those used Figure
Fetch IACK Instruction
IACK Data Read
IACK
Address
Data
Figure Timing Interrupt-Acknowledge (IACK)
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serial-port timing parameters (see Figure Figure
td(H1-SCK) tc(SCK) CLOCK SOURCE Delay time, high internal CLKX Cycle time, CLKX Pulse duration, CLKX high CLKX CLKX CLKX CLKX 2.5* tc(H)+12* [tc(SCK) [tc(SCK) 2]+5 -[tc(H) -[tc(H) -21] [tc(SCK) -10* tc(SCK) CLKR CLKX CLKX CLKX CLKX CLKX CLKX -[tc(H) -[tc(H) -21] [tc(SCK) -10* tc(SCK) CLKR CLKR CLKR CLKX CLKX CLKR 320C30 2.6* tc(H)+10* [tc(SCK) [tc(SCK) 2]+5 CLKX CLKR 320C30 UNIT
232*
232*
tw(SCK) tr(SCK) tf(SCK) td(DX)
Rise time, CLKX Fall time, CLKX Delay time, CLKX valid Setup time, before CLKR Hold time, from CLKR Delay time, CLKX internal high Setup time, before CLKR Hold time, input from CLKX Setup time, external before CLKX high Delay time, CLKX first bit, precedes CLKX high CLKX
tsu(DR)
th(DR)
td(FSX)
tsu(FSR)
th(FS)
tsu(FSX)
td(CH-DX)V
td(FSX-DX)V tdDXZ
Delay time, first bit, CLKX precedes Delay time, CLKX high high impedance following last data
This parameter production tested.
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serial-port timing parameters (continued)
Unless otherwise indicated, data-rate timings shown Figure Figure valid serial-port modes, including handshake. serial-port timing parameter tables. Timing diagrams shown Figure Figure show operations with serial port global-control register bits CLKXP CLKRP FSXP FSRP Timing diagrams shown Figure Figure depend upon length serial-port word, where bits, respectively.
CLKX/ (int) (ext)
Figure Serial-Port Timing Fixed-Data-Rate Mode
CLKX (int) (ext)
NOTE Timings expressly specified variable-data-rate mode same those fixed-data-rate mode.
Figure Serial-Port Timing Variable-Data-Rate Mode
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HOLD timing
HOLD asynchronous input that asserted time during clock cycle. specified timings met, exact sequence shown Figure occurs; otherwise, additional delay clock cycle possible. "timing parameters HOLD HOLDA" table defines timing parameters HOLD HOLDA signals. NOHOLD primary control register overrides HOLD signal. When this set, device comes hold prevents future hold cycles. Asserting HOLD prevents processor from accessing primary bus. Program execution continues until read from write primary requested. certain circumstances, first write pending, allowing processor continue until second write encountered.
HOLD/HOLDA timing (see Figure
tsu(HOLD) tv(HOLDA) tw(HOLD) tw(HOLDA) td(H1L-SH)H tdis(H1L-S) ten(H1L-S) tdis(H1L-RW) ten(H1L-RW) tdis(H1L-A) ten(H1L-A) tdis(H1H-D) Setup time, HOLD before Valid time, HOLDA after Pulse duration, HOLD Pulse duration, HOLDA Delay time, STRB high HOLD Disable time, STRB high impedance Enable time, STRB active Disable time, high impedance Enable time, active Disable time, address high impedance Enable time, address valid Disable time, high data high impedance 320C30 2tc(H) tc(H) 320C30 2tc(H) tc(H) UNIT
Numbers this column used Figure This parameter production tested.
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HOLD/HOLDA timing (continued)
HOLD HOLDA (see Note (M)STRB STRB
Write Data
NOTE HOLDA goes response HOLD going continues remain through cycle after HOLD returns high.
Figure Timing HOLD/HOLDA
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general-purpose timing
Peripheral pins include CLKX0/1, CLKR0/1, DX0/1, DR0/1, FSX0/1, FSR0/1, TCLK0/1. contents internal-control registers associated with each peripheral define modes these pins. peripheral timing following table defines peripheral general-purpose timing parameters.
timing parameters peripheral general-purpose (see Note Figure
tsu(GPIOH1L) th(GPIOH1L) Setup time, general-purpose input before Hold time, general-purpose input after 320C30 320C30 UNIT
td(GPIOH1H) Delay time, general-purpose output after high Numbers this column used Figure This parameter production tested. NOTE Peripheral pins include CLKX0 CLKR0 FSX0 FSR0 TCLK0 modes these pins defined contents internal control registers associated with each peripheral.
Peripheral
Figure Timing Peripheral General-Purpose
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changing peripheral modes following tables show timing parameters changing peripheral from general-purpose output general-purpose input reverse.
timing parameters peripheral changing from general-purpose output input mode (see Note Figure
th(H1H) tsu(GPIOH1L) Hold time after high Setup time, peripheral before 320C30 320C30 UNIT
th(GPIOH1L) Hold time, peripheral after Numbers this column used Figure NOTE Peripheral pins include CLKX0 CLKR0 FSX0 FSR0 TCLK0 modes these pins defined contents internal control registers associated with each peripheral.
Execute Store Peripheral Control Register
Buffers From Output Input
Synchronizer Delay
Value Terminal Seen Peripheral Control Register
Control Peripheral Output
Data Data Sampled Data Seen
Figure Timing Change Peripheral From General-Purpose Output Input Mode
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timing parameters peripheral changing from general-purpose input output mode (see Figure
320C30 td(GPIOH1H) Delay time, high peripheral switching from input output 320C30 UNIT
Execution Store Peripheral Control Register
Control Peripheral
Figure Timing Change Peripheral From General-Purpose Input Output Mode
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timer (TCLK0 TCLK1) timing
Valid logic-level periods polarity specified contents internal control registers. following table defines timing parameters timer pin.
timing parameters timer (TCLK0 TCLK1) (see Figure
320C30 tsu(TCLK-H1L) Setup time, TCLK before Hold time, TCLK after Delay time, high TCLK valid Cycle time, TCLK Pulse duration, TCLK high TCLK 320C30
UNIT
th(TCLK-H1L)
TCLK
td(TCLK-H1H)
TCLK TCLK TCLK TCLK TCLK tc(H) 2.6* tc(H) tc(H) [tc(TCLK)
tc(H) 2.6* tc(H) tc(H) [tc(TCLK)
tc(TCLK) tw(TCLK)
tc(H) 232* [tc(TCLK) 2]+5
tc(H) 232* [tc(TCLK) 2]+5
Numbers this column used Figure Timing parameters applicable synchronous input clock. Timing parameters applicable asynchronous input clock. This parameter production tested.
Timer NOTE Period polarity valid logic level specified contents internal control registers.
Figure Timing Timer
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timing
following table defines timing parameter pin.
timing parameters (see Figure
tdis(SHZ) ten(SHZ) Disable time, high impedance Enable time, high active 320C30 320C30 UNIT
Numbers this column used Figure This parameter production tested.
(see Note
NOTE Enabling destroys SMJ320C30 register memory contents. Assert reset SMJ320C30 restore known condition.
Figure Timing
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SMJ320C30 part order information
DEVICE SMJ320C30GBM40 SM320C30GBM40 SMJ320C30HFGM40 SM320C30HFGM40 5962-9052604MXA 5962-9052604MUA SMJ320C30GBM50 SM320C30GBM50 SMJ320C30HFGM50 SM320C30HFGM50 5962-9052605MXA 5962-9052605MUA TECHNOLOGY 0.7-µm CMOS 0.7-µm CMOS 0.7-µm CMOS 0.7-µm CMOS 0.7-µm CMOS 0.7-µm CMOS 0.7-µm CMOS 0.7-µm CMOS 0.7-µm CMOS 0.7-µm CMOS 0.7-µm CMOS 0.7-µm CMOS POWER SUPPLY OPERATING FREQUENCY PACKAGE TYPE Ceramic 181-pin Ceramic 181-pin Ceramic 196-pin quad flatpack with nonconductive Ceramic 196-pin quad flatpack with nonconductive Ceramic 181-pin Ceramic 196-pin quad flatpack with nonconductive Ceramic 181-pin Ceramic 181-pin Ceramic 196-pin quad flatpack with nonconductive Ceramic 196-pin quad flatpack with nonconductive Ceramic 181-pin Ceramic 196-pin quad flatpack with nonconductive PROCESSING LEVEL Standard Standard DESC DESC Standard Standard DESC DESC
PREFIX
MIL-STD-38535 (QML) Standard Processing
SPEED RANGE
DEVICE FAMILY SMJ320 Family
TEMPERATURE RANGE 55°C 125°C 70°C PACKAGE TYPE 181-Pin Grid Array (PGA) Ceramic Package 196-Pin Ceramic Quad Flatpack with nonconductive Known Good
TECHNOLOGY CMOS
DEVICE 320C30
Figure SMJ320C30 Device Nomenclature
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MECHANICAL DATA
(S-CQFP-F196)
1.365 (34,67) 1.325 (33,66) 1.200 (30,48) 0.600 (15,20) 0.225 (5,72) Width 0.175 (4,45)
CERAMIC QUAD FLATPACK WITH
Thermal Resistance Characteristics PARAMETER °C/W 28.9
2.505 (63,63) 2.485 (63,12)
1.710 (43,43) 1.690 (42,93)
1.150 (29,21) Places 0.061 (1,55) Places 0.059 (1,50)
0.105 (2,67) 0.018 (0,46)
0.010 (0,25) 0.006 (0,15) Braze 0.014 (0,36) 0.002 (0,05)
0.040 (1,02) 0.030 (0,76) 0.025 (0,64) DETAIL 0.020 (0,51) DETAIL
0.008 (0,20) 0.004 (0,10)
0.130 (3,30) DETAIL 4040231-6 04/96
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. Ceramic quad flatpack with flat leads brazed nonconductive tie-bar carrier This package hermetically sealed with metal lid. terminals will gold plated. Falls within JEDEC -113
above data applies SMJ320C30 196-pin QFP.
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MECHANICAL DATA (CONTINUED)
GA-GB (S-CPGA-P15
CERAMIC GRID ARRAY PACKAGE
1.400 (35,56)
0.050 (1,27) Places 0.022 (0,55) 0.016 (0,41) 0.140 (3,56) 0.120 (3,05) 0.100 (2,54)
1.540 (39,12) 1.480 (37,59) 0.110 (2,79) 0.095 (2,41) 0.040 (1,02) 0.025 (0,63)
1.590 (40,38) 1.535 (38,99) 0.205 (5,21) 0.205 (5,21) 0.060 (1,52) 0.060 (1,52)
Notes Large Outline Small Outline Cavity Cavity Down Cavity Cavity Down
MAXIMUM PINS WITHIN MATRIX
4040114-8 04/96 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Index mark appear bottom depending package vendor. Pins located within 0.010 (0,25) diameter true position relative each other maximum material condition within 0.030 (0,76) diameter relative edges ceramic. This package hermetically sealed with metal lids with ceramic lids using glass frit. pins gold plated solder dipped. Falls within MIL-STD-1835 CMGA7-PN CMGA19-PN JEDEC MO-067AG MO-066AG, respectively Thermal Resistance Characteristics PARAMETER °C/W 26.6
above data applies SMJ320C30 181-pin PGA.
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PACKAGE OPTION ADDENDUM
www.ti.com
2-May-2005
PACKAGING INFORMATION
Orderable Device 5962-9052604MUA 5962-9052604MXA 5962-9052604Q9A 5962-9052605MUA 5962-9052605MXA 5962-9052605QXC SM320C30GBM40 SM320C30GBM50 SM320C30HFGM40 SM320C30HFGM50 SMJ320C30GBM40 SMJ320C30GBM50 SMJ320C30HFGM40 SMJ320C30HFGM50
Status ACTIVE ACTIVE OBSOLETE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE ACTIVE
Package Type CPGA XCEPT CPGA CPGA CPGA CPGA CPGA CPGA
Package Drawing
Pins Package Plan
Lead/Ball Finish Call Call Call Call Call Call Call Call Call Call Call Call Call Call
Peak Temp Level-NC-NC-NC Level-NC-NC-NC Call Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC Level-NC-NC-NC
marketing status values defined follows: ACTIVE: Product device recommended designs. LIFEBUY: announced that device will discontinued, lifetime-buy period effect. NRND: recommended designs. Device production support existing customers, does recommend using this part design. PREVIEW: Device been announced production. Samples available. OBSOLETE: discontinued production device.
Plan planned eco-friendly classification: Pb-Free (RoHS) Green (RoHS Sb/Br) please check latest availability information additional product content details. TBD: Pb-Free/Green conversion plan been defined. Pb-Free (RoHS): TI's terms "Lead-Free" "Pb-Free" mean semiconductor products that compatible with current RoHS requirements substances, including requirement that lead exceed 0.1% weight homogeneous materials. Where designed soldered high temperatures, Pb-Free products suitable specified lead-free processes. Green (RoHS Sb/Br): defines "Green" mean Pb-Free (RoHS compatible), free Bromine (Br) Antimony (Sb) based flame retardants exceed 0.1% weight homogeneous material)
MSL, Peak Temp. Moisture Sensitivity Level rating according JEDEC industry standard classifications, peak solder temperature. Important Information Disclaimer:The information provided this page represents TI's knowledge belief date that provided. bases knowledge belief information provided third parties, makes representation warranty accuracy such information. Efforts underway better integrate information from third parties. taken continues take reasonable steps provide representative accurate information have conducted destructive testing chemical analysis incoming materials chemicals. suppliers consider certain information proprietary, thus numbers other limited information available release. event shall TI's liability arising such information exceed total purchase price part(s) issue this document sold Customer annual basis.
Addendum-Page
MECHANICAL DATA
MCFP023C JANUARY 1995 REVISED JUNE 1999
(S-CQFP-F196)
1.365 (34,67) 1.335 (33,91) 1.200 (30,48)
CERAMIC QUAD FLATPACK WITH NCTB
0.225 (5,72) 0.175 (4,45)
Width
1.710 (43,43) 1.690 (42,93) 2.505 (63,63) 2.485 (63,12)
1.150 (29,21) Places 0.061 (1,55) Places 0.059 (1,50)
0.105 (2,67)
0.018 (0,46) 0.013 (0,33) 0.007 (0,18) Braze 0.014 (0,36) 0.002 (0,05) 0.130 (3,30) DETAIL 4040231-6/J 01/99
0.040 (1,02) 0.030 (0,76) 0.025 (0,64) DETAIL 0.020 (0,51) DETAIL
0.009 (0,23) 0.004 (0,10)
NOTES:
linear dimensions inches (millimeters). This drawing subject change without notice. Ceramic quad flatpack with flat leads brazed non-conductive carrier This package hermetically sealed with metal lid. leads gold-plated solder-dipped. Leads shown clarity purposes Falls within JEDEC MO-113AB
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MECHANICAL DATA
MCPG014A FEBRUARY 1996 REVISED JANUARY
(S-CPGA-P181)
CERAMIC GRID ARRAY
1.590 (40,40) 1.560 (39,62)
1.400 (35,56) 0.100 (2,54)
Corner
Bottom View
0.185 (4,70) 0.140 (3,55)
0.055 (1,40) 0.045 (1,14)
0.050 (1,27) Places 0.022 (0,55) 0.016 (0,41)
0.140 (3,56) 0.120 (3,05)
4073426/C 11/01 NOTES: linear dimensions inches (millimeters). This drawing subject change without notice. Index mark appear bottom, depending package vendor. Pins located within 0.010 (0,25) diameter true position relative each other maximum material condition within 0.030 (0,76) diameter relative edge ceramic. This package hermetically sealed with metal lids with ceramic lids using glass frit. pins gold-plated solder-dipped. Falls within MIL-STD-1835 CMGA7-PN
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-55°C 125°C Operating Temperature Range, Processing Processed MIL

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