RTL8019AS Realtek Full-Duplex Ethernet Controller with Plug Play Funct

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

RTL8019AS Realtek Full-Duplex Ethernet Controller with Plug Play Funct

Datasheet Thumbnail

Top Searches for this datasheet

SPECIFICATION RTL8019AS
RTL8019AS Realtek Full-Duplex Ethernet Controller with Plug Play Function (RealPNP)
REALTEK SEMICONDUCTOR CORP.
HEAD OFFICE
INDUSTRY SCIENCE-BASED INDUSTRIAL PARK, HSINCHU 300, TAIWAN, R.O.C. TEL: 886-3-5780211 FAX: 886-3-5776047
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
CONTENTS
FEATURES GENERAL DESCRIPTION CONFIGURATION DESCRIPTION 4.1. Power Pins 4.2. Interface Pins 4.3. Memory Interface Pins (including BROM, EEPROM) 4.4. Medium Interface Pins 4.5. Output Pins REGISTER DESCRIPTIONS 5.1. Group NE2000 Registers 5.1.1. Register Table 5.1.2. Register Functions 5.1.2.1. NE2000 Compatible Registers 5.1.2.2. RTL8019AS Defined Registers 5.2. Group Plug Play (PnP) Registers 5.2.1. Card Control Registers 5.2.2. Logical Device Control Registers 5.2.3. Logical Device Configuration Registers FUNCTIONAL DESCRIPTIONS 6.1. RTL8019AS Configuration Modes 6.2. Plug Play 6.2.1. Initiation 6.2.2. Isolation Protocol 6.2.3. Plug Play Isolation Sequence 6.2.4. Reading Resource Data 6.2.5. auto detect mode 6.3. 9346 Contents 6.4. Boot 6.5. Behaviors 6.6. Loopback Diagnostic Operation 6.6.1. Loopback Operation 6.6.2. implement Loopback Test Electrical Specification Timings 7.1. Absolute Maximum Ratings 7.2. D.C. Characteristics 7.3. A.C. Timing Characteristics
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
FEATURES
100-pin PQFP RTL8019 software compatible Supports auto detect mode (RTL8019AS only) Compliant Ethernet IEEE802.3 10Base5, 10Base2, 10BaseT Software compatible with NE2000 both 16-bit slots Supports both jumper jumperless modes Supports Microsoft`s Plug Play configuration jumperless mode Supports Full-Duplex Ethernet function double channel bandwidth Supports three level power down modes: Sleep Power down with internal clock running Power down with internal clock halted Built-in data prefetch function improve performance Supports UTP, auto-detect (RTL8019AS only) Supports auto polarity correction 10BaseT Support lines Supports base address options extra address fully decode mode (RTL8019AS only) Supports 16K, 32K, 16K-page mode access BROM pages with bytes/page) Supports BROM disable command release memory after remote boot Supports flash memory read/write (RTL8019AS only) byte SRAM built (RTL8019AS only) 9346 (64*16-bit EEPROM) store resource configurations parameters Capable programming blank 9346 board manufacturing convenience Support diagnostic pins with programmable outputs
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
General Description
RTL8019AS highly integrated Ethernet Controller which offers simple solution implement Plug Play NE2000 compatible adapter with full-duplex power down features. With three level power down control features, RTL8019AS made ideal choice network device GREEN system. full-duplex function enables simultaneously transmission reception twisted-pair link full-duplex Ethernet switching hub. This feature only increases channel bandwidth from Mbps also avoids performance degrading problem channel contention characteristics Ethernet CSMA/CD protocol. Microsoft's Plug Play function relieve users from pains taking care adapter's resource configurations such IRQ, I/O, memory address, etc. However, special applications used Plug Play compatible device, RTL8019AS also supports jumper proprietary jumperless options. offer fully plug play solution, RTL8019AS provides auto-detect capability between integrated 10BaseT transceiver, interface. Besides, 10BaseT transceiver automatically correct polarity error receiving pair. Furthermore, lines base address options provided grand resource configuration flexibility. RTL8019AS supports 16k, byte BROM fiash memory interface. also offers page mode function which support 4M-byte BROM within only 16k-byte system memory space. Besides, BROM disable command provided release BROM memory space other system usage (e.g. EMM386, etc.) after BROM program loaded. RTL8019AS built with 16K-byte SRAM single chip. designed only provide more friendly functions also save effort SRAM sourcing inventory.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
CONFIGURATION
BA21 [PNP] BA20 [BS0] BA19 [BS1] BA18 [BS2] BA17 [BS3] BA16 [BS4] BA15 BA14 [PL0] BCSB EECS [PL1][EEDO] [IRQS0][EEDI] [IRQS1][EESK] [IRQS2]
LED2 [LED_TX] LED1 [LED_RX] [LED_CRS] LED0 [LED_COL] [LED_LINK] LEDBNC TPIN+ TPINVDD RXCD+ CDGND
[IOS0] [IOS1] [IOS2] [IOS3] SD15 SD14 SD13 SD12 SD11 SD10 IOCS16B [SLOT16] INT7 [IRQ15] INT6 [IRQ12] INT5 [IRQ11] INT4 [IRQ10]
RTL8019AS
TXVDD TPOUTTPOUT+ IOCHRDY RSTDRV SMEMWB SMEMRB
INT3 [IRQ5] INT2 [IRQ4] INT1 [IRQ3] INT0 [IRQ2/9]
IOWB IORB SA19 SA18 SA17 SA16 SA15 SA14 SA13 SA12 SA11 SA10
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
DESCRIPTIONS
4.1. Power Pins
Name Type power Ground Description
4.2. Interface Pins
97-100, Name INT7-0 Type Descriptions Address Enable. This signal must valid command. Interrupt request lines which mapped IRQ15, IRQ12, IRQ11, IRQ10, IRQ5, IRQ4, IRQ3, IRQ2/9 respectively. Only line selected reflect interrupt requests time. other lines tri-stated. RTL8019AS also uses these pins inputs monitor actual state corresponding interrupt lines bus. result recorded INTR register, which used software detect interrupt conflict. This signal driven insert wait cycles current host read/write command. Upon power-on reset, this acts input named SLOT16 detect whether 16-bit 8-bit slot use. this, connected pull-down resistor (about 27KW) externally. falling edge RSTDRV, RTL8019AS senses this pin's state. sensed high, adapter thought placed 16-bit slot where this connected host's IOCS16B pin, which typically pulled 300W resistor mother board. sensed low, adapter thought placed 8-bit slot where this merely pulled 27KW resistor. After having latched input state, this switched IOCS16B signal which open-drain output driven during 16-bit host data transfer. decoded from SA9-0. Host read command. Host write command. High active hardware reset signal from bus. Pulses with high level less than 800ns ignored. Host address bus. SA10 added implement fully decode ports, address 279h A79h. RTL8019, SA10 decoded. RTL8019AS, SA10 should valid access ports. Host data bus. Host memory read command.
IOCHRDY IOCS16B [SLOT16]
27-18, 1615, 13-7,
IORB IOWB RSTDRV SA19-0
87-88, 9095, 43-36
SD15-0 SMEMRB
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
SMEMWB Host memory write command. This added decode write command flash memory.
4.3. Memory Interface Pins (including BROM, EEPROM)
Name BCSB Type Description BROM chip select. Active signal, asserted when BROM read. RTL8019AS drives this when SA19-14 matches selected BROM memory base address either conditions below meets: SMEMRB SMEMWB RTL8019AS's flash memory write function enabled. 66-69, 71-74 77-82, 84-85 [79] [78] [77] EECS BA21-14 BD7-0 [EESK] [EEDI] [EEDO] 9346 chip select. Active high signal, asserted when 9346 read/write. BROM address. BROM data bus. 9346 serial data clock 9346 serial data input 9346 serial data output following pins defined jumper options. Their states latched falling edge RSTDRV, then they changed serve SRAM bus. Each them internally pulled down 100KW resistor. Therefore, input will when left open high when pulled resistor externally. [66] [PNP] When high jumperless mode (i.e. JP=low), RTL8019AS forced into Plug Play mode regardless contents 9346. following pins don't care jumperless mode (JP=low). [72-71, 69-67] [85-84, 82-81] [77, [80-78] [BS4-0] [IOS3-0] [PL1-0] [IRQS2-0] Select BROM size base address. Select base address. Select network medium type. Select interrupt line among INT7-0. When high, this selects jumper mode. When low, selects jumperless modes (including jumperless Plug Play).
After RTL8019AS latches jumper status upon power reset, these pins always* reflect value BPAGE register directly BROM page mode. normal mode, BA16-21 used BA14-15 BROM Size BA14 high SA14 SA14 BA15 high high SA15
*Note: RTL8019AS doesn't drive BA14-21 until SMEMRB goes from high low.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
4.4. Medium Interface Pins
Name Type Description This input used detect usage external interface. input should driven embedded high external MAU. When input high, RTL8019AS sets (bit5) CONFIG0 drives LEDBNC disable BNC. this used, should connected such that RTL8019AS acts like RTL8019. Please refer section 5.1.2.2. CONFIG0 more details. This collision input pair carries differential collision input signal from MAU. This receive input pair carries differential receive input signal from MAU. This transmit output pair contains differential line drivers which send Manchester encoded data MAU. These outputs source followers require pulldown resistors GND. This input pair receives Mbits/s differential Manchester encoded data from twisted-pair wire. This pair carries differential transmit output. output Manchester encoded signals have been pre-distorted prevent overcharge twisted-pair media thus reduce jitter. 20Mhz crystal external oscillator input. Crystal feedback output. This output used crystal connection only. must left open when driven with external oscillator.
54,53 56,55 49,48
CD+,CDRX+,RXTX+,TX-
59,58
TPIN+, TPIN-
45,46
TPOUT+, TPOUT-
4.5. Output Pins
Name LEDBNC Type Description This goes high when RTL8019AS's medium type 10Base2 mode auto-detect mode with link test failure. Otherwise, this low. This used control power convertor connected indicate used medium type. When LEDS0 CONFIG3 register RTL8019AS Page3) this acts LED_COL. When LEDS0=1, acts LED_LINK. When LEDS1 CONFIG3 register RTL8019AS Page3) these pins LED_RX LED_TX respectively. When LEDS1=1, these pins LED_CRS MCSB. Please refer section details lightening behavior LEDs.
LED0
62,63
LED1,LED2
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
Register Descriptions
registers RTL8019AS roughly divided into groups their address functions NE2000, other Plug Play (PnP). 5.1. Group NE2000 Registers This group includes pages registers which selected register. Each page contains registers. Besides those registers compatible with NE2000, RTL8019AS defines some registers software configuration feature enhancement. 5.1.1. Register Table (Hex) 10-17 18-1F
CLDA0 CLDA1 BNRY FIFO CRDA0 CRDA1
Page0
PSTART PSTOP BNRY TPSR TBCR0 TBCR1 RSAR0 RSAR1 RBCR0 8019ID0 RBCR1 8019ID1 CNTR0 CNTR1 CNTR2 Remote Port Reset Port
Page1 [R/W]
PAR0 PAR1 PAR2 PAR3 PAR4 PAR5 CURR MAR0 MAR1 MAR2 MAR3 MAR4 MAR5 MAR6 MAR7
Page2
PSTART PSTOP
Page3
9346CR BPAGE CONFIG1 CONFIG2 CONFIG3 TEST HLTCLK FMWP
TPSR
9346CR BPAGE CONFIG0 CONFIG1 CONFIG2 CONFIG3 CSNSAV INTR CONFIG4
Notes: denotes reserved. Registers with names typed bold italic format RTL8019AS defined registers supported standard NE2000 adapter.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
Page (PS1=0, PS0=0)
Name
CLDA0 PSTART CLDA1 PSTOP BNRY TPSR TBCR0 FIFO TBCR1 CRDA0 RSAR0 CRDA1 RSAR1 8019ID0 RBCR0 8019ID1 RBCR1 CNTR0 CNTR1 CNTR2
Type
TBC7 TBC15 RBC7 RBC15 CNT7 CNT7 CNT7
TBC6 TBC14 RBC6 RBC14 CNT6 CNT6 CNT6 RDCE
TBC5 TBC13 RBC5 RBC13 CNT5 CNT5 CNT5 CNTE
TBC4 TBC12 RBC4 RBC12 CNT4 OFST CNT4 CNT4 OVWE
TBC3 TBC11 RBC3 RBC11 CNT3 CNT3 CNT3 TXEE
TBC2 TBC10 RBC2 RBC10 CNT2 CNT2 CNT2 RXEE
TBC1 TBC9 RBC1 RBC9 CNT1 CNT1 CNT1 PTXE
TBC0 TBC8 RBC0 RBC8 CNT0 CNT0 CNT0 PRXE
Page (PS1=0, PS0=1)
Name PAR0 PAR1 PAR2 PAR3 PAR4 PAR5 CURR MAR0 MAR1 MAR2 MAR3 MAR4 MAR5 MAR6 MAR7 Type DA15 DA23 DA31 DA39 DA47 FB15 FB23 FB31 FB39 FB47 FB55 FB63 DA14 DA22 DA30 DA38 DA46 FB14 FB22 FB30 FB38 FB46 FB54 FB62 DA13 DA21 DA29 DA37 DA45 FB13 FB21 FB29 FB37 FB45 FB53 FB61 DA12 DA20 DA28 DA36 DA44 FB12 FB20 FB28 FB36 FB44 FB52 FB60 DA11 DA19 DA27 DA35 DA43 FB11 FB19 FB27 FB35 FB43 FB51 FB59 DA10 DA18 DA26 DA34 DA42 FB10 FB18 FB26 FB34 FB42 FB50 FB58 DA17 DA25 DA33 DA41 FB17 FB25 FB33 FB41 FB49 FB57 DA16 DA24 DA32 DA40 FB16 FB24 FB32 FB40 FB48 FB56
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
Page 2(PS1=1, PS0=0)
Name PSTART PSTOP TPSR Type
RDCE
CNTE
OFST OVWE
TXEE
RXEE
PTXE
PRXE
Page 3(PS1=1, PS0=1)
Name 9346CR BPAGE CONFIG0 CONFIG1 CONFIG2 CONFIG3 TEST CSNSAV HLTCLK INTR FMWP CONFIG4 Type EEM1 EEM0 EEM1 EEM0 VerID1 VerID0 IRQEN IRQS2 IRQS1 IRQEN BSELB BSELB FUDUP LEDS1 Reserved, write CSN7 CSN6 CSN5 HLT7 HLT6 HLT5 Reserved INT7 INT6 INT5 Flash Memory Write Protect Reserved PNPJP IRQS0 LEDS0 CSN4 HLT4 INT4 EECS EECS IOS3 CSN3 HLT3 INT3 EESK EESK IOS2 SLEEP SLEEP CSN2 HLT2 INT2 EEDI EEDI IOS1 PWRDN PWRDN CSN1 HLT1 INT1 EEDO IOS0 ACTIVEB CNS0 HLT0 INT0 IOMS
Note: registers marked with type='W*' written only bits EEM1=EEM0=1. 5.1.2. Register Functions 5.1.2.1. NE2000 Compatible Registers Command Register (00H; Type=R/W) This register used select register pages, enable disable remote operation issue commands.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
Symbol PS1,
Description Register Page Remark NE2000 compatible NE2000 compatible NE2000 compatible RTL8019AS Configuration
RD2-0 Function allowed Remote Read Remote Write Send Packet Abort/Complete remote
This must transmit packet. internally reset either after transmission completed aborted. Writing effect. controls nothing. only reflects value written this bit. POWER UP=0. This STOP command. When set, packets will received transmitted. POWER UP=1. Function Start Command Stop Command
ISR: Interrupt Status Register (07H; Type=R/W Page0) This register reflects status. host reads determine cause interrupt. Individual bits cleared writing into corresponding bit. must cleared after power
Symbol Description This when enters reset state cleared when start command issued also when receive buffer overflows cleared when more packets have been read from buffer. when remote operation been completed. when more network tally counters been set. This when receive buffer been exhausted. Transmit error when packet transmission aborted excessive collisions. This when packet received with more following errors: error Frame alignment error -Missed packet This indicates packet transmitted with errors. This indicates packet received with errors.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
IMR: Interrupt Mask Register (0FH; Type=W Page0, Type=R Page2) bits correspond bits register. POWER UP=all Setting individual bits will enable corresponding interrupts. DCR: Data Configuration Register (0EH; Type=W Page0, Type=R Page2)
Symbol FT1, Description Always FIFO threshold select Auto-initialize Remote Send Packet Command executed. Send Packet Command executed. Loopback Select Loopback mode selected. Bits must also programmed Loopback operation. Normal Operation This must zero. only supports dual 16-bit mode. POWER Byte Order Select (Not implement) byte placed MD15-8 byte MD7-0. (32xxx,80x86) byte placed MD7-0 byte MD15-8. (680x0) Word Transfer Select byte-wide transfer word-wide transfer
TCR: Transmit Configuration Register (0DH; Type=W Page0, Type=R Page2)
Symbol OFST Description Always Always Always Collision Offset Enable. Auto Transmit Disable. normal operation reception multicast address hashing disables transmitter, reception multicast address hashing enables transmitter. Mode Remark Normal Operation Internal Lookback External Lookback External Lookback
LB1,
logic comprises generator transmitter checker receiver. This controls activity logic. this set, inhibited transmitter. Otherwise appended transmitter. Conditions Mode normal normal loopback loopback Logic Activities Generator Checker enabled enabled disabled enabled enabled disabled disabled enabled
TSR: Transmit Status Register (04H; Type=R Page0)
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
This register indicates status packet transmission.
Symbol Description Window Collision. when collision detected after slot time (51.2us). Transmissions rescheduled normal collisions. Heartbeat. watches collision signal (i.e. Heartbeat signal) during first 6.4us interframe following transmission. This transceiver fails send this signal. Always Carrier Sense lost when carrier lost during transmitting packet. indicates aborted transmission because excessive collisions. indicates transmission collided with some other station network. Always This indicates transmission completes with errors.
RCR:
Receive Configuration Register (0CH; Type=W Page0, Type=R Page2)
Symbol Description Always Always When monitor mode set, received packets checked address match, good frame alignment buffered memory. Otherwise, packets will buffered memory. PRO=1, packets with physical destination address accepted. PRO=0, physical destination address must match node address programmed PAR05. AM=1, packets with multicast destination address accepted. AM=0, packets with multicast destination address rejected. AB=1, packets with broadcast destination address accepted. AB=0, packets with broadcast destination address rejected. AR=1, packets with length fewer than bytes accepted. AR=0, packets with length fewer than bytes rejected. SEP=1, packets with receive errors accepted. SEP=0, packets with receive errors rejected.
RSR: Receive Status Register (0CH; Type=R Page0)
Symbol Description Defferring. when carrier collision detected. Receiver Disabled. When enters monitor mode, this receiver disabled. Reset when receiver enabled after leaving monitor mode. when received packet multicast broadcast destination address. reset when received packet physical destination address. Missed Packet when incoming packet accepted because lack receive buffer monitor mode. Increment CNTR2 tally counter. Always Frame Alignment Error reflects incoming packet didn't byte boundary match last byte boundary. Increment CNTR0 tally counter. error reflects packet received with error. This will also errors. Increment CNTR1 tally counter. This indicates packet received with errors.
CLDA0, Current Local Registers (01H 02H; Type=R Page0) These registers read current local address. PSTART: Page Start Register (01H; Type=W Page0, Type=R Page Page Start register sets start page address receive buffer ring.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
PSTOP:
Page Stop Register (02H; Type=W Page0, Type=R Page2) Page Stop register sets stop page address receive buffer ring. mode PSTOP register should exceed 0x60, mode PSTOP register should exceed 0x80. Boundary Register (03H; Type=R/W Page0) This register used prevent overwrite receive buffer ring. typically used pointer indicating last receive buffer page host read. Transmit Page Start Register (04H; Type=W Page0) This register sets start page address packet transmitted.
BNRY:
TPSR:
TBCR0,1: Transmit Byte Count Registers (05H 06H; Type=W Page0) These registers byte counts packet transmitted. NCR: Number Collisions Register (05H; Type=R Page0) register records number collisions node experiences during packet transmission. First First Register (06H; Type=R Page0) This register allows host examine contents FIFO after loopback.
FIFO:
CRDA0, Current Remote Address registers (08H 09H; Type=R Page0) These registers contain current address remote DMA. RSAR0,1: Remote Start Address Registers (08H 09H; Type=W Page0) These registers start address remote DMA.
RBCR0,1: Remote Byte Count Registers (0AH 0BH; Type=W Page0) These registers data byte counts remote DMA. CNTR0: CNTR1: CNTR2: PAR0-5: Frame Alignment Error Tally Counter Register (0DH; Type=R Page0) Error Tally Counter Register (0EH; Type=R Page0) Missed Packet Tally Counter Register (0FH; Type=R Page0) Physical Address Registers (01H 06H; Type=R/W Page1) These registers contain Ethernet node address used compare destination adderss incoming packets acceptation rejection. Current Page Register (07H; Type=R/W Page1) This register points page address first receive buffer page used packet reception. Multicast Address Register (08H 0FH; Type=R/W Page1) These registers provide filtering bits multicast addresses hashed logic.
CURR:
MAR0-7:
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
5.1.2.2. RTL8019AS Defined Registers Page (PS1=0, PS0=0) registers defined contain RTL8019AS chip
Name 8019ID0 8019ID1 Type Bit7-0 (ASCII code "P") (ASCII code "p")
Page 3(PS1=1, PS0=1) Page3 Power Values before loading jumper states 9346 contents
Name 9346CR BPAGE CONFIG0 CONFIG1 CONFIG2 CONFIG3 TEST CSNSAV HLTCLK INTR FMWP CONFIG4 Type
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
Page3 Content Descriptions 9346CR: 9346 Command Register (01H; Type=R/W except Bit0=R)
Symbol EEM1-0 Description These bits select RTL8019AS operating mode. EEM1 EEM0 Operating Mode Normal (DP8390 compatible) Auto-load: Entering this mode will make RTL8019AS load contents 9346 like when RSTDRV signal asserted. This auto-load operation will take about 2ms. After completed, RTL8019AS goes back normal mode automatically (EEM1=EEM0 register reset 21H. 9346 programming: this mode, both local remote operation 8390 disabled. 9346 directly accessed bit3-0 which reflect states EECS, EESK,EEDI, EEDO pins respectively. Config register write enable: Before writing Page3 CONFIG1-3 registers, RTL8019AS must placed this mode. This will prevent RTL8019AS's configurations from accidental change.
EECS EESK EEDI EEDO
used. These bits reflect state EECS, EESK, EEDI EEDO pins auto-load 9346 programming mode.
BPAGE: BROM Page Register (02H; Type=R/W) This register selects BROM page read host. Totally select pages with bytes page. Thus maximum BROM size 256*16k=4M bytes.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
CONFIG0: RTL8019AS Configuration Register (03H; Type=R except Bit[7:6]=R/W)
Symbol VERID Description Version These bits defined below. Bit7 Bit6 Type Mode RTL8019 RTL8019A RTL8019AS, these bits when power written RTL8019AS's config write enable mode (EEM0=EEM1=1). Software uses these differences identify chip.
PNPJP
This when external used interface. Therefore when 10Base5 mode input high. This when jumper pulled high externally. This reflects state input. when set, indicates RTL8019 jumper mode. When set, this indicates that RTL8019 using 10Base2 thin cable networking medium. This will following cases: PL1=PL0=0 (auto-detect) link test fails PL1=PL0=1 Base Always
following table describes behavior bits pins cabling media.
Media Type 10Base5 10Base2 10BaseT Link disabled Auto detect Link Auto detect Link fail Auto detect Link fail Input Selected Media LEDBNC Output Original 8019 (For reference only)
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
CONFIG1: RTL8019AS Configuration Register (04H; Type=R except Bit7=R/W)
Symbol IRQEN Description Enable: This controls state interrupt request line selected IRQS2-0. this set, interrupt line goes high upon interrupt request will when there interrupt request. interrupt line will forced tri-state this reset. This bit's power-up initial value modified software EEM1=EEM0=1 9346CR register. Select These bits select INT7-0 reflect RTL8019AS's interrupt request status. unselected interrupt lines will tri-stated. IRQS2 IOS3-0 IRQS1 IRQS0 Interrupt Line INT0 INT1 INT2 INT3 INT4 INT5 INT6 INT7 Assigned IRQ2/9 IRQ3 IRQ4 IRQ5 IRQ10 IRQ11 IRQ12 IRQ15
IRQS2-0
Select base address. IOS3 IOS2 IOS1 IOS0 Base 300H 320H 340H 360H 380H 3A0H 3C0H 3E0H 200H 220H 240H 260H 280H 2A0H 2C0H 2E0H
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
CONFIG2: RTL8019AS Configuration Register (05H; Type=R except Bit[7:5]=R/W)
Symbol PL1-0 Description Select network medium types. Medium Type TP/CX auto-detect (10BaseT link test enabled) 10BaseT with link test disabled 10Base5 10Base2
BSELB
This bit, when set, forces BROM disabled regardless contents BS4-0. power-up initial value modified software EEM1=EEM0=1 9346CR register. These bits select BROM size memory base address. BROM Base size Disabled C000h, C800h, D000h, D800h, C000h, D000h, C000h, C400h, C800h, CC00h, D000h, D400h, D800h, DC00h, C000h, Page C400h, Page C800h, Page CC00h, Page D000h, Page D400h, Page D800h, Page DC00h, Page
BS4-0
RTL8019AS supports special BROM mode: page mode. page mode, BROM always occupies 16K-byte host memory space. However actual BROM size bytes. BROM divided into several 16K-byte pages. power boot page page program page responsible select other pages BPAGE register load their programs. page mode, bits BP7-0 BPAGE register mapped BA21-14 pins select proper BROM page. other modes, BA21-16 used BA15-14 outputs shown following table.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
BROM size
BA14 high SA14 SA14
BA15 high high SA15
CONFIG3: RTL8019AS Configuration Register (06H; Type=R except Bit[2:1]=R/W)
Symbol Description This negligible jumper mode. jumperless mode when set, indicates RTL8019AS operating Plug Play mode. This when high 9346 jumperless mode. When this set, RTL8019AS full-duplex mode which enables simultaneously transmission reception twisted-pair link full-duplex Ethernet switching hub. This feature only increases channel bandwidth from Mbps also avoids performance degrading problem channel contention characteristics Ethernet CSMA/CD protocol. These bits select outputs LED2-0 pins. LEDS0 LEDS1 LED0 LED_COL LED_LINK LED1 LED_RX LED_CRS LED2 LED_TX MCSB
FUDUP
LEDS1-0
SLEEP
PWRDN
Please refer section behavior LEDs. MCSB signal defined local buffer SRAM into standby mode while progress thus save powers. Reserved. Must write this bit. This bit, when set, puts RTL8019AS into sleep mode. sleep mode, signals (P.S. MCSB signal) except LEDBNC forced high turn LEDs. RTL8019AS still handles network transmission reception like normal mode. LEDBNC affected this bit. This bit's power-up initial value modified software when EEM1=EEM0=1. This when set, puts RTL8019AS into power down mode. RTL8019AS supports kinds power down modes, which selected contents HLTCLK register: mode power down with clock running mode power down with clock halted both power down modes, RTL8019AS's serial network interface transceiver turned off. network activities ignored. signals except LEDBNC forced high. LEDBNC forced disable convertor coaxial transceiver. power down mode2, RTL8019AS stops internal clock minimal power consumption. Registers except HLTCLK typically accessible this mode. This bit's initial value comes from 9346 modified EEM1=EEM0=1 9346CR register.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
ACTIVEB This inverse Activate register (index 30H). When RTL8019AS deactivated, BROM memory read accesses Group1 registers except HLTCLK register ignored. HLTCLK register logic work same when RTL8019AS active. Note: logical device control register only activate RTL8019AS. Therefore, HLTCLK register allowed written prevent RTL8019AS from dying when inactive clock-halted power-down mode.
CONFIG4 RTL8019AS Configuration Register (0DH; Type=R)
Symbol IOMS Description Reserved When this set, RTL8019AS uses SA15-SA0 decode address NE2000 registers. When this reset, RTL8019AS only decodes SA9-SA0 like RTL8019 does. This mode supported applications which might require fully decode address. This read-only comes from CONFIG4 byte(Offset 03H) 9346(refer section 6.3).
CSNSAV: Save Register (08H; Type=R) This register provided backup assigned register. HLTCLK: Halt Clock Register (09H; Type=W) This only active Group1 registers when RTL8019AS inactivated. Writing this register invalid RTL8019AS power down mode. (i.e. PWRDN CONFIG3 register zero.) data written this register determines RTL8019AS's power down mode.
Data (ASCII code 'R') (ASCII code 'H') Other values Power Down Mode Mode clock Running Mode clock Halted Ignored
INTR: Interrupt Register (0BH; Type=R) This register reflects states INT7-0 pins. FMWP: Flash Memory Write Protect Register (0Ch, Type=W) This register write only. write this register valid only when EEM0=EEM1=1. Sequentially writing bytes data (57H then A8H) this register enables flash memory write operation. Writing other data this register will reset write sequence disable flash write. flash memory write commands from host ignored write operation enabled.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
5.2. Group Plug Play (PnP) Registers Auto-configuration Ports Three 8-bit ports defined read/write operations. They called Autoconfiguration ports listed below.
Port Name ADDRESS WRITE_DATA READ_DATA Type Location 279H (Printer status port) A79H (Printer status port 800H) Relocatable range 200H 3FFH
Plug Play registers accessed first writing address desired register, which called "Register Index" following paragraph, ADDRESS port, followed read data from READ_DATA port write data WRITE_DATA port. write ADDRESS port followed number WRITE_DATA READ_DATA accesses same indexed register without need write ADDRESS port before each access. Address port also write destination initiation key, which will described later. Plug Play Registers Plug Play registers divided into card registers logical device registers. According Plug Play specification, card contain more than logical devices. card registers unique each card. However, logical device registers repeated each logical device card. Furthermore, card registers card control registers, while logical device registers divided into logical device control registers configuration registers. Although RTL8019AS card contains only logical device, following paragraph still depicts Plug Play registers same categorizing method. p.s. Those registers bits mentioned below read only with value=0.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
5.2.1. Card Control Registers
Index Name RD_DATA port Type Definition location READ_DATA port determined writing this register. Bits[7:0] become read port address bits[9:2]. Address bits[1:0] READ_DATA port always read this register causes card Isolation state compare card's serial This process will described more details section Bit[0] Reset command Setting this will reset logical devices restore configuration registers their power-up values. preserved. Bit[1] Wait command Setting this makes card return Wait state. preserved. Bit[2] Reset command Setting this will reset card's Both (index 06H) CSNSAV (index F5H) registers reset. Note that hardware will automatically clear bits there need software clear them. write this register will cause cards that have that matches write data[7:0] from Sleep state either Isolation state write data this command zero Config state write data zero. read from this register reads next byte resource data. Status register must polled until bit[0] before this register read. Bit[0] when indicates okay read next data byte from Resource Data register. write this register sets card's CSN. value uniquely assigned each card after serial identification process that each card individually selected during Wake[CSN] command. value written this register will also recorded CSNSAV register located register index Group Page3 offset 08H. (Only logical device RTL8019AS).
Serial Isolation
Config Control
Wake[CSN]
Resource Data
Status Card Select Number (CSN)
Logical Device Number
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
5.2.2. Logical Device Control Registers
Index Name Activate Type Definition each logical device there Activate register that controls whether logical device active bus. Bit[0], set, activates logical device. Before logical device activated, range check must disabled. This register used perform conflict check port range programmed logical device. Bit[1] This when set, enables range check. range check only valid when logical device inactive. Bit[0] set, this forces logical device respond reads logical device's assigned range with when range check operation. clear, logical device drives AAH.
Range Check
5.2.3. Logical Device Configuration Registers Memory Configuration Registers
Index Name BROM base address bits[23:16] BROM base address bits[15:0] Memory Control Type Definition Bits[23:20] bit[17] read only with values=0. other bits read/write bits. Bits[13:8] read only with values=0. other bits read/write bits. 00H. (Only 8-bit operation supported BROM)
Note: BROM size RTL8019AS determined 9346 contents memory configuration registers. Configuration Registers
Index Name base address bits[15:8] base address bits[7:0] Type Definition Bits[15:10] read only with values=0. other bits read/write bits. Bits[4:0] read only with values=0. other bits read/write bits.
Interrupt Configuration Registers
Index Name level Type Definition Read/write value indicating selected interrupt level. Bits[3:0] select which interrupt level used. selects IRQ1, fifteen selects IRQ15. IRQ0 valid interrupt selection represents interrupt selection.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
type Read/Write value indicating which type interrupt used selected above. Bit[1] Level, 1=high, 0=low Bit[0] Type, 1=level, 0=edge RTL8019AS, this register read only with value=02H.
Configuration Registers
Index Name channel select channel select Type Definition (indicating channel needed) (indicating channel needed)
Vendor Defined Registers
Index Name CONFIG0 CONFIG1 CONFIG2 CONFIG3 CSNSAV Vendor Control Type Definition Direct mapping Page3 CONFIG0 register. Direct mapping Page3 CONFIG1 register. Direct mapping Page3 CONFIG2 register. Direct mapping Page3 CONFIG3 register. Direct mapping Page3 CSNSAV register. Bit[2] Reset command Setting this will reset card's register (index 06H) CSNSAV register affected. This cleared hardware automatically.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
Functional Descriptions
6.1. RTL8019AS Configuration Modes RTL8019AS supports configuration modes: jumper, jumperless, PnP.
9346 Content ACTIVEB (a=0or1) (a=0or1) Mode Jumper jmpless CONFIG0 PNPJP CONFIG3 ACTIVEB
P.S. denotes don't care. RTL8019AS's resource configuration informations such base address, BROM memory base address, interrupt request line, etc., stored CONFIG3-0 registers Group1 Page3 well logical device configuration registers. Their power-up default values come from states jumper pins jumper mode contents 9346 jumperless mode. Their values modified software logical device configuration registers modes. update values will recorded CONFIG3-0 registers, too. This configuration only valid temporarily will lost after auto-load command, active RSTDRV, power Permanent changes configuration must done changing jumper states contents 9346. Note that BROM size modified temporarily. Plug Play logic work three configuration modes except that defined initiation key, named initiation key, should used instead initiation key. other words, initiation supported configuration modes while initiation only supported mode. using initiation key, software RTL8019AS Config state access logical device configuration registers even jumper jumperless modes. Power default ACTIVE state RTL8019, ACTIVEB 93C46 decides power-up adapter status even jumpless mode. standard application when BROM enabled, adapter should power inactive mode active jumperless mode. However RTL8019's jumper only decides jumperless mode. adapter's "ACTIVE" status changed properly same time when user changes jumper state. This causes application inconsistence when jumper used. RTL8019AS, change RTL8019's original specification into: ACTIVEB 9346 ignored when RTL8019AS jumper jumperless mode. adapter's power-up status always "ACTIVE" jumperless mode. However, active status still changed Activate register.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
differences between configuration modes shown following table.
Configuration Mode Jumper Jumperless Plug Play Resource Power-up Value Jumper Pins 9346 9346 Supported Initiation Initiation Initiation Initiation
Initial Values CONFIG1-3 Registers after RSTDRV Auto-load Command CONFIG1
Mode Jumper Jumperless Plug Play IRQEN IRQS2 IRQS1 IRQS0 IOS3 IOS2 jumper jumper jumper jumper jumper 9346 9346 9346 9346 9346 IOS1 jumper 9346 IOS0 jumper 9346
CONFIG2
Mode Jumper Jumperless Plug Play BSELB jumper jumper jumper jumper jumper 9346 9346 9346 9346 9346 jumper 9346 jumper 9346
CONFIG3
Mode Jumper Jumperless Plug Play FUDUP LEDS1 LEDS0 9346 9346 9346 9346 9346 9346 SLEEP PWRDN ACTIVEB 9346 9346 9346 9346
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
6.2. Plug Play 6.2.1. Initiation Plug Play logic quiescent power must enabled software. This done predefined series writes writes) ADDRESS port, which called initiation key. write sequence decoded RTL8019AS. proper series writes detected, then Plug Play auto-configuration ports enabled. write sequence will reset must issued from beginning data mismatch occurs. exact sequence initiation listed below hexadecimal notation. Initiation
Initiation
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
6.2.2. Isolation Protocol
simple algorithm used isolate each Plug Play card. This algorithm uses signals requires lock-step operation between Plug Play hardware isolation software.
State Isolation
Read from serial isolation register
from serial identifier
Drive "55H" SD[7:0]
bit="1H"
Leave [7:0] high-impedance SD[1:0]="01"
Wait next read from serial isolation register Drive "AAH" SD[7:0] Leave [7:0] high impedance SD[1:0]="10" After read completes fetch next from serial identifier
ID=0 other card ID=1
Read bits from serial identifier
State Sleep
card isolated
Figure Plug Play Card Isolation Algorithm
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
Serial Identifier element Plug Play isolation protocol that each card contains unique number, named serial identifier. serial identifier 72-bit unique, non-zero number composed 32-bit fields 8-bit checksum. first 32-bit field vendor identifier. other 32-bits value, example, serial number, part address, static number, long there will never cards single system with same 64-bit number. serial identifier accessed bit-serially isolation logic used differentiate cards.
Checksum Byte Byte Serial Number Byte Byte Byte Byte Vendor Byte Byte Byte
Shift
Figure Shifting Serial Identifier shift order Plug Play serial isolation resource data defined bit[0], bit[1], through bit[7]. Hardware Protocol isolation protocol invoked Plug Play software time. initiation described earlier, puts cards into configuration mode. hardware each card expects pairs read accesses READ_DATA port. card's response these reads depends value each serial identifier which being examined time, sequence shown Figure current serial identifier "1", then card will drive data complete first read cycle. "0", then card puts data driver into high impedance. cards high impedance will check data during read cycle sense another card driving SD[1:0] "01". During second read, card(s) that drove 55H, will drive AAH. high impedance card will check data sense another card driving SD[1:0] "10." high impedance card sensed another card driving data with appropriate data during both cycles, then that card ceases participate current iteration card isolation. Such cards, which lose out, will participate future iterations isolation protocol. NOTE: During each read cycle, Plug Play hardware drives entire 8-bit data bus, only checks lower bits. card driving card high impedance sense another card driving bus, then should prepare next pair reads. card shifts serial identifier uses shifted decide response. above sequence repeated entire 72-bit serial identifier.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
this process, card remains. This card assigned handle referred Card Select Number (CSN) that will used later select card. Cards which have been assigned will participate subsequent iterations isolation protocol. Cards must assigned before they will respond other commands. should noted that protocol permits 8-bit checksum stored non-volatile memory card generated on-card logic real-time. checksum algorithm implemented Linear Feedback Shift Register (LFSR), which shown Figure
Vendor Serial number
Read Serial Isolation register Reset values
Shift
Figure Checksum LFSR LFSR resets upon receiving Wake[CSN] command. next shift value LFSR calculated LFSR[1] LFSR[0] Serial Data. LFSR shifted right conclusion each pair reads Serial Isolation register. LFSR[7] assigned next shift value described above. After first pairs reads Serial Isolation register, LFSR will have value serial identifier checksum. Plug Play cards must drive IOCHRDY signal during serial isolation. However, cards drive IOCHRDY other time. Software Protocol Plug Play software sends initiation Plug Play cards place them into configuration mode. software then ready perform isolation protocol. Plug Play software generates pairs read cycles from READ_DATA port. software checks data returned from each pair reads driven hardware. both read back, then software assumes that hardware that position. other results assumed "0". During first bits, software generates checksum using received data. checksum compared with checksum read back last bits sequence.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
There other special considerations software protocol. During iteration, possible that combination never detected. also possible that checksum does match. either these cases occur first iteration, must assumed that READ_DATA port conflict. conflict detected, then READ_DATA port relocated. above process repeated until non-conflicting location READ_DATA port found. entire range between 200H 3FFH available, however practice expected that only locations will tried before software determines that Plug Play cards present. During subsequent iterations, occurrence either these special cases should interpreted absence further Plug Play cards (i.e. last card found previous iteration). This terminates isolation protocol. NOTE: software must delay msec prior starting first pair isolation reads, must wait msec between each subsequent pair isolation reads. This delay gives card time access information from possibly very slow storage devices.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
6.2.3. Plug Play Isolation Sequence Plug Play isolation sequence divided into four states: Wait Key, Sleep, Isolation, Config states. state transitions Plug Play card shown below.
Power RSTDRV Reset command
CSN=0 State Wait Active Commands active commands initiation State Sleep Active Commands Reset Reset Wait Wake [CSN] (WAKE<>0) (WAKE=CSN) WAKE<>CSN State Active Commands Reset Reset Wait Wake [CSN] Resource Data Status Logical Device Range Check Activate Configuration Registers
(WAKE=0) (CSN=0) Lose serial isolation (WAKE<>CSN) State Active Commands Reset Reset Wait RD_DATA Port Serial isolation Wake [CSN]
Isolation
Config
NOTES: CSN= Card Select Number RSTDRV causes state transition from current state Wait sets CSNs zero Wait command causes state transition from current state Wait Reset commands include Reset Reset commands. former sets cards' CSNs zero while latter only sets RTL8019 cards' CSNs zero. Both commands cause state transition.
Figure Plug Play Card State Transitions
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
power cards detect RSTDRV, their enter Wait state. There required msec delay from either RSTDRV Reset command Plug Play port access allow card load initial configuration information from non-volatile device, which 9346 RTL8019AS. Cards Wait state respond access their auto-configuration ports until initiation detected. Cards ignore access their Plug Play interface. When cards have received initiation key, they enter Sleep state. this state, cards listen Wake[CSN] command with write data 00H. This wake[CSN] command will send cards Isolation state reset serial identifier/resource data pointer beginning. first time cards enter Isolation state necessary READ_DATA port address using RD_DATA port command. software should then verify selected READ_DATA port address conflict with other devices isolation protocol. Next, pairs reads performed Serial Isolation register isolate card described previously. checksum read from card valid, then this means card been isolated. isolated card remains Isolation state while other cards have failed isolation protocol have returned Sleep state. this card unique number. Writing this value causes this card transition Config state. Sending Wake[0] command causes this card transition back Sleep state cards with value zero transition Isolation state. This entire process repeated until Plug Play cards detected. 6.2.4. Reading Resource Data Each card supports resource data structure stored non-volatile device (e.g. 9346) describe resources supported those requested functions card. Plug Play resource management software will arbitrate resources setup logical device configuration registers according resource data. Card resource data only read from cards Config state. card Config state different methods. card enters Config state response card "winning" serial isolation protocol having assigned. card also enters Config state response receiving Wake[CSN] command that matches card's CSN. described above, Plug Play cards function their serial identifier their resource data both come from same serial device. also stated above, pointer serial device reset response Wake[CSN] command. This implies that card enters Config state directly response Wake[CSN] command, 9-byte serial identifier must read first before card resource data accessed. Vendor Unique Serial Number valid; however, checksum byte, when read this way, valid. card that enters Config state after isolation protocol been already accessed bits serial identifier first read Resource Data register will return resource data.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
Card resource data read first polling Status register waiting bit[0] set. When this means that byte resource data ready read from Resource Data register. After Resource Data register read, Status register must polled before reading next byte resource data. This process repeated until resource data read. format resource data described following section. above operation implies that hardware responsible accumulating bits data Resource Data register. When this operation complete, status bit[0] set. When read performed Resource Data register, status bit[0] cleared, eight more bits shifted into Resource Data register, then status bit[0] again. 6.2.5. auto detect mode When using RTL8019, user needs setup card jumperless mode according host environments. typical operating modes RTL8019 card include: when used non-PnP card jumperless mode power-on active when used (2.1) BROM disabled, card mode power-on inactive (2.2) BROM enabled, card mode power-on active P.S. with BIOS, Windows Intel Configuration Manager, etc. called card mode(2.1) non-PnP drivers will fail initialize card. RTL8019AS supports auto-detect mode solve problem. card default state: mode power-on active with BROM disabled. card non-PnP will work like normal jumperless card. card which requires card power-on inactive, RTL8019AS will change itself into inactive state when first time init detected.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
6.3. 9346 Contents 9346 1k-bit EEPROM. Although actually addressed words, list contents bytes below convenience.
Bytes
bytes) bytes) bytes) (101 bytes) CONFIG1 CONFIG2 CONFIG3 CONFIG4 NE2000 IDPROM Ethernet node address Assigned card makers; negligible Plug Play Serial Identifier Vendor Serial Number Serial Checksum Plug Play Resource Data
Contents
Comments
Power-up initial value Page3 logical device configuration registers
Ethernet Product
Detail values 9346 CONFIG1-3 bytes
CONFIG1 CONFIG2 CONFIG3 IRQS2 FUDUP IRQS1 LEDS1 IRQS0 LEDS0 IOS3 IOS2 IOS1 PWRDN IOS0 ACTIVEB
P.S. denotes don't care. Example Plug Play Resource Data RTL8019AS (Total 73+5 bytes)
Plug Play Version Number Item byte version Vendor version ANSI Identifier String Item byte Length bits Length bits 15-8 Identifier string Logical Device Item byte Logical device ID0-3 Flag Flag Length: fixed bytes
Length: variable
bytes
'REALTEK PLUG PLAY ETHERNET CARD', Length: fixed bytes 4AH, 8CH, 80H, (use when BROM enabled) bytes given
Compatible Device (NE2000 compatible) Length: fixed Item byte
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
Compatible ID0-3 Format Item byte information Min. base bits Min. base bits 15-8 Max. base bits Max. base bits 15-8 Base alignment Range length Format Item byte mask bits mask bits 15-8 information 41H, D0H, 80H, Length: fixed Length: fixed Length: fixed bytes This example uses 16k-byte BROM. bytes bytes
Memory Format (optional) Item byte Length bits Length bits 15-8 Memory information Min. base bits 15-8 Min. base bits 23-16 Max. base bits 15-8 Max. base bits 23-16 Base alignment bits Base alignment bits 15-8 Range length bits 15-8 Range length bits 23-16 Item byte Checksum
Length: fixed bytes complement above resource data i.e. complement (0AH+10H+10H+.+79H)
6.4. Boot Whether EPROM flash memory used BROM, RTL8019AS's BROM read operation still same RTL8019's. supported BROM size same, too. write operation flash memory much like read except that SMEMWB command issued instead SMEMRB. block diagram below shows application when 128k*8bit flash memory (e.g. 29F010) used BROM.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
29F010
SA13-0 SMEMWB SMEMRB A13-0 A16-14 IO7-0 BA16-14 BD7-0 BCSB
From
Through RTL8019AS
this case, BROM page mode used. Before either read write BROM, appropriate page must BPAGE (page3, offset 02h) register first. RTL8019AS will always reflect content BPAGE onto BA14-21 bus. When RTL8019AS decodes valid BROM read write command, asserts BCSB low. Note flash memory write must enabled through RTL8019AS's FMWP register before host's flash write command.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
6.5. Behaviors This section describes lighting behaviors output signals which selected LEDS1 LEDS0 bits Page3 CONFIG3 register. P.S. assumed that when signal goes low. LED_TX:
Power
LED=low
Transmitting Packet?
LED=high (100
LED=low
LED_RX:
Power
LED=low
Receiving Packet?
LED=high (100 +10)
LED=low
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
LED_CRS=LED_TX+LED_RX: Carrier Sense
Power
LED=low
Packet? LED=high (100
LED=low
LED_COL: Collision
Power
LED=high
Collision (except Heartbeat)?
LED=low
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
LED1 (LED_RX LED_CRS) RTL8019's LED_RX LED_CRS sometimes keeps blinking when media type 2-in1 (UTP+BNC) adapter auto-detect both coaxial cable connected. case, RTL8019 actually using because link test fails. Many 8392 will falsely detect carrier when inteface properly terminated (e.g. coaxial cable connected). That carrier sense will then make RTL8019's LED_RX LED_CRS blink. problem that 8392s cause blinking, which makes phenomenon very ambiguous. Considering phenomenon normally awared upon power change RTL8019's original function solve problem some extent. specification LED_RX LED_CRS does reflect carrier sense when register stop mode). Thus, false carrier cabling problem upon power will cause LED1 blink anymore. Output States Power Down Modes
Output LEDBNC LED_LINK LED_COL LED_TX LED_RX LED_CRS Normal Mode Idle High Sleep Mode High High High High High Power Down Mode High High High High High
6.6. Loopback Diagnostic Operation 6.6.1. Loopback operation RTL8019AS provides loopback modes. loopback test, verify integrity data path, logic, address recognition logic cable connection status. Mode 1:Loopback through (LB1=0, LB0=1 TCR). data transmitted instead it's loopbacked NIC's deserializer. traffic cable ignored.
Ref:
8390
83910
Mode 2:Loopback through (LB1=1, LB0=0 TCR) Manchester encoded data transmitted MAU. It's loopbacked through NIC. traffic cable ignored.
Ref:
8390
83910
8392/RTL8005
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
Mode Loopback through cable (LB1=1, LB0=1 TCR) packets transmitted onto network RTL8009 receives incoming packets (not only MAU-loopbacked data) meantime.
CABLE
Ref:
8390
83910
8392/RTL8005
Alignment Reception FIFO reception FIFO 8-byte ring structure. first received byte location zero. When location pointer goes FIFO, wraps beginning FIFO overwrites previous data. packet reception, FIFO contents "order" (from ring structure's view) shown below. enabled (CRC TCR=0) 1-byte received packet data 4-byte 1-byte lower byte count 1-byte upper byte count 1-byte upper byte count disabled (CRC TCR=1) 5-byte received packet data 1-byte lower byte count 1-byte upper byte count 1-byte upper byte count 6.6.2. Implement Loopback Test verify integrity data path RCR=00h accept physical packet PAR0-5 accept packet DCR=40h (8-bit slot) (16-bit slot) TCR=02h, 04h, loopback test respectively enabled (CRC=0 TCR) clear packet check check FIFO after loopback Note: Loopback mode sensitive network traffic, values FIFO correct. verify logic Select loopback mode (e.g. mode test test generator RCR=00h accept physical packet
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
PAR0-5 accept packet TCR=04h (CRC enabled) DCR=40h (8-bit slot) (16-bit slot) clear packet check bytes FIFO after loopback
test checker RCR=00h accept physical packet PAR0-5 accept packet TCR=05h (CRC disabled) DCR=40h (8-bit slot) (16-bit slot) clear packet with good appended program check FIFO, after loopback CRC, expected: ISR=06h, RSR=02h (Tx: Rx:CRC error) good CRC, expected: ISR=02h, RSR=01h (Tx:OK, Note: loopback mode, received packets stored SRAM, isn't set. verify address recognition function Select loopback mode (e.g. mode test Right physical destination address RCR=00h accept physical packet PAR0-5 accept packet TCR=04h (CRC enabled) DCR=40h (8-bit slot) (16-bit slot) clear packet check after loopback Expected: ISR=06h (packets accepted, error) Wrong physical destination address RCR=00h accept physical packet PAR0-5 reject packet TCR=04h (CRC enabled) DCR=40h (8-bit slot) (16-bit slot) clear packet check after loopback Expected: ISR=02h (packets rejected, response)
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
Test Cable Connection There four physical medium types RTL8019. perform loopback mode test cable connection status. RCR=00h accept physical packet PAR0-5 accept packet TCR=06h (CRC enabled) DCR=40h (8-bit slot) (16-bit slot) clear packet check after loopback
10Base2 cable TSR=03h OK). cable FAIL, TSR=0Eh (Collision aborted). 10Base5 cable TSR=03h OK). connected cable FAIL, TSR=0Eh collision aborted). connected, TSR=53h (Carrier sense lost during transmission heartbeat fails.). 10BaseT with link test disabled RTL8019AS disables link test this case, cable FAIL doesn't affect TSR; TSR=03h. Auto-detection (10BaseT with link test enabled) RTL8019AS automatically switches from 10BaseT 10Base twisted-pair wire connected (10BaseT link test fails). twisted-pair wire TSR=03h BNC=0 CONFIG2 twisted-pair wire FAIL coaxial cable TSR=03h BNC=1 CONFIG2 Otherwise, TSR=0Eh (same 10Base2 connection fail).
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
Electrical Specifications Timings
7.1. Absolute Maximum Ratings Operating Temperature Storage Temperature Outputs Supply Voltages, with respect Ground -0.5V Power Dissipation Warning: Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only. Functionality above these limits recommended extended exposure "Absolute Maximum Ratings" affect device reliability. 7.2. D.C. Characteristics (Tc=0 Vcc=5V+5%)
Symbol Vol1 Voh1 Vol2 Voh2 Vol3 Rpull-low Parameter Input Voltage Input Voltage Output Voltage Output High Voltage Output Voltage Output High Voltage Output Voltage Internal Pull-Low Resistance Input Leakage Current Min. Typ. Max. Unit Iol=16mA, Note Ioh=8mA, Note Iol=4mA, Note Ioh=4mA, Note Iol=24mA, Note Conditions
Note Apply only INT7 INT0, SD15 SD0. Note Apply only MD0, MA13 MA0, Pins, EECS, MWRB, MRDB, BCSB. Note Apply only IOCHRDY, IOCS16B
7.3. A.C. Timing Characteristics Read/Write
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
SA0-11 IOCS16B
IORB, IOWB
IOCHRDY SD0-15 (read) SD0-15 (write)
Symbol
Parameter Host address valid IOCS16B Host address invalid IOCS16B high IOCHRDY goes from falling edge IORB IOWB when wait state insertion needed. Read data valid from falling edge IORB IOWB when wait state insertion needed. Read data valid IOCHRDY high when wait state needed Read data hold after IORB rising edge Write data setup IOWB rising edge Write data hold from IOWB rising edge
Min.
Typ.
Max.
Unit
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
BROM Read
SA19-0
SMEMRB IOCHRDY BA14-21 BCSB SD7-0
Symbol
Parameter SMEMRB IOCHRDY IOCHRDY width SMEMRB BA14-21 valid SMEMRB BCSB valid BA14-21 hold from SMEMRB rising edge BCSB hold from SMEMRB rising edge Read data hold from SMEMRB rising edge
Min.
Typ.
Max.
Unit
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
Serial EEPROM (9346) Auto-load
Symbol
Parameter EESK high width EESK width EEDI setup EESK rising edge EEDI hold from EESK rising edge EECS goes high EESK rising edge EECS goes from EESK falling edge EEDO setup EESK falling edge EEDO hold from EESK falling edge
Min.
Typ.
Max.
Unit
REALTEK Semiconductor Co., Ltd. reserved rights this document. part this document copied reproduced form means transferred third party without prior written consent REALTEK Semiconductor Co., Ltd. REALTEK reserves right change products specifications without notice. This document been carefully checked believed accurate. However REALTEK Semiconductor Co., Ltd. assumes responsibility inaccuracies.
8019AS.doc 2001-04-02
SPECIFICATION RTL8019AS
Note:
Symbol Dimension Dimension 106.3 118.1 129.9 2.70 3.00 3.30 20.1 35.8 0.11 0.51 0.91 102.4 112.2 122.0 2.60 2.85 3.10 11.8 16.5 0.18 0.30 0.42 10.2 0.04 0.15 0.26 541.3 551.2 561.0 13.75 14.00 14.25 777.6 787.4 797.2 19.75 20.00 20.25 19.7 25.6 31.5 0.50 0.65 0.80 726.4 740.2 753.9 18.45 18.80 19.15 962.6 976.4 990.2 24.45 24.80 25.15 39.4 47.2 55.1 1.00 1.20 1.40 88.6 94.5 104.3 2.25 2.40 2.65 0.10 1.Dimension include interlead flash. 2.Dimension does include dambar protrusion/intrusion. 3.Controlling dimension: Millimeter 4.General appearance spec. should based final visual inspection spec.
TITLE 100L 14x20 mm**2 FOOTPRINT PACKAGE OUTLINE DRAWING LEADFRAME MATERIAL: APPROVE SCALE CHECK Ricardo Chen DATE REALTEK SEMI-CONDUCTOR CO.,
8019AS.doc 2001-04-02

RTL8019AS Realtek Full-Duplex Ethernet Controller with Plug Play Funct

Top Searches for this datasheet

Other recent searches