700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUF

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700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUF

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ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
FEATURES
Fully integrated Four differential 3.3V 2.5V LVPECL outputs Selectable crystal oscillator interface LVCMOS/LVTTL TEST_CLK input Output frequency range: 31.25MHz 700MHz range: 250MHz 700MHz Supports Spread Spectrum Clocking (SSC) Parallel interface programming counter output dividers during power-up Serial wire interface Cycle-to-cycle jitter: 20ps (typical) Output skew: Output duty cycle: Full 3.3V mixed 3.3V core, 2.5V output operating supply 85°C ambient operating temperature Available both standard lead-free RoHS-complaint packages
XTAL_OUT
GENERAL DESCRIPTION
ICS84314-02 general purpose quad output frequency synthesizer member HiPerClockSthe HiPerClockSfamily High Performance Clock Solutions from ICS. When device uses parallel loading, bits programmable output divider hard-wired divide thus providing frequency range 125MHz 350MHz. serial programming mode, bits programmable output divider either divide divide providing frequency range 31.25MHz 700MHz. Additionally, device supports spread spectrum clocking (SSC) minimizing Electromagnetic Interference (EMI). cycle-cycle jitter broad frequency range ICS84314-02 make ideal clock generator variety demanding applications which require high performance.
BLOCK DIAGRAM
VCO_SEL
ASSIGNMENT
VCO_SEL
nP_LOAD
XTAL_IN
XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT
TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK VCCO
VCCO
ICS84314-02
32-Lead LQFP 1.4mm package body Package View
PHASE DETECTOR
Output Divider Serial Mode Parallel/Serial Mode (Power-up Default) Serial Mode Serial Mode
S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8
CONFIGURATION INTERFACE LOGIC
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
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700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
nP_LOAD input initially LOW. data inputs through passed directly divider. LOW-to-HIGH transition nP_LOAD input, data latched divider remains loaded until next transition nP_LOAD until serial event occurs. result, bits hardwired divider specific default state that will automatically occur during power-up. parallel mode, output divider serial mode, output divider either relationship between frequency, crystal frequency divider defined follows: fxtal fVCO value required values through shown Table Programmable Frequency Function Table. Valid values which will achieve lock 16MHz reference defined 350. frequency defined follows: fout fVCO fxtal Serial operation occurs when nP_LOAD HIGH S_LOAD LOW. shift register loaded sampling S_DATA bits with rising edge S_CLOCK. contents shift register loaded into divider output divider when S_LOAD transitions from LOW-to-HIGH. divide output divide values latched HIGH-to-LOW transition S_LOAD. S_LOAD held HIGH, data S_DATA input passed directly divider output divider each rising edge S_CLOCK.
FUNCTIONAL DESCRIPTION
NOTE: functional description that follows describes operation using 16MHz crystal. Valid loop divider values different crystal input frequencies defined Input Frequency Characteristics, Table NOTE ICS84314-02 features fully integrated therefore requires external components setting loop bandwidth. parallel-resonant, fundamental crystal used input on-chip oscillator. output oscillator divided prior phase detector. With 16MHz crystal, this provides 1MHz reference frequency. operates over range 250MHz 700MHz. output divider also applied phase detector. phase detector divider force output frequency times reference frequency adjusting control voltage. Note that some values (either high low), will achieve lock. output scaled divider prior being sent each LVPECL output buffers. divider provides output duty cycle. programmable features ICS84314-02 support input modes program divider. input operational modes parallel serial. Figure shows timing diagram each mode. parallel mode,
S_CLOCK
SERIAL LOADING
S_DATA S_LOAD
*NULL *NULL SSC0 **N1
**N0
nP_LOAD
PARALLEL LOADING
M0:M8
nP_LOAD
S_LOAD
Time
TABLE OUTPUT DIVIDER
Logic Value
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FIGURE PARALLEL SERIAL LOAD OPERATIONS FUNCTION TABLE (SERIAL LOAD) TABLE FUNCTION TABLE
Output Divide (Power-up Default)
**NOTE: only controlled through serial loading.
REV. NOVEMBER 2005
Logic Value
SSC0
State (Power-up Default)
*NOTE: NULL timing slot must observed.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
Type Input Input Power Power Power Output Output Output Output Description
TABLE DESCRIPTIONS
Number Name VCCO
Pulldown divider inputs. Data latched LOW-to-HIGH transition nP_LOAD input. LVCMOS LVTTL interface levels. Pullup Negative supply pin. Core power supply pin.
Output supply pins. Differential output synthesizer. LVPECL interface levels. Differential output synthesizer. LVPECL interface levels. Differential output synthesizer. LVPECL interface levels. Differential output synthesizer. LVPECL interface levels. Active High Master Reset. When logic HIGH, internal dividers reset causing true outputs inver Input Pulldown outputs high. When logic LOW, internal dividers outputs enabled. Asser tion does affect loaded values. LVCMOS LVTTL interface levels. Clocks serial data present S_DATA input into shift register S_CLOCK Input Pulldown rising edge S_CLOCK. LVCMOS LVTTL interface levels. Shift register serial input. Data sampled rising edge S_DATA Input Pulldown S_CLOCK. LVCMOS LVTTL interface levels. Controls transition data from shift register into dividers. S_LOAD Input Pulldown LVCMOS LVTTL interface levels. Power Analog supply pin. VCCA Selects between crystal oscillator test clock reference source. Selects XTAL inputs when HIGH. Selects XTAL_SEL Input Pullup TEST_CLK when LOW. LVCMOS LVTTL interface levels. TEST_CLK Input Pulldown Test clock input. LVCMOS LVTTL interface levels. Crystal oscillator interface. XTAL_IN input. XTAL_IN, Input XTAL_OUT output. XTAL_OUT Parallel load input. Determines when data present M8:M0 nP_LOAD Input Pulldown loaded into divider. LVCMOS LVTTL interface levels. Determines whether synthesizer bypass mode. VCO_SEL Input Pullup LVCMOS LVTTL interface levels. NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE PARALLEL
SERIAL MODE FUNCTION TABLE
Inputs Conditions S_CLOCK S_DATA Data Data Data Data Reset. Forces outputs LOW. Data inputs passed directly divider. Data latched into input registers remains loaded until next transition until serial event occurs. Serial input mode. Shift register loaded with data S_DATA each rising edge S_CLOCK. Contents shift register passed divider output divider. divider output divider values latched. Parallel serial input affect shift registers. S_DATA passed directly divider clocked.
nP_LOAD
Data Data
S_LOAD
NOTE: HIGH Don't care Rising edge transition Falling edge transition
TABLE PROGRAMMABLE FREQUENCY FUNCTION TABLE (NOTE
Frequency (MHz) Divide
NOTE These divide values frequency 16MHz.
resulting frequencies correspond
ystal TEST_CLK input
TABLE PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE (SERIAL PROGRAMMING MODE ONLY)
Input Logic Logic Divide Output Frequency (MHz) Q0:Q3, nQ0:nQ3 Minimum Maximum 62.5 31.25 87.5
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700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
4.6V -0.5V 50mA 100mA 47.9°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 85°C
Symbol VCCA VCCO ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE POWER SUPPLY CHARACTERISTICS, VCCA 3.3V±5%, VCCO 3.3V±5% 2.5V±5%, 85°C
Symbol VCCA VCCO ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 2.375 Typical Maximum 3.465 3.465 2.625 Units
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700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
Test Conditions Minimum -0.3 3.465V 3.465V 3.465V 3.465V, 3.465V, -150 Typical Maximum Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VCCA 3.3V±5%, VCCO 3.3V±5% 2.5V±5%, 85°C
Symbol Parameter Input High Voltage Input Voltage M0:M2, nP_LOAD, S_CLOCK, S_DATA, S_LOAD Input High Current XTAL_SEL, VCO_SEL TEST_CLK M0:M2, nP_LOAD, S_CLOCK, Input S_DATA, S_LOAD Current XTAL_SEL, VCO_SEL
TABLE LVPECL CHARACTERISTICS, VCCA 3.3V±5%, VCCO 3.3V±5% 2.5V±5%, 85°C
Symbol Parameter Output High Voltage; NOTE Output Voltage; NOTE Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
VSWING Peak-to-Peak Output Voltage Swing NOTE Outputs terminated with VCCO "Parameter Measurement Information" section, "Output Load Test Circuit" diagrams.
TABLE INPUT FREQUENCY CHARACTERISTICS, VCCA 3.3V±5%, VCCO 3.3V±5% 2.5V±5%, 85°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units TEST_CLK; NOTE XTAL_IN, XTAL_OUT; Input Frequency NOTE S_CLOCK NOTE input crystal reference frequency range, value must operate within 250MHz 700MHz range. Using minimum input frequency 12MHz, valid values 466. Using maximum frequency 40MHz, valid values 140.
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level Test Conditions Minimum Typical Fundamental Maximum Units
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700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
Test Conditions Minimum 31.25 33.33 Typical Maximum Units
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%, 85°C
Symbol FMAX jit(cc) jit(per) sk(o) Parameter Output Frequency Range Cycle-to-Cycle Jitter NOTE Period Jitter, RMS; NOTE Output Skew; NOTE Output Rise/Fall Time nP_LOAD Setup Time S_DATA S_CLOCK S_CLOCK S_LOAD nP_LOAD SSCred Hold Time S_DATA S_CLOCK S_CLOCK S_LOAD Modulation Frequency; NOTE Modulation Factor NOTE Spectral Reduction; NOTE Output Duty Cycle
Lock Time tLOCK Parameter Measurement Information section. NOTE Jitter performance using ystal inputs. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE This parameter defined accordance with JEDEC Standard NOTE Spread Spectrum clocking enabled.
TABLE CHARACTERISTICS, VCCA 3.3V±5%, VCCO 2.5V±5%, 85°C
Symbol FMAX jit(cc) jit(per) sk(o) Parameter Output Frequency Range Cycle-to-Cycle Jitter NOTE Period Jitter, RMS; NOTE Output Skew; NOTE Output Rise/Fall Time nP_LOAD Setup Time S_DATA S_CLOCK S_CLOCK S_LOAD nP_LOAD SSCred tLOCK
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Test Conditions
Minimum 31.25
Typical
Maximum
Units
Hold Time
S_DATA S_CLOCK S_CLOCK S_LOAD
Modulation Frequency; NOTE Modulation Factor NOTE Spectral Reduction; NOTE Output Duty Cycle Lock Time
33.33
notes Table above.
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ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
2.8V±0.04V
VCCA, VCCO
SCOPE
VCCA
SCOPE
LVPECL
LVPECL
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD TEST CIRCUIT
tsk(o)
tcycle
VREF
tcycle
jit(cc) tcycle -tcycle
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
contains 68.26% measurements contains 95.4% measurements contains 99.73% measurements contains 99.99366% measurements contains (100-1.973x10-7)% measurements
Clock Outputs
Histogram
Reference Point
(Trigger Edge)
Mean Period
(First edge after trigger)
PERIOD JITTER
nQ0:nQ3 Q0:Q3
OUTPUT RISE/FALL TIME
PERIOD
PERIOD
100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS84314-02 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with .01F bypass capacitor should connected each VCCA pin.
3.3V .01F VCCA .01F
FIGURE POWER SUPPLY FILTERING
RECOMMENDATIONS UNUSED INPUT OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUT: applications requiring crystal oscillator input, both XTAL_IN XTAL_OUT left floating. Though required, additional protection, resistor tied from XTAL_IN ground. TEST_CLK INPUT: applications requiring test clock, left floating. Though required, additional protection, resistor tied from TEST_CLK ground. LVCMOS CONTROL PINS: control pins have internal pull-ups pull-downs; additional resistance required added additional protection. resistor used. LVPECL OUTPUT unused LVPECL outputs left floating. recommend that there trace attached. Both sides differential output pair should either left floating terminated.
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700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
resonant crystal were chosen minimize error. optimum values slightly adjusted different board layouts.
CRYSTAL INPUT INTERFACE
ICS84314-02 been characterized with 18pF parallel resonant crystals. capacitor values, shown Figure below were determined using 25MHz, 18pF paral-
XTAL_IN 18pF Parallel stal XTAL_OUT ICS84332
Figure CRYSTAL INPUt INTERFACE
TERMINATION 3.3V LVPECL OUTPUTS
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
3.3V
FOUT
FOUT
((VOH VOL) (VCC
FIGURE LVPECL OUTPUT TERMINATION
FIGURE LVPECL OUTPUT TERMINATION
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700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
close ground level. Figure eliminated termination shown Figure
TERMINATION
2.5V LVPECL OUTPUT
Figure Figure show examples termination 2.5V LVPECL driver. These terminations equivalent terminating 2.5V, very
2.5V VCCO=2.5V
2.5V 2.5V VCCO=2.5V
2,5V LVPECL Driv
2,5V LVPECL Driv 62.5 62.5
FIGURE 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCCO=2.5V 2,5V LVPECL Driv
FIGURE 2.5V LVPECL TERMINATION EXAMPLE
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700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
guideline. layout actual system will depend selected component types, density components, density traces, stack P.C. board.
LAYOUT GUIDELINE
schematic ICS84314-02 layout example used this layout guideline shown Figure ICS84314-02 recommended board layout this example shown Figure This layout example used general
Logic Input Examples
Logic Input
Logic Input
Install
ICS84314_02 VCCO 0.1u VCCA 0.01u
VCO_SEL nP_LOAD X_OUT X_IN
VCCO
VCCO
T_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK VCCO
Logic Input pins
Install
Logic Input pins
0.1u
0.1u
VCC=3.3V VCCO=3.3V
(Option) 0.1u
(Option) 0.1u
FIGURE SCHEMATIC 3.3V/3.3V RECOMMENDED LAYOUT
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following component footprints used this layout example: resistors capacitors size 0603.
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
traces with transmission lines FOUT nFOUT should have equal delay adjacent each other. Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock trace same layer. Whenever possible, avoid vias clock traces. trace affect trace characteristic impedance hence degrade signal quality. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow more space between clock trace other signal trace. Make sure other signal trace routed between clock trace pair. matching termination resistors should located close receiver input pins possible. Other termination schemes also used shown this example.
POWER GROUNDING
Place decoupling capacitors close possible power pins. space allows, placing decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power generated via. Maximize size power (ground) decoupling capacitor. Maximize number vias between power (ground) pads. This reduce inductance between power (ground) plane component power (ground) pins. VCCA shares same power supply with VCC, insert filter C11, between. Place this filter close VCCA possible.
CLOCK TRACES TERMINATION
component placements, locations orientations should arranged achieve best clock signal quality. Poor clock signal quality degrade system performance cause system failure. synchronous high-speed digital system, clock signal less tolerable poor signal quality than other signals. ringing rising falling edge excessive ring back cause system failure. trace shape trace delay might restricted available space board component location. While routing traces, clock signal traces should routed first should locked prior routing other signal traces.
CRYSTAL
crystal should located close possible pins (XTAL_IN) (XTAL_OUT). trace length between should kept minimum avoid unwanted parasitic inductance capacitance. Other signal traces should routed near crystal traces.
FIGURE BOARD LAYOUT ICS84314-02
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ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
ICS84314-02 triangle modulation frequency deviation will exceed 0.6% down-spread from nominal clock frequency (+0.0% -0.5%). example amount down spread relative nominal clock frequency seen frequency domain, shown Figure ratio this width fundamental frequency typically 0.4%, will exceed 0.6%. resulting spectral reduction will greater than 7dB, shown Figure important note ICS84314-02 minimum spectral reduction component-specific reduction, will necessarily same system reduction.
SPREAD SPECTRUM
Spread-spectrum clocking frequency modulation technique reduction. When spread-spectrum enabled, 30kHz triangle waveform used with 0.5% down-spread (+0.0% -0.5%) from nominal 200MHz clock frequency. example triangle frequency modulation profile shown Figure below. ramp profile expressed Fnom Nominal Clock Frequency Spread mode (200MHz with 16MHz Nominal Modulation Frequency (30kHz) Modulation Factor (0.5% down spread) fnom fnom when fnom fnom when
Fnom
0.5/fm 1/fm
FIGURE TRIANGLE FREQUENCY MODULATION
FIGURE 200MHZ CLOCK OUTPUT
SPREAD-SPECTRUM SPREAD-SPECTRUM
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Fnom
0.4%
FREQUENCY DOMAIN
REV. NOVEMBER 2005
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE LEAD LQFP
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS84314-02 5051
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700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
LEAD LQFP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL
Reference Document: JEDEC Publication MS-026
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MINIMUM
NOMINAL
MAXIMUM
1.60 0.05 1.35 0.30 0.09 9.00 BASIC 7.00 BASIC 5.60 9.00 BASIC 7.00 BASIC 5.60 0.80 BASIC 0.45 0.60 0.75 0.10
REV. NOVEMBER 2005
0.15 1.40 0.37 1.45 0.45 0.20
ICS84314-02
700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUFFER
TABLE ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature ICS84314AY-02 ICS84314AY02 Lead LQFP tray 85°C ICS84314AY-02T ICS84314AY02 Lead LQFP 1000 tape reel 85°C ICS84314AY-02LF ICS84314A02L Lead "Lead-Free" LQFP tray 85°C ICS84314AY-02LFT ICS84314A02L Lead "Lead-Free" LQFP 1000 tape reel 85°C NOTE: that ordered with "LF" suffix number Pb-Free configuration RoHS compliant.
aforementioned trademark, HiPerClockS trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 84314AY-02
REV. NOVEMBER 2005

700MHZ, CRYSTAL-TO-3.3V/2.5V LVPECL FREQUENCY SYNTHESIZER W/FANOUT BUF

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