FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER

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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER

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ICS843101I-312
FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
FEATURES
312.5MHz nominal LVPECL output Selectable crystal oscillator interface designed 25MHz, 18pF parallel resonant crystal LVCMOS/LVTTL single-ended input Output frequency varied steps from nominal range: 560MHz 690MHz phase jitter 312.5MHz, using 25MHz crystal (1.875MHz 20MHz): 0.52ps (typical) Output supply modes Core/Output 3.3V/3.3V 3.3V/2.5V 2.5V/2.5V -40°C 85°C ambient operating temperature Available both standard lead-free RoHS-complaint packages
GENERAL DESCRIPTION
ICS843101I-312 phase-noise frequency margining synthesizer with freHiPerClockSquency margining capability member HiPerClockSfamily high performance clock solutions from ICS. default mode, device nominally generates 312.5MHz LVPECL output clock signal from 25MHz crystal input. There also frequency margining mode available where device programmed, using serial interface, vary output frequency down from nominal steps. ICS843101I-312 provided 16-pin TSSOP.
BLOCK DIAGRAM
Pullup Pulldown
ASSIGNMENT
S_LOAD S_DATA S_CLOCK VCCA MODE VCCO XTAL_OUT XTAL_IN
25MHz
XTAL_IN XTAL_OUT
Phase Detector
690MHz
Pulldown
ICS843101I-312
16-Lead TSSOP 4.4mm 5.0mm 0.92mm package body Package View
S_CLOCK S_DATA S_LOAD MODE
Pulldown Pulldown Pulldown Pulldown
Serial Control
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
some values (either high low), will achieve lock. output scaled output divider prior being sent LVPECL output buffer. divider provides output duty cycle. relationship between crystal input frequency, divider, frequency output frequency provided Table When changing back from frequency margining mode nominal mode, device will return default nominal configuration that will provide 312.5 output frequency. Serial operation occurs when S_LOAD HIGH. Serial data loaded either default mode frequency margining mode. 6-bit shift register loaded sampling S_DATA bits with rising edge S_CLOCK. After shifting 6-bit divider value, S_LOAD transitioned from HIGH which latches contents shift-register into divider control register. When S_LOAD LOW, transitions S_CLOCK S_DATA ignored.
FUNCTIONAL DESCRIPTION
ICS843101I-312 features fully integrated therefore requires external components setting loop bandwidth. 25MHz fundamental crystal used input chip oscillator. output oscillator into pre-divider. frequency margining mode, 25MHz crystal frequency divided 12.5MHz reference frequency applied phase detector. operates over range 560MHz 690MHz. output divider also applied phase detector. default mode ICS843101I-312 312.5MHz output frequency using 25MHz crystal. output frequency changed placing device into margining mode using mode using serial interface program feedback divider. Frequency margining mode operation occurs when MODE input HIGH. phase detector divider force output frequency times reference frequency adjusting control voltage. Note that
TABLE FREQUENCY MARGIN FUNCTION TABLE
XTAL (MHz) Pre-Divider Reference Frequency (MHz) 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 12.5 Feedback Divider M-Data (Binary) 101101 101110 101111 110000 110001 110010 110011 110100 110101 110110 110111 (MHz) 562.5 587.5 612.5 637.5 662.5 687.5 Output Divider Output Frequency (MHz) 281.25 287.5 293.75 306.25 312.5 318.75 331.25 337.5 343.75 Change -10.0 -8.0 -6.0 -4.0 -2.0 Nominal Mode 10.0
SERIAL LOADING
S_CLOCK S_DATA
S_LOAD
Time
FIGURE SERIAL LOAD OPERATIONS
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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
Negative supply pins. Pulldown Controls operation Serial input. LVCMOS/LVTTL interface levels. Shift register serial input. Data sampled rising edge S_CLOCK. Pulldown LVCMOS/LVTTL interface levels. Clock serial data present S_DATA input into shift register Pulldown rising edge S_CLOCK. LVCMOS/LVTTL interface levels. Select pin. When HIGH, selects input. Pulldown When LOW, selects XTAL inputs. LVCMOS/LVTTL interface levels. Output enable pin. Controls enabling disabling Q/nQ outputs. Pullup LVCMOS/LVTTL interface levels Analog supply pin. Core supply pin. Parallel resonant ystal interface. XTAL_OUT output, XTAL_IN input. Pulldown LVCMOS/LVTTL clock input. Differential output pair. LVPECL interface levels.
TABLE DESCRIPTIONS
S_LOAD S_DATA S_CLOCK VCCA XTAL_IN, XTAL_OUT VCCO Input Input Input Input Input Power Power Input Input Ouput Power Power
Output supply pin. MODE pin. default mode. HIGH frequency margining mode. MODE Input Pulldown LVCMOS/LVTTL interface levels. NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLDOWN RPULLUP Parameter Input Capacitance Input Pulldown Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE CONTROL INPUT FUNCTION TABLE
Input Outputs Enabled
TABLE CONTROL INPUT FUNCTION TABLE
Input Selected Source XTAL_IN, XTAL_OUT
TABLE MODE CONTROL INPUT FUNCTION TABLE
Input Mode Condition Default Mode Frequency Margining Mode
TABLE SERIAL MODE FUNCTION TABLE
Inputs S_LOAD S_CLOCK S_DATA Data Serial inputs ignored. Serial input mode. Shift register loaded with data S_DATA each rising edge S_CLOCK. Contents shift register latched. Conditions
NOTE: HIGH Don't care Rising edge transition Falling edge transition
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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
4.6V -0.5V 0.5V 50mA 100mA 89°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%, -40°C 85°C
Symbol VCCA VCCO ICCA ICCO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Core Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE POWER SUPPLY CHARACTERISTICS, VCCA 3.3V±5%,VCCO 2.5V±5%, -40°C 85°C
Symbol VCCA VCCO ICCA ICCO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Core Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 2.375 Typical Maximum 3.465 3.465 2.625 Units
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 2.5V±5%, -40°C 85°C
Symbol VCCA VCCO ICCA ICCO
843101AGI-312
Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Core Supply Current Analog Supply Current Output Supply Current
Test Conditions
Minimum 2.375 2.375 2.375
Typical
Maximum 2.625 2.625 2.625
Units
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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
Test Conditions 3.3V 2.5V 3.3V 2.5V Minimum Typical -0.3 -0.3 Maximum -150 Units ns/v
TABLE LVCMOS LVTTL CHARACTERISTICS, -40°C 85°C
Symbol Parameter Input High Voltage Input Voltage CLK, SEL, S_DATA, S_LOAD, S_CLOCK, MODE CLK, SEL, S_DATA, S_LOAD, S_CLOCK, MODE Input Transistion Rise/Fall Rate SEL, S_CLOCK, S_DATA, S_LOAD, MODE
Input High Current
3.465 2.625V 3.465 2.625V 3.465V 2.625V, 3.465V 2.625V,
Input Current
TABLE LVPECL CHARACTERISTICS, -40°C 85°C
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
NOTE Outputs terminated with VCCO
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using 18pF parallel resonant ystal. Test Conditions Minimum Typical Maximum Units Fundamental
TABLE INPUT FREQUENCY CHARACTERISTICS, -40°C
Symbol Parameter Input Frequency XTAL_IN/XTAL_OUT S_CLOCK
85°C
Minimum Typical Maximum Units
Test Conditions
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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
Test Conditions Mode 312.5MHz, (1.875MHz 20MHz) Minimum Typical 312.5 0.52 Maximum Units
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%, -40°C 85°C
Symbol fOUT Parameter Output Frequency Phase Jitter NOTE Output Rise/Fall Time
Output Duty Cycle S_DATA S_CLOCK Setup Time S_CLOCK S_LOAD S_DATA Hold Time S_CLOCK NOTE Characterized using 25MHz ystal.
TABLE CHARACTERISTICS, VCCA 3.3V±5%,VCCO 2.5V±5%, -40°C 85°C
Symbol fOUT Parameter Output Frequency Phase Jitter NOTE Output Rise/Fall Time Mode 312.5MHz, (1.875MHz 20MHz) Test Conditions Minimum Typical 312.5 0.46 Maximum Units
Output Duty Cycle S_DATA S_CLOCK Setup Time S_CLOCK S_LOAD S_DATA Hold Time S_CLOCK NOTE Characterized using 25MHz ystal.
TABLE CHARACTERISTICS, VCCA VCCO 2.5V±5%, -40°C 85°C
Symbol fOUT Parameter Output Frequency Phase Jitter NOTE Output Rise/Fall Time Mode 312.5MHz, (1.875MHz 20MHz) Test Conditions Minimum Typical 312.5 0.45 Maximum Units
Output Duty Cycle S_DATA S_CLOCK Setup Time S_CLOCK S_LOAD S_DATA Hold Time S_CLOCK NOTE Characterized using 25MHz ystal.
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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TYPICAL PHASE NOISE
312.5MHZ (3.3V)
Gigabit Ethernet Filter 312.5MHz
Phase Noise Jitter 1.875MHz 20MHz 0.52ps (typical)
NOISE POWER
-100 -110 -120 -130 -140 -150 -170 -180 -190 100k 100M
Phase Noise Data
OFFSET FREQUENCY (HZ)
843101AGI-312
-160
Phase Noise Result adding Gigabit Ethernet Filter data
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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
2.8V±0.04V
VCCA, VCCO
SCOPE
VCCA VCCO
SCOPE
LVPECL
LVPECL
-1.3V 0.165V
-0.5V 0.125V
3.3V CORE/3.3V OUTPUT LOAD TEST CIRCUIT
3.3V CORE/2.5V OUTPUT LOAD TEST CIRCUIT
Phase Noise Plot
Noise Power
VCCA, VCCO
SCOPE
LVPECL
Phase Noise Mask
Offset Frequency
-0.5V 0.125V
Jitter Area Under Masked Phase Noise Plot
2.5V CORE/2.5V OUTPUT LOAD TEST CIRCUIT
PHASE JITTER
Clock Outputs
PERIOD
PERIOD
100%
OUTPUT RISE/FALL TIME
843101AGI-312
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS843101I-312 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with 10µF .01F bypass capacitor should connected each VCCA. resistor also replaced ferrite bead.
3.3V 2.5V .01F VCCA .01F
FIGURE POWER SUPPLY FILTERING
CRYSTAL INPUT INTERFACE
ICS843101I-312 been characterized with 18pF parallel resonant crystals. capacitor values shown Figure below were determined using 25MHz, 18pF parallel resonant crystal were chosen minimize error.
XTAL_OUT 18pF Parallel Crystal XTAL_IN
Figure CRYSTAL INPUt INTERFACE
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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
RECOMMENDATIONS UNUSED INPUT PINS INPUTS:
CRYSTAL INPUT: applications requiring crystal oscillator input, both XTAL_IN XTAL_OUT left floating. Though required, additional protection, resistor tied from XTAL_IN ground. INPUT: applications requiring test clock, left floating. Though required, additional protection, resistor tied from input ground. LVCMOS CONTROL PINS: control pins have internal pull-ups pull-downs; additional resistance required added additional protection. resistor used.
TERMINATION 3.3V LVPECL OUTPUT
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
3.3V
FOUT
FOUT
((VOH VOL) (VCC
FIGURE LVPECL OUTPUT TERMINATION
FIGURE LVPECL OUTPUT TERMINATION
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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
very close ground level. Figure eliminated termination shown Figure
TERMINATION 2.5V LVPECL OUTPUT
Figure Figure show examples termination 2.5V LVPECL driver. These terminations equivalent terminating 2.5V,
2.5V 2.5V VCC=2.5V 2,5V LVPECL Driv 62.5 62.5
2.5V VCC=2.5V 2,5V LVPECL Driv
FIGURE 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V 2,5V LVPECL Driv
FIGURE 2.5V LVPECL TERMINATION EXAMPLE
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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS843101I-312. Equations example calculations also provided. Power Dissipation. total power dissipation ICS843101I-312 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 92mA 318.78mW Power (outputs)MAX 30mW/Loaded Output pair
Total Power_MAX (3.465V, with outputs switching) 318.78mW 30mW 348.78mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C. equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow linear feet minute multi-layer board, appropriate value 81.8°C/W Table below. Therefore, ambient temperature 85°C with outputs switching 85°C 0.349W *81.8°C/W 113.5°C. This below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE 16-PIN TSSOP, FORCED CONVECTION
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 89.0°C/W
118.2°C/W 81.8°C/W
106.8°C/W 78.1°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
Calculations Equations. purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
CCO_MAX
OH_MAX
CCO_MAX
0.9V
OH_MAX
0.9V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 0.9V)/50] 0.9V 19.8mW ))/R
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
[(2V 1.7V)/50] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30mW
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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE LEAD TSSOP
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 89.0°C/W
118.2°C/W 81.8°C/W
106.8°C/W 78.1°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS843101I-312 4093
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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
PACKAGE OUTLINE SUFFIX LEAD TSSOP
TABLE PACKAGE DIMENSIONS
SYMBOL 0.45 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 0.10 Millimeters Minimum 1.20 0.15 1.05 0.30 0.20 5.10 Maximum
Reference Document: JEDEC Publication MO-153
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FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER
TABLE ORDERING INFORMATION
Part/Order Number Marking Package Shipping Packaging Temperature ICS843101AGI-312 Lead TSSOP tube -40°C 85°C ICS843101AGI-312T Lead TSSOP 2500 tape reel -40°C 85°C ICS843101AGI-312LF Lead "Lead-Free" TSSOP tube -40°C 85°C ICS843101AGI-312LFT Lead "Lead-Free" TSSOP 2500 tape reel -40°C 85°C NOTE: that ordered with "LF" suffix number Pb-Free configuration RoHS complaint.
aforementioned trademarks, HiPerClockS FemtoClocks trademarks Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 843101AGI-312
REV. NOVEMBER 2005

FEMTOCLOCKSCRYSTAL-TO-LVPECL 312.5MHZ FREQUENCY MARGINING SYNTHESIZER

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