700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESI

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700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESI

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ICS8432-11
700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
FEATURES
Dual differential 3.3V LVPECL outputs Selectable crystal oscillator interface LVCMOS/LVTTL TEST_CLK TEST_CLK accept following input levels: LVCMOS LVTTL Maximum FOUT frequency: 700MHz Maximum FOUT/2 frequency: 350MHz range: 200MHz 700MHz Parallel interface programming counter frequency multiplier dividers Cycle-to-cycle jitter: 25ps (maximum) period jitter: 3.3V supply voltage 70°C ambient operating temperature
GENERAL DESCRIPTION
ICS8432-11 general purpose, dual output Crystal-to-3.3V Differential LVPECL High Frequency HiPerClockSSynthesizer member HiPerClockS family High Performance Clock Solutions from ICS. ICS8432-11 selectable TEST_CLK crystal inputs. TEST_CLK input accepts LVCMOS LVTTL input levels translates them 3.3V LVPECL levels. operates frequency range 200MHz 700MHz. frequency programmed steps equal value input reference crystal frequency. Output frequencies 700MHz FOUT 350MHz FOUT/2 programmed using serial parallel interfaces configuration logic. phase noise characteristics multiple frequency outputs ICS8432-11 makes ideal clock source Fiber Channel Infiniband applications.
BLOCK DIAGRAM
VCO_SEL XTAL_SEL TEST_CLK XTAL_IN XTAL_OUT
ASSIGNMENT
XTAL_OUT VCO_SEL nP_LOAD
TEST FOUT/2 nFOUT/2 VCCO FOUT nFOUT
XTAL_IN TEST_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK
ICS8432-11
FOUT nFOUT FOUT/2 nFOUT/2
S_LOAD S_DATA S_CLOCK nP_LOAD M0:M8 N0:N1
TEST
32-Lead LQFP 1.4mm package body Package View
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
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700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
nP_LOAD until serial event occurs. result, bits hardwired divider output divider specific default state that will automatically occur during power-up. TEST output when operating parallel input mode. relationship between frequency, input frequency divider defined follows: fVCO fxtal value required values through shown Table Programmable Frequency Function Table. Valid values which will achieve lock defined frequency defined follows: fOUT fVCO fxtal Serial operation occurs when nP_LOAD HIGH S_LOAD LOW. shift register loaded sampling S_DATA bits with rising edge S_CLOCK. contents shift register loaded into divider output divider when S_LOAD transitions from LOW-to-HIGH. divide output divide values latched HIGHto-LOW transition S_LOAD. S_LOAD held HIGH, data S_DATA input passed directly divider output divider each rising edge S_CLOCK. serial mode used program bits test bits internal registers determine state TEST output follows: TEST Output S_Data, Shift Register Input Output divider CMOS Fout/2
FUNCTIONAL DESCRIPTION
NOTE: functional description that follows describes operation using 25MHz clock input. Valid loop divider values different input frequencies defined Input Frequency Characteristics, Table NOTE
ICS8432-11 features fully integrated therefore requires external components setting loop bandwidth. differential clock input used input ICS8432-11. This input into phase detector. 25MHz clock input provides 25MHz phase detector reference frequency. operates over range 200MHz 700MHz. output divider also applied phase detector. phase detector divider force output frequency times reference frequency adjusting control voltage. Note, that some values (either high low), will achieve lock. output scaled divider prior being sent each LVPECL output buffers. divider provides output duty cycle. programmable features ICS8432-11 support input modes program divider output divider. input operational modes parallel serial. Figure1 shows timing diagram each mode. parallel mode, nP_LOAD input initially LOW. data inputs through passed directly divider output divider. LOW-to-HIGH transition nP_LOAD input, data latched divider remains loaded until next transition
SERIAL LOADING
S_CLOCK
S_DATA S_LOAD
NULL
nP_LOAD
PARALLEL LOADING
M0:M8, N0:N1 nP_LOAD
S_LOAD
Time
FIGURE PARALLEL SERIAL LOAD OPERATIONS
*NOTE:
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NULL timing slot must observed.
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ICS8432-11
700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
Type Input Input Input Unused Power Output Power Output Power Output Pullup divider inputs. Data latched LOW-to-HIGH transistion Pulldown nP_LOAD input. LVCMOS LVTTL interface levels. Pulldown Determines output divider value defined Table Function Table. LVCMOS LVTTL interface levels. connect. Negative supply pins. Test output which ACTIVE serial mode operation. Output driven parallel mode. LVCMOS interface levels. Core supply pin. Half frequency differential output synthesizer. 3.3V LVPECL interface levels. Output supply pin. Differential output synthesizer. 3.3V LVPECL interface levels. Active High Master Reset. When logic HIGH, internal dividers rset causing true outputs (FOUTx) inver outputs (nFOUTx) high. When logic LOW, internal dividers outputs enabled. Asser tion does affect loaded values. LVCMOS LVTTL interface levels. Clocks serial data present S_DATA input into shift register rising edge S_CLOCK. LVCMOS LVTTL interface levels. Shift register serial input. Data sampled rising edge S_CLOCK. LVCMOS LVTTL interface levels. Controls transition data from shift register into dividers. LVCMOS LVTTL interface levels. Analog supply pin. Selects between crystal test inputs reference source. LVCMOS LVTTL interface levels. Selects XTAL inputs when HIGH. Selects TEST_CLK when LOW. Test clock input. LVCMOS LVTTL interface levels. Crystal oscillator inputs. XTAL_IN input. XTAL_OUT output. Parallel load input. Determines when data present M8:M0 loaded into divider, when data present N1:N0 sets output divider value. LVCMOS LVTTL interface levels. Determines whether synthesizer bypass mode. LVCMOS LVTTL interface levels. Description
TABLE DESCRIPTIONS
Number Name TEST FOUT/2, nFOUT/2 VCCO FOUT, nFOUT
Input
Pulldown
S_CLOCK S_DATA S_LOAD VCCA XTAL_SEL TEST_CLK XTAL_IN, XTAL_OUT nP_LOAD VCO_SEL
Input Input Input Power Input Input Input Input Input
Pulldown Pulldown Pulldown
Pullup Pulldown
Pulldown Pullup
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN
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Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor
Test Conditions
Minimum
Typical
Maximum
Units
REV. 2005
ICS8432-11
700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
Inputs
TABLE PARALLEL
nP_LOAD
SERIAL MODES FUNCTION TABLE
Data Data S_LOAD S_CLOCK S_DATA Conditions Reset. counters reset. Data inputs passed directly divider. TEST output forced LOW. Data latched into input registers remains loaded until next transition until serial event occurs. Serial input mode. Shift register loaded with data S_DATA each rising edge S_CLOCK. Contents shift register passed divider. divider output divider values latched. Parallel serial input affect shift registers. S_DATA passed directly divider clocked.
Data Data
Data Data Data Data
NOTE: HIGH Don't care Rising edge transition Falling edge transition
TABLE PROGRAMMABLE FREQUENCY FUNCTION TABLE
Frequency (MHz) Divide
NOTE These divide values resulting frequencies correspond ystal TEST_CLK input frequency 25MHz.
TABLE PROGRAMMABLE OUTPUT DIVIDER FUNCTION TABLE
Inputs
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Output Frequency (MHz) Divider Value Minimum FOUT Maximum 87.5 FOUT/2 Minimum Maximum 62.5 31.25 15.625 87.5 43.75
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ICS8432-11
700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
4.6V -0.5V 50mA 100mA 47.9°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VCCA VCCO ICCA Parameter Positive Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS LVTTL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Input High Voltage Input Voltage M0-M4, M6-M8, S_CLOCK, TEST_CLK, Input S_DATA, S_LOAD, nP_LOAD High Current XTAL_SEL, VCO_SEL M0-M4, M6-M8, S_CLOCK, TEST_CLK, S_DATA, S_LOAD, nP_LOAD XTAL_SEL, VCO_SEL Output High Voltage Output Voltage TEST; NOTE TEST; NOTE Test Conditions Minimum -0.3 3.465V 3.465V 3.465V, 3.465V, Typical Maximum Units
Input Current
-150
NOTE Outputs terminated with VCCO/2. "Parameter Measurement Information" section, "3.3V Output Load Test Circuit" figure.
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700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
TABLE LVPECL CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing
NOTE Outputs terminated with VCCO
TABLE INPUT FREQUENCY CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol Parameter Test Conditions Minimum Typical Maximum Units TEST_CLK; NOTE XTAL_IN, XTAL_OUT; Input Frequency NOTE S_CLOCK NOTE input crystal TEST_CLK frequency range, value must operate within 200MHz 700MHz range. Using minimum input frequency 12MHz, valid values Using maximum frequency 25MHz, valid values
TABLE CRYSTAL CHARACTERISTICS
Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level Test Conditions Minimum Typical Maximum Units Fundamental
TABLE CHARACTERISTICS, VCCA VCCO 3.3V±5%, 70°C
Symbol FOUT tjit(cc) tjit(per) Parameter Output Frequency Cycle-to-Cycle Jitter; NOTE Period Jitter, RMS; NOTE Output Skew; NOTE Output Rise Time Output Fall Time nP_LOAD Setup Time S_DATA S_CLOCK S_CLOCK S_LOAD nP_LOAD Hold Time S_DATA S_CLOCK S_CLOCK S_LOAD Output Duty Cycle 50MHz 50MHz Test Conditions Minimum Typical Maximum Units
tsk(o)
Lock Time tLOCK parameters measured 500MHz unless noted otherwise. NOTE Jitter performance using XTAL inputs. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE This parameter defined accordance with JEDEC Standard
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REV. 2005
ICS8432-11
700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
PARAMETER MEASUREMENT INFORMATION
VCCA, VCCO
SCOPE
VREF
LVPECL
contains 68.26% measurements contains 95.4% measurements contains 99.73% measurements contains 99.99366% measurements contains (100-1.973x10-7)% measurements
Reference Point
Histogram
-1.3V 0.165V
(Trigger Edge)
Mean Period
(First edge after trigger)
3.3V OUTPUT LOAD TEST CIRCUIT
PERIOD JITTER
nFOUT FOUT nFOUT, nFOUT/2 FOUT, FOUT/2
nFOUT/2 FOUT/2
tsk(o)
tcycle
jit(cc) tcycle -tcycle
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
nFOUT, nFOUT/2 FOUT, FOUT/2
PERIOD
Clock Outputs
PERIOD
100%
OUPUT DUTY CYCLE/OUTPUT PULSE WIDTH/PERIOD
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OUTPUT RISE/FALL TIME
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tcycle
ICS8432-11
700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATIONS
STORAGE AREA NETWORKS
variety technologies used interconnection elements within SAN. tables below list common application frequencies well ICS8432-11 configurations used generate appropriate frequency.
Table COMMON SANS APPLICATIONS FREQUENCIES
Interconnect Technology Gigabit Ethernet Fibre Channel Infiniband Clock Rate 1.25 1.0625 2.1250 Reference Frequency SERDES (MHz) 125, 250, 156.25 106.25, 53.125, 132.8125 125, Crystal Frequency (MHz) 19.53125 16.6015625,
Table CONFIGURATION DETAILS
Interconnect Technology
SANS APPLICATIONS
ICS8432-11 Output Frequency SERDES (MHz) 156.25 156.25 53.125 106.25 132.8125 ICS8432-11 Settings
Crystal Frequency (MHz)
Gigabit Ethernet 19.53125 Fiber Channel Fiber Channel Infiniband 16.6015625
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700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS8432-11 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with .01F bypass capacitor should connected each VCCA pin.
3.3V .01F .01F
FIGURE POWER SUPPLY FILTERING
TERMINATION
LVPECL OUTPUTS
transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed drive
3.3V
FOUT
FOUT
((VOH VOL) (VCC
FIGURE LVPECL OUTPUT TERMINATION
FIGURE LVPECL OUTPUT TERMINATION
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700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
actual system will depend selected component types, density components, density traces, stacking P.C. board.
LAYOUT GUIDELINE
schematic ICS8432-11 layout example used this layout guideline shown Figure ICS8432-11 recommended board layout this example shown Figure This layout example used general guideline. lay-
FOUT FOUTN
ICS8432-11
TEST FOUT/2 nFOUT/2 VCCO FOUT nFOUT
VCO_SEL nP_LOAD X_OUT
VCCA S_LOAD S_DATA S_CLOCK 0.01u
X_IN T_CLK XTAL_SEL VCCA S_LOAD S_DATA S_CLOCK
REF_IN XTAL_SEL
0.1u 0.1u
VCC=3.3V
FIGURE SCHEMATIC
RECOMMENDED LAYOUT
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ICS8432-11
700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
differential output traces should have same length. Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock traces same layer. Whenever possible, avoid placing vias clock traces. Placement vias traces affect trace characteristic impedance hence degrade signal integrity. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow spearation least three trace widths between differential clock trace other signal trace. Make sure other signal traces routed between clock trace pair. matching termination resistors should located close receiver input pins possible.
following component footprints used this layout example: resistors capacitors size 0603.
POWER
GROUNDING
Place decoupling capacitors C15, close possible power pins. space allows, placement decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power caused via. Maximize power ground sizes number vias capacitors. This reduce inductance between power ground planes component power ground pins. filter consisting C11, should placed close VCCA possible.
CLOCK TRACES
TERMINATION
Poor signal integrity degrade system performance cause system failure. synchronous high-speed digital systems, clock signal less tolerant poor signal integrity than other signals. ringing rising falling edge excessive ring back cause system failure. shape trace trace delay might restricted available space board component location. While routing traces, clock signal traces should routed first should locked prior routing other signal traces.
CRYSTAL
crystal should located close possible pins (XTAL_IN) (XTAL_OUT). trace length between should kept minimum avoid unwanted parasitic inductance capacitance. Other signal traces should routed near crystal traces.
VCCA Close input pins receiver TL1N
TL1N
TL1, traces equal length
FIGURE BOARD LAYOUT
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ICS8432-11
REV. 2005
ICS8432-11
700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS8432-11. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS8432-11 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 110mA 381.2mW Power (outputs)MAX 30mW/Loaded Output pair outputs loaded, total power 30mW 60mW
Total Power_MAX (3.465V, with outputs switching) 381.2mW 60.4mW 441.2mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow linear feet minute multi-layer board, appropriate value 42.1°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.441W 42.1°C/W 88.6°C. This well below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE
32-PIN LQFP, FORCED CONVECTION
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
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Calculations Equations.
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS8432-11
700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
OH_MAX
CCO_MAX
1.0V
(VCCO_MAX VOH_MAX) 1.0V logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
1.7V
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 1V)/50) 20.0mW
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
))/R
CCO_MAX
OL_MAX
[(2V 1.7V)/50) 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30.2mW
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ICS8432-11
700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
LEAD LQFP
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS8432-11 3765
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ICS8432-11
700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
LEAD LQFP
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.30 0.09 MINIMUM NOMINAL -1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 -0.75 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
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REV. 2005
ICS8432-11
700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESIZER
Marking ICS8432CY-11 ICS8432CY-11 Package Lead LQFP Lead LQFP Shipping Packaging tray 1000 tape reel Temperature 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS8432CY-11 ICS8430CY-11T
aforementioned trademark, HiPerClockSis trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8432CY-11
REV. 2005

700MHZ/350MHZ, PHASE NOISE, CRYSTAL-TO- 3.3V LVPECL FREQUENCY SYNTHESI

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