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FEMTOCLOCKSCRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER FEATURES
Top Searches for this datasheetICS8430252-45 FEMTOCLOCKSCRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER FEATURES differential 3.3V LVPECL output LVCMOS/LVTTL output Crystal oscillator interface designed 25MHz, 18pF parallel resonant crystal 25MHz crystal generates both output frequency 156.25MHz (LVPECL) 125MHz (LVCMOS) frequency: 625MHz phase jitter 156.25MHz (1.875MHz 20MHz) using 25MHz crystal: 0.39ps (typical) Full 3.3V supply mode 70°C ambient operating temperature Industrial temperature available upon request Available both standard lead-free RoHS compliant packages GENERAL DESCRIPTION ICS8430252-45 output LVPECL LVCMOS/LVTTL Synthesizer optimized genHiPerClockSerate Ethernet reference clock frequencies member HiPerClocksfamily high performance clock solutions from ICS. Using 25MHz, 18pF parallel resonant crystal, following frequencies generated: 156.25MHz LVPECL output and, 125MHz LVCMOS output. 8430252-45 uses ICS' generation phase noise technology achieve lower typical phase jitter, easily meeting Ethernet jitter requirements. ICS8430252-45 packaged small 16-pin TSSOP package. BLOCK DIAGRAM Pullup ASSIGNMENT VCCO_A VCCA CLK_EN VCCO_B XTAL_IN XTAL_OUT XTAL_IN XTAL_OUT 25MHz Phase Detector 625MHz Feedback Divider CLK_EN Pullup ICS8430252-45 16-Lead TSSOP 4.4mm 5.0mm 0.92mm package body Package View Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice. 8430252CG-45 REV. DECEMBER 2005 ICS8430252-45 FEMTOCLOCKSCRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Type Description Output enable pin. LVCMOS/LVTTL interface levels. Table Function Table. Negative supply pin. LVCMOS/LVTTL clock output. Output supply output. connect. Analog supply pin. Core supply pin. Crystal oscillator interface. XTAL_IN input, XTAL_OUT output. Output supply outputs. Differential clock outputs. LVPECL interface levels. Clock enable pin. LVCMOS/LVTTL interface levels. Table Function Table. TABLE DESCRIPTIONS Number Name VCCO_A VCCA XTAL_OUT, XTAL_IN VCCO_B nQB, CLK_EN Input Power Output Power Unused Power Power Input Power Output Input Pullup Pullup TABLE CHARACTERISTICS Symbol Parameter RPULLUP Input Capacitance Power Dissipation Capacitance Input Pullup Resistor VCC, VCCA, VCCO_A, VCCO_B 3.465V Test Conditions Minimum Typical Maximum Units TABLE SELECT FUNCTION TABLE Input Output Hi-Z Active TABLE CLK_EN SELECT FUNCTION TABLE Input CLK_EN Active Outputs High Active 8430252CG-45 REV. DECEMBER 2005 ICS8430252-45 FEMTOCLOCKSCRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER 4.6V -0.5V 0.5V 50mA 100mA 89°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability. ABSOLUTE MAXIMUM RATINGS Supply Voltage, Inputs, Outputs, Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCO_A, VCCO_B 3.3V±5%, 70°C Symbol VCCA VCCO_A, VCCO_B ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units TABLE LVCMOS LVTTL CHARACTERISTICS, VCCA VCCO_A 3.3V±5%, 70°C Symbol Parameter Input High Voltage Input Voltage Input High Current Input Current CLK_EN CLK_EN 3.465V 3.465V, -150 Test Conditions Minimum -0.3 Typical Maximum Units Output High Voltage; NOTE Output Voltage; NOTE NOTE Outputs terminated with VCCO_A/2. Parameter Measurement Information Section, "3.3V Output Load Test Circuit". TABLE LVPECL CHARACTERISTICS, VCCA VCCO_B 3.3V±5%, 70°C Symbol VSWING Parameter Output High Voltage; NOTE Output Voltage; NOTE Peak-to-Peak Output Voltage Swing Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units NOTE Outputs terminated with VCCO_B 8430252CG-45 REV. DECEMBER 2005 ICS8430252-45 FEMTOCLOCKSCRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Test Conditions Minimum Typical Fundamental Maximum Units TABLE CRYSTAL CHARACTERISTICS Parameter Mode Oscillation Frequency Equivalent Series Resistance (ESR) Shunt Capacitance Drive Level NOTE: Characterized using 18pF parallel resonant crystal. TABLE CHARACTERISTICS, VCCA VCCO_A, VCCO_B 3.3V±5%, 70°C Symbol fOUT Parameter Output Frequency Range Phase Jitter (Random); NOTE Output Rise/Fall Time Output Duty Cycle 125MHz (1.875MHz 20MHz) 156.25MHz (1.875MHz 20MHz) Test Conditions Minimum Typical 156.25 0.41 0.39 Maximum Units NOTE Please refer Phase Noise Plots. 8430252CG-45 REV. DECEMBER 2005 ICS8430252-45 FEMTOCLOCKSCRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TYPICAL PHASE NOISE 156.25MHZ 10Gb Ethernet Filter 156.25MHz Phase Jitter (Random) 1.875Mhz 20MHz 0.39ps (typical) NOISE POWER -100 -110 Phase Noise Data -120 -130 -140 -160 -170 -180 -190 Phase Noise Result adding 10Gb Ethernet Filterto data 100k -150 100M OFFSET FREQUENCY (HZ) 8430252CG-45 REV. DECEMBER 2005 ICS8430252-45 FEMTOCLOCKSCRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER PARAMETER MEASUREMENT INFORMATION 1.65V±5% VCCA, VCCO_B SCOPE VCCA VCCO_A SCOPE LVPECL LVCMOS -1.3V±0.165V -1.65V±5% 3.3V CORE/3.3V LVPECL OUTPUT LOAD TEST CIRCUIT Phase Noise Plot 3.3V CORE/3.3V LVCMOS OUTPUT LOAD TEST CIRCUIT CCO_LVCMOS Noise Power Phase Noise Mask PERIOD Offset Frequency PERIOD 100% Jitter Area Under Masked Phase Noise Plot PHASE JITTER LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD PERIOD PERIOD Clock Outputs 100% LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD Clock Outputs LVCMOS OUTPUT RISE/FALL TIME LVPECL OUTPUT RISE/FALL TIME 8430252CG-45 REV. DECEMBER 2005 ICS8430252-45 FEMTOCLOCKSCRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER APPLICATION INFORMATION POWER SUPPLY FILTERING TECHNIQUES high speed analog circuitry, power supply pins vulnerable random noise. ICS8430252-45 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCO_X should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with .01F bypass capacitor should connected each VCCA pin. 3.3V .01F VCCA .01F FIGURE POWER SUPPLY FILTERING CRYSTAL INPUT INTERFACE ICS8430252-45 been characterized with 18pF parallel resonant crystals. capacitor values shown Figure below were determined using 25MHz, 18pF parallel resonant crystal were chosen minimize error. XTAL_OUT 18pF Parallel Crystal XTAL_IN Figure CRYSTAL INPUt INTERFACE 8430252CG-45 REV. DECEMBER 2005 ICS8430252-45 FEMTOCLOCKSCRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RECOMMENDATIONS UNUSED INPUT INPUTS: OUTPUT PINS OUTPUTS: LVCMOS OUTPUT: unused LVCMOS output left floating. recommend that there trace attached. LVPECL OUTPUT unused LVPECL outputs left floating. recommend that there trace attached. Both sides differential output pair should either left floating terminated. SELECT PINS: select pins have internal pull-ups pull-downs; additional resistance required added additional protection. resistor used. TERMINATION 3.3V LVPECL OUTPUT designed drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations. clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs 3.3V FOUT ((VOH VOL) (VCC FOUT FIGURE LVPECL OUTPUT TERMINATION FIGURE LVPECL OUTPUT TERMINATION 8430252CG-45 REV. DECEMBER 2005 ICS8430252-45 FEMTOCLOCKSCRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER POWER CONSIDERATIONS This section provides information power dissipation junction temperature ICS8430252-45. Equations example calculations also provided. Power Dissipation. total power dissipation ICS8430252-45 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load. Power (core)MAX VCC_MAX IEE_MAX 3.465V 75mA 259.88mW Power (outputs)MAX 30mW/Loaded Output pair outputs loaded, total power 30mW 90mW Total Power_MAX (3.465V, with outputs switching) 259.9mW 60mW 319.9mW Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C. equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow linear feet minute multi-layer board, appropriate value 81.8°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.320W 81.8°C/W 96.2°C. This well below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer). TABLE THERMAL RESISTANCE 16-PIN TSSOP, FORCED CONVECTION Velocity (Linear Feet Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 89.0°C/W 118.2°C/W 81.8°C/W 106.8°C/W 78.1°C/W NOTE: Most modern designs multi-layered boards. data second pertains most designs. 8430252CG-45 REV. DECEMBER 2005 ICS8430252-45 FEMTOCLOCKSCRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER Calculations Equations. purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure VOUT FIGURE LVPECL DRIVER CIRCUIT TERMINATION calculate worst case power dissipation into load, following equations which assume load, termination voltage logic high, VOUT VOH_MAX VCC_MAX 0.9V CCO_MAX OH_MAX 0.9V 1.7V logic low, VOUT CCO_MAX OL_MAX CC_MAX OL_MAX 1.7V Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. ))/R 2V))/R [(2V Pd_H OH_MAX CC_MAX CC_MAX OH_MAX OH_MAX CC_MAX OH_MAX CC_MAX [(2V 0.9V)/50] 0.9V 19.8mW Pd_L OL_MAX CC_MAX 2V))/R CC_MAX OL_MAX [(2V CC_MAX OL_MAX ))/R CC_MAX OL_MAX [(2V 1.7V)/50] 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30mW 8430252CG-45 REV. DECEMBER 2005 ICS8430252-45 FEMTOCLOCKSCRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER RELIABILITY INFORMATION TABLE JAVS. FLOW TABLE LEAD TSSOP Velocity (Linear Feet Minute) Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 137.1°C/W 89.0°C/W 118.2°C/W 81.8°C/W 106.8°C/W 78.1°C/W NOTE: Most modern designs multi-layered boards. data second pertains most designs. TRANSISTOR COUNT transistor count ICS8430252-45 2070 8430252CG-45 REV. DECEMBER 2005 ICS8430252-45 FEMTOCLOCKSCRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER LEAD TSSOP PACKAGE OUTLINE SUFFIX TABLE PACKAGE DIMENSIONS SYMBOL 0.45 -4.30 -0.05 0.80 0.19 0.09 4.90 6.40 BASIC 4.50 0.65 BASIC 0.75 0.10 Millimeters Minimum 1.20 0.15 1.05 0.30 0.20 5.10 Maximum Reference Document: JEDEC Publication MO-153 8430252CG-45 REV. DECEMBER 2005 ICS8430252-45 FEMTOCLOCKSCRYSTAL-TO-3.3V LVPECL FREQUENCY SYNTHESIZER TABLE ORDERING INFORMATION Part/Order Number Marking Package Shipping Packaging Temperature ICS8430252CG-45 30252C45 Lead TSSOP tube 70°C ICS8430252CG-45T 30252C45 Lead TSSOP 2500 tape reel 70°C ICS8430252CG-45LF Lead "Lead-Free" TSSOP tube 70°C ICS8430252CG-45LFT Lead "Lead-Free" TSSOP 2500 tape reel 70°C NOTE: that ordered with "LF" suffix number Pb-Free configuration RoHS compliant. aforementioned trademarks, HiPerClockS FemtoClocks trademarks Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 8430252CG-45 REV. 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