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700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR


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ICS843002-31
700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR
FEATURES
Outputs: high frequency differential LVPECL outputs Output frequency: 700MHz LVCMOS/LVTTL VCXO output with output enable Reference clock output with output enable LOCK detect output Input supports selectable inputs: differential input pair LVCMOS/LVTTL input clocks 13-bit VCXO feedback reference dividers provide wide range frequency translation ratio options FemtoClock frequency multiplier supports rate 560MHz 700MHz `Lock Detect' output reports lock status VCXO VCXO circuit provides jitter attenuation with loop bandwidth 250Hz below (user adjustable) phase jitter, random 12kHz 20MHz: <1ps (design target) 3.3V supply voltage 70°C ambient operating temperature Industrial temperature information available upon request Available both standard lead-free RoHS-compliant packages
GENERAL DESCRIPTION
ICS843002-31 member HiperClockSfamily high performance clock HiPerClockSsolutions from ICS. This monolithic device high-performance, PLL-based synchronous clock generator jitter attenuation circuit. ICS843002-31 contains clock multiplication stages that cascaded series. first stage VCXO-based that optimized provide reference clock jitter attenuation, jitter tolerant, provide stable reference clock second multiplication stage. second stage proprietary FemtoClockcircuit which high-frequency, sub-picosecond clock multiplier.
VCXO on-chip VCXO circuit that uses external, inexpensive pullable crystal 17.5 25MHz range. includes reference feedback dividers supporting complex multiplication ratios input reference clock rates 2.3kHz. External loop filter components used (two resistors capacitors) achieve loop bandwidth needed jitter attenuation recovered data clock. FemtoClock circuit multiply VCXO crystal frequency factor (selectable) provide clock output 700MHz. Clock Input/Output Configuration: Clock Inputs differential pair, singled ended (mux selected) Differential input pair support LVPECL, LVDS, LVHSTL, SSTL, HCSL single-ended LVCMOS LVTTL levels Singled ended inputs support LVCMOS LVTTL levels Clock Outputs, FemtoClockS LVPECL pairs (selectable output dividers) Clock Output, VCXO single ended output VCXO crystal frequency) Clock Output, other VCXO reference clock Example Applications: SONET/SDH line card clock generator 622.08MHz OC-48) using 8kHz frame clock input reference Jitter attenuation recovered communications clock Complex-ratio clock frequency translation between various communication protocols, such telecom, OC-12 rate conversion, 622.08MHz 34.368MHz, ratio 179/32 digital video, ITU-R601 SMPTE 252M/59.94, 27MHz 74.17582MHz, ratio 250/91
VCCA_XO XTAL_IN XTAL_OUT
ASSIGNMENT
XOFB0 XOFB1 XOFB2 XOFB3 XOFB4 XOFB5 XOFB6 XOFB7 XOFB8 XOFB9 XOFB10 XOFB11
ISET CLK0 nCLK0 OE_REF CLK1 SEL1 SEL0 CLK2
64-Lead TQFP, EPAD 10mm 10mm 1.0mm package body package View
XOFB12
ICS843002-31
REF_CLK VCLK LOCK VCCO_CMOS VCCO_PECL NPB0 NPB1 NPB2 VCCA
Preliminary Information presented herein represents product prototyping pre-production. noted characteristics based initial product characterization. Integrated Circuit Systems, Incorporated (ICS) reserves right change circuitry specifications without notice.
843002CY-31
XOIN12 XOIN11 XOIN10 XOIN9 XOIN8 XOIN7 XOIN6 XOIN5 XOIN4 XOIN3 XOIN2 XOIN1 XOIN0 NPA2 NPA1 NPA0
REV. NOVEMBER 2005
ICS843002-31
700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR
BLOCK DIAGRAM NOMINAL SYSTEM CONFIGURATION
NPB[2:0] NPA[2:0] NV[1:0]
VCXO Output Divider NV[1:0] Disabled Drive Output Divider NPA[2:0] 000: 001: 010: 011: 100: 101: 110: 111: Disabled Drive
ISET Charge Pump Current
VCLK
CLK0 nCLK0
External Loop Filter Connection 17.5 25MHz
XTAL_OUT XTAL_IN
CLK1
Input Divider
CLK2
XOIN[12:0] ÷8191
VCXO
FemtoClockFrequency Multiplier
Bypass VCXO Feedback Divider
Output Divider NPB[2:0] 000: 001: 010: 011: 100: 101: 110: 111: XOIN Output Output Output Disabled Drive
SEL1 SEL0 XOIN[12:0] XOFB[12:0]
XOFB[12:0] ÷8191
REF_CLK OE_REF
LOCK Detect
LOCK
NOTE application configuration (non-test/bypass modes). NOTE Bold lines primary clock paths (non-control/non-feedback lines). control lines signal paths shown this simplified block diagram.
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REV. NOVEMBER 2005
ICS843002-31
700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR
SIMPLIFIED BLOCK DIAGRAM CLOCK SIGNAL PATHS
BYPASS MODE
ISET Charge Pump Current External Loop Filter Connection 17.5 25MHz Bypass
VCXO Output Divider NV[1:0] Disabled Drive Output Divider NPA[2:0] NPA[2:0] 000: 001: 010: 011: 100: 101: 110: 111: Disabled Drive
VCLK
CLK0 nCLK0
XTAL_OUT
Input Divider XOIN[12:0] ÷8191
CLK1
XTAL_IN
VCXO
FemtoClockFrequency Multiplier
CLK2
000: 001: 010: 011: 111: Disabled
SEL1 SEL0
VCXO Feedback Divider XOFB[12:0] ÷8191
FemtoClockFeedback Divider 110: 101: XOFB 100: XOIN
NPB2 NPB1 NPB0
NOTE Setting SEL1:SEL0 enables bypass mode. Only clock signals CLK0/nCLK0 input pair routed device bypass mode. NOTE Bold lines show clock bypass paths. control lines signal paths shown this simplified block diagram.
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ICS843002-31
700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR
Description Loop filter connection pins. Charge pump current setting pin. Negative supply pins. Normally connected ground. VCXO output divider control pins. Pullup LVCMOS/LVTTL interface levels. Core power supply pins. Master Reset. When HIGH, resets internal dividers Pulldown LVCMOS outputs high impedance. LVCMOS LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup/ Inver ting differential clock input. Pulldown VCC/2 bias voltage when left floating. Output enable control reference clock output. When logic LOW, Pulldown reference clock output high impedance. When logic HIGH, output enabled. LVCMOS/LVTTL interface levels. Pulldown Clock input. LVCMOS/LVTTL interface levels. Pulldown Input clock select. LVCMOS/LVTTL interface levels. Pulldown Clock input. LVCMOS/LVTTL interface levels.
TABLE DESCRIPTIONS (CONTINUED NEXT PAGE)
Number Name LF1, ISET NV1, CLK0 nCLK0 OE_REF CLK1 SEL1, SEL0 CLK2 Type Analog Input/Output Analog Input/Output Power Input Power Input Input Input Input Input Input Input
XOIN12:XOIN1
Input
Pulldown
VCXO input divider control input. LVCMOS/LVTTL interface levels.
XOIN0 NPA2, NPA1, NPA0 VCCA NPB2, NPB1, NPB0 VCCO_PECL VCCO_CMOS LOCK VCLK REF_CLK
Input Input Power Input Input Power Output Output Power Output Output Output
VCXO input divider control input. LVCMOS/LVTTL interface levels. LVPECL output divider control QA/nQA outputs. Pulldown LVCMOS/LVTTL interface levels. Analog supply pin. LVPECL output divider control QB/nQB outputs. Pulldown LVCMOS/LVTTL interface levels. FemtoClockcircuit clock multiplication control input. Pulldown When HIGH, selects When LOW, selects LVCMOS/LVTTL interface levels. Output power supply LVPECL clock outputs. Pullup Differential clock output pair. LVPECL interface levels. Differential clock output pair. LVPECL interface levels. Output power supply LVCMOS outputs. Lock detect output. LVCMOS/LVTTL interface levels. VCXO clock output. LVCMOS/LVTTL interface levels. Reference clock output. LVCMOS/LVTTL interface levels.
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
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700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR
FROM PREVIOUS PAGE)
TABLE DESCRIPTIONS (CONTINUED
Number Name
Type
Description
XOFB12:XOFB1
Input
Pulldown
VCXO feedback divider control input. LVCMOS/LVTTL interface levels.
XOFB0 XTAL_OUT, XTAL_IN VCCA_XO
Input Input Power
Pullup
VCXO feedback divider control input. LVCMOS/LVTTL interface levels. VCXO crystal oscillator interface. XTAL_IN input. XTAL_OUT output. Analog power supply VCXO.
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Power Dissipation Capacitance (per LVCMOS output) Input Pullup Resistor Input Pulldown Resistor Output Impedance VCC, VCCA, VCCA_XO, VCCO_CMOS, VCCO_PECL 3.465V Test Conditions Minimum Typical Maximum Units
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ICS843002-31
700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR
QB/nQB output divider control pins, NPB[2:0] divide This sets QB/nQB LVPECL output pair 155.52MHz. (1.544MHz 44.736MHz outputs) Since 44.736MHz slightly higher than maximum VCXO output frequency, FemtoClock circuit will have used. Using pullable 22.368MHz XTAL_IN/XTAL_OUT, VCXO feedback divider pins, XOFB[12:0] 2796 input divider pins, XOIN[12:0] 193. This multiplies 1.544MHz reference 22.368MHz (1.544MHz 2796/193 22.368MHz). FemtoClock multiplication control pin, which sets 626.304MHz. QA/nQA output divider control pins, NPA[2:0] divide This sets QA/nQA LVPECL output pair 44.736MHz. QB/nQB output divider control pins, NPB[2:0] divide This sets QB/nQB LVPECL output pair 44.736MHz (1.544MHz 2.048MHz outputs) 2.048MHz output frequency requirement enough that FemtoClock circuit required. Only VCXO stage used this frequency translation. Using pullable 24.576MHz XTAL_IN/XTAL_OUT, VCXO feedback divider pins, XOFB[12:0] 3072 input divider pins, XOIN[12:0] 193. This multiplies 1.544MHz reference 2.048MHz (1.544MHz 3072/193 24.576MHz). VCXO Output Divider control pins, NV[1:0] /12. This divides 24.576MHz VCXO frequency down 2.048MHz.
SECTION FREQUENCY TRANSLATION
ICS843002-31 stage device, VCXO stage followed phase noise FemtoClock multiplier stage. VCXO uses pullable crystal lock reference clock provide output frequency 25MHz single-ended VCLK output. higher frequencies, phase noise FemtoClock multiply VCXO output clock 700MHz differential LVPECL output pairs (QA/nQA, QB/nQB). VCXO stage 13-bit input divider 13-bit feedback divider generate large integer ratios needed some frequency translation applications. When configuring device pullable crystals 17.5MHz 25MHz range VCXO stage, ensure that FemtoClock kept within range 560MHz 700MHz. Below examples: 8kHz 622.08MHz 155.52MHz This frequency translation requires both VCXO FemtoClock circuit. VCXO used multiply 19.44MHz reference clock FemtoClock which will multiplication from 19.44MHz 622.08MHz. Using 19.44MHz pullable crystal XTAL_IN/ XTAL_OUT, VCXO feedback divider pins, XOFB[12:0], 2430. This multiplies 8kHz reference clock 19.44MHz. FemtoClock multiplication control pin, which sets multiplication factor This sets FemtoClock 622.08MHz. QA/nQA output divider control pins, NPA[2:0] divide This sets QA/nQA LVPECL output pair 622.08MHz.
SECTION FREQUENCY CONFIGURATION
Frequency Configuration Table Examples (see following pages) intended show most common frequency translation requirements. sorted order descending input frequency. intended exhaustive configuration table because that would impractical with almost billion possible configurations. configuration concerned, frequencies 25MHz generated with VCXO while frequencies 25MHz require downstream FemtoClock which multiply VCXO output 700MHz. Complex integer ratios handled with VCXO stage FemtoClock circuit configured multiply VCXO output following example will illustrate configuration process. Assume have 1.544MHz clock which needs multiplied 622.08MHz (OC12). Obviously, FemtoClock multiplier will needed achieve 622.08MHz. Since FemtoClock selectable multiplication factor
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this means there viable VCXO crystal choices which fall within 17.5MHz 15MHz range: 22.217143MHz (/28 feedback divider) 19.44MHz (/32 feedback divider). feedback divider FemtoClock multiplier will give slightly better phase noise, this case 22.217143/1.544 cannot exactly achieved with 13-bit input feedback VCXO dividers. Using setting FemtoClock allows ratio 19.44/1.544 2430/193 which easily achievable. FemtoClock would 19.44MHz crystal would used. VCXO input divider would VCXO feedback divider would 2430. double check solution, perform following calculation: 1.544 2430 32/193 622.08MHz. FemtoClock multiplier output, QB/nQB, equal QA/nQA output frequency fraction frequency. following fractional values available:
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TABLE FREQUENCY CONFIGURATION EXAMPLES,
CONTINUED NEXT PAGE
Input Frequency (MHz) Application 622.08 622.08 (OC12) 622.08 311.04 (SONET) 622.08 155.52 (OC12 OC3) 622.08 77.76 (SONET) 622.08 51.84 (OC12 OC1) 622.08 38.88 (SONET) 622.08 19.44 (SONET) 622.08-> 44.736 (OC12 622.08 34.368 (OC12 622.08 32.064 (OC12 622.08 2.048 (OC12 622.08 1.544 (OC12 T1/J1) 622.08 622.08 626.304 622.08 622.08 622.08 622.08 622.08 311.04 311.04 (SONET) 311.04 155.52 (SONET) 311.04 77.76 (SONET) 311.04 51.84 (SONET) 311.04 38.88 (SONET) 311.04 19.44 (SONET) 311.04 622.08 (SONET) 311.04 622.08 (SONET) 311.04 44.736 (SONET 311.04 34.368 (SONET 311.04 32.064 (SONET 311.04 2.048 (SONET 311.04 1.544 (SONET T1/J1) 155.52 155.52 (OC3) 155.52 77.76 (SONET) 155.52 51.84 (OC3 OC1) 155.52 38.88 (SONET) 155.52 19.44 (SONET) 155.52 311.04 (SONET) 19.44 19.44 19.44 19.44 19.44 19.44 19.44 22.368 34.368 32.064 24.576 24.704 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 22.368 34.368 32.064 24.576 24.704 19.44 19.44 19.44 19.44 19.44 19.44 2430 1620 1620 3240 622.08 622.08 622.08 622.08 622.08 4860 3240 3240 6480 626.304 622.08 622.08 622.08 622.08 622.08 622.08
Output Frequency (MHz)
VCXO FemtoClock Output
Required VCXO Crystal Frequency (MHz)
VCXO Input Divider
VCXO Feedback Divider
VCXO Output Divider
FemtoClock ultiplication Factor
FemtoClock Output Frequency (MHz)
FemtoClock Output Divider
622.08
622.08
FemtoClock Output
622.08
311.04
FemtoClock Output
622.08
155.52
FemtoClock Output
622.08
77.76
FemtoClock Output
622.08
51.84
FemtoClock Output
622.08
38.88
FemtoClock Output
622.08
19.44
VCXO Output
622.08
44.736
FemtoClock Output
622.08
34.368
VCXO Output
622.08
32.064
VCXO Output
622.08
2.048
VCXO Output
622.08
1.544
VCXO Output
311.04
311.04
FemtoClock Output
311.04
155.52
FemtoClock Output
700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR
311.04
77.76
FemtoClock Output
311.04
51.84
FemtoClock Output
311.04
38.88
FemtoClock Output
311.04
19.44
VCXO Output
311.04
622.08
FemtoClock Output
311.04
622.08
FemtoClock Output
311.04
44.736
FemtoClock Output
311.04
34.368
VCXO Output
311.04
32.064
VCXO Output
311.04
2.048
VCXO Output
311.04
1.544
VCXO Output
155.52
155.52
FemtoClock Output
155.52
77.76
FemtoClock Output
155.52
51.84
FemtoClock Output
155.52
38.88
FemtoClock Output
155.52
19.44
VCXO Output
ICS843002-31
REV. NOVEMBER 2005
155.52
311.04
FemtoClock Output
843002CY
TABLE FREQUENCY CONFIGURATION EXAMPLES,
CONTINUED NEXT PAGE
Input Frequency (MHz) VCXO Feedback Divider Application 155.52 622.08 (OC3 OC12) 155.52 44.736 (OC3 155.52 34.368 (OC3 155.52 32.064 (OC3 155.52 2.048 (OC3 155.52 1.544 (OC3 T1/J1) 77.76 77.76 (SONET) 77.76 51.84 (SONET) 77.76 38.88 (SONET) 77.76 19.44 (SONET) 77.76 155.52 (SONET) 77.76 311.04 (SONET) 622.08 622.08 622.08 622.08 622.08 622.08 626.304 626.304 77.76 622.08 (SONET) 77.76 44.736 (SONET 77.76 34.368 (SONET 77.76 32.064 (SONET 77.76 2.048 (SONET 77.76 1.544 (SONET T1/E1) 51.84 51.84 (SONET) 51.84 38.88 (SONET) 51.84 19.44 (SONET) 51.84 77.76 (SONET) 51.84 155.52 (OC1 OC3) 51.84 311.04 (SONET) 51.84 622.08 (OC1 OC12) 51.84 44.736 (OC1 51.84 34.368 (OC1 51.84 32.064 (OC1 51.84 2.048 (OC1 51.84 1.544 (OC1 T1/J1) 44.736 44.736 (T3) 626.304 622.08 622.08 622.08 622.08 622.08 622.08 626.304 622.08 VCXO Output Divider FemtoClock ultiplication Factor 19.44 22.368 34.368 32.064 24.576 24.704 19.44 19.44 19.44 19.44 19.44 19.44 19.44 22.368 34.368 32.064 24.576 24.704 19.44 19.44 19.44 19.44 19.44 19.44 19.44 22.368 34.368 32.064 24.576 24.704 22.368 1215 1215 1620
Output Frequency (MHz)
VCXO FemtoClock Output
Required VCXO Crystal Frequency (MHz)
VCXO Input Divider
FemtoClock Output Frequency (MHz) FemtoClock Output Divider
155.52
622.08
FemtoClock Output
155.52
44.736
FemtoClock Output
155.52
34.368
VCXO Output
155.52
32.064
VCXO Output
155.52
2.048
VCXO Output
155.52
1.544
VCXO Output
77.76
77.76
FemtoClock Output
77.76
51.84
FemtoClock Output
77.76
38.88
FemtoClock Output
77.76
19.44
VCXO Output
77.76
155.52
FemtoClock Output
77.76
311.04
FemtoClock Output
77.76
622.08
FemtoClock Output
700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR
77.76
44.736
FemtoClock Output
77.76
34.368
VCXO Output
77.76
32.064
VCXO Output
77.76
2.048
VCXO Output
77.76
1.544
VCXO Output
51.84
51.84
FemtoClock Output
51.84
38.88
FemtoClock Output
51.84
19.44
VCXO Output
51.84
77.76
FemtoClock Output
51.84
155.52
FemtoClock Output
51.84
311.04
FemtoClock Output
51.84
622.08
FemtoClock Output
51.84
44.736
FemtoClock Output
51.84
34.368
VCXO Output
51.84
32.064
VCXO Output
51.84
2.048
VCXO Output
51.84
1.544
VCXO Output
ICS843002-31
REV. NOVEMBER 2005
44.736
44.736
FemtoClock Output
843002CY-31
TABLE FREQUENCY CONFIGURATION EXAMPLES,
CONTINUED NEXT PAGE
Input Frequency (MHz) VCXO Feedback Divider Application 44.736 1.544 T1/J1) 44.736 2.048 44.736 19.44 SONET) 44.736 32.064 44.736 34.368 44.736 38.88 SONET) 44.736 51.84 OC1) 44.736 77.76 SONET) 44.736 155.52 OC3) 44.736 311.04 SONET) 44.736 622.08 OC12) 38.88 38.88 (SONET) 38.88 19.44 (SONET) 626.304 626.304 626.304 38.88 77.76 (SONET) 38.88 155.52 (SONET OC3) 38.88 311.04 (SONET) 38.88 622.08 (SONET OC12) 38.88 44.736 (SONET 38.88 34.368 (SONET 38.88 32.064 (SONET 38.88 2.048 (SONET 38.88 ->1.544 (SONET DS1/J1) 34.368 34.368 (E3) 34.368 44.736 34.368 32.064 34.368 19.44 SONET) 34.368 2.048 34.368 1.544 32.064 32.064 (J3) 32.064 34.368 32.064 44.736 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 622.08 VCXO Output Divider FemtoClock ultiplication Factor 24.704 24.576 19.44 32.064 34.368 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 19.44 22.368 34.368 32.064 24.576 24.704 34.368 22.368 32.064 19.44 24.576 24.704 32.064 34.368 22.368 1215
Output Frequency (MHz)
VCXO FemtoClock Output
Required VCXO Crystal Frequency (MHz)
VCXO Input Divider
FemtoClock Output Frequency (MHz) FemtoClock Output Divider
44.736
1.544
VCXO Output
44.736
2.048
VCXO Output
44.736
19.44
VCXO Output
44.736
32.064
VCXO Output
44.736
34.368
VCXO Output
44.736
38.88
FemtoClock Output
44.736
51.84
FemtoClock Output
44.736
77.76
FemtoClock Output
44.736
155.52
FemtoClock Output
44.736
311.04
FemtoClock Output
44.736
622.08
FemtoClock Output
38.88
38.88
FemtoClock Output
38.88
19.44
VCXO Output
700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR
38.88
77.76
FemtoClock Output
38.88
155.52
FemtoClock Output
38.88
311.04
FemtoClock Output
38.88
622.08
FemtoClock Output
38.88
44.736
FemtoClock Output
38.88
34.368
VCXO Output
38.88
32.064
VCXO Output
38.88
2.048
VCXO Output
38.88
1.544
VCXO Output
34.368
34.368
VCXO Output
34.368
44.736
FemtoClock Output
34.368
32.064
VCXO Output
34.368
19.44
VCXO Output
34.368
2.048
VCXO Output
34.368
1.544
VCXO Output
32.064
32.064
VCXO Output
32.064
34.368
VCXO Output
ICS843002-31
REV. NOVEMBER 2005
32.064
44.736
FemtoClock Output
843002CY
TABLE FREQUENCY CONFIGURATION EXAMPLES,
CONTINUED NEXT PAGE
Input Frequency (MHz) Application 32.064 2.048 32.064 1.544 19.44 19.44 (SONET) 19.44 38.88 (SONET) 19.44 51.84 (SONET OC1) 19.44 77.76 (SONET) 19.44 155.52 (SONET OC3) 19.44 311.04 (SONET) 19.44 622.08 (SONET OC12) 19.44 44.736 (SONET 19.44 34.368 (SONET 19.44 32.064 (SONET 19.44 2.048 (SONET 2796 3088 3072 2430 4008 626.304 626.304 19.44 1.544 (SONET T1/J1) 19.44 666.5142857 (255/238 FEC) 19.44 669.3265823 (255/237 FEC) 19.44 672.1627119 (255/236 FEC) 2.048 2.048 (E1) 2.048 1.544 toT1/J1) 2.048 34.368 2.048 32.064 2.048 44.736 1.544 1.54 (T1/J1) 1.544 2.048 1.544 32.064 (T1/J1 1.544 34.368 (T1/J1 1.544 44.736 (T1/J1 8KHz 1.544MHz (Frame Clock 8KHz 2.048MHz (Frame Clock 8KHz 19.44MHz (Frame Clock SONET) 8KHz 32.064MHz (Frame Clock 24.576 24.704 19.44 19.44 19.44 19.44 19.44 19.44 19.44 22.368 34.368 32.064 24.576 24.704 669.3265823 672.1627119 666.5142857 20.82857143 20.9164557 21.00508475 24.576 24.704 34.368 32.064 22.368 24.704 24.576 32.064 34.368 22.368 24.704 24.576 19.44 32.064 4296 4008 3072 1215 1544 626.304 622.08 622.08 622.08 622.08 622.08 622.08
Output Frequency (MHz)
VCXO FemtoClock Output
Required VCXO Crystal Frequency (MHz) VCXO Input Divider VCXO Feedback Divider FemtoClock Output Divider VCXO Output Divider FemtoClock ultiplication Factor
FemtoClock Output Frequency (MHz)
32.064
2.048
VCXO Output
32.064
1.544
VCXO Output
19.44
19.44
VCXO Output
19.44
38.88
FemtoClock Output
19.44
51.84
FemtoClock Output
19.44
77.76
FemtoClock Output
19.44
155.52
FemtoClock Output
19.44
311.04
FemtoClock Output
19.44
622.08
FemtoClock Output
19.44
44.736
FemtoClock Output
19.44
34.368
VCXO Output
19.44
32.064
VCXO Output
19.44
2.048
VCXO Output
19.44
1.544
VCXO Output
700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR
19.44
666.5142857
FemtoClock Output
19.44
669.3265823
FemtoClock Output
19.44
672.1627119
FemtoClock Output
2.048
2.048
VCXO Output
2.048
1.544
VCXO Output
2.048
34.368
VCXO Output
2.048
32.064
VCXO Output
2.048
44.736
FemtoClock Output
1.544
1.544
VCXO Output
1.544
2.048
VCXO Output
1.544
32.064
VCXO Output
1.544
34.368
VCXO Output
1.544
44.736
FemtoClock Output
0.008
1.544
VCXO Output
0.008
2.048
VCXO Output
0.008
19.44
VCXO Output
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0.008
32.064
VCXO Output
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TABLE FREQUENCY CONFIGURATION EXAMPLES
Required VCXO Crystal Frequency (MHz) VCXO Input Divider VCXO Feedback Divider Application 8KHz 34.368MHz (Frame Clock 8KHz 44.736MHz (Frame Clock 8KHz 38.88MHz (Frame Clock SONET) 8KHz 77.76MHz (Frame Clock SONET) 8KHz ->155.52MHz (Frame Clock OC3) 8KHz 311.04MHz (Frame Clock SONET) 8KHz 622.08MHz (Frame Clock OC12) 4296 2796 2430 622.08 622.08 622.08 622.08 622.08 2430 2430 2430 2430 626.304 VCXO Output Divider FemtoClock ultiplication Factor FemtoClock Output Divider FemtoClock Output Frequency (MHz) 34.368 22.368 19.44 19.44 19.44 19.44 19.44
Input Frequency (MHz)
Output Frequency (MHz)
VCXO FemtoClock Output
0.008
34.368
VCXO Output
0.008
44.736
FemtoClock Output
0.008
38.88
FemtoClock Output
0.008
77.76
FemtoClock Output
0.008
155.52
FemtoClock Output
0.008
311.04
FemtoClock Output
0.008
622.08
FemtoClock Output
700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR
ICS843002-31
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4.6V -0.5V 0.5V -0.5V VCCO 0.5V 50mA 100mA 22.3°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, (LVCMOS) Outputs, (LVPECL) Continuous Current Surge Current Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VCCA VCCA_XO VCCO_CMOS VCCO_PECL 3.3V±5%, 70°C
Symbol VCCA, VCCA_XO VCCO_CMOS, VCCO_PECL ICCA Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS LVTTL CHARACTERISTICS, VCCA VCCA_XO VCCO_CMOS 3.3V±5%, 70°C
Symbol Parameter Input High Voltage Input Voltage OE_REF, SEL0, SEL1, XOIN[12:1], NPA[2:0], NPB[2:0], Input CLK1, CLK2, XOFB[12:1] High Current NV0, NV1, XOIN0, XOFB0 OE_REF, SEL0, SEL1, XOIN[12:1], NPA[2:0], NPB[2:0], Input CLK1, CLK2, XOFB[12:1] Current NV0, NV1, XOIN0, XOFB0 Output High Voltage Output Voltage REF_CLK, VCLK, LOCK; NOTE REF_CLK, VCLK, LOCK; NOTE Test Conditions Minimum -0.3 3.465V 3.465V 3.465V, 3.465V, -150 Typical Maximum Units
NOTE Outputs terminated with VCCO_CMOS/2.
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Test Conditions CLK0 nCLK0 CLK0 nCLK0 3.465V 3.465V 3.465V 3.465V -150 0.15 0.85 Minimum Typical Maximum Units
TABLE DIFFERENTIAL CHARACTERISTICS, VCCA VCCA_XO VCCO_CMOS VCCO_PECL 3.3V±5%, 70°C
Symbol Parameter Input High Current Input Current
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE NOTE Common mode voltage defined VIH. NOTE single ended applications, maximum input voltage CLK0, nCLK0 0.3V.
TABLE LVPECL CHARACTERISTICS, VCCA VCCA_XO VCCO_PECL 3.3V±5%, 70°C
Symbol Parameter Output High Voltage; NOTE Output Voltage; NOTE Test Conditions Minimum VCCO VCCO Typical Maximum VCCO VCCO Units
VSWING Peak-to-Peak Output Voltage Swing NOTE Outputs terminated with VCCO_PECL "Parameter Measurement Information" section, "3.3V Output Load Test Circuit".
TABLE CRYSTAL CHARACTERISTICS
Symbol CO/C1 Parameter Nominal Frequency Frequency Tolerance Frequency Stability Operating Temperature Range Load Capacitance Shunt Capacitance Pullability Ratio Equivalent Series Resistance Drive Level Mode Operation Fundamental Test Conditions Minimum Typical 19.44 ±TBD ±TBD Maximum Units
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Test Conditions Minimum 4.375 1.1875 Random jitter Deterministic jitter Total jitter Random jitter Deterministic jitter Total jitter Random jitter Deterministic jitter Total jitter Random jitter Deterministic jitter Total jitter CLK0/nCLK0 19.44MHz QA/B 77.76MHz VCLK REF_CLK 19.44MHz; NOTES CLK1/2 8kHz QA/B 77.76MHz VCLK REF_CLK 19.44MHz; NOTES 0.75 0.19 Typical Maximum Units
TABLE CHARACTERISTICS, VCCA VCCA_XO VCCO_CMOS VCCO_PECL 3.3V±5%, 70°C
Symbol Parameter QA/nQA fOUT Output Frequency QB/nQB VCLK REF_CLK OC-48 mask (12kHz 20MHz) 19.44MHz input, into CLK0 622.08MHz output; NOTE OC-12 mask (250kHz 5MHz) 19.44MHz input, into CLK0 155.52MHz output; NOTE
t(J)
Timing Jitter OC-48 mask (12kHz 20MHz) 8kHz input, into CLK2 622.08MHz output; NOTE OC-12 mask (250kHz 5MHz) 8kHz input, into CLK2 155.52MHz output; NOTE CLK0/nCLK0 CLK0/nCLK0 VCLK Input Output Clock Skew (rising clock edge) CLK0/nCLK0 REF_CLK CLK1 CLK2 CLK1 CLK2 VCLK CLK1 CLK2 REF_CLK
t(IO)
Output Rise/Fall Time Output Duty Cycle QA/QB 622.08MHz VCLK, REF_CLK 19.44MHz
Lock Time tLOCK Parameter Measurement Information section. NOTE External crystal 19.44MHz Eliptek ECX-5451. NOTE Loop bandwidth (-3dB) 180Hz; Loop Damping Factor (see Applications Section, Example Loop Filter Component Value, example case #4). NOTE Loop bandwidth (-3dB) 19Hz; Loop Damping Factor (see Applications Section, Example Loop Filter Component Value example case #2). NOTE XOIN XOFB (x32); NOTE XOIN XOFB 2430; (x32);
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PARAMETER MEASUREMENT INFORMATION
1.65V
VCCA, VCCA_XO, VCCO_PECL
SCOPE
VCCA, VCCA_XO, VCCO_CMOS
SCOPE
LVPECL
LVCMOS
-1.3V 0.165V
-1.65V
3.3V LVPECL OUTPUT LOAD TEST CIRCUIT
3.3V LVCMOS OUTPUT LOAD TEST CIRCUIT
VCLK
REF_CLK
tsk(o)
tsk(o)
LVPECL OUTPUT SKEW
LVCMOS OUTPUT SKEW
nQA, VCLK, REF_CLK
PERIOD
CCO_LVCMOS
PERIOD
PERIOD
100%
PERIOD
100%
LVPECL OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
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LVCMOS OUTPUT DUTY CYCLE/PULSE WIDTH/tPERIOD
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700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR
Phase Noise Plot
Noise Power
Phase Noise Mask
Clock Outputs
Offset Frequency
Jitter Area Under Masked Phase Noise Plot
PHASE JITTER
LVPECL OUTPUT RISE/FALL TIME
Clock Outputs
LVCMOS OUTPUT RISE/FALL TIME
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700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR APPLICATION INFORMATION
DESCRIPTION STAGES
ICS843002-31 stage frequency multiplication device, VCXO followed phase noise FemtoClock frequency multiplier. VCXO uses external pullable crystal which pulled ±100ppm VCXO circuitry phase lock input reference frequency. output frequency VCXO equal that external pullable crystal, which range 17.5MHz 25MHz. loop bandwidth VCXO typically range 10-250Hz which provides attenuation input reference clock jitter. Since VCXO high-Q oscillator circuit, intrinsic output jitter phase noise. VCXO output clock available from VCLK pin. FemtoClock frequency multiplier effective control bandwidth about 800kHz which means will track VCXO clock output. above equation calculates "normalized" loop bandwidth (denoted "NBW") which approximately equal bandwidth. does take into account effects damping factor second pole imposed does, however, provide useful approximation filter performance. prevent jitter VCLK modulation VCXO phase detector frequency, following general rule should observed: (VCXO PLL) (Phase Detector)
(Phase Detector) Input Frequency XOIN loop damping factor (DF) determined XOFB Divider
VCXO LOOP RESPONSE CONSIDERATIONS
Loop response characteristics VCXO affected setting VCXO feedback divider value (XOFB) external loop filter components. practical range loop bandwidth many applications 25Hz 1kHz. bandwidth less than 10Hz requires careful component selection possible metal shielding prevent clock output wander. damping factor greater should used ensure loop stability. When passband peaking <0.1dB desired SONET/SDH loop timing application, damping factor should higher. base bandwidth calculator also under development. assistance with loop filter bandwidth component selection suggestions, please contact your sales representative. (VCLK)
WHERE: Value capacitor loop filter farads
optional
optional
ISET
SETTING VCXO LOOP RESPONSE
VCXO loop response determined both fixed device characteristics other characteristics user. This includes values RSET shown External VCXO Components figure this page. VCXO loop bandwidth approximated (VCXO PLL) XOFB Divider
RSET
FIGURE EXTERNAL VCXO COMPONENTS
WHERE: Value resistor loop filter ohms Charge pump current amps (see table page VCXO Gain Hz/V (see table page XOFB Divider 8191
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NOTES EXTERNAL CRYSTAL LOAD CAPACITORS
loop filter schematic diagram, capacitors shown from ground ground. These optional crystal load capacitors which used center tune external pullable crystal (the crystal frequency only lowered adding capacitance, cannot raised). Note that addition external load capacitors will decrease crystal pull range Kvco value.
NOTES SETTING VALUE
another general rule, following relationship should maintained between components loop filter:
establishes second pole VCXO loop filter. higher damping factors calculate value based value that would used damping factor This will minimize baseband peaking loop instability that lead output jitter. also dampens VCXO input voltage modulation charge pump correction pulses. value that will result increased output phase noise phase detector frequency this. extreme cases where input jitter high, charge pump current high, small, VCXO input voltage supply ground rail resulting non-linear loop response. best value filter response software available from (please refer following section). should increased value until just starts affecting passband peak.
LOOP FILTER RESPONSE SOFTWARE
Online tools calculate loop filter response found www.icst.com.
NOTES SETTING CHARGE PUMP CURRENT
recommended range charge pump current 500A. Below 50A, loop filter charge leakage, capacitor leakage, become problem. This loop filter leakage cause locking problems, output clock cycle slips, frequency phase noise. seen loop bandwidth damping factor equations using filter response software available from ICS, increasing charge pump current (ICP) increases both bandwidth damping factor.
1E-3
CHARGE PUMP CURRENT, EXAMPLE SETTINGS
RSET 17.6K 8.8K 4.4K 2.2K Charge Pump Current (ICP) 62.5µA 125µA 250µA 500µA
ICP, Amps
100E-6
10E-6 RSET, 100k
FIGURE CHARGE PUMP CURRENT VALUE (EXTERNAL RESISTOR) GRAPH
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VCXO GAIN (KO) XTAL FREQUENCY
9000
8000
(Hz/V)
7000
6000
5000
4000
XTAL Frequency (MHz)
EXAMPLE LOOP FILTER COMPONENT VALUE
Example Case Number Input Reference Clock 8kHz 8kHz 19.44kHz 19.44MHz Device Configuration XTAL XOIN XOFB Frequency Divider Divider (MHz) 19.44 2430 19.44 19.44 19.44 2430 Divider Loop Filter Component Selection RSET Resistor Resistor (µF) (µF) 0.01 9.09 9.09 0.01 0.01 0.01 VCXO Performance Loop Loop Passband (-3dB) Damping Peaking (MHz) Factor (dB)
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3.3V .01F .01F
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS843002-31 provides separate power supplies isolate high switching noise from outputs internal PLL. VCC, VCCA, VCCA_XO, VCCO_X should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with .01F bypass capacitor should connected each VCCA pin.
FIGURE POWER SUPPLY FILTERING
DIFFERENTIAL CLOCK INPUT INTERFACE
CLK0 /nCLK0 accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL other differential signals. Both VSWING must meet VCMR input requirements. Figures show interface examples HiPerClockS CLK0/nCLK0 input driven most common driver types. input interfaces suggested here examples only. Please consult with vendor driver component confirm driver termination requirements. example Figure input termination applies HiPerClockS LVHSTL drivers. using LVHSTL driver from another vendor, their termination recommendation.
3.3V 3.3V
3.3V 1.8V
nCLK LVHSTL HiPerClockS LVHSTL Driver
LVPECL
nCLK
HiPerClockS Input
HiPerClockS Input
FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN HIPERCLOCKS LVHSTL DRIVER
FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V
3.3V 3.3V 3.3V nCLK LVPECL HiPerClockS Input
3.3V LVDS_Driv
nCLK
Receiv
FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVPECL DRIVER
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FIGURE HIPERCLOCKS CLK/nCLK INPUT DRIVEN 3.3V LVDS DRIVER
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DIFFERENTIAL CLOCK INPUT CIRCUIT USING DIFFERENTIAL INTERFACE SINGLE-ENDED CLOCKS
differential interface (CLK0/nCLK0) used third single-ended input support LVCMOS LVTTL clock driver. clock input connected CLK0 input pin, nCLK0 left unconnected. help reduce interference with internal circuits, external resistor placed series with clock signal near CLK0 input pint. Combined with input capacitance, this resistor acts pass signal filter. typical value this optional series filter resistor 100. This will lower both amplitude edge rate clock input signal. case very short clock trace series termination register needed.
Series Termination LVTTL LVCMOS Logic Output
Optional Series Filter Resistor
3.3V CLK0
3.3V
nCLK0
connection)
nCLK Differential Input Stage
External Circuitry
Internal Device Circuitry
FIGURE SINGLE-ENDED CLOCK INPUT INTERFACE
RECOMMENDATIONS UNUSED INPUT OUTPUT PINS INPUTS: OUTPUTS:
CRYSTAL INPUT: applications requiring crystal oscillator input, both XTAL_IN XTAL_OUT left floating. Though required, additional protection, resistor tied from XTAL_IN ground. INPUT: applications requiring clock input, left floating. Though required, additional protection, resistor tied from input ground. CLK/nCLK INPUT: applications requiring differential input, both nCLK left floating. Though required, additional protection, resistor tied from ground. LVCMOS CONTROL PINS: control pins have internal pull-ups pull-downs; additional resistance required added additional protection. resistor used.
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LVCMOS OUTPUT: unused LVCMOS output left floating. recommend that there trace attached. LVPECL OUTPUT unused LVPECL outputs left floating. recommend that there trace attached. Both sides differential output pair should either left floating terminated.
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700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR
contacted through solder shown Figure further information, please refer Application Note Surface Mount Assembly Amkor's Thermally /Electrically Enhance Leadframe Base Package, Amkor Technology.
EXPOSED SOLDER
THERMAL RELEASE PATH
exposed metal provides heat transfer from device P.C. board. exposed metal ground connected ground plane through thermal via. exposed device exposed metal
SOLDER SIGNAL TRACE
SIGNAL TRACE
GROUND PLANE THERM
Expose Metal (GROUND PAD)
FIGURE P.C. BOARD EXPOSED THERMAL RELEASE PATH EXAMPLE
TERMINATION
LVPECL OUTPUTS
designed drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs
3.3V
FOUT
((VOH VOL) (VCC
FOUT
FIGURE LVPECL OUTPUT TERMINATION
FIGURE LVPECL OUTPUT TERMINATION
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This section provides information power dissipation junction temperature ICS843002-31. Equations example calculations also provided. Power Dissipation. total power dissipation ICS843002-31 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.465V 395mA 1368.67mW Power (outputs)MAX 30mW/Loaded Output pair outputs loaded, total power 30mW 60mW
Total Power_MAX (3.465V, with outputs switching) 1368.67mW 60mW 1428.67mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C. equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow linear feet minute multi-layer board, appropriate value 17.2°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 1.429W 17.2°C/W 94.6°C. This well below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE 64-PIN TQFP, FORCED CONVECTION
Velocity (Linear Feet Minute)
Multi-Layer PCB, JEDEC Standard Test Boards 22.3°C/W
17.2°C/W
15.1°C/W
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Calculations Equations. purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
ICS843002-31
700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR
VCCO
VOUT VCCO
FIGURE LVPECL DRIVER CIRCUIT TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
CCO_MAX
OH_MAX
CCO_MAX
0.9V
OH_MAX
0.9V 1.7V
logic low, VOUT
CCO_MAX
OL_MAX
CCO_MAX
OL_MAX
1.7V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H 2V))/R
OH_MAX
CCO_MAX
CCO_MAX
OH_MAX
[(2V
CCO_MAX
OH_MAX
))/R
CCO_MAX
OH_MAX
[(2V 0.9V)/50) 0.9V 19.8mW
Pd_L
OL_MAX
CCO_MAX
2V))/R
CCO_MAX
OL_MAX
[(2V
CCO_MAX
OL_MAX
))/R
CCO_MAX
OL_MAX
[(2V 1.7V)/50) 1.7V 10.2mW Total Power Dissipation output pair Pd_H Pd_L 30mW
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700MHZ FEMTOCLOCKSVCXO BASED FREQUENCY TRANSLATOR JITTER ATTENUATOR RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE LEAD TQFP, EPAD
Velocity (Linear Feet Minute)
Multi-Layer PCB, JEDEC Standard Test Boards 22.3°C/W
17.2°C/W
15.1°C/W
TRANSISTOR COUNT
transistor count ICS843002-31 10,095
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PACKAGE OUTLINE SUFFIX LEAD TQFP, EPAD package depicted define Table dimension symbols)
TABLE PACKAGE DIMENSIONS LEAD TQFP, EPAD
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 0.17 0.09 MINIMUM NOMINAL -1.0 0.22 -12.00 BASIC 10.00 BASIC 5.00 Ref. 12.00 BASIC 10.00 BASIC 5.00 Ref. 0.50 BASIC 0.60 -0.75 0.08 1.20 0.15 1.05 0.27 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
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Marking Package Lead TQFP, EPAD Lead TQFP, EPAD Lead "Lead-Free" TQFP, EPAD Lead "Lead-Free" TQFP, EPAD Shipping Packaging tray tape reel tray tape reel Temperature 70°C 70°C 70°C 70°C
TABLE ORDERING INFORMATION
Part/Order Number ICS843002CY-31 ICS843002CY-31T ICS843002CY-31LF ICS843002CY-31LFT ICS843002CY31 ICS843002CY31
NOTE: that ordered with "LF" suffix number Pb-Free configuration RoHS compliant.
aforementioned trademarks, HiPerClockS FEMTOCLOCKS trademarks Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial applications. other applications such those requiring extended temperature range, high reliability, other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 843002CY-31
REV. NOVEMBER 2005

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