PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN PM5357

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PRELIMINARY REFERENCE DESIGN PMC-981070 ISSUE
PM5357 S/UNI-622-POS
S/UNI-622-POS REFERENCE DESIGN
PM5357
S/UNI-622-POS
SATURN USER NETWORK INTERFACE (622-POS)
REFERENCE DESIGN
PROPRIETARY CONFIDENTIAL PRELIMINARY ISSUE 1998
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PRELIMINARY REFERENCE DESIGN PMC-981070 ISSUE
PM5357 S/UNI-622-POS
S/UNI-622-POS REFERENCE DESIGN
PUBLIC REVISION HISTORY Issue Issue Date Details Change
1998 Document created.
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CONTENTS INTRODUCTION FEATURES APPLICATIONS REFERENCES BLOCK DIAGRAM. FUNCTIONAL DESCRIPTION S/UNI-622-POS MICROCONTROLLER BLOCK CIRCUITRY MBIT/S OPTICAL INTERFACE. EXTERNAL CONNECTOR POWER UP/DOWN CONSIDERATIONS. ANALOG POWER FILTERING. SYSTEM SIDE LINE TERMINATIONS
IMPLEMENTATION DESCRIPTION ROOT DRAWING, SHEET POS_BLOCK, SHEET SYS_INTERFACE, SHEET MICRO_BLOCK, SHEET WAN_CLOCKING, SHEET OPTICS_BLOCK, SHEET
SCHEMATICS.
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BILL MATERIALS.
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LIST FIGURES FIGURE S/UNI-622-POS WITH PMC-SIERRA ACHIPSETS. FIGURE S/UNI-622-POS DESIGN WITH LINK LAYER DEVICE FIGURE DIGITAL BLOCK DIAGRAM. FIGURE LINE INTERFACE TERMINATIONS FIGURE SYSTEM INTERFACE TERMINATIONS
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LIST TABLES TABLE INTERFACE CONNECTOR TABLE INTERFACE CONNECTOR TABLE MAJOR COMPONENTS LIST
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INTRODUCTION PM5357 S/UNI-622-POS standard product SATURN User Network Interface with SONET/SDH processing, Aand Packet mapping functions STS-12c (STM-4-4c) 622.08 Mbit/s rate. S/UNI-622-POS intended equipment implementing Asynchronous Transfer Mode (ATM) UserNetwork Interface (UNI), ANetwork-Network Interfaces (NNI), Packet Over SONET/SDH (POS) interfaces. interface used support several packet based protocols, including Point-to-Point Protocol (PPP). S/UNI-622-POS find application either switch-to-switch links switch-to-terminal links, both public network (WAN) private network (LAN) situations. S/UNI-622-POS reference design provides physical interface implementation SONET/SDH line card both Aand applications. provides single mode multimode optical interface OC-12c rate system side interface 50MHz 16-bit wide 100MHz 8-bit wide bus. applications, this reference design provides implementation Digital satisfying Bellcore Stratum Clock synchronization requirements.
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FEATURES Provides single mode multimode OC-12c rate 622.08 Mbit/s SONET/SDH Physical Layer Port Provides Utopia Level MHz, 16-bit ASingle-PHY System Interface Provides POS-PHY Level MHz, 16-bit Packet Over SONET/SDH Single-PHY System Interface Provides Utopia Level compatible, MHz, 8-bit ASingle-PHY System Interface Provides SATURN POS-PHY Level MHz, 8-bit Packet Over SONET/SDH Single-PHY System Interface Contains on-board microcontroller provide clocking requirements related wander transfer, holdover long time stability when using external VCXO
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APPLICATIONS S/UNI-622-POS reference design demonstrates physical interface implementation both Aand applications. list below shows networking equipment that incorporate S/UNI-622-POS device: Edge Aswitches physical interfaces switches hubs physical interfaces Packet switches hubs physical interfaces
Aapplication, S/UNI-622-POS reference design interfaces OC-12c rate SONET/SDH signal line side. drop side, S/UNI622-POS interfaces directly with Alayer processors switching adaptation functions using Utopia Level compliant synchronous FIFO style interface. Figure shows S/UNI-622-POS reference design complete Aswitching design. Utopia Level compliant interface also available drop side interface.
Figure
S/UNI-622-POS with PMC-Sierra AChipsets
Utopia Level
Utopia Level
Optics OC-12
PM73487 PM73488 PM73488
PM7322
PM5357
Traffic Manager
RCMP-800
ALayer
622-POS
Design
OC-12
ASwitch Fabric
PM73487
PM7322
Optics
PM5357
Traffic Manager
RCMP-800
ALayer
622-POS
Design
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Packet Over SONET/SDH application using protocol, S/UNI622-POS reference design interfaces OC-12c rate SONET/SDH signal line side. drop side, S/UNI-622-POS reference design interfaces directly with link layer processor using byte synchronous FIFO SATURN POS-PHY Level interface over which packets transferred. Figure shows S/UNI-622-POS reference design application.
Figure
S/UNI-622-POS Design with Link Layer Device
POS-PHY Level2/3
Optics OC-12
PM5357 Packet/IP Switch
Packet Port Interface Processor
622-POS
Design
OC-12 Optics
PM5357
Packet Port Interface Processor
622-POS
Design
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REFERENCES PMC-Sierra, Inc., PMC-980911 "PM5357 S/UNI-622-POS Data Sheet", Issue August 1998 Bell Communication Research SONET Transport Systems: Common Generic Criteria, GR-253-CORE, Issue December 1995
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BLOCK DIAGRAM
RS-232
Block
Flash
+/-, +/-,
Tx/Rx System
PM5357 S/UNI-622-POS
Signals
REFCLK
VCXO
Temperture Sensor
FPGA
Circuitry (Optional)
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UTOPIA POS-PHY INTERFACE
Micro Interface
Serial Signals
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FUNCTIONAL DESCRIPTION S/UNI-622-POS PM5357 S/UNI-622-POS SATURN User Network Interface monolithic integrated circuit that implements SONET/SDH processing, Amapping Packet Over SONET/SDH mapping functions STS-12c/STM-4-4c 622.08 Mbit/s rate. S/UNI-622-POS receives SONET/SDH streams using serial interface, recovers clock data processes section, line, path overhead. S/UNI-622-POS also configured clock data recovery clock synthesis by-pass where receives SONET/SDH frames byte-serial interface. S/UNI-622-POS performs framing (A1, A2), de-scrambling, detects alarm conditions, monitors section, line, path interleaved parity (B1, B3), accumulating error counts each level performance monitoring purposes. Line path remote error indications (M1, also accumulated. S/UNI-622-POS interprets received payload pointers (H1, extracts synchronous payload envelope which carries received Acell packet payload. When used implement AUNI NNI, S/UNI-622-POS frames Apayload using cell delineation. error correction provided. Idle/unassigned cells optionally dropped. Cells also dropped upon detection uncorrectable header check sequence error. Acell payloads descrambled written four cell FIFO buffer. received cells read from FIFO using 16-bit wide Utopia level (clocked MHz) 8-bit wide SATURN POS-PHY Level (clocked MHz) datapath interface. Counts received Acell headers that errored uncorrectable those that errored correctable accumulated independently performance monitoring purposes. When used implement packet transmission over SONET/SDH link, S/UNI-622-POS extracts Packet Over SONET/SDH (POS) frames from SONET/SDH synchronous payload envelope. Frames verified correct construction size. control escape characters removed. frame check sequence optionally verified correctness extracted packets placed receive FIFO. received packets read from FIFO through 16-bit POS-PHY Level (clocked MHz) 8-bit POS-PHY Level (clocked MHz) system side interface. Valid errored packet counts provided performance monitoring. S/UNI-622-POS
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Packet Over SONET/SDH implementation flexible enough support several link layer protocols, including HDLC, Frame Relay. S/UNI-622-POS transmits SONET/SDH streams using serial interface. S/UNI-622-POS also configured clock data recovery clock synthesis by-pass where transmits SONET/SDH frames byteserial interface. S/UNI-622-POS synthesizes transmit clock from 77.76MHz frequency reference performs framing pattern insertion (A1, A2), scrambling, alarm signal insertion, creates section, line, path interleaved parity codes (B1, required allow performance monitoring end. Line path remote error indications (M1, also inserted. S/UNI-622-POS generates payload pointer (H1, inserts synchronous payload envelope which carries Acell frame payload. S/UNI-622-POS also supports insertion large variety errors into transmit stream, such framing pattern errors, interleaved parity errors, illegal pointers, which useful system diagnostics tester applications. When used implement AUNI NNI, Acells written internal four cell FIFO using 16-bit wide UTOPIA Level (clocked MHz) 8-bit wide Utopia Level compatible (clocked MHz) datapath interface. Idle/unassigned cells automatically inserted when internal FIFO contains fewer than complete cell. S/UNI-622-POS provides generation header check sequence scrambles payload Acells. Each these transmit Acell processing functions enabled bypassed. When used implement Packet over SONET/SDH link, S/UNI-622-POS inserts frames into SONET/SDH synchronous payload envelope. Packets transmitted written into 256-byte FIFO through 16-bit SATURN POS-PHY Level (clocked MHz) 8-bit SATURN POSPHY Level (clocked MHz) system side interface. Frames built inserting flags, control escape characters fields. Either CRC-CCITT CRC-32 computed added frame. Several counters provided performance monitoring. line rate clocks required directly S/UNI-622-POS synthesizes transmit clock recovers receive clock using 77.76 reference clock. S/UNI-622-POS outputs differential PECL line data (TXD+/-). Optionally, S/UNI-622-POS also provides Synchronization controller that used control external VCXO reference order fully meet Bellcore GR-253-CORE jitter, wander, holdover stability requirements.
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S/UNI-622-POS configured, controlled monitored generic 8-bit microprocessor interface. S/UNI-622-POS also provides standard signal IEEE 1149.1 JTAG test port boundary scan board test purposes. S/UNI-622-POS implemented power, +3.3 Volt, CMOS technology. compatible digital inputs TTL/CMOS compatible digital outputs. High speed inputs outputs support 3.3V 5.0V compatible pseudo-ECL (PECL). S/UNI-622-POS packaged SBGA package. Detailed information about PM5357 S/UNI-622-POS available S/UNI-622POS data sheet PMC-980911. Microcontroller Block S/UNI-622-POS reference design uses 32-bit Motorola 68332 microcontroller running 16.337MHz on-board processor. microcontroller block contains separate flash program data storage run-time program execution. S/UNI-622-POS registers accessed through 9-bit address 8-bit data microprocessor interface 68332. microcontroller accessed through either RS-232 port Background Debugging Mode (BDM) connector reference board. RS232 port allows access serial port 68332. RS-232 port connected serial port using cable. firmware reference design resides FLASH ROM. user VT100 terminal emulation program interface firmware access hardware reference board. microcontroller also provides additional control external adapter cards through Utopia/POS-PHY interface connector. This allows microcontroller access external devices. Circuitry Circuitry Block consists VCXO, DAC, temperature sensor. circuitry utilizes S/UNI-622-POS's WANS block phase detector function complete digital PLL. Together with WANS block, S/UNI-622-POS reference design provides complete digital design generating stratum level clock that satisfies wander transfer, long term holdover stability. general block structure digital block diagram implementation S/UNI-622-POS seen Figure below.
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Figure
Digital Block Diagram
DPLL Structure
Reference Clock
Phase Detector
Loop Filter
Temperture Compensation
Output Clock
VCXO
S/UNI-622-POS Reference Design
Phase Detector
Loop Filter Temperture Compensation
Temp Sensor
Recovered Clock divided
WANS
S/UNI-622-POS
REFCLK+/D/A
VCXO
FPGA REFCLK+/-
digital implemented S/UNI-622-POS reference design based circuitry presented S/UNI-622-POS data sheet. Please refer PMC980911 detailed description functionality implemented WANS block. WANS block derives phase value based phase relationship between recovered clock VCXO clock, REFCLK+/-. digital filtering performed external 68332 microcontroller. Together with temperature sensor, circuitry block provides temperature VCXO linearity compensation. Mbit/s Optical Interface S/UNI-622-POS reference design provides single optical interface running Mbit/s OC-12c rate. line interface consists single mode multimode optical data link (ODL) termination scheme PECL signal into from S/UNI-622-POS transmit, TXD+/- receive, RXD+/signal pairs. suggested termination scheme PECL transmit receive signals shown Figure 3.3V ODL's.
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Figure
Optics
Line Interface Terminations
S/UNI-622-POS RxD+
RDGnd
RxD-
63.4
0.1uF
TxD+
49.9
49.9
TxDSD
Notes: (ODL power) 3.3V (trace impedance) typically
normal operation, S/UNI-622-POS performs clock data recovery incoming serial stream. option, internal clock data recovery bypassed setting RBYP high providing externally recovered receive clock RRCLK+/- pins. this mode RXD+/- sampled rising edge RRCLK+/-. Hewlett Packard provides HFCT/HFBR-5207 optical transceivers with clock data recovery HFCT/HFBR-5208 transceivers without clock data recovery. HFCT-5207 having matching HFCT-5208 another which provides extra signals recovered clock. using footprint that will both devices, either device used. This reference design intended internal clock data recovery only provides footprint fitting HFCT-5208 only. loss signal condition, indicated (signal degrade) lack data transitions consecutive periods, S/UNI-622-POS will squelch receive data clock recovery unit will switch reference clock (77.76MHz) keep recovered clock range. This technique guarantees
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that S/UNI-622-POS will generate indication when loses incoming light. HFCT-5208 single mode transceiver with 9-pin duplex receptacle used this reference design with clock data recovery performed within S/UNI-622-POS. External Connector S/UNI-622-POS reference design contains Molex connectors interfacing link layer board. first connector used microcontroller communication between microcontrollers S/UNI-622-POS reference design link layer board. supplies both 3.3V power supply S/UNI-622-POS board. also carries FIFO clock signals both Utopia POS-PHY interface. second connector used interfacing Utopia POS-PHY data control signals. Table Interface Connector Name MISO MOSI CS_MICRO Type Input Output Input Output Input Output Input Output Input Function Serial Clock. Clock microcontroller's QSPI module Master Slave Out. Serial Data microcontroller's QSPI module. Master Slave Serial Data microcontroller's QSPI module. Chip select communication between microcontrollers S/UNI-622-POS link layer boards. Signal indicate link layer micro master slave bus. M_MICRO micro 622-POS board master. M_MICRO link layer micro acts master. Interrupt signal from S/UNI-622-POS device
M/S_MICRO
INTB_622POS
Output
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Name RFCLK-
Type Output
Function Negative differential receive clock signal. This signal, along with RFCLK+ comprise differential RFCLK clock signal sent across connector. RFCLK used clock RDAT, RVAL, RSOC/RSOP RMOD, RPRTY, RERR, RENB, RCA/RPA, REOP Positive differential receive clock signal. This signal, along with RFCLK- comprise differential RFCLK clock signal sent across connector. RFCLK used clock RDAT, RVAL, RSOC/RSOP RMOD, RPRTY, RERR, RENB, RCA/RPA, REOP Positive differential receive clock signal. This signal, along with TFCLK- comprise differential TFCLK clock signal sent across connector. TFCLK used clock TDAT, TVAL, TSOC/TSOP TMOD, TPRTY, TERR, TENB, TCA/TPA, TEOP Negative differential receive clock signal. This signal, along with TFCLK+ comprise differential TFCLK clock signal sent across connector. TFCLK used clock TDAT, TVAL, TSOC/TSOP TMOD, TPRTY, TERR, TENB, TCA/TPA, TEOP POS-PHY: Receive Modulo POS-PHY Level this signal indicates number bytes carried RDAT bus. POS-PHY Level this signal ignored. This signal ignored Utopia Amode.
RFCLK+
Output
TFCLK+
Input
TFCLK-
Input
RMOD
Output
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Name RVAL
Type Output
Function Utopia level Receive Data Valid When high this signal indicates that RDAT, RSOC, RPRTY, RENB, valid. POS-PHY: Receive Data Valid When high this signal indicates that RDAT, RSOC/RSOP RMOD, RPRTY, RERR, RENB, RCA/RPA, REOP valid. This signal ignored Utopia level Amode.
A38, B30, C30, D16, D22, D34, D37, A3-A9, B3-B9, A19, B16, B40,
Connected.
Input
Volt supply
3.3V
Input Input
Volt supply Ground
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Table Interface Connector Name RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RDAT[8] RDAT[9] RDAT[10] RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15] RPRTY RENB Type Output Function UTOPIA: Receive Cell Data Utopia Level this carries Acell octets that read from receive FIFO. Utopia Level only RDAT[7:0] valid.
POS-PHY: Receive Packet Data POS-PHY Level this carries Packets that read from selected receive FIFO. POS-PHY Level only RDAT[7:0] valid.
Output Input
Output
Receive parity. receive parity signal indicates parity RDAT bus. Receive Write Enable. RENB signal active input which used initiate reads from receive FIFO. UTOPIA: Receive Direct Cell Available This signal indicates available cell. POS-PHY: Direct Receive Packet Available. POS-PHY Level this signal indicates when data available receive FIFO. POS-PHY Level this signal used RVAL signals valid data bus. UTOPIA: Receive Start Cell This signal marks start cell RDAT bus. POS-PHY: Receive Start Packet This signal marks start packet RDAT bus.
RSOC
Output
RSOP
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Name RERR
Type Output
Function POS-PHY: Receive Error This signal indicates that current packet been aborted. This signal ignored Utopia Amodes. POS-PHY: Receive Packet This signal marks packet RDAT bus. This signal ignored Utopia Amodes. Utopia POS-PHY: Transmit Write Enable. TENB signal active input which used initiate writes transmit FIFO Utopia: Transmit cell available signal This signal used indicate available cell FIFO space port. POS-PHY: Direct Transmit Packet Available. This signal transitions high when programmable minimum number free space available transmit FIFO. Utopia: Transmit Start Cell transmit start cell signal marks start cell TDAT bus. POS-PHY: Transmit Start Packet POS-PHY Level this signal indicates first word packet. POS-PHY Level this signal indicates first byte packet. POS-PHY: Transmit Error This signal indicates current packet must aborted. This signal ignored Utopia Amode POS-PHY: Transmit Packet This signal marks packet TDAT bus. This signal ignored Utopia Amodes.
REOP
Output
TENB
Input
Output
TSOC
Input
TSOP
TERR
Input
TEOP
Input
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Name TMOD
Type Input
Function POS-PHY: Transmit Word Modulo POS-PHY Level this signal indicates size current word. POS-PHY Level this signal ignored. This signal ignored Utopia Amodes. Transmit parity. transmit parity signal indicates parity TDAT bus. Utopia: Transmit Cell Data This carries Acell octets that written selected transmit FIFO.
TPRTY TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15]
INPUT INPUT
POS-PHY: Transmit Packet Data This data carries packet octets that written selected transmit FIFO. POS-PHY Level only TDAT[0:7] valid.
Power Up/Down Considerations protection structures pads necessary exercise caution when powering device down. protection devices behave diodes between power supply pins from pins power supply pins. Under extreme conditions possible blow these protection devices trigger latch more information required power sequence, refer S/UNI-622-POS data sheet. following features S/UNI-622-POS reference design ensure power power down occur properly.
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1.0K resistor placed series between supply VBIAS PBIAS pins. This resistor prevents excessive current from flowing from through VBIAS PBIAS supply case supply applied before supply applied bias pins. VDD, QAVD, regular pins supplied from same 3.3V power plane. This keeps voltage difference pins QAVD pins small, preventing current flow from pins VDD, QAVD pins. Sensitive pins filtered using 3.3V voltage regulator powered from power plane. These sensitive pins current limited voltage regulator that each cannot draw current higher than maximum latch current.
Analog Power Filtering S/UNI-622-POS performs clock data recovery very high speed. Analog circuitry responsible clock data recovery must free noise ensure reliable operation. Less sensitive analog power pins grouped together decoupled with single capacitor. more sensitive analog power pins S/UNI-622-POS decoupled using pass filter. most sensitive analog pins regulated using drop 3.3V voltage regulator supplied power rail.
System Side Line Terminations S/UNI-622-POS Reference Design capable system side interface speeds MHz. Because high frequency content system side signals, trace termination required insure reliable data transmission across interface. signals system side interface S/UNI-622POS Reference Design point point therefore series source resistor terminations. Figure illustrates relative positioning values these termination resistors. Resistor values different different link layer devices.
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Figure
Link Layer Device
System Interface Terminations
S/UNI-622-POS
Input
Output
Output
Notes:
Input
Terminations shown 3.3V Link Layer Device (trace impedance)
This termination scheme assumes that link layer device drives signals 3.3V levels.
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IMPLEMENTATION DESCRIPTION this document, S/UNI-622-POS schematics refer schematics titled "S/UNI-622-POS reference design". S/UNI-622-POS reference design schematics were captured using Cadence software, Concept Schematics Capture Tool.
ROOT DRAWING, Sheet This sheet provides overview major functional blocks S/UNI-622POS reference design. shows interconnections between POS_BLOCK, SYS_INTERFACE, MICRO_BLOCK, WAN_CLOCKING, OPTICS_BLOCK.
POS_BLOCK, Sheet POS_BLOCK shows S/UNI-622-POS' signals power circuitry. Series resistors used source terminate Utopia/POS-PHY lines. termination resistors combined with output impedance Utopia/POS-PHY pads matches impedance trace Ohms. capacitor placed across loop filter pins, resistor placed across TDREF0 TDREF1 pins. displays alarm status S/UNI-622-POS. resistor also placed series limit Vbias current prevent Vbias latchup. APS[4:0] pins tied through 4.7K resistors. pins provide control between S/UNI-622-POS devices implement function. When using mode, line data passed from S/UNI-622-POS device another using FPIN, PIN[7:0] FPOUT, POUT[7:0] pins. function implemented this reference design. Each pair power digital pins decoupled using capacitor. linear regulator additional filtering capacitors resistors provided provide clean 3.3V power source sensitive analog power pins. linear regulator circuitry also ensures that analog power pins draw current above maximum latch current 100mA during power
SYS_INTERFACE, Sheet SYS_INTERFACE block contains board connectors power supply circuitry. Sheet MOLEX pins connectors shown. Balun
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transformers used transform differential transmit receive clock signals single-ended signal S/UNI-622-MAX. crystal oscillator provides receive FIFO clocking POS-PHY Level Utopia Level compatible modes operation. oscillator substituted case POS-PHY Level Utopia Level compatible modes used. RFCLK+/- pins connector input (receive clock sourced from board), jumpers should each have pins connected together. onboard oscillator generate RFCLK, should each have pins connected. Sheet shows power reference board supplied either from external power supply through board connectors. Solder bridges used select desired power source. Fuses transils provided protect board from over-voltage over-current. MICRO_BLOCK, Sheet MICRO_BLOCK sheet shows 68332 microcontroller external circuitry. 68332 operates 16.337 using 37.7KHz crystal. (128K Flash SRAM provided program storage run-time execution. header allows microcontroller background debug mode downloading program FLASH debugging purposes. MC33064 voltage sensing circuit 68332 reset mode when voltage supply drops below 4.5V. WAN_CLOCKING, Sheet This sheet shows clocking circuitry used implement local clock reference compliant SONET Stratum clock specifications. precise power supply regulation circuitry used supplying power temperature sensor, ADC, DAC, Op-Amp, VCXO. power supply regulation circuitry consists LMC7660 voltage doubler, LT1129-5 dropout voltage regulator. This ensures power clocking circuitry component will have clean supply. temperature sensor connected 10-bit that outputs digitized data microcontroller through port. used supply control voltage VCXO. VCXO operates nominally 77.76 MHz. PECL buffer translates output VCXO into PECL signals REFCLK+/- pins S/UNI-622-POS. Op-Amp used 2.04V output voltage range VCXO. inputs come from FPGA.
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PM5357 S/UNI-622-POS
S/UNI-622-POS REFERENCE DESIGN
FPGA implements digital filtering algorithm providing clocking board. controlled microcontroller through data address bus. OPTICS_BLOCK, Sheet This sheet shows Optical Data Link (ODL) that provides optical electrical (O/E) function S/UNI-622-POS device. PECL signal runs controlled impedance signal lines properly terminated S/UNI-622-POS device. S/UNI-622-POS device interfaces HFCT-5208 Single mode Fiber Transceivers. HFCT-5208 transceivers 9-pin package with duplex receptacle.
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY REFERENCE DESIGN PMC-981070 ISSUE
PM5357 S/UNI-622-POS
S/UNI-622-POS REFERENCE DESIGN
SCHEMATICS
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY REFERENCE DESIGN PMC-981070 ISSUE
PM5357 S/UNI-622-POS
S/UNI-622-POS REFERENCE DESIGN
Bill Materials Table Major Components List Ref. Component Description PMC-Sierra, Inc. PM5357 S/UNI-622-POS Hewlett Packard HFCT-5208 Linear Technology LT1129-3.3 Linear Technology LTC1197 National Semiconductor LM50 Linear Technology LTC1257 National Semiconductor LMC6482 Linear Technology LT1129-5 National Semiconductor LMC7660 Switched Capacitor Voltage Converter Motorola MC33064 Pericom 74FCT3807 Motorola MC68332 PQFP SOIC20 SOIC8 SOIC8 SOIC8 SOIC8 SOIC8 SOT23 SOIC8 SOT-223 Package Type SBGA304 Quantity
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY REFERENCE DESIGN PMC-981070 ISSUE
PM5357 S/UNI-622-POS
S/UNI-622-POS REFERENCE DESIGN
Ref.
Component Description Actel 42MX-24-PL84 Atmel AT29C010A Cypress CY62128 Linear Technology LT1181A 100.00 VXCO Raltron VC7220A-LZ-30-77.760-PMC Crystal Oscillator 77.76 Crystal Oscillator
Package Type PLCC84 TSOP TSOP SOIC16
Quantity
SGS-Thomson SMLVT3V3
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY REFERENCE DESIGN PMC-981070 ISSUE
PM5357 S/UNI-622-POS
S/UNI-622-POS REFERENCE DESIGN
NOTES
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL
PRELIMINARY REFERENCE DESIGN PMC-981070 ISSUE
PM5357 S/UNI-622-POS
S/UNI-622-POS REFERENCE DESIGN
CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, Canada Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Site:
None information contained this document constitutes express implied warranty PMC-Sierra, Inc. sufficiency, fitness suitability particular purpose such information fitness, suitability particular purpose, merchantability, performance, compatibility with other parts systems, products PMC-Sierra, Inc., portion thereof, referred this document. PMC-Sierra, Inc. expressly disclaims representations warranties kind regarding contents information, including, limited express implied warranties accuracy, completeness, merchantability, fitness particular use, non-infringement. event will PMC-Sierra, Inc. liable direct, indirect, special, incidental consequential damages, including, limited lost profits, lost business lost data resulting from reliance upon information, whether PMC-Sierra, Inc. been advised possibility such damage. 1998 PMC-Sierra, Inc. PMC-981070 (P1) Issue date: 1998
PROPRIETARY CONFIDENTIAL PMC-SIERRA, INC., CUSTOMERS' INTERNAL

PM5357 S/UNI-622-POS S/UNI-622-POS REFERENCE DESIGN PM5357

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