PM5351 S/UNI-TETRA S/UNI-TETRA REFERENCE DESIGN PM5351 S/UNI

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PM5351 S/UNI-TETRA S/UNI-TETRA REFERENCE DESIGN PM5351 S/UNI

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PRELIMINARY REFERENCE DESIGN PMC-980322 ISSUE
PM5351 S/UNI-TETRA
S/UNI-TETRA REFERENCE DESIGN
PM5351 S/UNI
155-TETRA
S/UNI-TETRA
S/UNI-TETRA REFERENCE DESIGN WITH CLOCKING
REFERENCE DESIGN
ISSUE NOVEMBER 1998
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S/UNI-TETRA REFERENCE DESIGN
PUBLIC REVISION HISTORY Issue Issue Date Details Change
1998 Revised power filtering recommendation 1996 Document created.
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CONTENTS INTRODUCTION FEATURES APPLICATIONS INTERFACING REFERENCE DESIGN FAMILY.
REFERENCES DESIGN OVERVIEW BLOCK DIAGRAM. FUNCTIONAL DESCRIPTION S/UNI-TETRA OPTICAL LINE INTERFACE. MICROCONTROLLER BLOCK CIRCUITRY BLOCK SYSTEM SIDE LOOPBACK EXTERNAL CONNECTOR
IMPLEMENTATION DESCRIPTION ROOT DRAWING, SHEET TETRA_BLOCK, SHEET LOOPBACK_BLOCK, SHEET SYS_INTERFACE, SHEET MICRO_BLOCK, SHEET WAN_CLOCKING, SHEET OPTICS_BLOCK, SHEET
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SCHEMATICS. BILL MATERIALS.
LAYOUT
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LIST FIGURES FIGURE S/UNI-TETRA WITH PMC-SIERRA ACHIPSETS FIGURE S/UNI-TETRA DESIGN WITH LINK LAYER DEVICE. FIGURE STS-3C FRAME. FIGURE LINE INTERFACE TERMINATIONS FIGURE DIGITAL BLOCK DIAGRAM FIGURE LOOPBACK DIAGRAM. FIGURE ANALOG POWER FILTERING RECOMMANDATION
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LIST TABLES TABLE INTERFACE CONNECTOR TABLE INTERFACE CONNECTOR TABLE MAJOR COMPONENTS LIST
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INTRODUCTION PM5351 S/UNI-TETRA standard product Quad SATURN User Network Interface with SONET/SDH processing, Aand Packet mapping functions STS-3c (STM-1) 155.52 Mbit/s rate. S/UNI-TETRA intended equipment implementing Asynchronous Transfer Mode (ATM) User-Network Interface (UNI), ANetwork-Network Interfaces (NNI), Packet over Sonet (POS) interfaces. interface used support several packet based protocols, including Point-to-Point Protocol (PPP). S/UNI-TETRA find application either switch-to-switch links switch-to-terminal links, both public network (WAN) private network (LAN) situations. S/UNI-TETRA reference design provides physical interface implementation SONET/SDH line card both Aand applications. provides four optical interfaces OC-3 rates system side interface 25MHz 50MHz 16-bit wide bus. applications, this reference design provides implementation Digital satisfying Bellcore Stratum Clock synchronization requirements. recommendations this document preliminary subject change. Please check PMC-Sierra website newest updates document releases errata. change notification nessesary, customers sign change notification mailing list PMC-Sierra website.
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FEATURES Provides four OC-3 rate 155.52 Mbits/s SONET/SDH Physical Layer Ports Provides Utopia Level MHz, 16-bit AMulti-PHY System Interface Provides POS-PHY Level MHz, 16-bit Packet Over Sonet Multi-PHY System Interface Contains on-board microcontroller provide clocking requirements related wander transfer, holdover long time stability when using external VCXO Provides Dropside Loopback Diagnostic Purposes Implements Automatic Protection Switching (APS) controller line failure monitoring bytes signaling Provides software package demonstration evaluation S/UNITETRA reference board
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APPLICATIONS S/UNI-TETRA reference design demonstrates physical interface implementation both applications. list below shows networking equipment that incorporate S/UNI-TETRA device: Edge Aswitches physical Interface switches hubs physical Interface Packet switches hubs physical interface
Aapplication, S/UNI-TETRA reference designs interfaces four OC-3 rate SONET/SDH signal line side. drop side, S/UNITETRA interfaces directly with Alayer processors switching adaptation functions using Utopia Level compliant synchronous FIFO style interface. Figure shows example S/UNI-TETRA reference design complete Aswitching design using PMC-Sierra's Achipsets. Figure S/UNI-TETRA with PMC-Sierra AChipsets
Utopia Level
Utopia Level
Optics OC-3
Egress Device
Traffic Manager
TETRA
Design RCMP
ALayer
Multi-PHY Cell Optics OC-3
OC-3
ASwitch Fabric Egress Device
Optics
Traffic Manager
TETRA
Design RCMP
ALayer
Multi-PHY Cell Optics OC-3
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Packet Over Sonet application, using protocol, S/UNI-TETRA reference design interfaces OC-3 rate SONET/SDH signal line side. drop side, S/UNI-TETRA reference design interfaces directly with link layer processor using byte synchronous FIFO interface over which packets transferred. Figure shows S/UNI-TETRA reference design application. Figure S/UNI-TETRA Design with Link Layer Device
POS-PHY Level2
Optics OC-3
Packet/IP Switch
Packet Port Interface Processor
Multi-PHY Packet
TETRA
Design
OC-3 Optics
OC-3 Optics
Packet Port Interface Processor
Multi-PHY Packet
TETRA
Design
OC-3 Optics
Interfacing Reference Design Family S/UNI-TETRA reference design interfaced other Link layer reference boards PMC-Sierra Reference Design Family demonstration evaluation purposes. Aevaluation purpose, Atester adapter card available interfacing 4821A AUtopia Level tester S/UNI-TETRA reference board. Aapplication, next generation Alayer reference design board provides function Alink layer device S/UNI-TETRA reference design.
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REFERENCES PMC-Sierra, Inc., PM5351 S/UNI-TETRA Data Sheet, Issue March 1998 Bell Communication Research SONET Transport Systems: Common Generic Criteria, GR-253-CORE, Issue December 1995
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DESIGN OVERVIEW S/UNI-TETRA reference design consists S/UNI-TETRA device four optical transceivers four port optical physical interface either Asynchronous Transfer Mode (ATM) Packet Over Sonet (POS) applications. S/UNI-TETRA reference design contains on-board microcontroller, Motorola 68332, related circuitry perform synchronization using S/UNI-TETRA's WANS block. dropside Loopback function provided on-board FPGA. S/UNI-TETRA reference design capable maximum bandwidth approximately Mbps used line card. S/UNI-TETRA reference design contains dual-mode physical interface upper layer devices. ATM, S/UNI-TETRA reference design supports Utopia level APHY ALayer specification. Since S/UNI-TETRA quad chip, interface configured multi-PHY address polling over bus. Packet over Sonet, S/UNI-TETRA reference design supports POS-PHY level standard interfacing packet link layer device. S/UNI-TETRA reference design connects upper layer using data running 50MHz. S/UNI-TETRA supports both byte packet level transfer modes defined POS-PHY specification, PMC-971147. S/UNI-TETRA reference implements synchronization circuit that meets Bellcore GR-253-CORE SONET Stratum lower requirements clocking. circuitry generates clock that satisfies wander transfer, long term holdover stability according Bellcore specification utilizing S/UNI-TETRA's WANS block. loopback feature allows receive data looped back transmit stream drop side. This allows evaluation both line side drop side interface. external Field Programmable Gate Array (FPGA) implements loopback feature provides microprocessor interface 68322 microcontroller. This FPGA also provides transmit data reclocking. FPGA reclocks transmit data control signals meet setup hold times S/UNI-TETRA device. S/UNI-TETRA reference design either stand-alone evaluation platform interfaced other S/UNI reference designs. standalone board, S/UNI-TETRA reference design allows access on-chip registers, performs clocking function, performs system side loopback feature both Aand POS. When interfaced other reference boards, cell
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packet generation functions provided these external boards further demonstration evaluation S/UNI-TETRA device.
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BLOCK DIAGRAM
3.3/5V Supply
Loopback Block
Crystal Oscillator
Signals (Loopbacked)
FPGA
TFCLK, RFCLK Tx/Rx System
Switch
Signals
+/-, +/-,
PM5351 S/UNI-TETRA
Micro-interface Signals
Block
Micro Interface
Flash
REFCLK
FPGA
Alarm Status Indicator VCXO
Temperture Sensor
Circuitry
RS-232
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UTOPIA POS-PHY LEVEL INTERFACE
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FUNCTIONAL DESCRIPTION S/UNI-TETRA PM5351 S/UNI-TETRA SATURN User Network Interface monolithic integrated circuit that implements four channel SONET/SDH processing, Amapping Packet over SONET mapping functions STS-3c (STM-1) 155.52 Mbit/s rate. Figure shows overhead STS-3c frame. Figure STS-3c Frame
bytes bytes
Section Overhead (Regen. Section) Pointer Line Overhead (Multiplex Section)
bytes
ACell
ACell
bytes
ACell ACell
STS-3c Transport Overhead STM-1 Section Overhead
byte must indicate A
S/UNI-TETRA receives SONET/SDH streams using serial interface, recovers clock data processes section, line, path overhead. performs framing (A1, A2), descrambling, detects alarm conditions, monitors section, line, path interleaved parity (B1, while accumulating error counts each level performance monitoring purposes. Line path block error indications (M1, also accumulated. S/UNI-TETRA interprets received payload pointers (H1, extracts synchronous payload envelope which carries received Acell packet payload. When used implement AUNI NNI, S/UNI-TETRA frames Apayload using cell delineation. error correction provided. Idle/unassigned cells dropped according programmable filter. Cells also dropped upon detection uncorrectable header check sequence error. Acell payloads descrambled. Acells that passed written four cell FIFO buffer. received cells read from FIFO
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using generic wide Utopia level compliant datapath interface. Counts received Acell headers that errored uncorrectable also those that errored correctable accumulated independently performance monitoring purposes. transmit stream, Acells written internal four cell FIFO using generic 16-bit wide datapath interface. Idle/unassigned cells automatically inserted when internal FIFO contains less than cell. S/UNI-TETRA provides generation header check sequence scrambles payload Acells. Each these transmit Acell processing functions enabled bypassed. When used implement Packet transmission over SONET/SDH link, S/UNI-TETRA extracts Packet over SONET (POS) frames from SONET/SDH synchronous payload envelope. Frames verified correct construction size. Control Escape characters removed. error check sequence optionally verified correctness extracted packet placed received FIFO. received packets read from FIFO through drop side interface. Valid errored packet counts provided performance monitoring. S/UNI-TETRA Packet over SONET implementation flexible enough support several link layer protocols, including HDLC, Frame Relay. transmit stream, S/UNI-TETRA inserts frames into SONET/SDH synchronous payload envelope. Packets transmitted written into 256-byte FIFO through System Interface. Frames built inserting flags, Control Escape characters fields. Either CRC-CCITT CRC-32 computed added frame. Several counters provided performance monitoring. line rate clocks required directly S/UNI-TETRA synthesizes transmit clock recovers receive clock using 19.44 reference clock. Normally S/UNI-TETRA outputs only differential PECL line data (TXD+/-). Optionally, S/UNI-TETRA output differential transmit line rate clock (TXC+/-). S/UNI-TETRA also provides Synchronization controller that used control external VCXO order fully meet Bellcore GR-253-CORE jitter, wander, holdover stability requirements. Details S/UNI-TETRA found S/UNI-TETRA datasheet, PMC971028.
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Optical Line Interface S/UNI-TETRA reference design provides four optical line interfaces 155.52 Mbit/s OC-3 rate. line interface consists four optical data links (ODL) termination scheme PECL signals into from four S/UNI-TETRA transmit, TXD+/- receive, RXD+/- signal pairs. suggested termination scheme PECL transmit receive signals shown Figure both 3.3V ODLs. Figure Line Interface Terminations
Optics
S/UNI-TETRA RxD+ 2*Zo
RDRd
RxD-
TxD+
0.1uF
TDVDD
0.01uF
TxD-
R2/(R1+R2)
Notes: minimum input swing required optical device. switching threshold device (typically volts) (typically mVolts) (Zo/((RS1+Rs)+Z0) (S/UNI-TETRA's analog transmit power) 3.3V (trace impedance) typically (TxD source impedance) typically 15-20 interfacing 5.0V ODL, interfacing 3.3V ODL, 220,
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normal operation, S/UNI-TETRA performs clock recovery serial parallel conversion incoming data stream. loss signal condition, indicated each four pins, S/UNI-TETRA will squelch receive data clock recovery unit will switch reference clock (19.44MHz) keep recovered clock range. This technique guarantees that S/UNI-TETRA will generated indication when loses incoming light. this reference design, 3.3V transceivers used reduce power consumption match PECL level signals. Microcontroller Block S/UNI-TETRA reference design uses 32-bit Motorola 68332 microcontroller running 16.7MHz on-board processor. microcontroller block contains separate flash program data storage run-time program execution. S/UNI-TETRA registers accessed through 10-bit address 8-bit data microprocessor interface 68322. microcontroller accessed through either RS-232 port Background Debugging Mode (BDM) connector reference board. RS232 port allows access serial port 68332. RS-232 port connected serial port using cable. firmware reference design resides FLASH ROM. user VT100 terminal emulation program interface firmware access hardware reference board. serial port terminal should 9600 Baud, data bits, parity, stop bit. microcontroller also provides additional control external adapter cards through Utopia/POS-PHY interface connector. This allows microcontroller access external devices.
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Circuitry Block Circuitry Block consists VCXO, DAC, temperature sensor. circuitry utilizes S/UNI-TETRA's WANS phase comparator function block. Together with WANS block, S/UNI-TETRA reference design provides complete digital clocking design generating stratum level clock that satisfies wander, jitter transfer, long term holdover stability. general block structure digital block diagram implementation S/UNI-TETRA seen Figure below. Figure Digital Block Diagram
DPLL Structure
Reference Clock
Phase Detector
Loop Filter
Temperture Compensation
Output Clock
VCXO
S/UNI-TETRA Reference Design
Phase Detector
Loop Filter Temperture Compensation
Temp Sensor
Recovered Clock divided
WANS
S/UNI-TETRA
REFCLK
VCXO
FPGA VCOCLK
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WANS block derives phase value based phase relationship between recovered clock, RCLK VCXO clock, VCOCLK. digital filtering performed FPGA on-board reduce microprocessor load. also entirely implemented software using 68322 microcontroller. Together with temperature sensor, circuitry block provides temperature VCXO linearity compensation.
System Side Loopback Loopback block consists FPGA exchange switch. exchange switch allows S/UNI-TETRA's system side either connected external FPGA loopback functionality link layer interface board. exchange switch adds minimum delay presents capacitance impedance line. loopback setup shown Figure below. Figure Loopback Diagram
Normal Mode Loopback Mode
Loopback FPGA S/UNITETRA
POS/ASignals
Loopback FPGA S/UNITETRA
POS/ASignals
Link Layer
Link Layer
Exchange Switch
Exchange Switch
normal mode, S/UNI-TETRA's Dropside data control signals connected system interface connector. loopback mode, receive data control signals input into loopbacked FPGA transmit signals. FPGA supports both Aand loopbacks. loopback block supports multi-PHY direct status addressing mode with each having separate cell/packet available signals receive interface(DRCA/DRPA). loopback mode, FPGA polls both receive transmit cells/packets available signals. FPGA starts receive transmit cells/packets only when received data available. This eliminates need implement FIFO inside FPGA.
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External Connector S/UNI-TETRA reference design contains Molex connectors interfacing link layer board. Molex connectors have been measured with network analyzer showed adequate results running 50MHz. first connector used microprocessor communication between microcontroller S/UNI-TETRA reference in-house motherboard. supplies both 3.3V power supply S/UNI-TETRA board. also used FIFO clock signals both Utopia POS-PHY interface. second connector used interfacing Utopia POS-PHY data control signals. Table Interface Connector Name MISO MOSI CS_MICRO Type Input Output Input Output Input Output Input Output Input Function Serial Clock. Clock microcontroller's QSPI module Master Slave Out. Serial Data microcontroller's QSPI module. Master Slave Serial Data microcontroller's QSPI module. Chip select communication between microcontrollers S/UNI-TETRA motherboard. Signal indicate MB1503 master slave bus. M_MICRO micro TETRA board master. M_MICRO motherboard acts master. Interrupt signal from S/UNI-TETRA device Negative differential receive clock signal. This signal, along with RFCLK+ comprise differential RFCLK clock signal sent across connector. RFCLK used reference sample RDAT.
M/S_MICRO
INTB_TETRA RFCLK-
Output Output
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Name RFCLK+
Type Output
Function Positive differential receive clock signal. This signal, along with RFCLK- comprise differential RFCLK clock signal sent across connector. RFCLK used reference sample RDAT. Positive differential transmit clock signal. This signal, along with TFCLK+ comprise differential TFCLK clock signal sent across connector. TFCLK used reference sample TDAT. Negative differential transmit clock signal. This signal, along with TFCLK- comprise differential TFCLK clock signal sent across connector. TFCLK used reference sample TDAT. POS-PHY: Receive Modulo This signal indicates number bytes carried RDAT POS-PHY: Receive Data Valid This signal indicates validity receive data signal Connected.
TFCLK+
Input
TFCLK-
Input
RMOD
Output
RVAL
Output
A38, B30, C30, D16, D22, D34, D37,
Input
Volt supply
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Name 3.3V
Type Input Input
A3-A9, B3-B9, A19, B16, B40,
Function Volt supply Ground
Table Interface Connector Name RDAT[0] RDAT[1] RDAT[2] RDAT[3] RDAT[4] RDAT[5] RDAT[6] RDAT[7] RDAT[8] RDAT[9] RDAT[10] RDAT[11] RDAT[12] RDAT[13] RDAT[14] RDAT[15] RPRTY Type Output Function UTOPIA: Receive Cell Data This carries Acell octets that read from selected receive FIFO.
POS-PHY: Receive Packet Data This carries Packets that read from selected receive FIFO
Output
Receive parity. receive parity signal indicates parity RDAT bus.
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Name DRCA[1] DRCA[2] DRCA[3] DRCA[4] DRPA[1] DRPA[2] DRPA[3] DRPA[4] RADDR[0] RADDR[1] RADDR[2] RADDR[3] RADDR[4] RENB
Type Output
Function UTOPIA: Direct Receive Cell Available These signals indicate available cells transferred across UTOPIA bus.
POS-PHY: Direct Receive Packet Available These signals indicate available packet transferred across POS-PHY bus. Receive port address. These signals used select port read from polled.
Input
Input
Output
Receive Multi-Phy Write Enable. RENB signal active input which used initiate reads from receive FIFOs. UTOPIA: Receive Multi-PHY Cell Available This signal indicates available cell during receive port polling POS-PHY: Polled multi-PHY Receive Packet Available. This signal indicates when data available polled receive FIFO. UTOPIA: Receive Start Cell This signal marks start cell RDAT bus. POS-PHY: Receive Start Packet This signal marks start packet RDAT bus. POS-PHY: Receive Error This signal indicates that current packet been aborted. POS-PHY: Receive Packet This signal marks packet RDAT
PRPA RSOC Output
RSOP
RERR
Output
REOP
Output
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Name TENB
Type Input
Function Utopia POS-PHY: Transmit Multi-Phy Write Enable. TENB signal active input which used initiate writes transmit FIFOs Utopia: Transmit cell available signal This signal used indicate available cell FIFO space polled ports. POS-PHY: Polled Transmit multi-PHY Packet Available. This signal transitions high when programmable minimum number bytes available polled transmit FIFO. Utopia: Transmit Start Cell transmit start cell signal marks start cell TDAT bus. POS-PHY: Transmit Start Packet This signal indicates first word packet. Transmit Address. TADR[4:0] used select port that written being polled.
Output
PTPA
TSOC
Input
TSOP
TADDR[0] TADDR[1] TADDR[2] TADDR[3] TADDR[4] DTCA[1] DTCA[2] DTCA[3] DTCA[4] DTPA[1] DTPA[2] DTPA[3] DTPA[4] TERR
INPUT
Output
Utopia: Direct Transmit Cell Available These signals indicate available cells transferred across UTOPIA.
Input
POS-PHY: Direct Transmit Packet Available These signals provide direct status indication when some programmable number bytes available transmit FIFO. POS-PHY: Transmit Error This signal indicates current packet must aborted.
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Name TEOP
Type Input
Function POS-PHY: Transmit Packet This signal marks packet TDAT bus. POS-PHY: Selected multi-PHY Transmit Packet Available This signal transitions high when predefined minimum number bytes available selected transmit FIFO. POS-PHY: Transmit Word Modulo This signal indicates size current word. Transmit parity. transmit parity signal indicates parity TDAT bus. Utopia: Transmit Cell Data This carries Acell octets that written selected transmit FIFO.
STPA
Output
TMOD
Input
TPRTY TDAT[0] TDAT[1] TDAT[2] TDAT[3] TDAT[4] TDAT[5] TDAT[6] TDAT[7] TDAT[8] TDAT[9] TDAT[10] TDAT[11] TDAT[12] TDAT[13] TDAT[14] TDAT[15]
INPUT INPUT
POS-PHY: Transmit Packet Data This data carries packet octets that written selected transmit FIFO
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IMPLEMENTATION DESCRIPTION S/UNI-TETRA S/UNI-QUAD reference designs share same schematics S/UNI-TETRA/QUAD schematics mnemonic. S/UNIQUAD S/UNI-TETRA devices compatible both provide SONET Afunctionality. WANS block Packet Over Sonet functionality S/UNI-TETRA/QUAD reference design schematics implemented S/UNI-TETRA device. this document, S/UNI-TETRA schematics refer schematics titled "S/UNI-TETRA/QUAD reference design". S/UNI-TETRA reference design schematics were captured using Cadence software, Concept Schematics Capture Tool.
ROOT DRAWING, Sheet This sheet provides overview major functional blocks S/UNITETRA reference design. shows interconnections between TETRA_BLOCK, LOOPBACK_BLOCK, SYS_INTEFACE, MICRO_BLOCK, WAN_CLOCKING, OPTICS_1, OPTICS_2, OPTICS_3, OPTICS_4 blocks.
TETRA_BLOCK, Sheet TETRA_BLOCK shows S/UNI-TETRA's signals power circuitry. Series resistors used source terminate Utopia/POS-PHY lines. Ohms source termination resistor together with output impedance Utopia/POS-PHY pads matches impedance trace Ohms. series termination resistor provided reduce initial overshoot undershoot parasitic capacitance input pins. capacitors used loop filter pins, Four LEDs provided display alarm status from each four channels S/UNITETRA. resistor placed series with Vbias power rail limit Vbias current prevent Vbias latchup. digital analog ground pins connected single ground plane. Layout must ensure that noise from digital circuitry does coupled into analog pins. Figure shows analog power filtering recommandation S/UNI-TETRA.
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Figure Analog Power Filtering Recommandation
0.1uF
RAVD1_B
RAVD1_C
0.1uF
RAVD2_B
0.1uF
0.1uF
RAVD2_C
RAVD3_B
Linear Technology
+3.3V
0.1uF
LT1121
47uF 47uF 10uF
0.1uF
RAVD3_C
S/UNI-TETRA PM5351
RAVD4_B
0.1uF
0.1uF
RAVD4_C
TAVD1_A
47uF, 10uF Tantalum 6Vcapacitor 0.1uF Ceramic type
other analog power pins, RAVD1_A, RAVD2_A, RAVD3_A, RAVD4_A, QAVD_1, QAVD_2 should powered normal system 3.3V power rail have 0.1uF close each pin.
0.1uF
TAVD1_B
0.1uF
analog power filter circuitry with linear regulator front pre-filter with pole 2KHz rejects close 50db ripple noise seen power rail down 10KHz. This circuitry ensures S/UNI-TETRA will within optimal jitter performance even when powered noisy environment. analog power filter circuitry also ensures that analog power pins would powered after digital power pins. schematics, RAVD1<1>, RAVD1<2>, RAVD1<3> correspond RAVD1_A, RAVD1_B, RAVD1_C specified data sheet. digital power pins, every four pins decoupled using 0.1uF ceramic capacitor placed close pin.
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LOOPBACK_BLOCK, Sheet This sheet shows loopback function implemented TETRA's Utopia/POS-PHY Level2 interface signals. P15C16212 exchange switches connected Utopia/POS-PHY signals from both S/UNI-TETRA loopback FPGA. These switches controlled LB_EN signal. When loopback, signals driving board connector tied resistor arrays connected through switches. 74FCT3807 3.3V clock driver supplies receive clocks both S/UNITETRA board connector ATM/POS layer devices. transmit clock supplied from board connector during regular mode. When loopback mode, both transmit receive clocks supplied 74FCT3807 clock driver. FPGA operates mixed 5/3.3V mode. FPGA output level 3.3V Utopia/POS-PHY signals 3.3V requirement.
SYS_INTERFACE, Sheet SYS_INTERFACE block contains board connectors power supply circuitry. Sheet MOLEX pins connectors shown. Balun transformers used transform differential transmit receive clock signals single-ended signal S/UNI-TETRA. Sheet shows power reference board supplied either from external power supply through board connectors. Solder bridges used select desired power source. Fuses transils provided protect board from over-voltage over-current.
MICRO_BLOCK, Sheet MICRO_BLOCK sheet shows 68322 microcontroller external circuitry. 68322 operates 16.337 using 37.7KHz crystal. (128K Flash SRAM provided program storage run-time execution. header allows microcontroller background debug mode downloading program FLASH debugging purposes. MC33064 voltage sensing circuit 68322 reset mode when voltage supply drops below 4.5V. Three LEDs provided displaying board status.
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WAN_CLOCKING, Sheet This sheet shows clocking circuitry used implement local clock reference compliant SONET Stratum clock specifications. precise power supply regulation circuitry used supplying power temperature sensor, ADC, DAC, Op-Amp, VCXO. power supply regulation circuitry consists LMC7660 voltage doubler, LT1129-5 drop voltage regulator. This ensures power clocking circuitry component will have clean supply. temperature sensor connected 10-bit that outputs digitized data microcontroller through port. used supply control voltage VCXO. VCXO operates nominally 19.44 MHz. Op-Amp used 2.04V output voltage range VCXO. inputs come from FPGA. FPGA implements digital filtering algorithm providing clocking board. controlled microcontroller through data address bus.
OPTICS_BLOCK, Sheet This sheet shows four Optical Data Link (ODL) that provides optical electrical (O/E) function S/UNI-TETRA device. PECL signal runs controlled impedance signal lines properly terminated S/UNI-TETRA device. S/UNI-TETRA device interfaces four HFCT-5905 Singlemode Fiber Transceivers. HFCT-5905 transceivers package with mini MT-RJ connector interface. smaller footprint MT-RJ interface allows higher optical port density typical line card.
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SCHEMATICS
Bill Materials Table Major Components List Ref. U2-U5 Component Description PMC-Sierra, Inc. PM5351 S/UNI-TETRA Hewlett Packard http://www.hp.com HFCT-5905 U13, U14, U20-U23 Linear Technology LTC1197 National Semiconductor LM50 Linear Technology LTC1257 National Semiconductor LMC6482 Linear Technology LT1129-5 National Semiconductor LMC7660 Switched Capacitor Voltage Converter Motorola MC33064 Pericom PI5C16212 TSSOP SOIC8 SOIC8 SOIC8 SOIC8 SOIC8 SOT23 SOIC8 Style Package Type SBGA304 Quantity
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Ref. U18,
Component Description Pericom 74FCT807 Motorola MC68332 Actel 42MX-09-PL84 Atmel AT29C010A Cypress CY62128 Linear Technology LT1181A Linear Technology LT1121CST-3.3 50.00 VXCO Raltron VC7220A-LZ-30-19.440-PMC Crystal Oscillator 19.44 Crystal Oscillator
Package Type SOIC20 PQFP PLCC84 TSOP TSOP SOIC16 SOT223 Pins
Quantity
SGS-Thomson SMLVT3V3
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LAYOUT Please Contact PMC-Sierra Layout Drawings.
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NOTES
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CONTACTING PMC-SIERRA, INC. PMC-Sierra, Inc. 105-8555 Baxter Place Burnaby, Canada Tel: Fax: (604) 415-6000 (604) 415-6200 document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com (604) 415-4533 http://www.pmc-sierra.com
Document Information: Corporate Information: Application Information: Site:
None information contained this document constitutes express implied warranty PMC-Sierra, Inc. sufficiency, fitness suitability particular purpose such information fitness, suitability particular purpose, merchantability, performance, compatibility with other parts systems, products PMC-Sierra, Inc., portion thereof, referred this document. PMC-Sierra, Inc. expressly disclaims representations warranties kind regarding contents information, including, limited express implied warranties accuracy, completeness, merchantability, fitness particular use, non-infringement. event will PMC-Sierra, Inc. liable direct, indirect, special, incidental consequential damages, including, limited lost profits, lost business lost data resulting from reliance upon information, whether PMC-Sierra, Inc. been advised possibility such damage. 1998 PMC-Sierra, Inc. PMC-980322 (P2) Issue date: 1998
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PM5351 S/UNI-TETRA S/UNI-TETRA REFERENCE DESIGN PM5351 S/UNI

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