Low-Power, Compact 2.5Gbps/2.7Gbps Clock-Recovery Data-Retiming M

The Datasheet Archive - 100 Million Datasheets from 7500 Manufacturers.

Low-Power, Compact 2.5Gbps/2.7Gbps Clock-Recovery Data-Retiming M

Datasheet Thumbnail

Top Searches for this datasheet

19-2087; 3/02
Low-Power, Compact 2.5Gbps/2.7Gbps Clock-Recovery Data-Retiming
MAX3873 compact, low-power 2.488Gbps/ 2.67Gbps clock-recovery data-retiming SDH/SONET applications. phase-locked loop (PLL) recovers synchronous clock signal from serial data input. input data then retimed this recovered clock, providing clean data output. MAX3873 meets SDH/SONET jitter specifications, does require external reference clock frequency acquisition, provides excellent tolerance both deterministic sinusoidal jitter. MAX3873 provides loss-of-lock (LOL) output indicate whether lock. recovered data clock outputs with on-chip back terminations each line. clock output powered down used. MAX3873 implemented Maxim's second-generation SiGe process consumes only 260mW 3.3V supply (output clock disabled, output swing). device available 20-pin exposed-pad package operates from -40°C +85°C.
Features
Fully Integrated Clock Recovery Data Retiming Power Dissipation: 260mW with +3.3V Supply Clock Jitter Generation: 5mUIRMS Exceeds ANSI, ITU, Bellcore SDH/SONET Jitter Specifications Differential Input Range: 50mVP-P 1.6VP-P Single +3.3V Power Supply Fast Track (FASTRACK) Mode Available Clock Output Disabled Input Data Rate: 2.488Gbps 2.67Gbps Selectable Output Amplitude Tolerates 2000 Consecutive Identical Digits Loss-of-Lock Indicator Differential Data Clock Outputs Operating Temperature Range: -40°C +85°C
MAX3873
Applications
Switch Matrix Backplanes SDH/SONET Receivers Regenerators Add/Drop Multiplexers Digital Cross-Connects SDH/SONET Test Equipment DWDM Transmission Systems
FIL+
Ordering Information
PART MAX3873EGP TEMP RANGE -40°C +85°C PIN-PACKAGE QFN-EP* (4mm 4mm)
exposed
Configuration
FIL-
VIEW
Typical Application Circuit appears data sheet.
RATESET SDI+ SDIVCC SDO+ SDOVCC_BUF SCLKO+ SCLKO-
MAX3873
MODE
FASTRACK
QFN**
**NOTE: EXPOSED MUST SOLDERED SUPPLY GROUND.
Maxim Integrated Products
VCC_VCO
SCLKEN
pricing, delivery, ordering information, please contact Maxim/Dallas Direct! 1-888-629-4642, visit Maxim's website www.maxim-ic.com.
Low-Power, Compact 2.5Gbps 2.7Gbps Clock-Recovery Data-Retiming MAX3873
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, VCC.-0.5V +5.0V Voltage SDI± (VCC 1.0V) (VCC 0.5V) Output Current SDO±, SCLKO± .22mA Voltage LOL, FASTRACK, FIL±, SCLKEN MODE, RATESET.-0.5V (VCC 0.5V) Continuous Power Dissipation +85°C) 20-Pin (derate 20.0mW/°C above +85°C) .1300mW Operating Temperature Range .-40°C +85°C Storage Temperature Range .-50°C +150°C Processing Temperature.+400°C Lead Temperature (soldering, 10s) .+300°C
Stresses beyond those listed under "Absolute Maximum Ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated operational sections specifications implied. Exposure absolute maximum rating conditions extended periods affect device reliability.
ELECTRICAL CHARACTERISTICS
(VCC 3.0V 3.6V, -40°C +85°C. Typical values 2.488Gbps, 3.3V, +25°C, unless otherwise noted.) (Note
PARAMETER Supply Current SYMBOL CONDITIONS MODE GND, SCLKEN (Note MODE OPEN, SCLKEN High (Note (Figure (Figure DC-coupled (Figure MODE Open (Note Differential Output Swing MODE (Note MODE (Note Differential Output Resistance Output Common-Mode Voltage MODE Open (Note MODE (Note MODE (Note INPUT/OUTPUT SPECIFICATIONS (FASTRACK, LOL, SCLKEN, MODE, RATESET) Input High Voltage Input Voltage Input Current Output High Voltage Output Voltage sourcing 40µA sinking VID/4 0.17 0.13 0.08 1000 mVP-P 1600 UNITS
INPUT SPECIFICATIONS (SDI+, SDI-) Differential Input Voltage Single-Ended Input Voltage Input Common-Mode Voltage Input Termination mVP-P
OUTPUT SPECIFICATIONS (SDO+, SDO-, SCLKO+, SCLKO-)
Low-Power, Compact 2.5Gbps 2.7Gbps Clock-Recovery Data-Retiming
ELECTRICAL CHARACTERISTICS
(VCC 3.0V 3.6V, 0.01µF, -40°C +85°C. Typical values 3.3V, 2.488Gbps, +25°C, unless otherwise noted.) (Note
PARAMETER Serial Input Data Rate Clock-to-Q Delay Jitter Peaking Jitter Transfer Bandwidth tCLK-Q SYMBOL RATESET RATESET High (Figure (Note 2MHz RATESET 70kHz, 0.4UI deterministic jitter input data Sinusoidal Jitter Tolerance (Note 100kHz, 0.4UI deterministic jitter input data 1MHz, 0.4UI deterministic jitter input data 10MHz, 0.4UI deterministic jitter input data Jitter Generation Clock Output Edge Speed Data Output Edge Speed Tolerated Consecutive Identical Digits SDI± Input Return Loss (-20log(S11)) Frequency Acquisition Time Assert Time 100kHz 2.5GHz 2.5GHz 4.0GHz (Figure (Figure JGEN (Note (20% 80%) (20% 80%) 2.12 0.33 0.15 2000 mUIRMS mUIP-P bits UIP-P CONDITIONS 2.488 2.67 UNITS Gbps
MAX3873
Note -40°C, characteristics guaranteed design characterization. Note outputs open. Note VCC. Note characteristics guaranteed design characterization. Note Relative falling edge SCLKO+. Figure Note Measured with PRBS. Note Jitter 12kHz 20MHz.
Low-Power, Compact 2.5Gbps 2.7Gbps Clock-Recovery Data-Retiming MAX3873
0.4V 800mV SCLKO+ 0.4V 800mV 0.4V AC-COUPLED SINGLE-ENDED INPUT (CML PECL) 25mV tCLK-Q 25mV tCLK
Figure Definition Clock-to-Q Delay
0.8V DC-COUPLED SINGLE-ENDED INPUT
Figure Definition Input Voltage Swing
SERIAL DATA <2µs
1200 BITS PATTERN DATA CLOCK PHASE ALIGNED INPUT DATA FASTRACK
Figure Definition Phase Acquisition Time
INPUT DATA
ASSERT TIME OUTPUT
FREQUENCY ACQUISITION TIME
Figure Definition Assert Time Frequency Acquisition Time
Low-Power, Compact 2.5Gbps 2.7Gbps Clock-Recovery Data-Retiming
Typical Operating Characteristics
+25°C, unless otherwise noted.)
RECOVERED CLOCK DATA (2.488Gbps, PATTERN, 50mVP-P)
MAX3873 toc01
MAX3873
RECOVERED CLOCK DATA (2.67Gbps, PATTERN, 50mVP-P)
MAX3873 toc02
125mV/div
125mV/div
100ps/div
100ps/div
RECOVERED CLOCK JITTER (2.488Gbps)
MAX3873 toc03
JITTER TOLERANCE (2.488Gbps, PATTERN, 50mVP-P)
MAX3873 toc04
WITH 0.2UI
INPUT JITTER (UIp-p)
WITH 0.4UI DETERMINISTIC JITTER
BELLCORE MASK 1000 10,000
PATTERN 2.0psRMS 10ps/div
JITTER FREQUENCY (kHz)
JITTER TRANSFER
MAX3873 toc05
SUPPLY CURRENT TEMPERATURE (SCLKO DISABLED)
MAX3873 toc06
SUPPLY CURRENT TEMPERATURE (SCLKO ENABLED)
SUPPLY CURRENT (mA) OUTPUT SWING OUTPUT SWING OUTPUT SWING
MAX3873 toc07
-0.5 TRANSFER (dB) -1.0 -1.5 -2.0 -2.5 -3.0 FREQUENCY (Hz)
SUPPLY CURRENT (mA) OUTPUT SWING OUTPUT SWING OUTPUT SWING
BELLCORE MASK
TEMPERATURE (°C)
TEMPERATURE (°C)
Low-Power, Compact 2.5Gbps 2.7Gbps Clock-Recovery Data-Retiming MAX3873
Typical Operating Characteristics (continued)
+25°C, unless otherwise noted.)
PULLIN RANGE (RATESET
MAX3873 toc08
ERROR RATIO INPUT AMPLITUDE
10-3 10-4 ERROR RATIO 10-5 10-6 10-7 10-8 10-9 10-10
MAX3873 toc09
FREQUENCY (GHz)
10-2
AMBIENT TEMPERATURE (°C)
INPUT VOLTAGE (mVp-p)
JITTER TOLERANCE INPUT DETERMINISTIC JITTER
MAX3873 toc10
JITTER TOLERANCE PULSE-WIDTH DISTORTION
SINUSOIDAL JITTER TOLERANCE (UIP-P) INPUT DATA FILTERED 1870MHz 4TH-ORDER BESSEL FILTER fJITTER 10MHz PRBS fJITTER 1MHz
MAX3873 toc11
SINUSOIDAL JITTER TOLERANCE (UIP-P) 0.05 0.10 0.15 PRBS fJITTER 10MHz fJITTER 1MHz
0.20
DETERMINISTIC JITTER (UIP-P)
INPUT PULSE-WIDTH DISTORTION
Description
NAME RATESET SDI+ SDIFASTRACK VCC_VCO MODE 3.3V Supply Voltage Positive Serial Data Input Negative Serial Data Input Fast Track Control, Input. When FASTRACK high, switched fasttrack mode fast phase acquisition. When FASTRACK low, operates normally. 3.3V Supply Voltage Output Amplitude Mode Select. MODE OPEN sets output amplitude high; MODE high sets output amplitude medium; MODE sets output amplitude low. FUNCTION Input Rate Select. Connect 2.488Gbps data high 2.67Gbps data.
Low-Power, Compact 2.5Gbps 2.7Gbps Clock-Recovery Data-Retiming
Description (continued)
NAME SCLKEN SCLKOSCLKO+ VCC_BUF SDOSDO+ FILFIL+ Exposed FUNCTION Clock Output Enable, Input. When SCLKEN OPEN SCLKEN High, clock outputs (SCLKO±) enabled. When SCLKEN Low, clock outputs disabled SCLKO± VCC. Negative Clock Output, CML. This output disabled setting SCLKEN Low. Positive Clock Output, CML. This output disabled setting SCLKEN Low. 3.3V Output Buffer Supply Voltage Negative Data Output, Positive Data Output, Loss-of-Lock Output, (Active-Low). output indicates lock failure. Supply Ground Negative Loop Filter Connection. Connect 0.01µF capacitor between FIL+ FIL-. Positive Loop Filter Connection. Connect 0.01µF capacitor between FIL+ FIL-. Ground. exposed must soldered circuit board ground proper electrical thermal operation.
MAX3873
Detailed Description
MAX3873 consists fully integrated phaselocked loop (PLL), input amplifier, output buffers (Figure consists phase/frequency detector, loop filter, voltage-controlled oscillator (VCO). This device designed deliver best combination jitter performance power dissipation using fully-differential signal architecture low-noise design techniques.
Input Amplifier
input amplifier provides internal line terminations accept differential input amplitude from 50mV 1600mV structure input amplifier shown Figure
Phase Detector
phase detector incorporated MAX3873 produces voltage proportional phase difference between incoming data internal clock. Because feedback nature, drives error voltage zero, aligning recovered clock center incoming data retiming.
Frequency Detector
FIL+ FILRATESET
SDO+
MAX3873
SDOMODE
SDI+ SDIPHASE FREQUENCY DETECTOR LOOP FILTER SCLKEN SCLKO+ SCLKO-
digital frequency detector (FD) aids frequency acquisition during startup conditions. frequency difference between received data clock derived sampling outputs each edge data input signal. drives until frequency difference reduced zero. Once frequency acquisition complete, returns neutral state.
Loop Filter
phase detector frequency detector outputs summed into loop filter. external capacitor, required damping ratio. Design Procedure section guidelines selecting this capacitor.
FASTRACK
Figure Functional Diagram
Low-Power, Compact 2.5Gbps 2.7Gbps Clock-Recovery Data-Retiming MAX3873
loop filter output controls on-chip running either 2.488GHz 2.67GHz. provides phase noise trimmed correct frequency. Clock jitter generation typically 2psRMS within jitter band 12kHz 20MHz. example, using 2000pF results jitter peaking 0.2dB. Reducing below 500pF might result instability. recommended value 0.01µF guarantee maximum jitter peaking less than 0.1dB. must high-quality capacitor type better.
Loss-of-Lock Monitor
loss-of-lock (LOL) monitor incorporated MAX3873 indicate either loss frequency lock absence incoming data. Under loss lock conditions, momentarily assert high noise.
FASTRACK Mode
MAX3873 fast-track (FASTRACK) mode decrease locking time switched data applications. applications where input data switched from source another, there brief period where there valid data input MAX3873. absence input data, phase will slowly drift from ideal position. enabling FASTRACK during reacquisition, time required regain phase alignment reduced. This accomplished increasing loop bandwidth approximately 50%. bandwidth MAX3873 also linearly dependent upon transition density input data. using preamble 1200 bits pattern during switching, loop bandwidth increased factor approximately (see Figure Thus using pattern preamble enabling FASTRACK, bandwidth increased factor approximately resulting fastest possible reacquisition phase lock. FASTRACK increases rate which MAX3873 acquires proper phase, assuming that already running proper frequency. startup conditions, however, frequency significantly different from input data, time required lock incoming data increased approximately 1.0ms.
Design Procedure
Setting Loop Filter
MAX3873 designed both regenerator receiver applications. fully integrated classic second-order feedback system, with loop bandwidth (JBW) below 2.0MHz. external capacitor, adjusted loop damping. Figures show open-loop closed-loop transfer functions. zero frequency, function external capacitor approximated according (3000)
with expressed overdamped system, jitter peaking (JP) second-order system approximated
HO(j2f) (dB)
H(j2f) (dB) 2000pF CLOSED-LOOP GAIN
OPEN-LOOP GAIN
0.01µF
0.01µF 5.3kHz
2000pF 26kHz
(kHz) 1000 1000
(kHz)
Figure Open-Loop Transfer Function
Figure Closed-Loop Transfer Function
Low-Power, Compact 2.5Gbps 2.7Gbps Clock-Recovery Data-Retiming
Sinusoidal Jitter Tolerance Input Deterministic Jitter Trade-Offs
MAX3873 excellent jitter tolerance. Adding input will close opening result reduced sinusoidal jitter tolerance. typically tolerate more than 0.3UIP-P 10MHz jitter when measured with PRBS data stream with 0.4UI deterministic jitter (DJ). This gives total high-frequency jitter tolerance 0.7UI. Refer Jitter Tolerance Pulse-Width Distortion Jitter Tolerance Deterministic Jitter graphs Typical Operating Characteristics section.
Applications Information
Consecutive Identical Digits (CID)
MAX3873 phase frequency drift absence data transitions. result, long runs consecutive zeros ones tolerated while maintaining less than 10-10. tolerance tested using PRBS, substituting long zeros simulate worst case. tolerance 2000 bits typical.
MAX3873
Exposed-Pad Package
exposed-pad (EP), 20-pin incorporates features that provide very thermal-resistance path heat removal from electrical ground MAX3873 must soldered circuit board proper thermal electrical performance.
Input Output Terminations
MAX3873's digital outputs (SDO+, SDO-, SCLKO+, SCLKO-) have selectable output amplitude controlled MODE input. SCLKO outputs used, they disabled (see Supply Current Temperature graph Typical Operating Characteristics section). structure high-speed digital outputs shown Figure MODE input sets current current source, thereby controlling output swing. SCLKEN input sets current SCLKO current source 0mA, disabling output. structure inputs (SDI±) shown Figure Unless input DC-coupled output, AC-coupling with inputs avoid upsetting common-mode voltage.
Layout
Circuit board layout design significantly affect MAX3873's performance. good high-frequency design techniques, including minimizing ground inductance using controlled-impedance transmission lines data clock signals. Power-supply decoupling should placed close pins possible. Isolate input from output signals reduce feedthrough.
MAX3873
SDI+
OUT+
OUT-
SDI-
MODE
SCLKO ONLY
SCLKEN
MAX3873
Figure Output Model
Figure Input Model
Low-Power, Compact 2.5Gbps 2.7Gbps Clock-Recovery Data-Retiming MAX3873
Typical Application Circuit
SWITCH CARD
2.5Gbps OPTICAL TRANSCEIVER
MAX3873
CROSSPOINT SWITCH
SDI+ SDI-
FIL+
FIL-
MODE
MAX3873
FASTRACK RATESET 20-PIN
SDO+ SDOSCLKO+ SCLKOSCLKEN
Chip Information
TRANSISTOR COUNT: 2028 PROCESS: SiGe BiCMOS
Low-Power, Compact 2.5Gbps 2.7Gbps Clock-Recovery Data-Retiming
Package Information
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
12,16,20, QFN.EPS
MAX3873
Low-Power, Compact 2.5Gbps 2.7Gbps Clock-Recovery Data-Retiming MAX3873
Package Information (continued)
(The package drawing(s) this data sheet reflect most current specifications. latest package outline information, www.maxim-ic.com/packages.)
Maxim cannot assume responsibility circuitry other than circuitry entirely embodied Maxim product. circuit patent licenses implied. Maxim reserves right change circuitry specifications without notice time.
Maxim Integrated Products, Gabriel Drive, Sunnyvale, 94086 408-737-7600 2002 Maxim Integrated Products Printed registered trademark Maxim Integrated Products.

Low-Power, Compact 2.5Gbps/2.7Gbps Clock-Recovery Data-Retiming M

Top Searches for this datasheet

Other recent searches