EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process Package Option

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EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process Package Option

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SN54AC10, SN74AC10 TRIPLE 3-INPUT POSITIVE-NAND GATES
EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process Package Options Include Plastic Small-Outline (D), Shrink Small-Outline (DB), Thin Shrink Small-Outline (PW) Packages, Ceramic Chip Carriers (FK) Flatpacks (W), Standard Plastic Ceramic DIPS
SN54AC10 PACKAGE SN74AC10 PACKAGE (TOP VIEW)
description
'AC10 contain three independent 3-input NAND gates. devices perform Boolean function positive logic. SN54AC10 characterized operation over full military temperature range 55°C 125°C. SN74AC10 characterized operation from 40°C 85°C.
FUNCTION TABLE (each gate) INPUTS OUTPUT
SN54AC10 PACKAGE (TOP VIEW)
internal connection
logic symbol
logic diagram, each gate (positive logic)
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12. numbers shown packages.
Please aware that important notice concerning availability, standard warranty, critical applications Texas Instruments semiconductor products disclaimers thereto appears this data sheet. EPIC trademark Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1996, Texas Instruments Incorporated
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DALLAS, TEXAS 75265
SN54AC10, SN74AC10 TRIPLE 3-INPUT POSITIVE-NAND GATES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Input voltage range, (see Note Output voltage range, (see Note Input clamp current, VCC) Output clamp current, VCC) Continuous output current, VCC) Continuous current through Maximum power dissipation 55°C still air) (see Note package 1.25 package package package Storage temperature range, Tstg 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only, functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTES: input output voltage ratings exceeded input output current ratings observed. maximum package power dissipation calculated using junction temperature 150°C board trace length mils, except package, which trace length zero.
recommended operating conditions (see Note
SN54AC10 Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise fall rate 3.15 3.85 1.35 1.65 SN74AC10 3.15 3.85 1.35 1.65 UNIT
Operating free-air temperature NOTE Unused inputs must held high prevent them from floating.
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AC10, SN74AC10 TRIPLE 3-INPUT POSITIVE-NAND GATES
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS GND, ±0.1 0.002 0.001 0.001 0.36 0.36 0.36 1.65 1.65 2.56 3.86 4.86 25°C 2.99 4.99 5.49 SN54AC10 3.85 3.85 0.44 0.44 0.44 SN74AC10 2.46 3.76 4.76 UNIT
more than output should tested time, duration test should exceed
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER tPLH tPHL FROM (INPUT) (OUTPUT) 25°C SN54AC10 SN74AC10 10.5 UNIT
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER tPLH tPHL FROM (INPUT) (OUTPUT) 25°C SN54AC10 SN74AC10 UNIT
operating characteristics, 25°C
PARAMETER Power dissipation capacitance TEST CONDITIONS UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
SN54AC10, SN74AC10 TRIPLE 3-INPUT POSITIVE-NAND GATES
PARAMETER MEASUREMENT INFORMATION
TEST tPLH/tPHL Open From Output Under Test (see Note Open In-Phase Output tPHL Out-of-Phase Output LOAD CIRCUIT Input (see Note tPLH tPHL tPLH
VOLTAGE WAVEFORMS
NOTES: includes probe capacitance. input pulses supplied generators having following characteristics: MHz, outputs measured time with input transition measurement.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
IMPORTANT NOTICE Texas Instruments subsidiaries (TI) reserve right make changes their products discontinue product service without notice, advise customers obtain latest version relevant information verify, before placing orders, that information being relied current complete. products sold subject terms conditions sale supplied time order acknowledgement, including those pertaining warranty, patent infringement, limitation liability. warrants performance semiconductor products specifications applicable time sale accordance with TI's standard warranty. Testing other quality control techniques utilized extent deems necessary support this warranty. Specific testing parameters each device necessarily performed, except those mandated government requirements. CERTAIN APPLICATIONS USING SEMICONDUCTOR PRODUCTS INVOLVE POTENTIAL RISKS DEATH, PERSONAL INJURY, SEVERE PROPERTY ENVIRONMENTAL DAMAGE ("CRITICAL APPLICATIONS"). SEMICONDUCTOR PRODUCTS DESIGNED, AUTHORIZED, WARRANTED SUITABLE LIFE-SUPPORT DEVICES SYSTEMS OTHER CRITICAL APPLICATIONS. INCLUSION PRODUCTS SUCH APPLICATIONS UNDERSTOOD FULLY CUSTOMER'S RISK. order minimize risks associated with customer's applications, adequate design operating safeguards must provided customer minimize inherent procedural hazards. assumes liability applications assistance customer product design. does warrant represent that license, either express implied, granted under patent right, copyright, mask work right, other intellectual property right covering relating combination, machine, process which such semiconductor products services might used. TI's publication information regarding third party's products services does constitute TI's approval, warranty endorsement thereof.
Copyright 1998, Texas Instruments Incorporated

EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process Package Option

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