SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER diff
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ICS889831
SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
differential LVPECL/ECL outputs pair accept following differential input levels: LVPECL, LVDS, CML, SSTL internal input termination Maximum output frequency: 2.1GHz Output skew: 30ps (maximum) Part-to-part skew: 185ps (maximum) Additive phase jitter, RMS: 0.27ps (typical) Propagation delay: 570ps (maximum) LVPECL mode operating voltage supply range: 2.5V 3.3V mode operating voltage supply range: -3.3V 2.5V -40°C 85°C ambient operating temperature Lead-Free package fully RoHS compliant
GENERAL DESCRIPTION
ICS889831 high speed 1-to-4 Differentialto-LVPECL/ECL Fanout Buffer member HiPerClockSof HiPerClockSfamily high performance clock solutions from ICS. ICS889831 optimized high speed very output skew, making suitable demanding applications such SONET, Gigabit Gigabit Ethernet, Fibre Channel. internally terminated differential input VREF_ allow other differential signal families such LVDS, LVHSTL easily interfaced input with minimal external components. device also output enable which useful system test debug purposes. ICS889831 packaged small 16-pin VFQFN package which makes ideal space-constrained applications.
BLOCK DIAGRAM
ASSIGNMENT
VREF_AC
ICS889831
16-Lead VFQFN 0.95 package body Package View
VREF_AC
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SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Type Description Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Differential output pair. LVPECL interface levels. Positive supply pins. Synchronizing clock enable. When LOW, outputs will outputs will HIGH next transition inputs. Input threshold VCC/2V. Includes pull-up resistor. Default state HIGH when left floating. internal latch clocked falling edge input signal LVTTL LVCMOS interface levels. Inver ting differential clock input. internal input termination Reference voltage AC-coupled applications. Termination input. Non-inver ting differential clock input. internal input termination Negative supply pin.
TABLE DESCRIPTIONS
Number Name Output Output Output Power
Input
Pullup
VREF_AC
Input Output Input Input Power
Output Differential output pair. LVPECL interface levels. NOTE: Pullup refers internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP Parameter Input Pullup Resistor Test Conditions Minimum Typical Maximum Units
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SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Outputs
TABLE CONTROL INPUT FUNCTION TABLE
Input Q0:Q3 Disabled; nQ0:nQ3 Disabled; HIGH
Enabled Enabled After switches, clock outputs disabled enabled following falling input clock edge shown Figure
VCC/2
VCC/2
VOUT Swing
FIGURE TIMING DIAGRAM
TABLE TRUTH TABLE
Inputs 0(1) Outputs Q0:Q3 nQ0:nQ3 1(1)
NOTE next negative transition input signal (IN).
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ICS889831
SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
4.6V (LVPECL mode, NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage -4.6V (ECL mode, device. These ratings stress specifi-0.5V cations only. Functional operation product 0.5V 0.5V these conditions conditions beyond those 50mA 100mA ±50mA ±100mA 0.5mA -65°C 150°C 51.5°C/W lfpm) listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Negative Supply Voltage, Inputs, (LVPECL mode) Inputs, (ECL mode) Outputs, Continuous Current Surge Current Input Current, Current, Input Sink/Source, IREF_AC Storage Temperature, TSTG Package Thermal Impedance,
(Junction-to-Ambient)
Operating Temperature Range, -40°C +85°C
TABLE POWER SUPPLY CHARACTERISTICS, 2.5V 3.3V
Symbol Parameter Positive Supply Voltage Power Supply Current Test Conditions Minimum 2.375 Typical Maximum 3.465 Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, 2.5V 3.3V
Symbol Parameter Input High Voltage Input Voltage Input High Current Input Current 3.465V 3.465V, -150 Test Conditions Minimum Typical Maximum Units
TABLE CHARACTERISTICS, 2.5V 3.3V
Symbol VREF_AC VDIFF_IN Parameter Differential Input Resistance Input High Voltage Input Voltage Input Voltage Swing Reference Voltage Differential Input Voltage Swing Input Current; NOTE (IN, nIN) (IN, nIN) (IN, nIN) (IN, nIN) Test Conditions IN-to-VT Minimum 0.15 1.42 1.37 Typical Maximum 0.15 1.32 Units
NOTE Guaranteed design.
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SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Conditions Minimum 1.125 1.895 Typical 1.005 1.78 Maximum 0.935 1.67 Units
TABLE LVPECL CHARACTERISTICS, 2.375V 3.465V;
Symbol VOUT VDIFF_OUT Parameter Output High Voltage; NOTE Output Voltage; NOTE Output Voltage Swing Differential Output Voltage Swing
NOTE Outputs terminated with
TABLE CHARACTERISTICS, -3.3V -2.5V 3.3V
Symbol fMAX Parameter Maximum Output Frequency Propagation Delay; (Differential); NOTE Output Skew; NOTE t-to-Par Skew; NOTE Buffer Additive Phase Jitter, RMS; refer Additive Phase Jitter section Output Rise/Fall Time Clock Enable Setup Time Clock Enable Hold Time 155.52MHz, Integration Range: 12kHz 20MHz Condition Output Swing 450mV Input Swing: 100mV Input Swing: 800mV Minimum 0.27 Typical Maximum Units
tsk(o) tsk(pp) tjit
tR/tF
parameters characterized 1GHz unless otherwise noted. NOTE Measured from differential input crossing point differential output crossing point. NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured output differential cross points. NOTE Defined skew between outputs different devices operating same supply voltages with equal load conditions. Using same type inputs each device, outputs measured differential cross points. NOTE This parameter defined accordance with JEDEC Standard
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SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
ADDITIVE PHASE JITTER
spectral purity band specific offset from fundamental compared power fundamental called Phase Noise. This value normally expressed using Phase noise plot most often specified plot many applications. Phase noise defined ratio noise power present band specified offset from fundamental frequency power value fundamental. This ratio expressed decibels (dBm) ratio power
band power fundamental. When required offset specified, phase noise called value, which simply means specified offset from fundamental. investigating jitter frequency domain, better understanding effects desired application over entire time record signal. mathematically possible calculate expected error rate given phase noise plot.
Additive Phase Jitter 155.52MHz
(12kHz 20MHz) 0.27ps typical
PHASE NOISE dBc/HZ
-100 -110 -120 -130 -140 -150 -160 -170 -180 -190 100k 100M
OFFSET FROM CARRIER FREQUENCY (HZ)
with most timing specifications, phase noise measurements have issues. primary issue relates limitations equipment. Often noise floor equipment higher than noise floor device. This illustrated above.
vice meets noise floor what shown, actually lower. phase noise dependant input source measurement equipment.
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SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
PARAMETER MEASUREMENT INFORMATION
SCOPE
Cross Points
LVPECL
-0.375V -1.465V
OUTPUT LOAD TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
PART PART
tsk(pp)
tsk(o)
PART-TO-PART SKEW
OUTPUT SKEW
Clock Outputs
nQ0:nQ3 Q0:Q3
OUTPUT RISE/FALL TIME
PROPAGATION DELAY
VIN, VOUT
VDIFF_IN, VDIFF_OUT 1600mV (typical)
HOLD SET-UP
800mV (typical)
SETUP HOLD TIME
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SINGLE ENDED DIFFERENTIAL INPUT VOLTAGE SWING
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ICS889831
SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER APPLICATION INFORMATION
TERMINATION 3.3V LVPECL OUTPUTS
clock layout topology shown below typical termination LVPECL outputs. different layouts mentioned recommended only guidelines. FOUT nFOUT impedance follower outputs that generate ECL/LVPECL compatible outputs. Therefore, terminating resistors current path ground) current sources must used functionality. These outputs designed drive transmission lines. Matched impedance techniques should used maximize operating frequency minimize signal distortion. Figures show different layouts which recommended only guidelines. Other suitable clock layouts exist would recommended that board designers simulate guarantee compatibility across printed circuit clock component process variations.
3.3V
FOUT
FOUT
((VOH VOL) (VCC
FIGURE LVPECL OUTPUT TERMINATION
FIGURE LVPECL OUTPUT TERMINATION
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SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
ground level. Figure eliminated termination shown Figure
TERMINATION 2.5V LVPECL OUTPUTS
Figure Figure show examples termination 2.5V LVPECL driver. These terminations equivalent terminating 2.5V, very close
2.5V VCC=2.5V
2.5V 2.5V VCC=2.5V 2,5V LVPECL Driv 62.5 62.5
2,5V LVPECL Driv
FIGURE 2.5V LVPECL DRIVER TERMINATION EXAMPLE
FIGURE 2.5V LVPECL DRIVER TERMINATION EXAMPLE
2.5V VCC=2.5V 2,5V LVPECL Driv
FIGURE 2.5V LVPECL TERMINATION EXAMPLE
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SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
BUILT-IN TERMINATION INTERFACES
most common driver types. input interfaces suggested here examples only. driver from another vendor, their termination recommendation. Please consult with vendor driver component confirm driver termination requirements.
2.5V LVPECL INPUT
WITH
/nIN with built-in terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL other differential signals. Both must meet input requirements.Figures show interface examples HiPerClockS IN/nIN input with built-in terminations driven
3.3V 2.5V
2.5V
2.5V
2.5V
LVDS
2.5V LVPECL
Receiver With Built-In
Receiver With Built-In
FIGURE HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN DRIVEN LVDS DRIVER
FIGURE HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN DRIVEN LVPECL DRIVER
2.5V
2.5V
2.5V
2.5V
Open Collector
Built-in Pull-up
Receiver With Built-In
Receiver With Built-In
FIGURE HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN DRIVEN OPEN COLLECTOR DRIVER
FIGURE HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN DRIVEN DRIVER WITH BUILT-IN PULLUP
2.5V
2.5V
SSTL
Receiver With Built-In
FIGURE HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN DRIVEN SSTL DRIVER
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SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
BUILT-IN TERMINATION INTERFACES
most common driver types. input interfaces suggested here examples only. driver from another vendor, their termination recommendation. Please consult with vendor driver component confirm driver termination requirements.
3.3V LVPECL INPUT
WITH
/nIN with built-in terminations accepts LVDS, LVPECL, LVHSTL, CML, SSTL other differential signals. Both VOUT must meet VCMR input requirements. Figures show interface examples HiPerClockS IN/nIN input with built-in terminations driven
3.3V
3.3V
3.3V
3.3V
LVDS
LVPECL
Receiver With Built-In
Receiver With Built-In
FIGURE HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN DRIVEN LVDS DRIVER
FIGURE HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN DRIVEN LVPECL DRIVER
3.3V
3.3V
3.3V
3.3V
CML- Open Collector
CML- Built-in Pull-Up
Receiver With Built-In
Receiver With Built-In
FIGURE HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN DRIVEN DRIVER WITH OPEN COLLECTOR
FIGURE HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN DRIVEN DRIVER WITH BUILT-IN PULLUP
3.3V
3.3V
SSTL
Receiver With Built-In
FIGURE HIPERCLOCKS IN/nIN INPUT WITH BUILT-IN DRIVEN SSTL DRIVER
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SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
BUILT-IN TERMINATION UNUSED INPUT HANDLING
3.3V DIFFERENTIAL INPUT
WITH
prevent oscillation reduce noise, recommended have pullup pulldown connect true compliment unused input shown Figure
3.3V 3.3V
Receiver with Built-In
FIGURE UNUSED INPUT HANDLING
2.5V DIFFERENTIAL INPUT
WITH
BUILT-IN TERMINATION UNUSED INPUT HANDLING
prevent oscillation reduce noise, recommended have pullup pulldown connect true compliment unused input shown Figure
2.5V 2.5V
Receiver with Built-In
FIGURE UNUSED INPUT HANDLING
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ICS889831
SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
2.5V LVPECL driver with couple. ICS889831 outputs LVPECL driver. this example, assume traces long transmission line receiver high input impedance without built-in matched load. example 3.3V LVPECL termination shown this schematic. Additional termination approaches shown LVPECL Termination Application Note.
SCHEMATIC EXAMPLE
Figure shows schematic example ICS889831. This schematic provides examples input output handling. ICS889831 input built-in termination resistors. input directly accept various types differential signal without couple. couple termination, ICS889831 also provides VREF_AC proper offset level after couple. This example shows ICS889831 input driven
3.3V 3.3V 3.3V 0.1u
2.5V VREF_AC
ICS889831
LVPECL
82.5
82.5
3.3V 3.3V
3.3V 0.1u 82.5 82.5
FIGURE ICS889831 APPLICATION SCHEMATIC EXAMPLE
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ICS889831
SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS839831. Equations example calculations also provided.
Power Dissipation. total power dissipation ICS889831 core power plus power dissipated load(s). following power dissipation 3.63V, which gives worst case results. NOTE: Please refer Section details calculating power dissipated load.
Power (core)MAX VCC_MAX IEE_MAX 3.63V 60mA 217.8mW Power (outputs)MAX 30.94mW/Loaded Output pair outputs loaded, total power 30.94mW 123.8mW Power Dissipation built-in terminations: Assume input driven 3.3V SSTL driver shown Figure estimated approximately 1.75V drop across nIN. Total Power Dissipation built-in terminations (1.75V)2 30.6mW
Total Power_MAX (3.63V, with outputs switching) 217.8mW 123.8mW 30.6mW 372.2mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C.
equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow linear feet minute multi-layer board, appropriate value 51.5°C/W Table below. Therefore, ambient temperature 85°C with outputs switching 85°C 0.372W 51.5°C/W 104°C. This well below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE
16-PIN VFQFN, FORCED CONVECTION
JAvs. Velocity (Linear Feet Minute)
Multi-Layer PCB, JEDEC Standard Test Boards 51.5°C/W
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Calculations Equations.
ICS889831
SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
purpose this section derive power dissipated into load. LVPECL output driver circuit termination shown Figure
VOUT
FIGURE LVPECL DRIVER CIRCUIT
TERMINATION
calculate worst case power dissipation into load, following equations which assume load, termination voltage
logic high, VOUT
OH_MAX
CC_MAX
0.935V
(VCC_MAX VOH_MAX) 0.935V logic low, VOUT
CC_MAX
OL_MAX
CC_MAX
1.67V
OL_MAX
1.67V
Pd_H power dissipation when output drives high. Pd_L power dissipation when output drives low. Pd_H
OH_MAX
CC_MAX
2V))/R
CC_MAX
OH_MAX
[(2V
CC_MAX
OH_MAX
))/R
CC_MAX
OH_MAX
[(2V 0.935V)/50] 0.935V 19.92mW
Pd_L
OL_MAX
CC_MAX
2V))/R
CC_MAX
OL_MAX
[(2V
CC_MAX
OL_MAX
))/R
CC_MAX
OL_MAX
[(2V 1.67V)/50] 1.67V 11.02mW Total Power Dissipation output pair Pd_H Pd_L 30.94mW
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ICS889831
SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
LEAD VFQFN
Flow (Linear Feet Minute)
Multi-Layer PCB, JEDEC Standard Test Boards
51.5°C/W
TRANSISTOR COUNT
transistor count ICS889831 compatible with SY89831U
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ICS889831
SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
LEAD VFQFN
PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.25 0.30 0.25 1.25 0.50 0.18 0.50 BASIC 1.25 0.80 0.25 Reference 0.30 MINIMUM 0.05 MAXIMUM
Reference Document: JEDEC Publication MO-220
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SKEW, 1-TO-4 DIFFERENTIAL LVPECL-TO-LVPECL/ECL FANOUT BUFFER
Marking 831A 831A Package Lead VFQFN Lead VFQFN Lead "Lead-Free" VFQFN Lead "Lead-Free" VFQFN Shipping Packaging tube 3500 tape reel tube 3500 tape reel Temperature -40°C 85°C -40°C 85°C -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS889831AK ICS889831AKT ICS889831AKLF ICS889831AKLFT
NOTE: that ordered with "LF" suffix number Pb-Free configuration RoHS compliant.
aforementioned trademark, HiPerClockSis trademark Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 889831AK
REV. JUNE 2005
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