SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Full

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SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Full

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ICS87931I
SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Fully integrated LVCMOS/LVTTL outputs, typical output impedance Selectable differential CLK0, nCLK0 LVCMOS/LVTTL clock redundant clock applications Maximum output frequency: 150MHz range: 220MHz 480MHz External feedback "zero delay" clock regeneration Output skew, Same Frequency: 300ps (maximum) Output skew, Different Frequency: 400ps (maximum) Cycle-to-cycle jitter: 100ps (maximum) 3.3V supply voltage -40°C 85°C ambient operating temperature compatible with MPC931
GENERAL DESCRIPTION
ICS87931I voltage, skew LVCMOS/LVTTL Clock Multiplier/Zero Delay HiPerClockSBuffer member HiPerClockSfamily High Performance Clock Solutions from ICS. With output frequencies 150MHz, ICS87931I targeted high performance clock applications. Along with fully integrated PLL, ICS87931I contains frequency configurable outputs external feedback input regenerating clocks with "zero delay".
Selectable clock inputs, CLK1 differential CLK0, nCLK0 support redundant clock applications. CLK_SEL input determines which reference clock used. output divider values Bank controlled DIV_SELA, DIV_SELB DIV_SELC, respectively. test system debug purposes, PLL_SEL input allows bypassed. When LOW, input resets internal dividers forces outputs high impedance state. effective fanout ICS87931I increased utilizing ability each output drive series terminated transmission lines.
ASSIGNMENT
DIV_SELC DIV_SELB DIV_SELA VDDO
VDDA POWER_DN CLK1 CLK0 nCLK0 VDDO EXTFB_SEL CLK_SEL PLL_SEL
ICS87931I
32-Lead LQFP 1.4mm package body package View
CLK_EN0 CLK_EN1 EXT_FB VDDO
BLOCK DIAGRAM
POWER_DN Pullup PLL_SEL Pullup CLK_SEL Pulldown CLK1 Pullup
CLK0
Pullup
PHASE DETECTOR
÷2/÷4 ÷2/÷4
nCLK0 None EXTFB_SEL Pulldown EXT_FB Pullup
DIV_SELA Pulldown DIV_SELB Pulldown CLK_EN0 Pullup CLK_EN1 Pullup DIV_SELC Pulldown Pullup POWER-ON RESET ÷4/÷6 DISABLE LOGIC
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SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Type Description connect. Analog supply pin. Controls frequency being output dividers. LVCMOS LVTTL interface levels. Clock input. LVCMOS LVTTL interface levels. Active Master reset. When logic LOW, internal dividers reset causing outputs low. When logic HIGH, internal dividers outputs enabled. LVCMOS LVTTL interface levels. Non-inver ting differential clock input.
TABLE DESCRIPTIONS
Number 24,25 Name VDDA POWER_DN CLK1 CLK0 nCLK0 CLK_EN0, CLK_EN1 EXT_FB VDDO QC0, PLL_SEL Power Input Input Input Input Input Power Input Input Power Output Input Pullup Pullup Pullup Unused
CLK_SEL EXTFB_SEL QB1, QA1, DIV_SELA DIV_SELB DIV_SELC
Input Input Output Output Input Input Input
Pullup Pullup/ Inver ting differential clock input. VCC/2 default when left floating. Pulldown Power supply ground. Controls enabling disabling clock outputs. Table Pullup LVCMOS LVTTL interface levels. External feedback. When LOW, selects internal feedback. Pullup When HIGH, selects EXT_FB. LVCMOS LVTTL interface levels. Output supply pins. Bank clock outputs.7 typical output impedance. LVCMOS LVTTL interface levels. Selects between reference clocks input Pullup output dividers. When HIGH, selects PLL. When LOW, bypasses PLL. LVCMOS LVTTL interface levels. Clock select input. Selects Phase Detector Reference. Pulldown When LOW, selects CLK0, nCLK0. When HIGH, selects CLK1. LVCMOS LVTTL interface levels. Pulldown External feedback select. LVCMOS LVTTL interface levels. Bank clock outputs.7 typical output impedance. LVCMOS LVTTL interface levels. Bank clock outputs.7 typical output impedance. LVCMOS LVTTL interface levels. Determines output divider values Bank described Table Pulldown LVCMOS LVTTL interface levels. Determines output divider values Bank described Table Pulldown LVCMOS LVTTL interface levels. Determines output divider values Bank described Table Pulldown LVCMOS LVTTL interface levels.
NOTE: Pullup Pulldown refer internal input resistors. table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN ROUT Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Power Dissipation Capacitance (per output) Output Impedance Test Conditions Minimum Typical VDDA, VDDO 3.465V Maximum Units
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SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Function Logic CLK0, nCLK0 Bypass Logic CLK1 Enabled EXT_FB VCO/2 Enable Outputs QA(÷4); QB(÷4); QC(÷6)
TABLE CONTROL INPUT FUNCTION TABLE
Inputs Control CLK_SEL PLL_SEL EXTFB_SEL POWER_DN DIV_SELA:DIV_SELC
Internal Feedback VCO/1 Master Reset/Output QA(÷2); QB(÷2); QC(÷4)
TABLE CLK_ENX FUNCTION TABLE
Inputs CLK_EN1 CLK_EN0 DIV_SELA:DIVSELC Toggle Toggle Toggle Toggle Toggle Toggle Toggle
TABLE FREQUENCY FUNCTION TABLE
Inputs DIV_ SELA DIV_ SELB DIV_ SELC POWER_DN VCO/2 VCO/2 VCO/2 VCO/2 VCO/4 VCO/4 VCO/4 VCO/4
Outputs VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/8 VCO/8 VCO/2 VCO/2 VCO/4 VCO/4 VCO/2 VCO/2 VCO/4 VCO/4 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/4 VCO/8 VCO/8 VCO/4 VCO/6 VCO/4 VCO/6 VCO/4 VCO/6 VCO/4 VCO/6 POWER_DN VCO/8 VCO/12 VCO/8 VCO/12 VCO/8 VCO/12 VCO/8 VCO/12 POWER_DN POWER_DN POWER_DN POWER_DN
TABLE INPUT REFERENCE FREQUENCY
Inputs DIV_ SELA
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OUTPUT FREQUENCY FUNCTION TABLE (INTERNAL FEEDBACK ONLY)
Outputs
DIV_ SELB
DIV_ SELC
POWER_DN
POWER_DN 2/3x 2/3x 2/3x 2/3x
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POWER_DN POWER_DN
POWER_DN POWER_DN 4/3x 4/3x 4/3x 4/3x
ICS87931I
SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
VCO/2 POWER_DN QA(÷2) QB(÷4) QC(÷6)
FIGURE POWER_DN TIMING DIAGRAM
CLK_EN0
CLK_EN1
QA(÷2)
QB(÷4)
QC(÷6) CLK_EN0
CLK_EN1
FIGURE CLK_ENX TIMING DIAGRAMS
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4.6V -0.5V VDDA -0.5V VDDO 0.5V 47.9°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol VDDA VDDO IDDA IDDO Parameter Analog Supply Voltage Output Supply Voltage Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 Typical Maximum 3.465 3.465 Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Input High Voltage DIV_SELA:DIV_SELC, CLK_EN0, CLK_EN1, POWER_DN, nMR, CLK_SEL, PLL_SEL, EXTFB_SEL CLK1, EXT_FB DIV_SELA:DIV_SELC, CLK_EN0, CLK_EN1, POWER_DN, nMR, CLK_SEL, PLL_SEL, EXTFB_SEL CLK1, EXT_FB -20mA 20mA Test Conditions Minimum Typical -0.3 -0.3 Maximum ±120 Units
Input Voltage Input Current
Output High Voltage; NOTE Output Voltage; NOTE
NOTE Outputs terminated with VDDO/2. Parameter Measurement section, 3.3V Output Load Test Circuit.
TABLE DIFFERENTIAL CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Input Current Test Conditions Minimum Typical Maximum ±120 0.85 Units
Peak-to-Peak Input Voltage 0.15 Common Mode Input Voltage; VCMR NOTE NOTE single ended applications, maximum input voltage CLK0, nCLK0 VDDA 0.3V. NOTE Common mode voltage defined VIH.
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SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
Test Conditions Minimum Typical Maximum Units
TABLE INPUT REFERENCE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol Parameter Input Reference Frequency fREF NOTE: Input reference frequency limited divider selection lock range.
TABLE CHARACTERISTICS, VDDA VDDO 3.3V±5%, -40°C 85°C
Symbol fMAX Parameter QAx, Output Frequency Propagation Delay; NOTE QAx, QBx, CLK1 EXT_FB CLK0, nCLK0 EXT_FB Test Conditions fref 50MHz, Same Frequency Different Frequency 0.8V 2.0V -375 -100 -200 Minimum Typical Maximum Units
tsk(o) tjitter(cc)
fVCO tR/tF tLOCK tPZL, tPZH
Output Skew; NOTE Cycle-to-Cycle Jitter NOTE Lock Range Output Rise Time; NOTE Output Duty Cycle Lock Time Output Enable Time; NOTE
Output Disable Time; NOTE tPLZ, tPHZ parameters measured fMAX unless noted otherwise. NOTE Measured from differential input crossing point VDDO/2 output NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VDDO/2. NOTE These parameters guaranteed characterization. tested production. NOTE This parameter defined accordance with JEDEC Standard
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SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
PARAMETER MEASUREMENT INFORMATION
VDDA, VDDO 1.65V±5%
SCOPE LVCMOS
VDDA
nCLK0
Cross Points
CLK0
-1.165V±5%
3.3V OUTPUT LOAD TEST CIRCUIT
DIFFERENTIAL INPUT LEVEL
tsk(o)
jit(cc) tcycle -tcycle
1000 Cycles
OUTPUT SKEW
CYCLE-TO-CYCLE JITTER
0.8V Clock Outputs
0.8V
CLK1
nCLK0 CLK0
OUTPUT RISE/FALL TIME
EXT_FB
VDDO
QAx, QBx,
Pulse Width
PERIOD
PERIOD
tPERIOD
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PROPAGATION DELAY
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QAx, QBx,
tcycle
tcycle
ICS87931I
SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER APPLICATION INFORMATION
WIRING
DIFFERENTIAL INPUT ACCEPT SINGLE ENDED LEVELS
might need adjusted position V_REF center input voltage swing. example, input clock swing only 2.5V 3.3V, V_REF should 1.25V R2/R1 0.609.
Figure shows differential input wired accept single ended levels. reference voltage V_REF VDD/2 generated bias resistors This bias circuit should located close possible input pin. ratio
Single Ended Clock Input V_REF nCLK 0.1u
FIGURE SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
here examples only. Please consult with vendor driver component confirm driver termination requirements. example Figure input termination applies HiPerClockS LVHSTL drivers. using LVHSTL driver from another vendor, their termination recommendation.
DIFFERENTIAL CLOCK INPUT INTERFACE
/nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL other differential signals. Both VSWING must meet VCMR input requirements. Figures show interface examples HiPerClockS CLK/nCLK input driven most common driver types. input interfaces suggested
3.3V 3.3V
3.3V 1.8V
nCLK LVHSTL HiPerClockS LVHSTL Driver
LVPECL
nCLK
HiPerClockS Input
HiPerClockS Input
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN HIPERCLOCKS LVHSTL DRIVER
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V nCLK LVPECL HiPerClockS Input
3.3V 3.3V LVDS_Driv
nCLK
Receiv
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
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SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
sible power pin. pass filter clean analog supply should also located close VDDA possible.
SCHEMATIC EXAMPLE
Figure shows schematic example using ICS87931I. recommended have decouple capacitor power pin. Each decoupling capacitor should located close pos-
DIV_SELC DIV_SELB DIV_SELA
Receiv
3.3V POWER_DN 0.01u
DIV_SELC DIV_SELB DIV_SELA VDDO
3.3V PECL Driv
CLK_EN0 CLK_EN1 EXT_FB VDDO
VDDA POWER_DN CLK1 CLK0 nCLK0
VDDO EXTFB_SEL CLK_SEL PLL_SEL
Logic Input Examples
CLK_EN0 CLK_EN1
Logic Input
Logic Input
Install
ICS87931I
Receiv
Logic Input pins
Install
Logic Input pins
(U1-13)
(U1-21)
(U1-28)
VDD=3.3V
0.1uF
0.1uF
0.1uF
Space (i.e. intstalled)
FIGURE ICS87931I SCHEMATIC EXAMPLE
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SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER
trace delay might restricted available space board component location. While routing traces, clock signal traces should routed first should locked prior routing other signal traces. differential output traces should have same length. Avoid sharp angles clock trace. Sharp angle turns cause characteristic impedance change transmission lines. Keep clock traces same layer. Whenever possible, avoid placing vias clock traces. Placement vias traces affect trace characteristic impedance hence degrade signal integrity. prevent cross talk, avoid routing other signal traces parallel with clock traces. running parallel traces unavoidable, allow separation least three trace widths between differential clock trace other signal trace. Make sure other signal traces routed between clock trace pair. series termination resistors should located close driver pins possible.
following component footprints used this layout example: resistors capacitors size 0603.
POWER
GROUNDING
Place decoupling capacitors close possible power pins. space allows, placement decoupling capacitor component side preferred. This reduce unwanted inductance between decoupling capacitor power caused via. Maximize power ground sizes number vias capacitors. This reduce inductance between power ground planes component power ground pins. filter consisting C11, should placed close VDDA possible.
CLOCK TRACES
TERMINATION
Poor signal integrity degrade system performance cause system failure. synchronous high-speed digital systems, clock signal less tolerant poor signal integrity than other signals. ringing rising falling edge excessive ring back cause system failure. shape trace
Trace
VCCA
Other signals
Trace
FIGURE BOARD LAYOUT ICS87931I
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SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE
Velocity (Linear Feet Minute)
Single-Layer PCB, JEDEC Standard Test Boards Multi-Layer PCB, JEDEC Standard Test Boards 67.8°C/W 47.9°C/W
55.9°C/W 42.1°C/W
50.1°C/W 39.4°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
TRANSISTOR COUNT
transistor count ICS87931I 2942
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PACKAGE OUTLINE SUFFIX
TABLE PACKAGE DIMENSIONS
JEDEC VARIATION DIMENSIONS MILLIMETERS SYMBOL 0.45 -0.05 1.35 0.30 0.09 MINIMUM NOMINAL -1.40 0.37 -9.00 BASIC 7.00 BASIC 5.60 Ref. 9.00 BASIC 7.00 BASIC 5.60 Ref. 0.80 BASIC 0.60 -0.75 0.10 1.60 0.15 1.45 0.45 0.20 MAXIMUM
Reference Document: JEDEC Publication MS-026
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Marking ICS87931BI ICS87931BI Package Lead LQFP Lead LQFP Tape Reel Count tray 1000 Temperature -40°C 85°C -40°C 85°C
TABLE ORDERING INFORMATION
Part/Order Number ICS87931BYI ICS87931BYIT
While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 87931BYI
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SKEW, 1-TO-6 LVCMOS/LVTTL CLOCK MULTIPLIER/ZERO DELAY BUFFER Full

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