EXPRESSJITTER ATTENUATOR Five differential LVDS output pairs diff

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EXPRESSJITTER ATTENUATOR Five differential LVDS output pairs diff

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ICS874005
EXPRESSJITTER ATTENUATOR
Five differential LVDS output pairs differential clock input nCLK supports following input types: LVPECL, LVDS, LVHSTL, SSTL, HCSL Output frequency range: 98MHz 160MHz Input frequency range: 98MHz 128MHz range: 490MHz 640MHz Cycle-to-cycle jitter: 30ps (maximum) 3.3V operating supply bandwidth modes allow system designer make jitter attenuation/tracking skew design trade-offs 70°C ambient operating temperature Available both standard lead-free RoHS compliant packages
GENERAL DESCRIPTION
ICS874005 high performance Differential-to-LVDS Jitter Attenuator designed HiPerClockSuse Express systems. some Express systems, such those found desktop PCs, Express clocks generated from bandwidth, high phase noise frequency synthesizer. these systems, jitter attenuator required attenuate high frequency random deterministic jitter components from synthesizer from system board. ICS874005 bandwidth modes: 200kHz, 400kHz, 800kHz. 200kHz mode will provide maximum jitter attenuation, with higher tracking skew spread spectrum modulation from motherboard synthesizer attenuated. 400kHz provides intermediate bandwidth that easily track triangular spread profiles, while providing good jitter attenuation. 800kHz bandwidth provides best tracking skew will pass most spread profiles, jitter attenuation will good lower bandwidth modes. Because some 2.5Gb serdes have multipliers while others have than multipliers, 874005 mode multiplication mode (i.e. 100MHz input/125MHz output) using F_SEL pins.
BANDWIDTH
BW_SEL Bandwidth: ~200kHz Float Bandwidth: ~400kHz (Default) Bandwidth: ~800kHz
ICS874005 uses Generation FemtoClock technology achive lowest possible phase noise. device packaged Lead TSSOP package, making ideal space constrained applications such Express add-in cards.
BLOCK DIAGRAM
Pulldown F_SELA Pulldown BW_SEL Float ~200kHz Float ~400kHz ~800kHz Pulldown nCLK Pullup
F_SELA (default)
ASSIGNMENT
nQB2 nQA1 VDDO nQA0 BW_SEL VDDA F_SELA VDDO nQB1 nQB0 F_SELB nCLK
nQA0
Phase Detector
640MHz
nQA1
F_SELB (default)
nQB0 nQB1 nQB2
(fixed)
ICS874005
24-Lead TSSOP
4.40mm 7.8mm 0.92mm package body
F_SELB Pulldown Pulldown Pullup
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Package View
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ICS874005
EXPRESSJITTER ATTENUATOR
Type Output Output Power Output Output Input Description Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels. Output supply pins. Differential output pair. LVDS interface levels. Inver ting differential feedback output. Active HIGH Master Reset. When logic HIGH, internal dividers reset causing true outputs (nQx) inver outputs Pulldown (Qx) high. When logic LOW, internal dividers outputs enabled. LVCMOS/LVTTL interface levels. Pullup/ Bandwidth input. Table Pulldown Analog supply pin. Frequency select QAx/nQAx outputs. Pulldown LVCMOS/LVTTL interface levels. Core supply pin. Output enable pins. When HIGH, QAx/nQAx outputs active. When LOW, QAx/nQAx outputs high impedance Pullup state. LVCMOS/LVTTL interface levels. Pulldown Non-inver ting differential clock input. Pullup Inver ting differential clock input. Power supply ground. Output enable pins. When HIGH, QBx/nQBx outputs Pullup active. When LOW, QBx/nQBx outputs high impedance state. LVCMOS/LVTTL interface levels. Frequency select QBx/nQBx outputs. Pulldown LVCMOS/LVTTL interface levels. Differential output pair. LVDS interface levels. Differential output pair. LVDS interface levels.
TABLE DESCRIPTIONS
Number Name nQB2, nQA1, VDDO QA0, nQA0 nFB_OUT
BW_SEL VDDA F_SELA nCLK F_SELB nQB0, nQB1,
Input Power Input Power Input Input Input Power Input Input Output Output
NOTE: Pullup Pulldown refer internal input resistors. Table Characteristics, typical values.
TABLE CHARACTERISTICS
Symbol RPULLUP RPULLDOWN Parameter Input Capacitance Input Pullup Resistor Input Pulldown Resistor Test Conditions Minimum Typical Maximum Units
TABLE OUTPUT ENABLE FUNCTION TABLE
Inputs OEA/OEB Enabled Outputs QAx/nQAx QBx/nQBx Enabled
TABLE BANDWIDTH/PLL BYPASS CONTROL
Inputs PLL_BW Float Bandwidth ~200kHz ~800kHz ~400kHz
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ICS874005
EXPRESSJITTER ATTENUATOR
4.6V -0.5V -0.5V VDDO 0.5V 70°C/W lfpm) -65°C 150°C NOTE: Stresses beyond those listed under Absolute Maximum Ratings cause permanent damage device. These ratings stress specifications only. Functional operation product these conditions conditions beyond those listed Characteristics Characteristics implied. Exposure absolute maximum rating conditions extended periods affect product reliability.
ABSOLUTE MAXIMUM RATINGS
Supply Voltage, Inputs, Outputs, Package Thermal Impedance, Storage Temperature, TSTG
TABLE POWER SUPPLY CHARACTERISTICS, VDDA VDDO 3.3V±5%, 70°C
Symbol VDDA VDDO IDDA IDDO Parameter Core Supply Voltage Analog Supply Voltage Output Supply Voltage Power Supply Current Analog Supply Current Output Supply Current Test Conditions Minimum 3.135 3.135 3.135 Typical Maximum 3.465 3.465 3.465 Units
TABLE LVCMOS/LVTTL CHARACTERISTICS, VDDA VDDO 3.3V±5%, 70°C
Symbol Parameter Input High Voltage OEA, OEB, F_SELA, F_SELB BW_SEL Input Voltage Input Voltage Input High Current OEA, OEB, F_SELA, F_SELB BW_SEL BW_SEL OEA, F_SELA, F_SELB BW_SEL BW_SEL, OEA, F_SELA, F_SELB 3.465V 3.465V 3.465V, 3.465V, -150 VDD/2 Test Conditions Minimum -0.3 VDD/2 Typical Maximum Units
Input Current
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EXPRESSJITTER ATTENUATOR
Test Conditions nCLK nCLK 3.465V 3.465V 3.465V 3.465V -150 0.15 0.85 Minimum Typical Maximum Units
TABLE DIFFERENTIAL CHARACTERISTICS, VDDA VDDO 3.3V±5%, 70°C
Symbol Parameter Input High Current Input Current
Peak-to-Peak Input Voltage
VCMR Common Mode Input Voltage; NOTE NOTE Common mode voltage defined VIH. NOTE single ended applications, maximum input voltage CLK, nCLK 0.3V.
TABLE LVDS CHARACTERISTICS, VDDA VDDO 3.3V±5%, 70°C
Symbol Parameter Differential Output Voltage Magnitude Change Offset Voltage Magnitude Change 1.35 Test Conditions Minimum Typical Maximum Units
TABLE CHARACTERISTICS, VDDA VDDO 3.3V±5%, 70°C
Symbol fMAX tjit(cc) tsk(o) Parameter Output Frequency Cycle-to-Cycle Jitter, NOTE Output Skew; NOTE Output Rise/Fall Time Test Conditions Minimum Typical Maximum Units
Output Duty Cycle NOTE This parameter defined accordance with JEDEC Standard NOTE Defined skew between outputs same supply voltage with equal load conditions. Measured VDDO/2. NOTE These parameters guaranteed characterization. tested production.
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EXPRESSJITTER ATTENUATOR
PARAMETER MEASUREMENT INFORMATION
VDD, VDDO VDDA
3.3V±5% POWER SUPPLY Float
SCOPE
nCLK
LVDS
Cross Points
3.3V LVDS OUTPUT LOAD TEST CIRCUIT
nQA0, nQA1 nQB0:nQB2 QA0, QB0:QB2
DIFFERENTIAL INPUT LEVEL
jit(cc) tcycle -tcycle
1000 Cycles
CYCLE-TO-CYCLE JITTER
Clock Outputs
OUTPUT RISE/FALL TIME
Input
LVDS
VOD/
VOS/
DIFFERENTIAL OUTPUT VOLTAGE SETUP
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OFFSET VOLTAGE SETUP
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tcycle
tcycle
tsk(o)
OUTPUT SKEW
nQA0, nQA1 nQB0:nQB2
QA0, QB0:QB2
PERIOD
PERIOD
100%
OUTPUT DUTY CYCLE/PULSE WIDTH/PERIOD
Input
LVDS
ICS874005
EXPRESSJITTER ATTENUATOR APPLICATION INFORMATION
POWER SUPPLY FILTERING TECHNIQUES
high speed analog circuitry, power supply pins vulnerable random noise. ICS874005 provides separate power supplies isolate high switching noise from outputs internal PLL. VDD, VDDA, VDDO should individually connected power supply plane through vias, bypass capacitors should used each pin. achieve optimum jitter performance, power supply isolation required. Figure illustrates resistor along with .01F bypass capacitor should connected each VCCA pin.
3.3V .01F VDDA .01F
FIGURE POWER SUPPLY FILTERING
WIRING DIFFERENTIAL INPUT ACCEPT SINGLE ENDED LEVELS
Figure shows differential input wired accept single ended levels. reference voltage V_REF VDD/2 generated bias resistors This bias circuit should located close possible input pin. ratio might need adjusted position V_REF center input voltage swing. example, input clock swing only 2.5V 3.3V, V_REF should 1.25V R2/R1 0.609.
Single Ended Clock Input V_REF nCLK 0.1u
FIGURE SINGLE ENDED SIGNAL DRIVING DIFFERENTIAL INPUT
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EXPRESSJITTER ATTENUATOR
here examples only. Please consult with vendor driver component confirm driver termination requirements. example Figure input termination applies HiPerClockS LVHSTL drivers. using LVHSTL driver from another vendor, their termination recommendation.
3.3V 3.3V
DIFFERENTIAL CLOCK INPUT INTERFACE
/nCLK accepts LVDS, LVPECL, LVHSTL, SSTL, HCSL other differential signals. Both VSWING must meet VCMR input requirements. Figures show interface examples HiPerClockS CLK/nCLK input driven most common driver types. input interfaces suggested
3.3V 1.8V
nCLK LVHSTL HiPerClockS LVHSTL Driver
LVPECL
nCLK
HiPerClockS Input
HiPerClockS Input
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN HIPERCLOCKS LVHSTL DRIVER
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
3.3V 3.3V 3.3V nCLK LVPECL HiPerClockS Input
3.3V 3.3V LVDS_Driv
nCLK
Receiv
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVPECL DRIVER
FIGURE HIPERCLOCKS CLK/NCLK INPUT DRIVEN 3.3V LVDS DRIVER
RECOMMENDATIONS UNUSED INPUT OUTPUT PINS INPUTS: OUTPUTS:
LVCMOS CONTROL PINS: control pins have internal pull-ups pull-downs; additional resistance required added additional protection. resistor used. LVDS unused LVDS output pairs either left floating terminated with across. they left floating, recommend that there trace attached.
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ICS874005
EXPRESSJITTER ATTENUATOR
receiver input. multiple LVDS outputs buffer, only partial outputs used, recommended terminate un-used outputs.
3.3V
LVDS DRIVER TERMINATION
general LVDS interface shown Figure differential transmission line environment, LVDS drivers require matched load termination across near
3.3V LVDS_Driv
Differiential Transmission Line
FIGURE TYPICAL LVDS DRIVER TERMINATION
SCHEMATIC EXAMPLE
Figure shows example ICS874005 application schematic. this example, device operated VDD=3.3V. decoupling capacitor should located close possible power pin. input driven 3.3V LVPECL driver.
3.3V
VDDO 3.3V
nQB2 nQA1 VDDO nQAO BW_SEL VDDA F_SELA VDDO nQB1 nQB0 F_SELB nCLK
10uF
0.01u
BW_SEL F_SELA
F_SELB
874005_tssop24 nCLK
LVPECL Driv
(U1:23)
(U1:11)
(U1:4)
10uf
.1uf
.1uf
.1uf
FIGURE ICS874005 SCHEMATIC EXAMPLE
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ICS874005
EXPRESSJITTER ATTENUATOR POWER CONSIDERATIONS
This section provides information power dissipation junction temperature ICS874005. Equations example calculations also provided. Power Dissipation. total power dissipation ICS874005 core power plus power dissipated load(s). following power dissipation 3.3V 3.465V, which gives worst case results.
Power (core)MAX VDD_MAX (IDD_MAX IDDA_MAX) 3.465V (85mA 15mA) 346.5mW Power (outputs)MAX VDDO_MAX IDDO_MAX 3.465V 115mA 398.48mW
Total Power_MAX 346.5mW 398.48mW 745mW
Junction Temperature. Junction temperature, temperature junction bond wire bond directly affects reliability device. maximum recommended junction temperature HiPerClockSdevices 125°C. equation follows: Pd_total Junction Temperature Junction-to-Ambient Thermal Resistance Pd_total Total Device Power Dissipation (example calculation section above) Ambient Temperature order calculate junction temperature, appropriate junction-to-ambient thermal resistance must used. Assuming moderate flow linear feet minute multi-layer board, appropriate value 63°C/W Table below. Therefore, ambient temperature 70°C with outputs switching 70°C 0.745W 63°C/W 117°C. This below limit 125°C. This calculation only example. will obviously vary depending number loaded outputs, supply voltage, flow, type board (single layer multi-layer).
TABLE THERMAL RESISTANCE 24-LEAD TSSOP, FORCED CONVECTION
Velocity (Linear Feet Minute)
Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W
63°C/W
60°C/W
NOTE: Most modern designs multi-layered boards. data second pertains most designs.
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ICS874005
EXPRESSJITTER ATTENUATOR RELIABILITY INFORMATION
TABLE JAVS. FLOW TABLE LEAD TSSOP
Velocity (Linear Feet Minute)
Multi-Layer PCB, JEDEC Standard Test Boards 70°C/W
63°C/W
60°C/W
TRANSISTOR COUNT
transistor count ICS874005 1206
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EXPRESSJITTER ATTENUATOR
PACKAGE OUTLINE SUFFIX
LEAD TSSOP
TABLE PACKAGE DIMENSIONS
SYMBOL 0.45 -4.30 0.65 BASIC 0.75 0.10 -0.05 0.80 0.19 0.09 7.70 6.40 BASIC 4.50 Millimeters Minimum 1.20 0.15 1.05 0.30 0.20 7.90 Maximum
Reference Document: JEDEC Publication MO-153
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ICS874005
EXPRESSJITTER ATTENUATOR
TABLE ORDERING INFORMATION
Part/Order Number ICS874005AG ICS874005AGT ICS874005AGLF ICS874005AGLFT Marking ICS874005AG ICS874005AG Package Lead TSSOP Lead TSSOP Lead "Lead-Free" TSSOP Lead "Lead-Free" TSSOP Shipping Packaging tube 2500 tape reel tube 2500 tape reel Temperature 70°C 70°C 70°C 70°C
NOTE: that ordered with "LF" suffix number Pb-Free configuration RoHS complaint.
aforementioned trademarks, HiPerClockS FemtoClock trademarks Integrated Circuit Systems, Inc. subsidiaries United States and/or other countries. While information presented herein been checked both accuracy reliability, Integrated Circuit Systems, Incorporated (ICS) assumes responsibility either infringement patents other rights third parties, which would result from use. other circuits, patents, licenses implied. This product intended normal commercial industrial applications. other applications such those requiring high reliability other extraordinary environmental requirements recommended without additional processing ICS. reserves right change circuitry specifications without notice. does authorize warrant product life support devices critical medical instruments. 874005AG
REV. JANUARY 2006

EXPRESSJITTER ATTENUATOR Five differential LVDS output pairs diff

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