Flow-Through Architecture Optimizes Layout Center-Pin Configurations M

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Flow-Through Architecture Optimizes Layout Center-Pin Configurations M

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54AC11027, 74AC11027 TRIPLE 3-INPUT POSITIVE-NOR GATES
Flow-Through Architecture Optimizes Layout Center-Pin Configurations Minimize High-Speed Switching Noise EPIC (Enhanced-Performance Implanted CMOS) 1-µm Process 500-mA Typical Latch-Up Immunity 125°C Package Options Include Plastic Small-Outline Packages, Ceramic Chip Carriers, Standard Plastic Ceramic 300-mil DIPs
54AC11027 PACKAGE 74AC11027 PACKAGE (TOP VIEW)
description
These devices contain three independent 3-input gates. They perform Boolean functions positive logic. 54AC11027 characterized operation over full military temperature range 55°C 125°C. 74AC11027 characterized operation from 40°C 85°C.
FUNCTION TABLE (each gate) INPUTS OUTPUT
54AC11027 PACKAGE (TOP VIEW)
internal connection
logic symbol
logic diagram (positive logic)
This symbol accordance with ANSI/IEEE 91-1984 Publication 617-12. numbers shown packages. EPIC trademark Texas Instruments Incorporated.
PRODUCTION DATA information current publication date. Products conform specifications terms Texas Instruments standard warranty. Production processing does necessarily include testing parameters.
Copyright 1993, Texas Instruments Incorporated
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DALLAS, TEXAS 75265
54AC11027, 74AC11027 TRIPLE 3-INPUT POSITIVE-NOR GATES
absolute maximum ratings over operating free-air temperature range (unless otherwise noted)
Supply voltage range, Input voltage range, (see Note Output voltage range, (see Note Input clamp current, VCC) Output clamp current, VCC) Continuous output current, VCC) Continuous current through Storage temperature range 65°C 150°C
Stresses beyond those listed under "absolute maximum ratings" cause permanent damage device. These stress ratings only functional operation device these other conditions beyond those indicated under "recommended operating conditions" implied. Exposure absolute-maximum-rated conditions extended periods affect device reliability. NOTE input output voltage ratings exceeded input output clamp-current ratings observed.
recommended operating conditions
54AC11027 Supply voltage High-level input voltage Low-level input voltage Input voltage Output voltage High-level output current Low-level output current Input transition rise fall rate Operating free-air temperature 3.15 3.85 1.35 1.65 74AC11027 3.15 3.85 1.35 1.65 UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
54AC11027, 74AC11027 TRIPLE 3-INPUT POSITIVE-NOR GATES
electrical characteristics over recommended operating free-air temperature range (unless otherwise noted)
PARAMETER TEST CONDITIONS GND, 0.36 0.36 0.36 1.65 1.65 2.58 3.94 4.94 25°C 54AC11027 3.85 3.85 0.44 0.44 0.44 74AC11027 2.48 UNIT
more than output should tested time, duration test should exceed
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER tPLH tPHL FROM (INPUT) (OUTPUT) 25°C 10.9 54AC11027 11.7 12.9 74AC11027 10.9 UNIT
switching characteristics over recommended operating free-air temperature range, (unless otherwise noted) (see Figure
PARAMETER tPLH tPHL FROM (INPUT) (OUTPUT) 25°C 54AC11027 74AC11027 UNIT
operating characteristics, 25°C
PARAMETER Power dissipation capacitance gate TEST CONDITIONS UNIT
POST OFFICE 655303
DALLAS, TEXAS 75265
54AC11027, 74AC11027 TRIPLE 3-INPUT POSITIVE-NOR GATES
PARAMETER MEASUREMENT INFORMATION
From Output Under Test (see Note Output Input (see Note tPHL tPLH LOAD CIRCUIT VOLTAGE WAVEFORMS
NOTES: includes probe capacitance. Input pulses supplied generators having following characteristics: MHz, outputs measured time with input transition measurement.
Figure Load Circuit Voltage Waveforms
POST OFFICE 655303
DALLAS, TEXAS 75265
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Copyright 1998, Texas Instruments Incorporated

Flow-Through Architecture Optimizes Layout Center-Pin Configurations M

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