PM3351 ELAN 1x100 2-PORT 10/100 MBIT/S ETHERNET SWITCH PM335
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PM3351 ELAN 1x100
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PM3351 Elan 1x100
2-Port Fast Ethernet Switch Reference Design
PROPRIETARY CONFIDENTIAL
ADVANCE Issue April 1998
PMC-Sierra, Inc.
8555 Baxter Place Burnaby, Canada .415.6000
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PM3351 ELAN 1x100
2-PORT 10/100 MBIT/S ETHERNET SWITCH
CONTENTS REFERENCES OVERVIEW FUNCTIONAL DESCRIPTION Feature List PM3351 Elan 1x100 IMPLEMENTATION DESCRIPTION 100M Fast Ethernet Switch Circuitry Common Components Configuration Resistors Configuration Resistor Functions INTERFACE DESCRIPTION. RJ45 Definition.16 Expansion Interface LAYOUT DESCRIPTION. Power Ground Plane Isolation.20 Component Placement.22 APPENDIX DESIGN CONSIDERATIONS Power Supply Decoupling Unused CMOS Inputs Additional Layout Considerations Component Selection APPENDIX BILL MATERIALS CONTACTING PMC-SIERRA ATTACHMENT SCHEMATICS
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REFERENCES PMC-Sierra PM3351 Datasheet, Issue (July 1997) ISO/IEEE 8802.3 CSMA/CD Local Area Networking Specification (1993) IEEE 802.3u Parameters, Physical Layer, Medium Attachment Units Repeater Mbit/s Operation (January 1995) IEEE 802.3x Specification 802.3 Full Duplex Operation (September 1996) National Semiconductor DP83840A Datasheet (1996) National Semiconductor DP83223 Datasheet (December 1996) National Semiconductor 100BASE-TX Unmanaged Repeater Design Recommendations (Appnote 1010) (October 1995) National Semiconductor 10/100 Ethernet Common Magnetics Using DP83840A DP83223 (April 1996)
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OVERVIEW This document describes implementation 2-port Fast Ethernet Switch based PMC-Sierra's PM3351 Elan 1x100 Standard Product. This reference design embodies PMC-Sierra's guidelines suggestions designing Ethernet switch. This reference design intended operate modes: Stand-alone mode, where this design provides complete functionality 2-port Fast Ethernet Switch, This design interface with other switch reference designs through expansion backplane. combined with 24-port PM3350 ELAN 8x10 10Mbit/s Ethernet Switch reference design form 24+2 switch another 2-port Fast Ethernet Switch Reference design build 4-port Mbit/s switch. addition PM3351 Elan 1x100 devices, this reference design incorporates onboard SRAM, EPROM, oscillators, 100BaseT chips (National DP83840A, DP83223 chipset), 100BaseT magnetics, RJ45 jacks, status LEDs other miscellaneous devices complete switch design. complete list components found Bill Materials. Functional Description gives list features this reference design. Implementation Description provides detailed description major components which found schematics (included Attachment Interface Description lists RJ45 expansion definitions. Layout Description describes component placement guidelines general layout considerations. readers interested more additional in-depth considerations this reference design, Design Consideration section provides many tips guidelines high-speed circuit board design component selection. Finally, Bill Materials schematics included end.
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FUNCTIONAL DESCRIPTION block diagram this reference design shown Figure following summary features offered this switch. Feature List Complete 2-port full-duplex 100BASE-T non-blocking switching Operates completely stand-alone switch, conjunction with other switch cards using expansion bus. combined with 24-port PM3350 ELAN 8x10 10Mbit/s Ethernet Switch reference design form 24+2 switch another 2-port Fast Ethernet Reference design build 4-port Mbit/s switch Supports system bandwidth Mbit/s using expansion Filters switches packets using locally-maintained database1 Performs packet switching, IEEE 802.1d compliant transparent bridging, both Store-and-forward mode with full check.
Refer System Configuration determine number addresses supported firmware programmed into EPROM. system configured support addresses. PM3351 datasheet.
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Fig. Reference Design System Block Diagram
System Clocks
Expansion
Arbiter
1x100 3351
DP83840 10/100M
1x100 3351
DP83840 10/100M
DP83223 100BAS E-TX Transceiver
DP83223 100BAS E-TX Transceiver
agnetics
Status LEDs Status LEDs
agnetics
RJ45
RJ45
Port
Port
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PM3351 Elan 1x100 Fig. Block Diagram
Embedded
Cache Cache
Expansion
Interface
Transmit Channel Logic Receive Controller
FIFO FIFO
100BaseT Transmit 100BaseT Transmit
100BaseT
Expansion Registers
External memory Interface
SRAM EPROM
PM3351 Overview PM3351 low-cost, highly integrated stand-alone single-chip switching device 10/100 Mbit/s Ethernet (IEEE 802.3u, IEEE 802.12) switching bridging applications. device supports processing required switching Ethernet packets between on-chip Medium Independent Interface (MII) port built-in Gbit/s expansion port, which other PM3351 devices attached. addition, PM3351 directly compatible with PM3350, 8-port 10Mbps Ethernet switch chip. PM3351 used with PM3350 create non-blocking switches configurations shown table below, with each Mbit/s port configured full-duplex each Mbit/s port configured half-duplex initialization, switching, interfacing, management statistics gathering functions performed PM3351, minimizing size cost switching
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with more Mbit/s ports. Switch configuration management performed either remotely (in-band), on-chip SNMP MIB. PM3351 chip contains required elements high-performance Ethernet switch: interface connection physical-layer transceivers, MAC-layer processing logic, buffer FIFOs, high-speed engine fast packet transfers, local memory interface external buffer memory, fully-compatible master slave unit modular expansion, powerful switch processing unit that implements switching bridging functions. only additional components required each Mbit/s switch port compliant transceiver (supports 100BaseTX/FX, 100BaseT4,100BaseT2, future 802.3-compliant 100Mbit PHYs), passive line interface devices, bank external memory system clock. amount external memory extended Mbytes SRAM, depending amount packet buffering required number addresses supported. Switch configuration information provided PM3351 using single non-volatile device.
Table
Non-Blocking Configurations PM3351 Devices Switch Port Configuration 64x10 56x10 1x10/100 48x10 1x10/100 40x10 2x10/100 32x10 2x10/100 24x10 2x10/100 16x10 3x10/100 8x10 4x10/100 4x10/100
PM3350 Devices
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IMPLEMENTATION DESCRIPTION schematics 2-Port Elan 1x100 Reference Design, Revision included Attachment core functionality consists identical2 "ports" "slices" 100M circuitry, each using PM3351, SRAM memory, physical interface components. Additionally, board contains EPROM code download, Arbiter, connectors, timing sources miscellaneous "glue" circuitry. Functional blocks described below. major components described slice 100M circuitry. same description apply both slices: Port Sheets Port Sheets
component ID's listed parenthesis after each component name.
Note that component designated PRES schematic indicates signal either pulled-up, pulled-down, left unconnected (floating).
2Identical
except EPROM which only PM3351 connected
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100M Fast Ethernet Switch Circuitry PM3351 (SH3), (SH6) PM3351 Elan 1x100 chip forms core each slice 100M switch circuitry. SRAM U11, U12, U21, (SH4); U19, (SH7) Four, 128K 8-bit, 15ns SRAM chips (512K bytes total) used provide storage each PM3351. SRAM used address tables, packet buffer storage, data structures required during operation. EPROM (SH2) board uses 256K 8-bit EPROM PM3351 boot code, switching code, SNMP code (when available), special function code (e.g., custom display, aging, backpressure, VLAN, etc.). EPROM must faster. Code downloaded into first PM3351 device [U14], which turn will download code other PM3351 device [U9]. application code image does include SNMP management, then smaller 128K 8-bit device adequate. This device socket ease replacement. 10/100M Physical Layer Device (SH5), (SH8) National Semiconductor DP83840A Physical Layer device 10BASE-T 100BASE-Tx Ethernet systems. contains layer functions, supports full-duplex operation. features Media Independent Interface (MII) which used connect PM3351 device, interfaces with sublayer through DP83223 Twister Pair Transceiver. comes 100-pin PQFP package.
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U15/U6 Configuration Interface:
SIGNAL NAME
DESCRIPTION
CONFIG
SETTING
Equalization Resistor
R83/R4
Open
cable lengths 100m cable lengths 100m Autonegotiation enabled Autonegotiation enabled
Extended Cable Resistor
R95/R3
Open
Operating Mode
R147/R67
Open
Operating Mode
R96/R7
Open
Please refer current issue National Semiconductor Databook additional information describing this 10/100M physical layer device. Transceiver (SH5), (SH8) National Semiconductor DP83223 TWISTER transceiver interfaces with meters UTP5 cable 100M data rate. compliant with ANSI X3T12 TP-PMD standard IEEE 802.3 100BASE-TX standard. comes 28-pin PLCC package. Note that MLT-3 encoding used (100BASE-TX). U17/U7 Configuration Interface:
SIGNAL NAME EQSEL
DESCRIPTION
CONFIG
SETTING
Equalization Select
R151/R73
Open
Adaptive Equalization Mode
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Please refer current issue National Semiconductor Databook information describing this Twister Pair Transceiver device. Line Interface Circuitry line interface circuitry consists transformers, connectors passive networks necessary interface National DP83223A transceiver cables carrying Ethernet BaseT signals. This circuitry reflects recommendations National Semiconductor Databook associated application notes. Please refer Design Considerations section details this circuitry. Transformers (SH8), (SH5) Single 100-BASE-TX transformers with common mode chokes used this reference design. Dual directional transformers used save space cost, given that crosstalk between transmit receive acceptable (better than 35dB). Please refer component selection section Appendix vendor information. RJ45 Connectors (SH8), (SH5) There RJ45 connectors connection Ethernet BaseT segments switch. Shielded RJ45 connectors used minimize electromagnetic interference (EMI). These connectors configured "hub" connection. Please refer Interface Description section details definition. Layer LEDs D10, D11, (SH5); (SH8); (SH4) There five LEDs port, arranged horizontally next featured port. They indicate status information shown following table:
D1/D8
Full Duplex LED: Indicates Full Duplex mode status Mbit/s operation. Inacitve Full Duplex Mbit/s mode. Collision LED: Indicates presence collision activity Mbit/s Mbit/s operation. This meaning Full Duplex operation. Receive LED: Indicates presence receive activity.
D2/D9
D3/D10
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D4/D11 D5/D12
Transmit LED: Indicates presence transmit activity. Link LED: Indicates Good Link status.
Status LEDs D13-D26 (SH4/7) Status LEDs which used RISC controller indicate system status. Common Components System Clocks (SH2) system clock PM3351 devices sourced from crystal oscillator [U8]. 74AC540 buffer [U5] used drive clock signal each chip. clock sourced from crystal oscillator [U4]. 74AC540 also used drive clock signal each PM3351 arbiter. Both oscillators have sockets ease replacement. Sockets omitted lower cost manufacturing. Edge Connector Termination Resistors R164-R171 (SH3) This resistors pull-up control signals ensure that they contain stable values when agent actively driving bus. This includes FRAME, TRDY, IRDY, INTA, DEVSEL, STOP, SERR, PERR. Connector (SH2) This edge connector connects onboard expansion port backplane. used interface this board other reference designs such 24-port Ethernet Switch using PM3350. When this reference design operating stand-alone mode, this edge connector used. Please refer Interface Description section definitions.
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Note that this connection compliant specification, v2.1. This because redefinition required arbitration (see Arbiter description), fact that there more than "PCI device load" single board attached bus. Arbiter (SH2) Arbiter implements simple round-robin algorithm control access PM3351 devices onto expansion bus. This arbiter implemented 44-PLCC CPLD (Xilinx XC9572). Please contact PMC-Sierra, Ethernet Division, information implementation arbiter. This arbiter should removed when this reference design board interfaced 24-port Ethernet Switch reference design. this case, arbiter 24port reference design assumes control over bus. Because this, additional REQ/GNT signals PM3351 devices routed through backplane, which accomplished re-defining some unused pins connector. This device socket ease replacement. Headers Jumpers
(SH2)
REQ0/1 Enable: connected, PM3351 request appears edge connector processing external arbiter. This header connected only when another reference design connected this board, this board configured slave board (i.e. arbiter populated, arbiter external board control bus). GNT0/1 Enable: connected, grants received from external arbiter over edge connector enabled PM3351 interface. This header connected only when another reference design connected this board, this board configured slave board (i.e. arbiter populated, arbiter external board control bus). Clock Source: clock sourced from on-board oscillator [U4], from edge connector [P1]. Connecting this header selects on-board oscillator. Jumper header when board being operated stand-alone, board clock source another reference design. Port ERST Enable: Connect header implement watchdog capability port PM3351. watchdog timeout will invoke system reset.
(SH2)
(SH2)
(SH3)
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(SH2) JP8-2 (SH2) JP9-2 (SH2) JP10 (SH2)
Reset Select: Jumper board part multi-board system. Clock Test Point System Clock Test Point Control Signals Test Points: 1=GND, 2=FRAME, 3=IRDY, 4=TRDY, 5=DEVSEL, 6=GND. PM3351 Debug Pins PM3351 IDSEL: 1-2. Selects Address Jumper board used with PM3350 reference board, board part PM3351 system designated slave/slave board. 2-3. Selects Address Jumper board part PM3351 system designated master/slave board.
JP11 (SH3) JP12 (SH3)
JP13 (SH4)
Bank 1-2. Jumper PM3351 (bank slave device. 2-3. Jumper PM3351 (bank master device.
JP14 (SH4)
PM3351 Reserved Bit: 1-2. Default
JP15 (SH4)
PM3351 CHIPID1: 1-2. Jumper PM3351 configured slave device. 2-3. Jumper PM3351 configured master device.
JP16 (SH6) JP17 (SH6)
PM3351 Debug Pins PM3351 IDSEL: 1-2. Selects Address Jumper board used with PM3350 reference board, board part PM3351 system designated slave/slave board. 2-3. Selects Address Jumper board part PM3351 system designated master/slave board, operated standalone mode.
JP18 (SH7)
PM3351 Reserved Bit: 1-2. Default.
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JP19 (SH7)
PM3351 CHIPID1: 1-2. Jumper PM3351 configured slave also slave. 2-3. Jumper PM3351 configured slave master.
Reset Debounce Circuit (SH2) Dallas DS1233 "EconoReset" device used provide power-up reset reset debounce function. monitors status power supply (Vcc) will automatically assert reset when threshold crossed. Reset maintained active minimum time 350ms. Reset Switch (SH2) This switch master reset reference design board. Power Supply Connectors JK1, (SH9) This reference design board requires 5.0V power supply capable providing minimum Amps. Configuration Resistors Each "slice" 100M port circuitry uses bank 4.7K resistors configure PM3351 after reset. Configuration Resistors provide default pull-up/down values local memory data bus, which read PM3351 after reset. resistor functions default values given below.
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Function PCIRUN RISCRUN Reserved IMDIS PCI3V FIRM CHIPID CHIPID CHIPID CHIPID RTCDIV RTCDIV RTCDIV RTCDIV RTCDIV RTCDIV MXSEL1 MXSEL0 MSLO MDCAS MTYPE3 MTYPE3 MTYPE3 MTYPE2 MTYPE2 MTYPE2 MTYPE1 MTYPE1 MTYPE1 MTYPE0 MTYPE0 MTYPE0
Bank R197 R172 R198 R199 R200 R201 R202 R203 R173 R204 R205 R206 R207 R208 R209 R210 R211 R212 R213 R214 R215 R216 R217 R218 R219 R220 R221 R222 R223 R224 R225 R226
Value JP13 JP14 JP15
Bank R250 R251 R252 R253 R254 R255 R256 R257 R175 R258 R259 R260 R261 R262 R263 R264 R265 R266 R267 R268 R269 R270 R271 R272 R273 R274 R275 R276 R277 R278 R279 R280
Value JP18 JP19
Data
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Configuration Word Functions PCIRUN: This input PM3351 selects default operating mode interface. logic device responds memory space accesses master. logic device disabled from responding memory space accesses will master. RISCRUN: logic halts Switch Processor upon reset, effectively placing PM3351 into stand-by mode. IMDIS: Internal memory disable, which controls bootcode fetch location. High boot strapped from external local memory, boot strapped from on-chip ROM. PCI3V: This selects interface signaling environment. High 3.3V, CHIPID: These 4-bits determine chip's address. This used second nibble (bits PM3351's address space bus. nibble (bits initialized zero (0), software control required. RTCDIV: These 6-bits determine setting Real-Time Clock Divisor. MTYPE Configuration These twelve resistors PM3351 divided into four groups three bits each. Each combination selects eight different memory types. These bits read data during start-up, tell RISC access memory. Each group corresponds four banks memory. reference design board: Bank configured type SRAM, Bank configured type EPROM (unused) Bank configured type EPROM Bank configured type EPROM (LED select)
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MTYPE Reserved Reserved SRAM Reserved Reserved EPROM DRAM
Memory Type
Speed
DRAM/Fast Page DRAM
memory configuration this reference design four 128K 8bit, 15ns SRAM chips PM3351.
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INTERFACE DESCRIPTION This section detailed description physical interfaces this reference design, which include RJ45 connectors, Expansion connector. RJ45 Definition Each RJ45 connectors reference design have following definition.
Signal Name Receive Pair UTP5 Cable. Type Description Transmit Pair UTP5 Cable.
pins defined such that port looks like port. This allows direct cable connection from switch port computer. crossover cable needed connect switch port another switch port.
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Expansion Interface
Signal Name AD[31:0] Type Description Multiplexed address/data bus, used host PM3351 transfer addresses data.
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CBE[3:0] Address/data/command parity, supplies even parity computed over AD[31:0] CBE[3:0] lines during valid data phases; sampled (when PM3351 acting target) driven (when PM3351 acts initiator) clock edge after respective data phase. transaction delimiter (framing signal); HIGH-to-LOW transition this signal indicates that transaction beginning (with address phase); LOW-to-HIGH transition indicates that next valid data phase will currently ongoing transaction. Transaction Initiator (master) ready, used transaction initiator master indicate that ready data transfer. valid data phase ends with data transfer when both IRDY* TRDY* sampled asserted same clock edge. Transaction Target ready, used transaction target slave indicate that ready data transfer. valid data phase ends with data transfer when both IRDY* TRDY* sampled asserted same clock edge. Transaction termination request, driven current target slave abort, disconnect retry current transfer. Command/Byte-Enable lines. These lines supply command during address phase byte enables during data phase each transaction.
FRAME*
IRDY*
TRDY*
STOP*
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DEVSEL*
Device acknowledge: driven target indicate initiator that address placed AD[31:0] lines, together with command CBE[3:0] lines, been decoded accepted valid reference target's address space. Once asserted, held asserted until FRAME* de-asserted; otherwise, indicates conjunction with STOP* TRDY*) target-abort. Device identification (slot) select. Assertion IDSEL signals PM3351 that being selected configuration space access. requests. They only used when expansion used interface with another board, such 24-port Ethernet Reference Design. specification defines only Request signal. this case, extra Request signals occupy following unused pins connector: -12V (REQ1*), TRST* (REQ0*)
IDSEL
REQ* REQ1* REQ0*
GNT* GNT1* GNT0*
grant from arbiter; this indicates PM3351 that been granted control bus. These only used when expansion used interface with another board, such 24-port Ethernet Reference Design. specification defines only Grant signal. this case, extra Grant signals occupy following unused pins connector: INTB* (GNT1*), INTC* (GNT0*)
INT* PERR*
Interrupt request. This signals interrupt request host. parity error signal, asserted PM3351 slave, sampled PM3351 master, indicate parity error AD[31:0] CBE[3:0] lines. System error, used PM3351 indicate central resource that there parity error AD[31:0] CBE[3:0] lines during address phase. clock; supplies clock signal PM3351. reset (system reset). Performs hardware reset PM3351 associated peripherals when asserted.
SERR*
PCICLK RST*
Note: indicates active-low signals, which corresponds used specification. numbers listed first
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LAYOUT DESCRIPTION Figure shows layout this reference design. purpose this diagram show Ground plane isolation scheme order minimize noise-coupling between various portions circuits, EMI. This diagram shows only approximate placement components. layout meant guarantee correct operation performance design. particular, vendor recommendations should consulted. Here, power plane cuts based recommendations found National Semiconductor 100BASE-TX Unmanaged Repeater Design appnote (Appnote 1010, October 1995). Power Ground Plane Isolation There three islands planes shown Fig. each "slice" 100M port circuitry. plane cuts isolate Analog high-speed (125Mbps 4B/5B encoding) circuitry traces DP83223 magnetics, high-speed (125M PECL 4B/5B encoding) digital circuitry traces DP83223 DP83840A, rest lower-speed (max. 50MHz) digital circuitry board. Power into Analog PECL planes ferrite beads (inductors). Important signals DP83223 DP83840A isolated specific plane shown figure. These islands same plane with minimum separation between adjacent islands. There islands Ground planes shown entire board. Ground plane cuts isolate "cable" side from "switch". Chassis ground covers "cable" side magnetics RJ45 connector, whereas System ground covers rest board. Chassis ground used provide quiet ground plane UTP5 connection minimize into RJ45 connection. single System ground plane used minimize impedance, thus reducing ground noise. System ground plane overlaps islands, which minimizes fringing fields edges islands. connect chassis ground island system's chassis ground, mounting screws used chassis ground contact points they make mechanical contact with mounting bracket which turn connects mechanically chassis. Furthermore, shield RJ45 connector should connected chassis ground island order effective.
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Fig. Board Layout
RJ45 Analog
83223
RJ45 Plane Analog
83223
PECL
PECL
83840
Digital
83840 Common System Circuit ELAN 1x100 PM3351
Digital
ELAN 1x100 PM3351
Edge Connector
TDTD+
RDRD+
TXOTX+
PMIDPMID+
DP83223 Analog
SDSD+
PECL
Digital
DP83840
Digital
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Component Placement overall placement strategies components are: Place analog circuitry away from digital circuitry. Keep analog transmit side components (mostly passive) separate from analog receive side components. Keep transformer close RJ45 possible that commonmode noise riding traces coming from RJ45 will suppressed transformer before radiate. With adequate bypassing decoupling digital side digital ground noise will propagate analog section. Furthermore, additional filtering with ferrite beads analog power supply reduces noise seen analog side, attenuates noise generated analog side. Local decoupling capacitors also placed near analog digital power supply pins.
addition, following guidelines used: source termination resistors placed near outputs load termination resistors placed near inputs. pull down resistors placed near output pins. decoupling capacitors placed near power supply pins. bypassing capacitors analog side placed near ferrite beads. bulk decoupling capacitors (22uF) placed near power entrance.
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APPENDIX DESIGN CONSIDERATIONS those interested more additional in-depth considerations this reference design, this Design Consideration section provides many tips guidelines highspeed circuit board design component selection. Power Supply Decoupling Power pins Analog power supply pins DP83840A DP83223 devices requires special attention filter noise. power pins PECL plane Analog plane, 0.01uF 0.1uF bypassing capacitor placed near each power pin, together with 22uF bulk decoupling capacitors entire plane. 0.01uF 0.1uF decoupling capacitor also placed close each digital power possible. Ferrite beads used digital power pins because they series inductance which limits current that required recharge decoupling capacitors. noise attenuation required, small surface mount series resistor ohms) added series with power pin. Fig. Power Supply Decoupling
(place close possible) Analog plane Analog power decoupling PECL power decoupling PECL plane (place close possible) Digital plane (place close possible) PECL plane Ferrite bead 0.01uF Digital Plane 22uF 0.01uF 22uF Analog power 0.01uF
PECL power 0.01uF Digital power 0.1uF Analog plane
Digital power decoupling Analog power plane decoupling
PECL power plane decoupling
Ferrite bead 22uF
PECL plane 0.01uF
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Power planes Analog circuitry draws mostly constant current requires little switching current. Therefore, ferrite beads used isolate Analog plane from noisy PECL/Digital plane. Bulk decoupling provided Digital islands. 22uF electrolytic capacitors used this purpose, they placed entrance each Digital island. addition, 22uF capacitors placed after ferrite bead that feeds power PECL islands. Please consult National Semiconductor datasheets more detail power supply decoupling devices. Unused CMOS Inputs "Floating" CMOS inputs (those that left unconnected) switch unpredictably, causing unwanted noise power consumption. Therefore, unused inputs should connected their inactive state: ground power rail. Unused bidirectionals should "pulled" through series resistor (4.7k greater) avoid shortcircuits occurring bi-directionals erroneously configured outputs. Additional Layout Considerations High-speed Traces High speed traces should kept short possible general. This applies traces with high-speed data between RJ45 connector, magnetics DP83223, which carry 125Mbps data (125 Mbit/s 4B/5B encoding). These traces should treated transmission lines, with proper terminations applied (please refer schematics terminations. Also please consult device vendor datasheets recommendations proper termination). addition, pair traces differential signals should have same length, minimize signal distortion jitter. traces with high-speed data between RJ45 connector, magnetics DP83223 should have impedance 50ohm, order match 100ohm differential impedance UTP5 cable. Controlled impedance traces used ensure 50ohm impedance. Considerations reduced proper routing, decoupling, power ground distribution, shielding, filtering. Most items listed below improvement also lend themselves towards improving system level performance.
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Routing Guidelines Proper decoupling termination effective ways reducing EMI. following some routing guidelines which will help reduce EMI: Data lines should kept away from clock signals avoid noise coupling. high speed signals should routed near vicinity RJ45 modular jack transformer order prevent common-mode noise coupling onto cable. Footprints capacitors placed along signals with fast rise fall times. event that fast edges causes excessive EMI, they slowed down timing system level performance compromised) using these capacitors.
Power Ground planes power plane should kept away from RJ45 modular jack transformer prevent noise coupling. When separate power planes used, keep power planes away from each other. Ensure that each section power plane, there ground plane larger size underneath. larger ground plane, plus physical separation power planes, will reduce return current noise from fringing into adjacent planes. Power planes should also kept away from edge board prevent noise fringing between power ground planes edge card causing unwanted emission. Ensure that power ground planes different sections overlap order prevent noise coupling. Provide chassis ground plane under RJ45 modular jack.
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Component Selection SRAM following table shows selection compatible SRAM's that used this design:
Vendor Toshiba Hitachi
Configuration 128K 128K 128K
Part Number TC558128AJ-15 HM628127HBJP-15 IDT71024S15Y
Package 32SOJ 32SOJ 32SOJ
RJ45 Connector 8-pin position RJ45 modular jacks used this reference design. There three types modular jacks: non-filtered non-shielded shielded non-filtered shielded filtered (capacitive filtering inductive filtering)
shielded non-filtered jack used reference design. Furthermore, order shielding effective, shield should electrically connected chassis ground impedance connection (i.e. using copper finger stocks firm mechanical contact with mounting bracket). Typically, shielded portion jack will extend through opening mounting bracket make firm mechanical contact with bracket sides. following vendors provide RJ45 connectors: Stewart Connectors Kycon Tel: 717-235-7512 Tel: 800-522-6752 Tel: 800-544-6941
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PM3351 ELAN 1x100
2-PORT 10/100 MBIT/S ETHERNET SWITCH
Power Dynamics
Tel: 201-736-5722
Transformer following transformers recommended: Pulse Engineering PE68515 Valor PT4171S Tel: 619-674-8100 Tel: 800-318-2567
Both have chokes built-in. They pin-compatible. PE68515 selected because better overall performance. Oscillator on-board oscillators provide timing reference PM3351 device, National chipset, interface. oscillators should +/-100ppm better. stability figure oscillator should include variation calibration, temperature, voltage, load, aging, shock, vibration, specified over lift time oscillator. Either CMOS oscillator used. following list vendors that provide these oscillators: Motron Industries Connor Winfield Champion Frequency Control Group Ecliptek Tel: 605-665-9321 Tel: 708-851-4722 Tel: 708-451-1000 Tel: 717-486-3411 Tel: 714-433-1200
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2-PORT 10/100 MBIT/S ETHERNET SWITCH
APPENDIX BILL MATERIALS This table lists components used this reference design. Note that compatible components substituted, this guaranteed. Please refer Component Selection section Appendix suggestions alternative sources some major components.
Item Board Description Mfgr Panasonic Part Number ECU-V1H104KBW
surface mount bypass capacitor, 1206 C10, package C11, C16, C23, C24, C26, C27, C28, C29, C30, C31, C32, C35, C36, C37, C38, C40, C41, C42, C43, C44, C45, C47, C51, C56, C57, C58, C59, C60, C61, C62, C63, C64, C65, C68, C69, C70, C71, C72, C73, C74, C75, C76, C78, C80, C81, C82, C83, C84, C85, C87, C88, C89, C90, C91, C99, C100, C101, C102, C103, C104, C105, C106, C107, C108, C109, C112, C113, C115, C116, C117, C118, C121, C122, C124, C125, C126, C127, C128, C129, C130, C132, C138, C139, C142, C146, C149, C150,C155, C156, C157, C158, C159, C160, C161, C162, C163, C164
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2-PORT 10/100 MBIT/S ETHERNET SWITCH
C25, C46, surface mount bypass capacitor Size C50, C52, C53, C54, C66, C79, C86, C93, C131, C135, C140, C141, C145, C147, C151, C152, C153, C154, C165, C166
Panasonic
ECS-T1AC226R
0.01uF multi-layer ceramic Panasonic C12, C15, C19, chip capacitor, 1206 C20, C22, C33, package C34, C39, C48, C49, C55, C67, C77, C92, C96, C110, C114, C119, C120, C133, C134, C136, C137, C148 C13, C14, C17, C94, C95, 1000 multi-layer ceramic chip capacitor, 0805 package multi-layer ceramic chip 0805 package Panasonic
ECU-V1H103KBM
ECU-V1H102KBM
C18,
Panasonic
ECU-V1H090DCN
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2-PORT 10/100 MBIT/S ETHERNET SWITCH
Item
Board C21, C111
Description 0.001 ceramic disc capacitor 1206 Size
Mfgr Panasonic
Part Number ECK-D3D102KBP
C123 C143, C144
D10, D11, D12, D13, D14, D15, D16, D17, D18, D19, D20, D21, D22, D23, D24, D25, FB1, FB2, FB3, FB4, FB5, FB6, FB7, JP1, Ferrite Bead 1206 package Murata BLM31A700SPTM03
double header 0.100 inch spacing single header 0.100 inch spacing Header Header
Sullins
PZC04DACN
JP3, JP6, JP7, JP8, JP10 JP11, JP12, JP13, JP14, JP15, JP16, JP17, JP18, JP19
Sullins
PZC02SACN
12.1 12.2
Single RJ45 jack with shield, position transistor SOT-23 package
558505-1
National
MMBT2222A
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2-PORT 10/100 MBIT/S ETHERNET SWITCH
Item
Board R10, R13, R15, R16, R20, R21, R24, R25, R34, R44, R45, R57, R63, R64, R67, R68, R70, R71, R73, R76, R77, R78, R79, R83, R86, R87, R90, R95, R96, R97, R99, R102, R106, R107, R109, R111, R113, R116, R124, R133, R138, R147, R148, R149, R151, R153, R154, R155, R156, R157, R164, R165, R166, R167, R168, R169, R170, R172, R173, R175, R176, R177, R178, R179, R197, R198, R199, R200, R201, R202, R203, R204, R205, R206, R207, R208, R209, R210, R211, R212, R213, R214, R215, R216, R217, R218, R219, R220, R221, R222, R223, R224, R225, R226, R250, R251, R252, R253, R254, R255, R256, R257, R258, R259, R260, R261, R262, R263, R264, R265, R266, R267, R268, R269, R270, R271, R272, R273, R274, R275, R276, R277, R278, R279, R280, R289, R290 R14, R17, R23, R27, R30, R103, R108, R112, R118, R121, R128
Description 4.7K ohm, 0.1W chip resistor 0805 package
Mfgr Panasonic
Part Number ERJ-6GEYJ4.7K
ohm, 0805
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2-PORT 10/100 MBIT/S ETHERNET SWITCH
R11, R12, R19, R33, R50, R98, R100, R101, R105, R123, R130 R18, R22, R104, R110
ohm, 0805
ohm, 0805
Item
Board R26, R36, R47, R55, R61, R65, R119, R122, R127, R139, R141, R144 R28, R31, R115, R120 R29, R32, R51, R53, R56, R66, R117, R125, R131, R140, R143, R145 R35, R48, R126, R132
Description ohm, 0805
Mfgr
Part Number
ohm, 0805
ohm, 0805
ohm, 0805
Panasonic
ERJ-6ENF75
R38,R40, R41, R42, ohm, 0805 R43, R46, R58, R81, R84, R85, R88, R89, R91, R93, R94, R136, R162, R163, R174, R180, R181, R182, R183, R184, R185, R186, R187, R188, R189, R190, R191, R192, R193, R194, R195, R196, R233, R234, R235, R236, R237, R238, R239, R240, R241, R242, R243, R244, R245, R246, R247, R248, R249 R49, R129 ohm, 0805
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2-PORT 10/100 MBIT/S ETHERNET SWITCH
R52, R54, R62, R69, R72, R137, R142, R146, R150, R158 R59, R92, R135 R74, R152 R80, R82, R227, R228, R229, R230, R231, R232, R281, R282, R283, R284, R285, R286, R287, R288 R171
ohm, 0805
1.0K ohm, 0805 ohm, 0805 ohm, 0805
2.7K ohm, 0805 Pushbutton Panasonic EVQ-QEC05K PE-68515L
10/100M Transformer Pulse Engineering
U11, U12, 128K SRAM, 32SOJ U19, U20, U21, CPLD 40.0 Clock Oscillator 50.0 Clock Oscillator Inverting Tri-State Buffer
Hitachi
HM628127HBJP-15
XILINX Epson America
XC9572-15 SG-531PH40.000MC SG-531PH50.000MC 74AC540 DP83840AVCE
Epson America
National Semi
10/100M Ethernet Physical National Semi Layer PQFP
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2-PORT 10/100 MBIT/S ETHERNET SWITCH
Line
Board
Description 100BASE-TX Transceiver PLCC
Mfgr National
Part Number DP83223VCE
Fast Ethernet Switch metal package EPROM, bit; 256K 32DIP package
PMC-Sierra
PM3351
AM27C020 -150DC
U13,
Octal Flip-Flop Regulator,
National Semi Linear Technology Dallas E.F. Johnson E.F. Johnson
74AC825SC LT1585CT-3.3
Econo Reset Banana jacks Banana jacks black
DS1233 111-0102-001 111-0103-001
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bit/s itch
Physical Layer Port Sheet
SRAM, Config Resistors, LED's Sheet Clocks, PCIBus, EPROM Sheet
PM3351 Port Sheet
PM3351 Port Bypass caps, Regulator Sheet SRAM, Config Resistors, LED's Sheet Sheet
Physical Layer Port Sheet
Inc.
ivisio
ortland, 3351 Ref. Design
Mond 1997 heet
RBITER R176 R177 R178 R179 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K I/FI I/FO/FI I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO/FI I/FO/FI I/FO/FI I/FO XC9572 I/FI I/FO I/FO I/FO I/FO I/FO I/FO I/FO I/FO FO/FO FO/FO I/FO/FI I/FO/FI I/FO/FI/MR I/FO/FI I/FO/FI I/FO/FI FO/CLK0 FO/CLK1 FRAME A17_0 A16_0 A15_0 A14_0 A13_0 A12_0 A11_0 A10_0 A9_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 27C020
D7_0 D6_0 D5_0 D4_0 D3_0 D2_0 D1_0 D0_0 CS2_0 RD_0
REQ_0 REQ_1
RESET
PCICLK_2
CBE2 FRAME
DEVSEL
SERR
AD15 CBE1
PERR
AD30 AD31 AD29 AD28 AD26 AD27 AD25 AD24 AD23 AD22 AD20 AD21 AD19 AD18 AD16 AD17 CLOCK SELECT CBE3
AD10
CBE0
IRDY
AD14 AD13
AD11 AD12
PCI_CONN
CLOCK 74AC540 R159 R160 R161 R180
61.9 61.9 61.9 61.9 61.9
C123 500PF
SYSTEM CLOCK SCLK_0 SCLK_1 PCICLK_0 PCICLK_1 PCICLK_2 RESET PHY_RESET PCICLK_0 SCLK_0 C151 22uF C152 22uF C153 22uF C154 22uF R135 1.0K ERST RESET Manual Reset itle DS1233
Sierra, Inc.
ortlan U.S.A.
thernet Division
Ref. sign Bus, rbiter, ysClk, EPROM
Size Date: Document Number Monday, November 1997 Sheet
A17_0 A16_0 A15_0 A14_0 A13_0 A12_0 A11_0 A10_0 A9_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 D31_0 D30_0 D29_0 D28_0 D27_0 D26_0 D25_0 D24_0 D23_0 D22_0 D21_0 D20_0 D19_0 D18_0 D17_0 D16_0 D15_0 D14_0 D13_0 D12_0 D11_0 D10_0 D9_0 D8_0 D7_0 D6_0 D5_0 D4_0 D3_0 D2_0 D1_0 D0_0 WR3_0 WR2_0 WR1_0 WR0_0 RD_0 CS3_0 CS2_0 CS0_0 MEMCLK_0
R162 R163 R181 R182 R183 R184 R185 R186 R187 R188 R189 R190 R191 R192 R193 R194 R195 R196
MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10 MD31 MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 MD19 MD18 MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10 MWR3 MWR2 MWR1 MWR0 MGWE MRAS MCS3 MCS2 MCS1 MCS0 MEMCLK MINT IDSEL CBE3 CBE1 AD30 AD31 AD29 AD28 AD26 AD27 AD25 AD24 AD23 AD22 AD20 AD21 AD19 AD18 AD16 AD17 AD15 AD14 AD13 AD11 AD12 AD10 CBE0 MRDY CBE2 FRAME IRDY DEVSEL PERR SERR PCICLK
X_CLK X_EN RX_CLK RX_ER RX_DV RXD3 RXD2 RXD1 RXD0 MDIO ERST
XCLK_0 XD3_0 XD2_0 XD1_0 XD0_0 XEN_0 CRS_0 COL_0 RXCLK_0 RXER_0 RXDV_0 RXD3_0 RXD2_0 RXD1_0 RXD0_0 MDC_0 MDIO_0 ERST
JP10
FRAME IRDY DEVSEL PERR R164 R165 R166 R167 R168 R169 R170 R171 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 2.7K
JP11
SERR
PM3351
BIAS5V BIAS5V
4.7K
R136
4.7K 4.7K
CLK25 SCLK
SCLK_0
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itle Size Date:
thernet Division
REQ_0 PCICLK_0 RESET
AD24 AD25 AD27 AD26 AD28 AD29 AD31 AD30 AD31 AD29
CBE3
AD17 AD16 AD18 AD19 AD21 AD20 AD22 AD23 1.0K
SERR PERR DEVSEL IRDY FRAME CBE2 JP12
AD15
CBE1
AD10 AD12 AD11 AD13 AD14
CBE0
ortl U.S.A. Ref. Desig
Document Number Monday, November 1997 Sheet
SRAM
A16_0 A15_0 A14_0 A13_0 A12_0 A11_0 A10_0 A9_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 128KX8 D31_0 D30_0 D29_0 D28_0 D27_0 D26_0 D25_0 D24_0 CS0_0 RD_0 WR3_0 A16_0 A15_0 A14_0 A13_0 A12_0 A11_0 A10_0 A9_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 128KX8 JP13 A16_0 A15_0 A14_0 A13_0 A12_0 A11_0 A10_0 A9_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 128KX8 D23_0 D22_0 D21_0 D20_0 D19_0 D18_0 D17_0 D16_0 CS0_0 RD_0 WR2_0 A16_0 A15_0 A14_0 A13_0 A12_0 A11_0 A10_0 A9_0 A8_0 A7_0 A6_0 A5_0 A4_0 A3_0 A2_0 A1_0 A0_0 128KX8 D7_0 D6_0 D5_0 D4_0 D3_0 D2_0 D1_0 D0_0 CS0_0 RD_0 WR0_0 JP14 JP15 D15_0 D14_0 D13_0 D12_0 D11_0 D10_0 D9_0 D8_0 CS0_0 RD_0 WR1_0
Configuration Resisto
R197 R172 R198 R199 R200 R201 R202 R203 R173 R204 R205 R206 R207 R208 R209 R210 R211 R212 R213 R214 R215 R216 R217 R218 R219 R220 R221 R222 R223 R224 R225 R226 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K D31_0 D30_0 D29_0 D28_0 D27_0 D26_0 D25_0 D24_0 D23_0 D22_0 D21_0 D20_0 D19_0 D18_0 D17_0 D16_0 D15_0 D14_0 D13_0 D12_0 D11_0 D10_0 D9_0 D8_0 D7_0 D6_0 D5_0 D4_0 D3_0 D2_0 D1_0 D0_0
R227 R228 D7_0 D6_0 D5_0 D4_0 D3_0 D2_0 D1_0 D0_0 CS3_0 MEMCLK_0 RESET CLKEN 74AC825SC R229 R230 R231 R232
390R 390R 390R 390R 390R 390R 390R 390R
Sierra, Inc.
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thernet Division
Portlan U.S.A. Ref. Design Memory
Size Date: Document Number Monday, November 1997 Sheet
38.3 38.3 R115 VPECL_0 C112 .1uF C115 .1uF PE68515 R144 R141 R127 R139 R119 R122 RXI+ RXIR123 R130 10.5 10.5 Receive Common Mode Choke Isolation Xformer R120 C110 .01uF
4.7K
4.7K
4.7K
4.7K
4.7K
RCLKGND IOGND4 IOGND5 IOGND6 REFGND
IOGND1 IOGND2 IOGND3 PCSGND
IOVCC4 IOVCC5 IOVCC6 REFVCC
IOVCC1 IOVCC2 IOVCC3 PCSVCC
4.7K
R133
R138
R106
R102
XCLK_0 XD3_0 XD2_0 XD1_0 XD0_0 XEN_0 CRS_0 COL_0 RXCLK_0 RXER_0 RXDV_0 RXD3_0 RXD2_0 RXD1_0 RXD0_0 MDC_0 MDIO_0 R147 R107 R155 R154 R153 R149 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
X_CLK INTERFACE X_EN X_ER CRS/PHYAD2 RX_CLK RX_ER/PHYAD4 RX_DV RXD3 RXD2 RXD1 RXD0 RXEN MDIO INTERFACE REPEAT 10BT BPALIGN BP4B5B BPSCR REFIN CLK25M CLOCK OSCIN INTERFACE
Mb/s INTERFACE DP83840A 10/100Mb/s ETHERNET
RDSD+ DLBEN/PHYAD0 ENCSEL/PHYAD1 RXI+ RXIT XSREQ
R111
4.7K
82.5
82.5
82.5
82.5
82.5
82.5
PMID+ PMIDSD+ SDU17 PMRD+ PMRDDP83223 TWISTER
XO14 RXGND RXGND XGND XGND RXVCC RXVCC XVCC XVCC .01uF
Isolation Xformer
Common Mode Choke Transmit
Auto Xformer
Mb/s INTERFACE
4.7K R143 R131 R117 R145 R140 R125
R151
EQSEL LBEN ENCSEL CDET XREF 1000pF 10.5 1000pF 10.5
4.7K 4.7K
JTAG INTERFACE
LED1 LED2 LED3 LED4 LED5
R157
4.7K R150 R146 R158 R137 R142
RJ45S-X2
INTERFACE
R105 R101
SCLK_0
R113 4.7K
Place Close
CGMGND CRMGND ANAGND
CRMVCC ECLVCC CGMVCC
RES_0(4) RES_0(3) RES_0(2) RES_0(1)
ANAVCC PLLVCC
OGND PLLGND DGND RXGND
OVCC DVCC RXVCC
R148 R156 4.7K 4.7K
R124
4.7K
R104
1000pF R112 R103
R116 VPECL_0 R109 4.7K 4.7K
R108
R118
R289 4.7K
R110
R100 10.5
Chassis Ground
R126
R132
R128
Ferrite Bead R152 C148 C147 .01uF 22uF
Ferrite Bead C137 C120 C118 C139 .1uF C138 .1uF C140 22uF C141 22uF .01uF .01uF .1uF
Ferrite Bead C133
VA_0 C119 C117 .1uF C116 .1uF C135 22uF C111 .001uF
.01uF .01uF
Ferrite Bead .01uF 22uF
Sierra, Inc.
itle
Portlan U.S.A. PM3351 Port Ref. Design
Size Document Number
R121
thernet Division
SHIELD2 SHIELD1
SPEED_10 SPD_100/PHYAD3 RESET LOWPWR
PHY_RESET
47.5
R129
47.5
A16_1 A15_1 A14_1 A13_1 A12_1 A11_1 A10_1 A9_1 A8_1 A7_1 A6_1 A5_1 A4_1 A3_1 A2_1 A1_1 A0_1 D31_1 D30_1 D29_1 D28_1 D27_1 D26_1 D25_1 D24_1 D23_1 D22_1 D21_1 D20_1 D19_1 D18_1 D17_1 D16_1 D15_1 D14_1 D13_1 D12_1 D11_1 D10_1 D9_1 D8_1 D7_1 D6_1 D5_1 D4_1 D3_1 D2_1 D1_1 D0_1 WR3_1 WR2_1 WR1_1 WR0_1 RD_1 CS3_1 CS0_1 MEMCLK_1
R174 R233 R234 R235 R236 R237 R238 R239 R240 R241 R242 R243 R244 R245 R246 R247 R248
MA17 MA16 MA15 MA14 MA13 MA12 MA11 MA10 MD31 MD30 MD29 MD28 MD27 MD26 MD25 MD24 MD23 MD22 MD21 MD20 MD19 MD18 MD17 MD16 MD15 MD14 MD13 MD12 MD11 MD10 MWR3 MWR2 MWR1 MWR0 MGWE MRAS MCS3 MCS2 MCS1 MCS0 MEMCLK MINT IDSEL CBE3 CBE1 AD30 AD31 AD29 AD28 AD26 AD27 AD25 AD24 AD23 AD22 AD20 AD21 AD19 AD18 AD16 AD17 AD15 AD14 AD13 AD11 AD12 AD10 CBE0 MRDY CBE2 FRAME IRDY DEVSEL PERR SERR PCICLK
X_CLK X_EN RX_CLK RX_ER RX_DV RXD3 RXD2 RXD1 RXD0 MDIO ERST
CLK_1 D3_1 D2_1 D1_1 D0_1 XEN_1 CRS_1 COL_1 RXCLK_1 RXER_1 RXDV_1 RXD3_1 RXD2_1 RXD1_1 RXD0_1 MDC_1 MDIO_1 ERST
JP16
PM3351
BIAS5V BIAS5V
4.7K
R249 R291
4.7K 4.7K
CLK25 SYSCLK
SCLK_1
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itle Size Date:
thernet Division
REQ_1 PCICLK_1 RESET
AD24 AD25 AD27 AD26 AD28 AD29 AD31 AD30 AD30 AD28
CBE3
AD17 AD16 AD18 AD19 AD21 AD20 AD22 AD23 1.0K
SERR PERR DEVSEL IRDY FRAME CBE2 JP17
AD15
CBE1
AD10 AD12 AD11 AD13 AD14
CBE0
Portland, U.S.A. 3351 Port Ref. Design
Document Number Monday, November 1997 Sheet
SRAM
A16_1 A15_1 A14_1 A13_1 A12_1 A11_1 A10_1 A9_1 A8_1 A7_1 A6_1 A5_1 A4_1 A3_1 A2_1 A1_1 A0_1 128KX8 D31_1 D30_1 D29_1 D28_1 D27_1 D26_1 D25_1 D24_1 CS0_1 RD_1 WR3_1 A16_1 A15_1 A14_1 A13_1 A12_1 A11_1 A10_1 A9_1 A8_1 A7_1 A6_1 A5_1 A4_1 A3_1 A2_1 A1_1 A0_1 128KX8 D15_1 D14_1 D13_1 D12_1 D11_1 D10_1 D9_1 D8_1 CS0_1 RD_1 WR1_1 JP19
Confi guratio Resistors
JP18 R250 R251 R252 R253 R254 R255 R256 R257 R175 R258 R259 R260 R261 R262 R263 R264 R265 R266 R267 R268 R269 R270 R271 R272 R273 R274 R275 R276 R277 R278 R279 R280 D31_1 D30_1 D29_1 D28_1 D27_1 D26_1 D25_1 D24_1 D23_1 D22_1 D21_1 D20_1 D19_1 D18_1 D17_1 D16_1 D15_1 D14_1 D13_1 D12_1 D11_1 D10_1 D9_1 D8_1 D7_1 D6_1 D5_1 D4_1 D3_1 D2_1 D1_1 D0_1
A16_1 A15_1 A14_1 A13_1 A12_1 A11_1 A10_1 A9_1 A8_1 A7_1 A6_1 A5_1 A4_1 A3_1 A2_1 A1_1 A0_1 128KX8 D23_1 D22_1 D21_1 D20_1 D19_1 D18_1 D17_1 D16_1 CS0_1 RD_1 WR2_1 A16_1 A15_1 A14_1 A13_1 A12_1 A11_1 A10_1 A9_1 A8_1 A7_1 A6_1 A5_1 A4_1 A3_1 A2_1 A1_1 A0_1
128KX8 D7_1 D6_1 D5_1 D4_1 D3_1 D2_1 D1_1 D0_1 CS0_1 RD_1 WR0_1
R281 R282 D7_1 D6_1 D5_1 D4_1 D3_1 D2_1 D1_1 D0_1 CS3_1 MEMCLK_1 RESET CLKEN 74AC825SC R283 R284 R285 R286 R287 R288
390R 390R 390R 390R 390R 390R 390R 390R
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itle
thernet Division
Portlan U.S.A. PM3351 Ref. Design Memory
Size Date: Document Number Monday, November 1997 Sheet
38.3
38.3
.01uF 82.5 82.5 82.5 82.5 82.5 82.5 .1uF .1uF PE68515 10.5 10.5 Receive PMRD+ PMRDDP83223 TWISTER 4.7K 4.7K Place Close PHY_RESET R290 4.7K 4.7K 1000pF 10.5 1000pF 10.5 47.5 47.5 D680 EQSEL LBEN ENCSEL CDET XREF RXGND RXGND XGND XGND RXVCC RXVCC XVCC XVCC .01uF RJ45S-X2 Common Mode Choke Isolation Xformer PMID+ PMIDSD+ SDRXI+ RXIVPECL_1
4.7K
4.7K
4.7K
4.7K
4.7K
RCLKGND IOGND4 IOGND5 IOGND6 REFGND
IOGND1 IOGND2 IOGND3 PCSGND
IOVCC4 IOVCC5 IOVCC6 REFVCC
IOVCC1 IOVCC2 IOVCC3 PCSVCC
4.7K
4.7K
XCLK_1 XD3_1 XD2_1 XD1_1 XD0_1 XEN_1 CRS_1 COL_1 RXCLK_1 RXER_1 RXDV_1 RXD3_1 RXD2_1 RXD1_1 RXD0_1 MDC_1 MDIO_1 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K 4.7K
X_CLK INTERFACE X_EN X_ER CRS/PHYAD2 RX_CLK RX_ER/PHYAD4 RX_DV RXD3 RXD2 RXD1 RXD0 RXEN MDIO INTERFACE REPEAT 10BT BPALIGN BP4B5B BPSCR REFIN CLK25M OSCIN CLOCK INTERFACE
Mb/s INTERFACE DP83840A 10/100Mb/s ETHERNET
RDSD+ DLBEN/PHYAD0 ENCSEL/PHYAD1
Isolation Xformer
Mb/s INTERFACE
RXI+ RXI- LED1 LED2 LED3 LED4 LED5
Common Mode Choke Transmit
Auto Xformer
4.7K 4.7K
JTAG INTERFACE
INTERFACE
SCLK_1
4.7K
CGMGND CRMGND ANAGND
CRMVCC ECLVCC CGMVCC
RES_0(4) RES_0(3) RES_0(2) RES_0(1)
ANAVCC PLLVCC
OGND PLLGND DGND RXGND
OVCC DVCC RXVCC
4.7K 4.7K
10.5
1000pF
VPECL_1 4.7K 4.7K
Chassis Ground
Ferrite Bead .01uF 22uF
Ferrite Bead .01uF .01uF .1uF .1uF .1uF 22uF 22uF
Ferrite Bead
VA_1 .1uF .1uF 22uF .001uF
.01uF .01uF
Ferrite Bead .01uF 22uF
Sierra, Inc.
itle Size Date:
Portlan U.S.A. 3351 Port Design
Document Number Monday, November 1997 Sheet
thernet Division
SHIELD2 SHIELD1
SPEED_10 SPD_100/PHYAD3 RESET LOWPWR
C104 .1uF
C102 .1uF
C125 .1uF
C105 .1uF
C108 .1uF
C100 .1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.01uF .01uF .1uF .1uF .1uF .1uF C124 .1uF C101 .1uF 22uF 22uF .1uF .01uF .01uF
.1uF
.1uF
.1uF
C122 .1uF
.1uF
C126 .1uF
C127 .1uF
C128 .1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
C114 .01uF .01uF C134 C136 .1uF C113 .1uF .1uF .1uF .1uF C132 .1uF 22uF C145 22uF .1uF .01uF .01uF
C129 .1uF
C130 .1uF
.1uF
C121 .1uF
C107 .1uF
.1uF
22uF
C131 22uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
22uF
22uF
Case connected plane (pin2)
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
C149 .1uF
.1uF
.1uF
1585CT -3.3-ND 4.6A
C167 2200uF ALUMINUM ELECT
C103 .1uF .1uF C142 .1uF .1uF .1uF .1uF C146 .1uF C106 .1uF C109 .1uF .1uF .1uF .1uF .1uF C150 C143 10uF C144 10uF
C155
C156
C157
C158
C159
C160
C161
C162
C163
C164
C165
C166
Sierra, Inc.
itle
thernet Division
Portlan U.S.A. 3351 Design Power
Size Date: Document Number Monday, November 1997 Sheet
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
.1uF
22uF
22uF
PMC-970390 ISSUE ADVANCE
PM3351 ELAN 1x100
2-PORT 10/100 MBIT/S ETHERNET SWITCH
CONTACTING PMC-SIERRA PMC-Sierra, Inc. Ethernet Products Division 9400 Gemini Beaverton, 97008 Telephone: 520-1800 Facsimile: 520-1700 Document Information: Product Information: Applications information: Site: document@pmc-sierra.com info@pmc-sierra.com apps@pmc-sierra.com http://www.pmc-sierra.com
Seller will have obligation liability respect defects damage caused unauthorized use, mis-use, accident, external cause, installation error, normal wear tear. There warranties, representations guarantees kind, either express implied custom, regarding product performance, including those regarding quality, merchantability, fitness purpose, condition, design, title, infringement thirdparty rights, conformance with sample. Seller shall responsible loss damage whatever nature resulting from reliance upon, information contained this document. event will Seller liable Buyer other party loss profits, loss savings, punitive, exemplary, incidental, consequential special damages, even Seller knowledge possibility such potential loss damage even caused Seller's negligence. 1998 PMC-Sierra, Inc. PMC-970390 Issue Printed Issue date: April 1998
PMC-Sierra, Inc.
8555 Baxter Place Burnaby, Canada .415.6000
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