3.3V CMOS 16-BIT IDT74LVCH16374A EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3

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3.3V CMOS 16-BIT IDT74LVCH16374A EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3

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IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
3.3V CMOS 16-BIT IDT74LVCH16374A EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3-STATE OUTPUTS, TOLERANT BUS-HOLD
Typical tSK(o) (Output Skew) 250ps 2000V MIL-STD-883, Method 3015; 200V using machine model 200pF, 3.3V 0.3V, Normal Range 2.7V 3.6V, Extended Range CMOS power levels (0.4µ typ. static) inputs, outputs, tolerant Supports insertion Available SSOP, TSSOP, TVSOP packages
FEATURES:
DESCRIPTION
DRIVE FEATURES: APPLICATIONS:
High Output Drivers: ±24mA Reduced system switching noise
3.3V mixed voltage systems Data communication telecommunication systems
LVCH16374A 16-bit edge-triggered D-type register built using advanced dual metal CMOS technology. This high-speed, low-power register ideal buffer register data synchronization storage. Output Enable (OE) clock (CLK) controls organized operate each device 8-bit registers 16-bit register with common clock. Flow-through organization signal pins simplifies layout. inputs designed with hysteresis improved noise margin. pins LVCH16374A driven from either 3.3V devices. This feature allows this device translator mixed 3.3V/5V supply system. LVCH16374A been designed with ±24mA output driver. This driver capable driving moderate heavy load while maintaining speed performance. LVCH16374A "bus-hold" which retains inputs' last state whenever input goes high impedance. This prevents floating inputs eliminates need pull-up/down resistors.
FUNCTIONAL BLOCK DIAGRAM
1CLK
2CLK
SEVEN OTHER CHANNELS
SEVEN OTHER CHANNELS
logo registered trademark Integrated Device Technology, Inc.
1999 Integrated Device Technology, Inc.
MARCH 1999
DSC-4643/2
IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
CONFIGURATION
ABSOLUTE MAXIMUM RATINGS(1)
Symbol Description VTERM Terminal Voltage with Respect Storage Temperature Output Current Continuous Clamp Current, Continuous Current through each -0.5 +6.5 +150 ±100
Unit
1CLK
TSTG IOUT
NOTE: Stresses greater than those listed under ABSOLUTE MAXIMUM RATINGS cause permanent damage device. This stress rating only functional operation device these other conditions above those indicated operational sections this specification implied. Exposure absolute maximum rating conditions extended periods affect reliability.
CAPACITANCE +25°C, 1.0MHz)
Symbol COUT CI/O Parameter(1) Input Capacitance Output Capacitance Port Capacitance Conditions VOUT Typ. Max. Unit
NOTE: applicable device type.
DESCRIPTION
Names xCLK Data Inputs
2CLK
Description Clock Inputs Output Enable Inputs (Active LOW) 3-State Outputs
SSOP/ TSSOP/ TVSOP VIEW
NOTE: These pins have "Bus-Hold". other pins standard inputs, outputs, I/Os.
FUNCTION TABLE (EACH FLIP-FLOP)(1)
Inputs xCLK Outputs Q(2)
NOTES: HIGH Voltage Level Don't Care Voltage Level High-Impedance LOW-to-HIGH transition Output level before indicated steady-state input conditions were established.
IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE
Following Conditions Apply Unless Otherwise Specified: Operating Condition: -40°C +85°C
Symbol IOZH IOZL IOFF ICCL ICCH ICCZ High Impedance Output Current (3-State Output pins) Input/Output Power Leakage Clamp Diode Voltage Input Hysteresis Quiescent Power Supply Current 5.5V 2.3V, -18mA 3.3V 3.6V -0.7 -1.2 3.6V 5.5V Parameter Input HIGH Voltage Level Input Voltage Level Input Leakage Current 2.3V 2.7V 2.7V 3.6V 2.3V 2.7V 2.7V 3.6V 3.6V 5.5V Test Conditions Min. Typ.(1) Max. Unit
Quiescent Power Supply Current Variation
5.5V(2) input 0.6V, other inputs
NOTES: Typical values 3.3V, +25°C ambient. This applies disabled state only.
BUS-HOLD CHARACTERISTICS
Symbol IBHH IBHL IBHH IBHL IBHHO IBHLO
NOTES: Pins with Bus-Hold identified description. Typical values 3.3V, +25°C ambient.
Parameter(1) Bus-Hold Input Sustain Current Bus-Hold Input Sustain Current Bus-Hold Input Overdrive Current 2.3V 3.6V
Test Conditions 0.8V 1.7V 0.7V 3.6V
Min.
Typ.(2)
Max. ±500
Unit
IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
OUTPUT DRIVE CHARACTERISTICS
Symbol Parameter Output HIGH Voltage 2.3V 2.3V 2.7V Output Voltage 2.3V 3.6V 2.3V 2.7V 24mA 0.1mA 12mA 12mA 24mA Test Conditions(1) 2.3V 3.6V 0.1mA 12mA Min. Max. 0.55 Unit
NOTE: must within min. max. range shown ELECTRICAL CHARACTERISTICS OVER OPERATING RANGE table appropriate range. 40°C 85°C.
OPERATING CHARACTERISTICS, 3.3V 0.3V, 25°C
Symbol Parameter Power Dissipation Capacitance Flip-Flop Outputs enabled Power Dissipation Capacitance Flip-Flop Outputs disabled Test Conditions 0pF, 10Mhz Typical Unit
SWITCHING CHARACTERISTICS(1)
2.7V Symbol fMAX tPLH tPHL tPZH tPZL tPHZ tPLZ tSK(o) Propagation Delay xCLK Output Enable Time Output Disable Time Set-up Time HIGH LOW, data before Hold Time HIGH LOW, data after Pulse duration, HIGH Output Skew(2) Parameter Min. Max. 3.3V 0.3V Min. Max. Unit
NOTES: TEST CIRCUITS WAVEFORMS. 40°C 85°C. Skew between outputs same package switching same direction.
IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
TEST CIRCUITS WAVEFORMS TEST CONDITIONS
Symbol VLOAD VCC(1)= 3.3V±0.3V VCC(1)= 2.7V VCC(2)= 2.5V±0.2V Unit
OPPOSITE PHASE INPUT TRANSITION SAME PHASE INPUT TRANSITION tPLH OUTPUT tPLH tPHL tPHL
Link
Propagation Delay
ENABLE CONTROL INPUT tPZL OUTPUT SWITCH NORMALLY CLOSED tPZH OUTPUT SWITCH NORMALLY OPEN HIGH VLOAD/2 tPHZ tPLZ DISABLE
Pulse Generator D.U.T. VOUT
VLOAD Open
VLOAD/2
Link
Test Circuit Outputs
Link
DEFINITIONS: Load capacitance: includes probe capacitance. Termination resistance: should equal ZOUT Pulse Generator. NOTES: Pulse Generator Pulses: Rate 10MHz; 2.5ns; 2.5ns. Pulse Generator Pulses: Rate 10MHz; 2ns; 2ns.
NOTE: Diagram shown input Control Enable-LOW input Control Disable-HIGH.
Enable Disable Times
SWITCH POSITION
Test Open Drain Disable Enable Disable High Enable High Other Tests Switch VLOAD Open
DATA INPUT TIMING INPUT ASYNCHRONOUS CONTROL SYNCHRONOUS CONTROL
tREM
Link
Set-up, Hold, Release Times
tPLH2 tPHL2
Link
INPUT
tPLH1
tPHL1
LOW-HIGH-LOW PULSE HIGH-LOW-HIGH PULSE
OUTPUT
Link
OUTPUT
Pulse Width
tSK(x) tPLH2 tPLH1 tPHL2 tPHL1
Output Skew tSK(X)
NOTES: tSK(o) OUTPUT1 OUTPUT2 outputs. tSK(b) OUTPUT1 OUTPUT2 same bank.
IDT74LVCH16374A 3.3V CMOS 16-BIT EDGE-TRIGGERED D-TYPE FLIP-FLOP
ORDERING INFORMATION
Bus-Hold Temp. Range Family XXXX Device Type Package
Shrink Small Outline Package Thin Shrink Small Outline Package Thin Very Small Outline Package
374A 16-Bit Edge-Triggered D-Type Flip-Flop with 3-State Outputs Double-Density, ±24mA Bus-hold -40°C +85°C
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3.3V CMOS 16-BIT IDT74LVCH16374A EDGE-TRIGGERED D-TYPE FLIPFLOP WITH 3

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